- 11 9月, 2021 1 次提交
-
-
由 zoujr 提交于
-
- 10 9月, 2021 3 次提交
-
-
由 zoujr 提交于
-
由 Jiawei Lin 提交于
* misc: add submodule huancun * huancun: integrate huancun to SoC as L3 * remove l2prefetcher * update huancun * Bump HuanCun * Use HuanCun instead old L2/L3 * bump huancun * bump huancun * Set L3NBanks to 4 * Update rocketchip * Bump huancun * Bump HuanCun * Optimize debug configs * Configs: fix L3 bug * Add TLLogger * TLLogger: fix release ack address * Support write prefix into database * Recoding more tilelink info * Add a database output format converter * missqueue: add difftest port for memory difftest during refill * misc: bump difftest * misc: bump difftest & huancun * missqueue: do not check refill data when get Grant * Add directory debug tool * config: increase client dir size for non-inclusive cache * Bump difftest and huancun * Update l2/l3 cache configs * Remove deprecated fpga/* * Remove cache test * Remove L2 preftecher * bump huancun * Params: turn on l2 prefetch by default * misc: remove duplicate chisel-tester2 * misc: remove sifive inclusive cache * bump difftest * bump huancun * config: use 4MB L3 cache * bump huancun * bump difftest * bump difftest Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn> Co-authored-by: NTangDan <tangdan@ict.ac.cn>
-
由 Yinan Xu 提交于
This commit changes how uop and data are read in reservation stations. It helps the issue timing. Previously, we access payload array and data array after we decide the instructions that we want to issue. This method makes issue selection and array access serialized and brings critial path. In this commit, we add one more read port to payload array and data array. This extra read port is for the oldest instruction. We decide whether to issue the oldest instruction and read uop/data simultaneously. This change reduces the critical path to each selection logic + read + Mux (previously it's selection + arbitration + read). Variable oldestOverride indicates whether we choose the oldest ready instruction instead of the normal selection. An oldestFirst option is added to RSParams to parameterize whether we need the age logic. By default, it is set to true unless the RS is for ALU. If the timing for aged ALU rs meets, we will enable it later.
-
- 09 9月, 2021 3 次提交
-
-
由 Lemover 提交于
* mmu.l2tlb: l2tlb now support multiple parallel mem accesses 8 missqueue entry and 1 page table worker mq entry only supports page leaf entry ptw supports all the three level entries * mmu.tlb: fix bug of mq.refill_vpn and out.ready * mmu.tlb: fix bug of perf counter * mmu.tlb: l2tlb's l3 now 128 sets and 4 ways * mmu.tlb: miss queue now will 'merge' same mem req addr * mmu.l2tlb: ptw doesn't access last level pte * mmu.l2tlb: add mem req mask into ptw func block_decoupled doesn't work well and has bug in signal ready * mmu.l2tlb: fix bug of sfence to fsm add a new state s_check_pte to ptw fsm now take memPte from outside, doesn't store it inside mem_resp_valid will arrive a cycle before mem_resp_data * mmu.l2tlb: rm some state in fsm * mmu.tlb: set itlb default size * mmu.l2tlb: unkonwn mq wait bug, change code style to avoid it * mmu.l2tlb: opt, mq's entry with cache_l3 would not be blocked * mmu.l2tlb: add many time out assert * mmu.l2tlb: fix bug of mq enq state change & wait_id * Revert "mmu.tlb: l2tlb's l3 now 128 sets and 4 ways" This reverts commit 216e4192e4b01e68ce5502135318bc2473434907. * Revert "mmu.tlb: set itlb default size" This reverts commit 670bf1e408384964c601c0a55defbc767eb80698. * mmu.l2tlb: set miss queue size to 9 and set filter size to 8 if they are equal, itlb may loss its req
-
由 Yinan Xu 提交于
This commit adds some simple instruction fusion cases in decode stage. Currently we only implement instruction pairs that can be fused into RV64GCB instructions. Instruction fusions are detected in the decode stage by FusionDecoder. The decoder checks every two instructions and marks the first instruction fused if they can be fused into one instruction. The second instruction is removed by setting the valid field to false. Simple fusion cases include sh1add, sh2add, sh3add, sexth, zexth, etc. Currently, ftq in frontend needs every instruction to commit. However, the second instruction is removed from the pipeline and will not commit. To solve this issue, we temporarily add more bits to isFused to indicate the offset diff of the two fused instruction. There are four possibilities now. This feature may be removed later. This commit also adds more instruction fusion cases that need changes in both the decode stage and the funtion units. In this commit, we add some opcode to the function units and fuse the new instruction pairs into these new internal uops. The list of opcodes we add in this commit is shown below: - szewl1: `slli r1, r0, 32` + `srli r1, r0, 31` - szewl2: `slli r1, r0, 32` + `srli r1, r0, 30` - byte2: `srli r1, r0, 8` + `andi r1, r1, 255` - sh4add: `slli r1, r0, 4` + `add r1, r1, r2` - sr30add: `srli r1, r0, 30` + `add r1, r1, r2` - sr31add: `srli r1, r0, 31` + `add r1, r1, r2` - sr32add: `srli r1, r0, 32` + `add r1, r1, r2` - oddadd: `andi r1, r0, 1`` + `add r1, r1, r2` - oddaddw: `andi r1, r0, 1`` + `addw r1, r1, r2` - orh48: mask off the first 16 bits and or with another operand (`andi r1, r0, -256`` + `or r1, r1, r2`) Furthermore, this commit adds some complex instruction fusion cases to the decode stage and function units. The complex instruction fusion cases are detected after the instructions are decoded into uop and their CtrlSignals are used for instruction fusion detection. We add the following complex instruction fusion cases: - addwbyte: addw and mask it with 0xff (extract the first byte) - addwbit: addw and mask it with 0x1 (extract the first bit) - logiclsb: logic operation and mask it with 0x1 (extract the first bit) - mulw7: andi 127 and mulw instructions. Input to mul is AND with 0x7f if mulw7 bit is set to true.
-
由 Lemover 提交于
* mmu.tlb: l2tlb's l3 now 128 sets and 4 ways * mmu.tlb: set itlb default size
-
- 08 9月, 2021 1 次提交
-
-
由 zfw 提交于
* Alu: fix andn, orn, xnor * Decode: change instruction name
-
- 06 9月, 2021 4 次提交
-
-
由 Steve Gou 提交于
add new ittage indirect target predictor
-
由 William Wang 提交于
dcache,lq: make dcache to lq refill faster
-
由 Yinan Xu 提交于
This commit assigns exu.io.out.fflags to RegNext(fu.io.fflags) if the function unit has fastUopOut but has not implemented it. Previously it causes a bug that fflags may be one cycle earlier than expected. This commit also removes the extra logic in FmacExeUnit and FmiscExeUnit. They are exactly the same as ExeUnit now.
-
由 YikeZhou 提交于
* backend, rename: support elimination of mv inst whose lsrc=0 [known bug] instr page fault not properly raised after sfence.vma * backend, roq: [bug fix] won't label me with exception as writebacked
-
- 05 9月, 2021 5 次提交
-
-
由 Jiawei Lin 提交于
-
由 Lingrui98 提交于
-
由 Yinan Xu 提交于
This commit adds support for load balance between different issue ports when the function unit is not pipelined and the reservation station has more than one issue ports. We use a ping pong bit to decide which port to issue the instruction. At every clock cycle, the bit is flipped.
-
由 Lemover 提交于
* mmu.l2tlb: l2tlb now support multiple parallel mem accesses 8 missqueue entry and 1 page table worker mq entry only supports page leaf entry ptw supports all the three level entries * mmu.tlb: fix bug of mq.refill_vpn and out.ready
-
由 Yinan Xu 提交于
This commit adds assertion in MaskData to check the width of mask and data. When the width of mask is smaller than the width of data, (~mask & data) and (mask & data) will always clear the upper bits of the data. This usually causes unexpected behavior. This commit adds explicit width declarations where MaskData is used.
-
- 04 9月, 2021 3 次提交
-
-
由 Jiawei Lin 提交于
* Makefile: add '--gen-mem-verilog'
-
由 Jiawei Lin 提交于
* FMA: spearate fadd/fmul/fma * exu: enable fast uop out from fmacExeUnit Co-authored-by: NYinan Xu <xuyinan@ict.ac.cn>
-
由 Lingrui98 提交于
-
- 03 9月, 2021 15 次提交
-
-
由 Jiuyang Liu 提交于
-
由 Lingrui98 提交于
-
由 LinJiawei 提交于
-
由 Lingrui98 提交于
-
由 William Wang 提交于
-
由 Steve Gou 提交于
frontend: add ittage indirect predictor
-
由 Guokai Chen 提交于
-
由 Lingrui98 提交于
-
由 Guokai Chen 提交于
-
由 Lingrui98 提交于
-
由 Jiawei Lin 提交于
* Multiplier: adjust pipeline
-
由 William Wang 提交于
mem: use vaddr based store to load forward for better timing
-
由 Yinan Xu 提交于
This commit adds an 8-entry buffer for fdivSqrt function unit input. Set hasInputBuffer to true to enable input buffers for other function units.
-
由 Guokai Chen 提交于
-
由 Lingrui98 提交于
* previously we only modify jmpTarget on misprediction, and that's because we only use ftb to predict jalr target. However, with the presence of an indirect branch predictor, there exists such case that an indirect branch is correctly predicted when the target in ftb entry is wrong.
-
- 02 9月, 2021 5 次提交
-
-
由 Lemover 提交于
* Revert "Revert "l0tlb: add a new level tlb to each mem pipeline (#936)" (#945)" This reverts commit b052b972. * fu: remove unused import * mmu.tlb: 2 load/store pipeline has 1 dtlb * mmu: remove btlb, the l1-tlb * mmu: set split-tlb to 32 to check perf effect * mmu: wrap tlb's param with TLBParameters * mmu: add params 'useBTlb' dtlb size is small: normal 8, super 2 * mmu.tlb: add Bundle TlbEntry, simplify tlb hit logic(coding) * mmu.tlb: seperate tlb's storage, relative hit/sfence logic tlb now supports full-associate, set-associate, directive-associate. more: change tlb's parameter usage, change util.Random to support case that mod is 1. * mmu.tlb: support normalAsVictim, super(fa) -> normal(sa/da) be carefull to use tlb's parameter, only a part of param combination is supported * mmu.tlb: fix bug of hit method and victim write * mmu.tlb: add tlb storage's perf counter * mmu.tlb: rewrite replace part, support set or non-set * mmu.tlb: add param outReplace to receive out replace index * mmu.tlb: change param superSize to superNWays add param superNSets, which should always be 1 * mmu.tlb: change some perf counter's name and change some params * mmu.tlb: fix bug of replace io bundle * mmu.tlb: remove unused signal wayIdx in tlbstorageio * mmu.tlb: separate tlb_ld/st into two 'same' tlb * mmu.tlb: when nWays is 1, replace returns 0.U before, replace will return 1.U, no influence for refill but bad for perf counter * mmu.tlb: give tlb_ld and tlb_st a name (in waveform)
-
由 William Wang 提交于
-
由 William Wang 提交于
-
由 William Wang 提交于
-
由 William Wang 提交于
-