Makefile: add '--gen-mem-verilog'

Makefile

@@ -47,19 +47,12 @@ $(TOP_V): $(SCALA_FILE)
 	mkdir -p $(@D)
 	mill -i XiangShan.runMain $(FPGATOP) -td $(@D)                       \
 		--config $(CONFIG) --full-stacktrace --output-file $(@F)     \
-		--disable-all --remove-assert \
+		--disable-all --remove-assert --infer-rw \
+		--repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf \
+		--gen-mem-verilog full \
 		$(SIM_ARGS) \
 		--num-cores $(NUM_CORES)
-	# $(MEM_GEN) $(@D)/$(@F).conf --tsmc28 --output_file $(@D)/tsmc28_sram.v > $(@D)/tsmc28_sram.v.conf
-	# $(MEM_GEN) $(@D)/$(@F).conf --output_file $(@D)/sim_sram.v
-	# sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' $@
-	# @git log -n 1 >> .__head__
-	# @git diff >> .__diff__
-	# @sed -i 's/^/\/\// ' .__head__
-	# @sed -i 's/^/\/\//' .__diff__
-	# @cat .__head__ .__diff__ $@ > .__out__
-	# @mv .__out__ $@
-	# @rm .__head__ .__diff__
+	 sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' $@
 
 deploy: build/top.zip
 
@@ -79,16 +72,9 @@ $(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
 	@date -R | tee -a $(TIMELOG)
 	$(TIME_CMD) mill -i XiangShan.test.runMain $(SIMTOP) -td $(@D)       \
 		--config $(CONFIG) --full-stacktrace --output-file $(@F)     \
-		--num-cores $(NUM_CORES) $(SIM_ARGS)
-		#--infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf   \
-	# $(MEM_GEN) $(@D)/$(@F).conf --output_file $(@D)/$(@F).sram.v
-	# @git log -n 1 >> .__head__
-	# @git diff >> .__diff__
-	# @sed -i 's/^/\/\// ' .__head__
-	# @sed -i 's/^/\/\//' .__diff__
-	#@cat .__head__ .__diff__ $@ $(@D)/$(@F).sram.v > .__out__
-	# @mv .__out__ $@
-	# @rm .__head__ .__diff__
+		--num-cores $(NUM_CORES) $(SIM_ARGS)						\
+		--infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf \
+		--gen-mem-verilog full
 	sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V)
 
 sim-verilog: $(SIM_TOP_V)