bundle: add a full target in update bundle

src/main/scala/xiangshan/frontend/FrontendBundle.scala

@@ -295,6 +295,7 @@ class BranchPredictionUpdate(implicit p: Parameters) extends BranchPredictionBun
   val new_br_insert_pos = Vec(numBr, Bool())
   val old_entry = Bool()
   val meta = UInt(MaxMetaLength.W)
+  val full_target = UInt(VAddrBits.W)
   // val ghist = new GlobalHistory() This in spec_meta
 
   def fromFtqRedirectSram(entry: Ftq_Redirect_SRAMEntry) = {

src/main/scala/xiangshan/frontend/NewFtq.scala

@@ -871,10 +871,11 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
   io.toBpu.update := DontCare
   io.toBpu.update.valid := commit_valid && do_commit
   val update = io.toBpu.update.bits
-  update.false_hit := commit_hit === h_false_hit
-  update.pc        := commit_pc_bundle.startAddr
-  update.preds.hit := commit_hit === h_hit || commit_hit === h_false_hit
-  update.meta      := commit_meta.meta
+  update.false_hit   := commit_hit === h_false_hit
+  update.pc          := commit_pc_bundle.startAddr
+  update.preds.hit   := commit_hit === h_hit || commit_hit === h_false_hit
+  update.meta        := commit_meta.meta
+  update.full_target := commit_target
   update.fromFtqRedirectSram(commit_spec_meta)
 
   val commit_real_hit = commit_hit === h_hit