- 06 5月, 2022 1 次提交
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由 Yinan Xu 提交于
difftest: fix support for Spike
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- 05 5月, 2022 5 次提交
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由 Yinan Xu 提交于
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由 William Wang 提交于
s1_tag_match_way is vaild iff tag_read.valid and meta_read.valid in s0 for the same req
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
XiangShan does not support fs=0 because when fs=0, all floating-point states are not accessible. Spike supports fs=0. To diff with Spike, we temporarily set fs to 1 when initialized.
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由 Yinan Xu 提交于
Add support for the WFI instruction
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- 04 5月, 2022 2 次提交
- 29 4月, 2022 1 次提交
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由 Yinan Xu 提交于
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- 28 4月, 2022 2 次提交
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由 Yinan Xu 提交于
To test WFI, we delay the interrupts for more cycles.
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由 Yinan Xu 提交于
The RISC-V WFI instruction is previously decoded as NOP. This commit adds support for the real wait-for-interrupt (WFI). We add a state_wfi FSM in the ROB. After WFI leaves the ROB, the next instruction will wait in the ROB until an interrupt.
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- 26 4月, 2022 1 次提交
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由 Jay 提交于
*** Description *** - During multi-thread verilator emulation, the reset_ncycle(size_t cycles) function will trigger the flash_read() function where a NULL pointer *flash_base will be used since we init flash after the reset_ncycle. - This bug is triggered in some seeds, while others runs in a normal way. *** Solution *** - init flash before reset_cycles()
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- 25 4月, 2022 3 次提交
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由 wakafa 提交于
* difftest: fix false-positive difftest intRF writeback, adapt to new difftest API * csr: skip mip difftest * bump difftest * bump difftest
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由 cui fliter 提交于
* fix some typos Signed-off-by: Ncuishuang <imcusg@gmail.com>
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由 Jay 提交于
* Bump difftest and ready-to-run * add copy-and-run test for CI * Bump ready-to-run: update NEMU * CI: specify reference in ready-to-run repo
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- 14 4月, 2022 1 次提交
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由 Lemover 提交于
old missqueue: cache req miss slot and mem access-er Problem: these two func are totally different, make mq hard to handle in a single select policy. Solution: divide these two funciton into two module. new MissQueue: only hold reqs that page cache miss and need re-req cache, a simple flushable queue llptw: Last level ptw, only access ptes, priorityMux queue * mmu: rename PTW.scala to L2TLB.scala * mmu: rename PTW to L2TLB * mmu: rename PtwFsm to PTW * mmu.l2tlb: divide missqueue into 'missqueue' and llptw old missqueue: cache req miss slot and mem access-er Problem: these two func are totally different, make mq hard to handle in single select policy. Solution: divide these two funciton into two module. new MissQueue: only hold reqs that page cache miss and new re-req cache llptw: Last level ptw, only access ptes * mmu.l2tlb: syntax bug that misses io assign * mmu.l2tlb: fix bug that mistakes ptw's block signal
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- 02 4月, 2022 1 次提交
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由 William Wang 提交于
* mem: optimize missq reject to lq timing DCache replay request is quite slow to generate, as it need to compare load address with address in all valid miss queue entries. Now we delay the usage of replay request from data cache. Now replay request will not influence normal execuation flow until load_s3 (1 cycle after load_s2, load result writeback to RS). It is worth mentioning that "select refilling inst for load writeback" will be disabled if dcacheRequireReplay in the last cycle. * dcache: compare probe block addr instead of full addr * mem: do not replay from RS when ldld vio or fwd failed ld-ld violation or forward failure will let an normal load inst replay from fetch. If TLB hit and ld-ld violation / forward failure happens, we write back that inst immediately. Meanwhile, such insts will not be replayed from rs. It should fix "mem: optimize missq reject to lq timing" * mem: fix replay from rs condition * mem: reduce refill to use latency This commit update lq entry flag carefully in load_s3 to avoid extra refill delay. It will remove the extra refill delay introduced by #1375 without harming memblock timing. In #1375, we delayed load refill when dcache miss queue entry fails to accept a miss. #1375 exchanges performance for better timing. * mem: fix rs feedback priority When dataInvalid && mshrFull, a succeed refill should not cancel rs replay.
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- 01 4月, 2022 2 次提交
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由 Lemover 提交于
Corner Case that makes l2tlb's performance decrease sharply: core may have mis-speculative memory access, which may cause tlb-miss and ptw req to l2tlb. In l2tlb, the reqs may still miss and even have invalid pte that won't be stored in l2tlb.cache. If the relative ptes are invalid, these reqs will be held by miss queue and wait for page walker performing page table walk one by one. It's too slow and will raise time out assert in l2tlb.missqueue. Solution: store invalid entries(only super entries) into sp. Bad news is that sp only has16 entries, so invaid entries will pollute sp as well. Good news is that the invalid reqs are always in same super page, so only one entries is mostly enough. * l2tlb.cache: sp entries now handles invalid entries * l2tlb.cache: fix syntax error, forgot assgin some signals
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由 Jiawei Lin 提交于
Add support for compiling XiangShan with CIRCT
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- 31 3月, 2022 3 次提交
- 30 3月, 2022 1 次提交
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由 Lemover 提交于
* bump huancun * sram: fix sram, keep rdata when w.valid * tlb: when refill, just return miss at next cycle, rm unused assert
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- 28 3月, 2022 2 次提交
- 27 3月, 2022 3 次提交
- 26 3月, 2022 1 次提交
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由 Jiawei Lin 提交于
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- 23 3月, 2022 2 次提交
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由 Jay 提交于
* IFU <bug-fix>: deal with itlb miss for resend * IFU <bug fix>: enable crossPageFault for resend-pf Co-authored-by: NDeltaZero <lacrosseelis@gmail.com>
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由 Leway Colin 提交于
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- 22 3月, 2022 1 次提交
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由 wakafa 提交于
* readme: update dir structure description and sync en/zh readme * readme: update fig of nanhu-arch * readme: update docs information * readme: fix md format
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- 15 3月, 2022 1 次提交
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由 wakafa 提交于
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- 06 3月, 2022 1 次提交
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由 Yinan Xu 提交于
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- 28 2月, 2022 3 次提交
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由 Steve Gou 提交于
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由 Steve Gou 提交于
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由 William Wang 提交于
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- 25 2月, 2022 1 次提交
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由 Jay 提交于
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- 24 2月, 2022 2 次提交