roq: optimize commit timing and block commits when exceptions occur

For single port SRAM icache, we disable read when write. So we disable
if1_cango when flush if2 register

to not pass fu.ready to dispatch through rs

idx      -> index
red      -> redirect
fb       -> feedback
iss      -> issue
sel      -> select
bub      -> bubble
cnt      -> count
wu       -> wakeup
bp       -> bypass

Store whole cache line in one SRAM.
Let backend engineers manually split it into smaller banks.

If we DontCare a register write data, chisel will convert it to 0 (or somthing else?).
Thus, for exceptionVec, we cannot simply DontCare the wdata.
Instead, we have to assign them separately.

s2_hit use s3_valid :)

1. do not update state in select stage, turn to mask at issue stage
2. put redirect checking of select from ctrl module to data module
3. bypass does not check redirect
4. optimize select index generate
5. if fixedDelay is 0, do not use bypassQueue module