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体验新版 GitCode,发现更多精彩内容 >>
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ded91833
编写于
1月 20, 2021
作者:
Y
Yinan Xu
浏览文件
操作
浏览文件
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电子邮件补丁
差异文件
dispatch2: optimize busyTable read timing
上级
209167cb
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
16 addition
and
10 deletion
+16
-10
src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala
src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala
+9
-6
src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala
src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala
+7
-4
未找到文件。
src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala
浏览文件 @
ded91833
...
...
@@ -55,14 +55,17 @@ class Dispatch2Fp extends XSModule {
io
.
readRf
(
3
*
i
)
:=
io
.
fromDq
(
index
(
fpReadPortSrc
(
i
))).
bits
.
psrc1
io
.
readRf
(
3
*
i
+
1
)
:=
io
.
fromDq
(
index
(
fpReadPortSrc
(
i
))).
bits
.
psrc2
io
.
readRf
(
3
*
i
+
2
)
:=
io
.
fromDq
(
index
(
fpReadPortSrc
(
i
))).
bits
.
psrc3
io
.
readState
(
3
*
i
).
req
:=
io
.
fromDq
(
index
(
fpReadPortSrc
(
i
))).
bits
.
psrc1
io
.
readState
(
3
*
i
+
1
).
req
:=
io
.
fromDq
(
index
(
fpReadPortSrc
(
i
))).
bits
.
psrc2
io
.
readState
(
3
*
i
+
2
).
req
:=
io
.
fromDq
(
index
(
fpReadPortSrc
(
i
))).
bits
.
psrc3
}
val
readPortIndex
=
Wire
(
Vec
(
exuParameters
.
FpExuCnt
,
UInt
(
2.
W
)))
fpStaticIndex
.
zipWithIndex
.
map
({
case
(
index
,
i
)
=>
readPortIndex
(
index
)
:=
i
.
U
})
fpDynamicIndex
.
zipWithIndex
.
map
({
case
(
index
,
i
)
=>
readPortIndex
(
index
)
:=
fpDynamicExuSrc
(
i
)})
for
(
i
<-
0
until
dpParams
.
IntDqDeqWidth
)
{
io
.
readState
(
3
*
i
).
req
:=
io
.
fromDq
(
i
).
bits
.
psrc1
io
.
readState
(
3
*
i
+
1
).
req
:=
io
.
fromDq
(
i
).
bits
.
psrc2
io
.
readState
(
3
*
i
+
2
).
req
:=
io
.
fromDq
(
i
).
bits
.
psrc3
}
/**
* Part 3: dispatch to reservation stations
*/
...
...
@@ -81,9 +84,9 @@ class Dispatch2Fp extends XSModule {
val
src1Ready
=
VecInit
((
0
until
4
).
map
(
i
=>
io
.
readState
(
i
*
3
).
resp
))
val
src2Ready
=
VecInit
((
0
until
4
).
map
(
i
=>
io
.
readState
(
i
*
3
+
1
).
resp
))
val
src3Ready
=
VecInit
((
0
until
4
).
map
(
i
=>
io
.
readState
(
i
*
3
+
2
).
resp
))
enq
.
bits
.
src1State
:=
src1Ready
(
readPortIndex
(
i
))
enq
.
bits
.
src2State
:=
src2Ready
(
readPortIndex
(
i
))
enq
.
bits
.
src3State
:=
src3Ready
(
readPortIndex
(
i
))
enq
.
bits
.
src1State
:=
src1Ready
(
indexVec
(
i
))
enq
.
bits
.
src2State
:=
src2Ready
(
indexVec
(
i
))
enq
.
bits
.
src3State
:=
src3Ready
(
indexVec
(
i
))
XSInfo
(
enq
.
fire
(),
p
"pc 0x${Hexadecimal(enq.bits.cf.pc)} with type ${enq.bits.ctrl.fuType} "
+
p
"srcState(${enq.bits.src1State} ${enq.bits.src2State} ${enq.bits.src3State}) "
+
...
...
src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala
浏览文件 @
ded91833
...
...
@@ -61,13 +61,16 @@ class Dispatch2Int extends XSModule {
val
index
=
WireInit
(
VecInit
(
intStaticMapped
(
i
)
+:
intDynamicMapped
))
io
.
readRf
(
2
*
i
)
:=
io
.
fromDq
(
index
(
intReadPortSrc
(
i
))).
bits
.
psrc1
io
.
readRf
(
2
*
i
+
1
)
:=
io
.
fromDq
(
index
(
intReadPortSrc
(
i
))).
bits
.
psrc2
io
.
readState
(
2
*
i
).
req
:=
io
.
fromDq
(
index
(
intReadPortSrc
(
i
))).
bits
.
psrc1
io
.
readState
(
2
*
i
+
1
).
req
:=
io
.
fromDq
(
index
(
intReadPortSrc
(
i
))).
bits
.
psrc2
}
val
readPortIndex
=
Wire
(
Vec
(
exuParameters
.
IntExuCnt
,
UInt
(
2.
W
)))
intStaticIndex
.
zipWithIndex
.
map
({
case
(
index
,
i
)
=>
readPortIndex
(
index
)
:=
i
.
U
})
intDynamicIndex
.
zipWithIndex
.
map
({
case
(
index
,
i
)
=>
readPortIndex
(
index
)
:=
intDynamicExuSrc
(
i
)})
for
(
i
<-
0
until
dpParams
.
IntDqDeqWidth
)
{
io
.
readState
(
2
*
i
).
req
:=
io
.
fromDq
(
i
).
bits
.
psrc1
io
.
readState
(
2
*
i
+
1
).
req
:=
io
.
fromDq
(
i
).
bits
.
psrc2
}
/**
* Part 3: dispatch to reservation stations
*/
...
...
@@ -89,8 +92,8 @@ class Dispatch2Int extends XSModule {
val
src1Ready
=
VecInit
((
0
until
4
).
map
(
i
=>
io
.
readState
(
i
*
2
).
resp
))
val
src2Ready
=
VecInit
((
0
until
4
).
map
(
i
=>
io
.
readState
(
i
*
2
+
1
).
resp
))
enq
.
bits
.
src1State
:=
src1Ready
(
readPortIndex
(
i
))
enq
.
bits
.
src2State
:=
src2Ready
(
readPortIndex
(
i
))
enq
.
bits
.
src1State
:=
src1Ready
(
indexVec
(
i
))
enq
.
bits
.
src2State
:=
src2Ready
(
indexVec
(
i
))
enq
.
bits
.
src3State
:=
DontCare
XSInfo
(
enq
.
fire
(),
p
"pc 0x${Hexadecimal(enq.bits.cf.pc)} with type ${enq.bits.ctrl.fuType} "
+
...
...
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