Regfile, BusyTable: do not handle writeback now

src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala

@@ -515,13 +515,16 @@ class ReservationStationData
   io.ctrl.srcUpdate(IssQueSize).zipWithIndex.map{ case (h, i) => // h: port, i: 0~srcNum-1
     val (bpHit, bpHitReg, bpData) = bypass(srcSeq(i), srcTypeSeq(i), enqCtrl.valid)
     val (wuHit, wuData)           = wakeup(srcSeq(i), srcTypeSeq(i), enqCtrl.valid)
+    val wuHitReg = RegNext(wuHit)
+    val wuDataReg = RegNext(wuData)
     when (bpHitReg) { dataWrite(enqPtrReg, i, bpData) }
-    when (RegNext(wuHit)) { dataWrite(enqPtrReg, i, RegNext(wuData)) }
+    when (wuHitReg) { dataWrite(enqPtrReg, i, wuDataReg) }
     h := bpHit || wuHit
     // NOTE: enq bp is done here
     XSDebug(bpHit, p"EnqBPHit: (${i.U})\n")
+    XSDebug(wuHit, p"EnqWuHit: (${Binary(io.ctrl.srcUpdate(iqSize).asUInt())})\n")
     XSDebug(bpHitReg, p"EnqBPHitData: (${i.U}) data:${Hexadecimal(bpData)}\n")
-    XSDebug(wuHit, p"EnqWbHit: (${i.U}) data:${Hexadecimal(wuData)} data will be writen into data at next cycle\n")
+    XSDebug(wuHitReg, p"EnqWuHitData: (${i.U}) data:${Hexadecimal(wuDataReg)}\n")
   }
   if (nonBlocked) { io.ctrl.fuReady := true.B }
   else { io.ctrl.fuReady := io.deq.ready }

src/main/scala/xiangshan/backend/regfile/Regfile.scala

@@ -35,9 +35,8 @@ class Regfile
   if (!useBlackBox) {
     val mem = Mem(NRPhyRegs, UInt(len.W))
     for (r <- io.readPorts) {
-      val raddr_reg = RegNext(r.addr)
-      val rdata = if (hasZero) Mux(raddr_reg === 0.U, 0.U, mem(raddr_reg)) else mem(raddr_reg)
-      r.data := rdata
+      val rdata = if (hasZero) Mux(r.addr === 0.U, 0.U, mem(r.addr)) else mem(r.addr)
+      r.data := RegNext(rdata)
     }
     for (w <- io.writePorts) {
       when(w.wen) {

src/main/scala/xiangshan/backend/rename/BusyTable.scala

@@ -30,7 +30,7 @@ class BusyTable(numReadPorts: Int, numWritePorts: Int) extends XSModule {
   val tableAfterAlloc = tableAfterWb | allocMask
 
   for((raddr, rdy) <- io.rfReadAddr.zip(io.pregRdy)){
-    rdy := !tableAfterWb(raddr)
+    rdy := !table(raddr)
   }
 
   table := tableAfterAlloc