fence: timing optimization by changing fsm to avoid sbEmpty usage

src/main/scala/xiangshan/backend/fu/Fence.scala

@@ -20,41 +20,51 @@ class Fence extends FunctionUnit{ // TODO: check it
   val fencei = IO(Output(Bool()))
   val toSbuffer = IO(new FenceToSbuffer)
 
-  val (valid, src1, uop, func, lsrc1, lsrc2) = (
+  val (valid, src1) = (
     io.in.valid,
-    io.in.bits.src(0),
-    io.in.bits.uop,
-    io.in.bits.uop.ctrl.fuOpType,
-    io.in.bits.uop.ctrl.lsrc1,
-    io.in.bits.uop.ctrl.lsrc2
+    io.in.bits.src(0)
   )
 
-  val s_sb :: s_tlb :: s_icache :: s_none :: Nil = Enum(4)
-  val state = RegInit(s_sb)
+  val s_idle :: s_wait :: s_tlb :: s_icache :: s_fence :: Nil = Enum(5)
+  val state = RegInit(s_idle)
+  /* fsm
+   * s_idle    : init state, send sbflush
+   * s_wait  : send sbflush, wait for sbEmpty
+   * s_tlb   : flush tlb, just hold one cycle
+   * s_icache: flush icache, just hold one cycle
+   * s_fence : do nothing, for timing optimiaztion
+   */
 
   val sbuffer = toSbuffer.flushSb
   val sbEmpty = toSbuffer.sbIsEmpty
+  val uop = RegEnable(io.in.bits.uop, io.in.fire())
+  val func = uop.ctrl.fuOpType
+  val lsrc1 = uop.ctrl.lsrc1
+  val lsrc2 = uop.ctrl.lsrc2
 
   // NOTE: icache & tlb & sbuffer must receive flush signal at any time
-  sbuffer      := valid && state === s_sb && !sbEmpty
-  fencei       := (state === s_icache && sbEmpty) || (state === s_sb && valid && sbEmpty && func === FenceOpType.fencei)
-  sfence.valid := (state === s_tlb && sbEmpty) || (state === s_sb && valid && sbEmpty && func === FenceOpType.sfence)
-  sfence.bits.rs1  := Mux(state === s_sb, lsrc1 === 0.U, RegEnable(lsrc1 === 0.U, io.in.fire()))
-  sfence.bits.rs2  := Mux(state === s_sb, lsrc2 === 0.U, RegEnable(lsrc2 === 0.U, io.in.fire()))
-  sfence.bits.addr := Mux(state === s_sb, src1,          RegEnable(src1, io.in.fire()))
-
-  when (state === s_sb && valid && func === FenceOpType.fencei && !sbEmpty) { state := s_icache }
-  when (state === s_sb && valid && func === FenceOpType.sfence && !sbEmpty) { state := s_tlb }
-  when (state === s_sb && valid && func === FenceOpType.fence  && !sbEmpty) { state := s_none }
-  when (state =/= s_sb && sbEmpty) { state := s_sb }
+  sbuffer      := state === s_wait
+  fencei       := state === s_icache
+  sfence.valid := state === s_tlb
+  sfence.bits.rs1  := lsrc1 === 0.U
+  sfence.bits.rs2  := lsrc2 === 0.U
+  sfence.bits.addr := RegEnable(src1, io.in.fire())
 
-  assert(!(io.out.valid && io.out.bits.uop.ctrl.rfWen))
-  io.in.ready := state === s_sb
-  io.out.valid := (state =/= s_sb && sbEmpty) || (state === s_sb && sbEmpty && valid)
+  when (state === s_idle && valid) { state := s_wait }
+  when (state === s_wait && func === FenceOpType.fencei && sbEmpty) { state := s_icache }
+  when (state === s_wait && func === FenceOpType.sfence && sbEmpty) { state := s_tlb }
+  when (state === s_wait && func === FenceOpType.fence  && sbEmpty) { state := s_fence }
+  when (state =/= s_idle && state =/= s_wait) { state := s_idle }
+
+  io.in.ready := state === s_idle
+  io.out.valid := state =/= s_idle && state =/= s_wait
   io.out.bits.data := DontCare
-  io.out.bits.uop := Mux(state === s_sb, uop, RegEnable(uop, io.in.fire()))
+  io.out.bits.uop := uop
 
-  assert(!(valid || state =/= s_sb) || io.out.ready) // NOTE: fence instr must be the first(only one) instr, so io.out.ready must be true
+  XSDebug(valid, p"In(${io.in.valid} ${io.in.ready}) state:${state} Inpc:0x${Hexadecimal(io.in.bits.uop.cf.pc)} InroqIdx:${io.in.bits.uop.roqIdx}\n")
+  XSDebug(state =/= s_idle, p"state:${state} sbuffer(flush:${sbuffer} empty:${sbEmpty}) fencei:${fencei} sfence:${sfence}\n")
+  XSDebug(io.out.valid, p" Out(${io.out.valid} ${io.out.ready}) state:${state} Outpc:0x${Hexadecimal(io.out.bits.uop.cf.pc)} OutroqIdx:${io.out.bits.uop.roqIdx}\n")
 
-  XSDebug(valid || state=/=s_sb || io.out.valid, p"In(${io.in.valid} ${io.in.ready}) Out(${io.out.valid} ${io.out.ready}) state:${state} sbuffer(flush:${sbuffer} empty:${sbEmpty}) fencei:${fencei} sfence:${sfence} Inpc:0x${Hexadecimal(io.in.bits.uop.cf.pc)} InroqIdx:${io.in.bits.uop.roqIdx} Outpc:0x${Hexadecimal(io.out.bits.uop.cf.pc)} OutroqIdx:${io.out.bits.uop.roqIdx}\n")
+  assert(!(io.out.valid && io.out.bits.uop.ctrl.rfWen))
+  assert(!io.out.valid || io.out.ready, "when fence is out valid, out ready should always be true")
 }
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