exu,div: set io.in.valid though the instruction is flushed

src/main/scala/xiangshan/backend/exu/Exu.scala

@@ -100,7 +100,7 @@ abstract class Exu(val config: ExuConfig) extends XSModule {
     val src2 = in.bits.src2
     val src3 = in.bits.src3
 
-    fu.io.in.valid := in.valid && sel && !in.bits.uop.roqIdx.needFlush(io.redirect)
+    fu.io.in.valid := in.valid && sel
     fu.io.in.bits.uop := in.bits.uop
     fu.io.in.bits.src.foreach(_ <> DontCare)
     if (fuCfg.srcCnt > 0) {

src/main/scala/xiangshan/backend/fu/Radix2Divider.scala

@@ -85,6 +85,6 @@ class Radix2Divider(len: Int) extends AbstractDivider(len) {
   io.out.bits.data := Mux(ctrlReg.isW, SignExt(res(31,0),xlen), res)
   io.out.bits.uop := uopReg
 
-  io.out.valid := state === s_finish && !kill
+  io.out.valid := state === s_finish
   io.in.ready := state === s_idle
 }
\ No newline at end of file

src/main/scala/xiangshan/backend/fu/SRT4Divider.scala

@@ -220,7 +220,7 @@ class SRT4Divider(len: Int) extends AbstractDivider(len) {
   )
 
   io.in.ready := state===s_idle
-  io.out.valid := state===s_finish && !kill
+  io.out.valid := state===s_finish
   io.out.bits.data := Mux(ctrlReg.isW,
     SignExt(res(31, 0), len),
     res