ExcitingUtils: a wrapper of chisel's BoringUtils

ExcitingUtils provides some API to display and check connections between source and sinks

Remove xiangshan.utils

Add csr read and write instructions

Log: turn off log at chisel level when we don't need it

Lsu: retired store should not be canceled by redirect

disable l2cache/l2prefetcher, support remote run-emu

xiangshan,utils,LogUtils: optimize wires

* Remove assert(), since they can be done at cpp files if needed
* Calculate `(GTimer() >= disp_begin) && (GTimer() <= disp_end)` at the
  top level module only once, and wire such bool signal to where XSLog()
  is called. This can reduce the number of instances of counter created
  while GTimer() is callled.
* Remove xsLogLevel. It seems meaningless, since we either need all logs
  for debugging, or no logs for running tests only.
* With the above optimizion, running microbench with test input spends
  120s on 9900k with log completely disabled (comment out the log code),
  but only spends 147s on 9900k with log enabled.

Adapt device address

IssueQueue: enable alu's bypass and all issueQueue recv bypass(may change it later)

dispatch2: allow configurations via exuConfig