Merge remote-tracking branch 'origin/master' into csr

.github/workflows/emu.yml

@@ -36,7 +36,7 @@ jobs:
           echo $AM_HOME
           echo $NEMU_HOME
           echo $NOOP_HOME
-          make -C $AM_HOME/tests/cputest/ ARCH=riscv64-noop V=OFF AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME run
+          make -C $AM_HOME/tests/cputest/ ARCH=riscv64-noop B=0 E=0 AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME run
 
   riscv-tests:
     runs-on: self-hosted
@@ -53,4 +53,4 @@ jobs:
           echo $NEMU_HOME
           echo $NOOP_HOME
           echo $RVTEST_HOME
-          make -C $RVTEST_HOME/isa/ SUITES+=rv64ui SUITES+=rv64um V=OFF NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME noop_run
+          make -C $RVTEST_HOME/isa/ SUITES+=rv64ui SUITES+=rv64um B=0 E=0 NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME noop_run

Makefile

@@ -11,7 +11,8 @@ IMAGE ?= temp
 
 # remote machine with high frequency to speedup verilog generation
 REMOTE ?= localhost
-REMOTE_PREFIX ?= /nfs/24/$(abspath .)/
+REMOTE_PREFIX ?= /nfs/24
+REMOTE_PRJ_HOME = $(REMOTE_PREFIX)/$(abspath .)/
 
 .DEFAULT_GOAL = verilog
 
@@ -48,7 +49,7 @@ $(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
 ifeq ($(REMOTE),localhost)
 	mill chiselModule.test.runMain $(SIMTOP) -X verilog -td $(@D) --output-file $(@F)
 else
-	ssh $(REMOTE) "cd $(REMOTE_PREFIX) && mill chiselModule.test.runMain $(SIMTOP) -X verilog -td $(@D) --output-file $(@F)"
+	ssh $(REMOTE) "cd $(REMOTE_PRJ_HOME) && mill chiselModule.test.runMain $(SIMTOP) -X verilog -td $(@D) --output-file $(@F)"
 endif
 
 
@@ -103,13 +104,12 @@ SEED = -s $(shell seq 1 10000 | shuf | head -n 1)
 # use 'emu -h' to see more details
 B ?= 0
 E ?= -1
-V ?= ALL
 
 emu: $(EMU)
 ifeq ($(REMOTE),localhost)
-	@$(EMU) -i $(IMAGE) $(SEED) -b $(B) -e $(E) -v $(V)
+	@$(EMU) -i $(IMAGE) $(SEED) -b $(B) -e $(E)
 else
-	ssh $(REMOTE) "cd $(REMOTE_PREFIX) && $(EMU) -i $(IMAGE) $(SEED) -b $(B) -e $(E) -v $(V)"
+	ssh $(REMOTE) "cd $(REMOTE_PRJ_HOME) && $(EMU) -i $(REMOTE_PREFIX)/$(IMAGE) $(SEED) -b $(B) -e $(E)"
 endif
 
 cache:

debug/Makefile

@@ -2,17 +2,12 @@ ARCH = ARCH=riscv64-noop
 NANOS_HOME ?= $(AM_HOME)/../nanos-lite
 SINGLETEST = ALL=min3
 
-B ?= 0
-E ?= -1
-V ?= ALL
-EMU_ARGS = B=$(B) E=$(E) V=$(V)
-
 # ------------------------------------------------------------------
 # bulid CPU and run dummy test
 # ------------------------------------------------------------------
 
 cpu:
-	$(MAKE) -C $(AM_HOME)/tests/cputest $(ARCH) ALL=dummy $(EMU_ARGS) run
+	$(MAKE) -C $(AM_HOME)/tests/cputest $(ARCH) ALL=dummy run
 
 # ------------------------------------------------------------------
 # run different test sets

src/main/scala/system/SoC.scala

@@ -10,9 +10,9 @@ import chisel3.util.experimental.BoringUtils
 import xiangshan.{XSConfig, XSCore}
 
 trait HasSoCParameter {
-  val EnableILA = true
-  val HasL2cache = true
-  val HasPrefetch = true
+  val EnableILA = false
+  val HasL2cache = false
+  val HasPrefetch = false
 }
 
 class ILABundle extends Bundle {}
@@ -79,4 +79,4 @@ class XSSoc(implicit val p: XSConfig) extends Module with HasSoCParameter {
   val meipSync = RegNext(RegNext(io.meip))
   BoringUtils.addSource(mtipSync, "mtip")
   BoringUtils.addSource(meipSync, "meip")
-}
\ No newline at end of file
+}

src/main/scala/xiangshan/backend/exu/LsExeUnit.scala

@@ -182,8 +182,8 @@ class LsExeUnit extends Exu(Exu.lsuExeUnitCfg){
   val expRedirect = io.redirect.valid && io.redirect.bits.isException
   val brRedirect = io.redirect.valid && !io.redirect.bits.isException
   for(i <- 0 until 8){
-    when(expRedirect || brRedirect && stqData(i).brTag.needBrFlush(io.redirect.bits.brTag) && stqValid(i)){
-      stqValid(i) := false.B
+    when((i.U >= stqCommited) && (expRedirect || brRedirect && stqData(stqPtr(i)).brTag.needBrFlush(io.redirect.bits.brTag) && stqValid(stqPtr(i)))){
+      stqValid(stqPtr(i)) := false.B
     }
     XSDebug("sptrtable: id %d ptr %d valid  %d\n", i.U, stqPtr(i), stqValid(stqPtr(i)))
   }

src/main/scala/xiangshan/utils/LogUtils.scala

@@ -17,27 +17,13 @@ object XSLogLevel extends Enumeration {
 }
 
 object XSLog {
-
-  def displayLog: Bool = {
-    val disp_begin, disp_end = WireInit(0.U(64.W))
-    BoringUtils.addSink(disp_begin, "DISPLAY_LOG_START")
-    BoringUtils.addSink(disp_end, "DISPLAY_LOG_END")
-    assert(disp_begin <= disp_end)
-    (GTimer() >= disp_begin) && (GTimer() <= disp_end)
-  }
-
-  def xsLogLevel: UInt = {
-    val log_level = WireInit(0.U(64.W))
-    BoringUtils.addSink(log_level, "DISPLAY_LOG_LEVEL")
-    assert(log_level < XSLogLevel.maxId.U)
-    log_level
-  }
-
   def apply(debugLevel: XSLogLevel)
            (prefix: Boolean, cond: Bool, pable: Printable)
            (implicit name: String): Any = {
     val commonInfo = p"[$debugLevel][time=${GTimer()}] $name: "
-    when (debugLevel.id.U >= xsLogLevel && cond && displayLog) {
+    val logEnable = WireInit(false.B)
+    BoringUtils.addSink(logEnable, "DISPLAY_LOG_ENABLE")
+    when (cond && logEnable) {
       printf((if (prefix) commonInfo else p"") + pable)
     }
   }

src/test/csrc/common.h

@@ -42,18 +42,6 @@ void init_device(void);
 bool is_finished(void);
 int get_exit_code(void);
 
-// log
-enum {
-  LOG_ALL = 0,
-  LOG_DEBUG,
-  LOG_INFO,
-  LOG_WARN,
-  LOG_ERROR,
-  LOG_OFF
-};
-
-uint64_t getLogLevel(const char * str);
-
 void app_error(const char *fmt, ...);
 
 int monitor(void);

src/test/csrc/emu.h

@@ -26,7 +26,7 @@ class Emulator {
   // emu control variable
   uint32_t seed;
   uint64_t max_cycles, cycles;
-  uint64_t log_begin, log_end, log_level;
+  uint64_t log_begin, log_end;
 
   std::vector<const char *> parse_args(int argc, const char *argv[]);
 
@@ -71,7 +71,7 @@ class Emulator {
     image(nullptr),
     dut_ptr(new std::remove_reference<decltype(*dut_ptr)>::type),
     seed(0), max_cycles(-1), cycles(0),
-    log_begin(0), log_end(-1), log_level(LOG_ALL)
+    log_begin(0), log_end(-1)
   {
     // init emu
     auto args = parse_args(argc, argv);
@@ -84,7 +84,6 @@ class Emulator {
     // set log time range and log level
     dut_ptr->io_logCtrl_log_begin = log_begin;
     dut_ptr->io_logCtrl_log_end = log_end;
-    dut_ptr->io_logCtrl_log_level = log_level;
 
     // init ram
     extern void init_ram(const char *img);

src/test/csrc/log.cpp

-#include <cstdio>
-#include <cstring>
-#include "common.h"
-
-uint64_t getLogLevel(const char * str) {
-  if(!strcmp("ALL", str)){
-    return LOG_ALL;
-  } else if(!strcmp("DEBUG", str)){
-    return LOG_DEBUG;
-  } else if(!strcmp("INFO", str)){
-    return LOG_INFO;
-  } else if(!strcmp("WARN", str)){
-    return LOG_WARN;
-  } else if(!strcmp("ERROR", str)){
-    return LOG_ERROR;
-  } else if(!strcmp("OFF", str)){
-    return LOG_OFF;
-  } else {
-    printf("Unknown verbosity level!\n");
-    exit(-1);
-  }
-}

src/test/csrc/main.cpp

@@ -22,7 +22,6 @@ const struct option Emulator::long_options[] = {
   { "image",          1, NULL, 'i' },
   { "log-begin",      1, NULL, 'b' },
   { "log-end",        1, NULL, 'e' },
-  { "verbose",        1, NULL, 'v' },
   { "help",           0, NULL, 'h' },
   { 0,                0, NULL,  0  }
 };
@@ -35,7 +34,6 @@ void Emulator::print_help(const char *file) {
   printf("  -i, --image=FILE      run with this image file\n");
   printf("  -b, --log-begin=NUM   display log from NUM th cycle\n");
   printf("  -e, --log-end=NUM     stop display log at NUM th cycle\n");
-  printf("  -v, --verbose=STR     verbosity level, can be one of [ALL, DEBUG, INFO, WARN, ERROR]\n");
   printf("  -h, --help            print program help info\n");
   printf("\n");
 }
@@ -43,7 +41,7 @@ void Emulator::print_help(const char *file) {
 std::vector<const char *> Emulator::parse_args(int argc, const char *argv[]) {
   std::vector<const char *> args = { argv[0] };
   int o;
-  while ( (o = getopt_long(argc, const_cast<char *const*>(argv), "-s:C:hi:m:b:e:v:", long_options, NULL)) != -1) {
+  while ( (o = getopt_long(argc, const_cast<char *const*>(argv), "-s:C:hi:m:b:e:", long_options, NULL)) != -1) {
     switch (o) {
       case 's': 
         if(std::string(optarg) != "NO_SEED") {
@@ -58,7 +56,6 @@ std::vector<const char *> Emulator::parse_args(int argc, const char *argv[]) {
                 break;
       case 'b': log_begin = atoll(optarg);  break;
       case 'e': log_end = atoll(optarg); break;
-      case 'v': log_level = getLogLevel(optarg); break;
       default:
                 print_help(argv[0]);
                 exit(0);

src/test/scala/top/XSSim.scala

@@ -8,6 +8,7 @@ import bus.axi4._
 import chisel3.stage.ChiselGeneratorAnnotation
 import device.AXI4RAM
 import xiangshan._
+import utils._
 
 class DiffTestIO extends XSBundle {
   val r = Output(Vec(64, UInt(XLEN.W)))
@@ -81,14 +82,8 @@ class XSSimTop extends Module {
   BoringUtils.addSink(difftest.scause, "difftestScause")
   io.difftest := difftest
 
-  val log_begin, log_end, log_level = Wire(UInt(64.W))
-  log_begin := io.logCtrl.log_begin
-  log_end := io.logCtrl.log_end
-  log_level := io.logCtrl.log_level
-
-  BoringUtils.addSource(log_begin, "DISPLAY_LOG_START")
-  BoringUtils.addSource(log_end, "DISPLAY_LOG_END")
-  BoringUtils.addSource(log_level, "DISPLAY_LOG_LEVEL")
+  val logEnable = (GTimer() >= io.logCtrl.log_begin) && (GTimer() < io.logCtrl.log_end)
+  BoringUtils.addSource(logEnable, "DISPLAY_LOG_ENABLE")
 }
 
 object TestMain extends App {