dispatch2: allow configurations via exuConfig

src/main/scala/xiangshan/backend/Backend.scala

@@ -34,7 +34,7 @@ class Backend(implicit val p: XSConfig) extends XSModule
   val brq = Module(new Brq)
   val decBuf = Module(new DecodeBuffer)
   val rename = Module(new Rename)
-  val dispatch = Module(new Dispatch)
+  val dispatch = Module(new Dispatch(exeUnits.map(_.config)))
   val roq = Module(new Roq)
   val intRf = Module(new Regfile(
     numReadPorts = NRReadPorts,

src/main/scala/xiangshan/backend/dispatch/Dispatch.scala

@@ -3,10 +3,11 @@ package xiangshan.backend.dispatch
 import chisel3._
 import chisel3.util._
 import xiangshan._
+import xiangshan.backend.exu.ExuConfig
 import xiangshan.utils._
 import xiangshan.backend.regfile.RfReadPort
 
-class Dispatch extends XSModule {
+class Dispatch(exuCfg: Array[ExuConfig]) extends XSModule {
   val io = IO(new Bundle() {
     val redirect = Flipped(ValidIO(new Redirect))
     // from rename
@@ -27,14 +28,14 @@ class Dispatch extends XSModule {
     val enqIQData = Vec(exuParameters.ExuCnt, ValidIO(new ExuInput))
   })
   // pipeline between rename and dispatch
-  val dispatch1 = Module(new Dispatch1())
+  val dispatch1 = Module(new Dispatch1)
   for (i <- 0 until RenameWidth) {
     PipelineConnect(io.fromRename(i), dispatch1.io.fromRename(i), dispatch1.io.recv(i), false.B)
   }
   val intDq = Module(new DispatchQueue(dp1Paremeters.IntDqSize, RenameWidth, IntDqDeqWidth, "IntDpQ"))
   val fpDq = Module(new DispatchQueue(dp1Paremeters.FpDqSize, RenameWidth, FpDqDeqWidth, "FpDpQ"))
   val lsDq = Module(new DispatchQueue(dp1Paremeters.LsDqSize, RenameWidth, LsDqDeqWidth, "LsDpQ"))
-  val dispatch2 = Module(new Dispatch2())
+  val dispatch2 = Module(new Dispatch2(exuCfg))
 
   dispatch1.io.redirect <> io.redirect
   dispatch1.io.toRoq <> io.toRoq

src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala

@@ -3,10 +3,11 @@ package xiangshan.backend.dispatch
 import chisel3._
 import chisel3.util._
 import xiangshan._
+import xiangshan.backend.exu.ExuConfig
 import xiangshan.backend.regfile.RfReadPort
 import xiangshan.utils.{XSDebug, XSInfo}
 
-class Dispatch2 extends XSModule{
+class Dispatch2(exuCfg: Array[ExuConfig]) extends XSModule{
   val io = IO(new Bundle() {
     // from dispatch queues
     val fromIntDq = Flipped(Vec(IntDqDeqWidth, DecoupledIO(new MicroOp)))
@@ -21,9 +22,9 @@ class Dispatch2 extends XSModule{
     val fpPregRdy = Vec(NRReadPorts, Input(Bool()))
 
     // enq Issue Queue
-    val numExist = Input(Vec(exuParameters.ExuCnt, UInt(log2Ceil(IssQueSize).W)))
-    val enqIQCtrl = Vec(exuParameters.ExuCnt, DecoupledIO(new MicroOp))
-    val enqIQData = Vec(exuParameters.ExuCnt, ValidIO(new ExuInput))
+    val numExist = Input(Vec(exuCfg.length, UInt(log2Ceil(IssQueSize).W)))
+    val enqIQCtrl = Vec(exuCfg.length, DecoupledIO(new MicroOp))
+    val enqIQData = Vec(exuCfg.length, ValidIO(new ExuInput))
   })
 
   for (i <- 0 until IntDqDeqWidth) {
@@ -40,7 +41,7 @@ class Dispatch2 extends XSModule{
   }
 
   // inst indexes for reservation stations
-  val rsIndexGen = Module(new DispatchGen())
+  val rsIndexGen = Module(new DispatchGen(exuCfg))
   rsIndexGen.io.fromIntDq := io.fromIntDq
   rsIndexGen.io.fromFpDq := io.fromFpDq
   rsIndexGen.io.fromLsDq := io.fromLsDq

src/main/scala/xiangshan/backend/dispatch/DispatchGen.scala

@@ -3,9 +3,10 @@ package xiangshan.backend.dispatch
 import chisel3._
 import chisel3.util._
 import xiangshan._
-import xiangshan.utils.{XSDebug}
+import xiangshan.backend.exu.ExuConfig
+import xiangshan.utils.XSDebug
 
-class DispatchGen extends XSModule {
+class DispatchGen(exuCfg: Array[ExuConfig]) extends XSModule {
   val io = IO(new Bundle() {
     // from dispatch queues
     val fromIntDq = Flipped(Vec(IntDqDeqWidth, ValidIO(new MicroOp)))
@@ -60,19 +61,29 @@ class DispatchGen extends XSModule {
     (0 until exunum).map(i => IQIndex(priority(i)))
   }
 
-  val bruIQIndex = genIQIndex(exuParameters.JmpCnt, IntDqDeqWidth, io.fromIntDq.map(_.bits.ctrl.fuType === FuType.jmp),
+  val intCanAcceptMatrix = io.fromIntDq.map(deq =>
+    (0 until exuParameters.IntExuCnt).map(i => exuCfg(i).canAccept(deq.bits.ctrl.fuType))
+  )
+  val fpCanAcceptMatrix = io.fromFpDq.map(deq =>
+    (exuParameters.IntExuCnt until exuParameters.IntExuCnt + exuParameters.FpExuCnt).map(i => exuCfg(i).canAccept(deq.bits.ctrl.fuType))
+  )
+  val lsCanAcceptMatrix = io.fromFpDq.map(deq =>
+    (exuParameters.IntExuCnt + exuParameters.FpExuCnt until exuParameters.ExuCnt).map(i => exuCfg(i).canAccept(deq.bits.ctrl.fuType))
+  )
+  val bruIQIndex = genIQIndex(exuParameters.JmpCnt, IntDqDeqWidth, intCanAcceptMatrix.map(_(0)),
     (0 until exuParameters.JmpCnt).map(i => io.numExist(i)))
-  val aluIQIndex = genIQIndex(exuParameters.AluCnt, IntDqDeqWidth, io.fromIntDq.map(_.bits.ctrl.fuType === FuType.alu),
+  val aluIQIndex = genIQIndex(exuParameters.AluCnt, IntDqDeqWidth, intCanAcceptMatrix.map(_(exuParameters.JmpCnt)),
     (0 until exuParameters.AluCnt).map(i => io.numExist(exuParameters.JmpCnt+i)))
-  val mulIQIndex = genIQIndex(exuParameters.MulCnt, IntDqDeqWidth, io.fromIntDq.map(_.bits.ctrl.fuType === FuType.mul),
+  val mulIQIndex = genIQIndex(exuParameters.MulCnt, IntDqDeqWidth, intCanAcceptMatrix.map(_(exuParameters.JmpCnt+exuParameters.AluCnt)),
     (0 until exuParameters.MulCnt).map(i => io.numExist(exuParameters.JmpCnt+exuParameters.AluCnt+i)))
-  val muldivIQIndex = genIQIndex(exuParameters.MduCnt, IntDqDeqWidth, io.fromIntDq.map(_.bits.ctrl.fuType === FuType.div),
+  val muldivIQIndex = genIQIndex(exuParameters.MduCnt, IntDqDeqWidth, io.fromIntDq.zipWithIndex.map({case (deq, i) =>
+    deq.bits.ctrl.fuType === FuType.div || (deq.bits.ctrl.fuType === FuType.mul && i.U > mulIQIndex(0)) }),
     (0 until exuParameters.MduCnt).map(i => io.numExist(exuParameters.JmpCnt+exuParameters.AluCnt+exuParameters.MulCnt+i)))
-  val fmacIQIndex = genIQIndex(exuParameters.FmacCnt, FpDqDeqWidth, io.fromFpDq.map(_.bits.ctrl.fuType === FuType.fmac),
+  val fmacIQIndex = genIQIndex(exuParameters.FmacCnt, FpDqDeqWidth, if (exuParameters.FmacCnt > 0) fpCanAcceptMatrix.map(_(0)) else Seq(),
     (0 until exuParameters.FmacCnt).map(i => io.numExist(exuParameters.IntExuCnt+i)))
-  val fmiscIQIndex = genIQIndex(exuParameters.FmiscCnt, FpDqDeqWidth, io.fromFpDq.map(_.bits.ctrl.fuType === FuType.fmisc),
+  val fmiscIQIndex = genIQIndex(exuParameters.FmiscCnt, FpDqDeqWidth, if (exuParameters.FmiscCnt > 0) fpCanAcceptMatrix.map(_(exuParameters.FmacCnt)) else Seq(),
     (0 until exuParameters.FmiscCnt).map(i => io.numExist(exuParameters.IntExuCnt+exuParameters.FmacCnt+i)))
-  val lduIQIndex = genIQIndex(exuParameters.LduCnt, LsDqDeqWidth, io.fromLsDq.map(_.bits.ctrl.fuType === FuType.ldu),
+  val lduIQIndex = genIQIndex(exuParameters.LduCnt, LsDqDeqWidth, lsCanAcceptMatrix.map(_(0)),
     (0 until exuParameters.LduCnt).map(i => io.numExist(exuParameters.IntExuCnt+exuParameters.FpExuCnt+i)))
 //  val stuIQIndex = genIQIndex(exuParameters.StuCnt, LsDqDeqWidth, io.fromLsDq.map(_.bits.ctrl.fuType === FuType.stu))
   val stuIQIndex = genIQIndex(exuParameters.StuCnt, LsDqDeqWidth, io.fromLsDq.map(deq => FuType.isMemExu(deq.bits.ctrl.fuType)),