Add CSR

src/main/scala/xiangshan/Bundle.scala

@@ -21,6 +21,7 @@ class CtrlFlow extends XSBundle {
   val intrVec = Vec(12, Bool())
   val isRVC = Bool()
   val isBr = Bool()
+  val crossPageIPFFix = Bool()
 }
 
 // Decode DecodeWidth insts at Decode Stage

src/main/scala/xiangshan/XSCore.scala

@@ -88,6 +88,12 @@ case class XSConfig
   EnableDebug: Boolean = true
 )
 
+object XSCoreConfig {
+  val config: XSConfig = XSConfig()
+}
+
+
+
 class XSCore(implicit val p: XSConfig) extends XSModule {
   val io = IO(new Bundle {
     val imem = new SimpleBusC

src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala

 package xiangshan.backend.exu
 
 import chisel3._
-import xiangshan.backend.fu.Jump
+import xiangshan.{ExuOutput, FuType, XSConfig}
+import xiangshan.backend.fu.{CSR, Jump}
 
-// NOTE: BRUOpType is at backend/package.scala
-
-// TODO: add csr
 class JmpExeUnit extends Exu(Exu.jmpExeUnitCfg) {
 
   val jmp = Module(new Jump)
 
-  io <> jmp.io
+  jmp.io.out.ready := io.out.ready
+  jmp.io.dmem <> DontCare
+  jmp.io.scommit := DontCare
+  jmp.io.redirect := io.redirect
+
+  lazy val p = XSConfig(
+    FPGAPlatform = false
+  )
+
+  val csr = Module(new CSR()(p))
+  csr.io.cfIn := io.in.bits.uop.cf
+  csr.io.fpu_csr := DontCare
+  csr.io.instrValid := DontCare
+  csr.io.imemMMU := DontCare
+  csr.io.dmemMMU := DontCare
+  csr.io.out.ready := io.out.ready
+  csr.io.in.bits.src3 := DontCare
+  val csrOut = csr.access(
+    valid = io.in.valid && io.in.bits.uop.ctrl.fuType===FuType.csr,
+    src1 = io.in.bits.src1,
+    src2 = io.in.bits.src2,
+    func = io.in.bits.uop.ctrl.fuOpType
+  )
+
+  val csrExuOut = Wire(new ExuOutput)
+  csrExuOut.uop := io.in.bits.uop
+  csrExuOut.data := csrOut
+  csrExuOut.redirectValid := false.B
+  csrExuOut.redirect := DontCare
+  csrExuOut.debug := DontCare
+
+  jmp.io.in.bits := io.in.bits
+  jmp.io.in.valid := io.in.valid && io.in.bits.uop.ctrl.fuType===FuType.jmp
 
+  io.in.ready := io.out.ready
+  io.out.bits := Mux(jmp.io.in.valid, jmp.io.out.bits, csrExuOut)
+  io.out.valid := io.in.valid
 }
\ No newline at end of file

src/main/scala/xiangshan/backend/fu/FunctionUnit.scala

@@ -23,9 +23,23 @@ case class FuConfig
   hasRedirect: Boolean
 )
 
+class FunctionUnitIO extends XSBundle {
+  val in = Flipped(Decoupled(new Bundle {
+    val src1 = Output(UInt(XLEN.W))
+    val src2 = Output(UInt(XLEN.W))
+    val src3 = Output(UInt(XLEN.W))
+    val func = Output(FuOpType())
+  }))
+  val out = Decoupled(Output(UInt(XLEN.W)))
+}
+
 abstract class FunctionUnit(cfg: FuConfig) extends XSModule
 
 object FunctionUnit {
+
+  val csrCfg =
+    FuConfig(FuType.csr, 1, 0, writeIntRf = true, writeFpRf = false, hasRedirect = false)
+
   val jmpCfg =
     FuConfig(FuType.jmp, 1, 0, writeIntRf = true, writeFpRf = false, hasRedirect = true)
 

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -251,16 +251,6 @@ class Roq(implicit val p: XSConfig) extends XSModule {
     BoringUtils.addSource(RegNext(0.U), "difftestIntrNO")
     //TODO: skip insts that commited in the same cycle ahead of exception
 
-    //csr debug signals
-    val ModeM = WireInit(0x3.U)
-    BoringUtils.addSource(ModeM, "difftestMode")
-    BoringUtils.addSource(emptyCsr, "difftestMstatus")
-    BoringUtils.addSource(emptyCsr, "difftestSstatus") 
-    BoringUtils.addSource(emptyCsr, "difftestMepc")
-    BoringUtils.addSource(emptyCsr, "difftestSepc")
-    BoringUtils.addSource(emptyCsr, "difftestMcause")
-    BoringUtils.addSource(emptyCsr, "difftestScause")
-
     class Monitor extends BlackBox {
       val io = IO(new Bundle {
         val clk = Input(Clock())

src/main/scala/xiangshan/frontend/Ibuffer.scala

@@ -18,6 +18,7 @@ class Ibuffer extends XSModule {
     io.out(i).bits.exceptionVec := DontCare
     io.out(i).bits.intrVec := DontCare
     io.out(i).bits.isBr := DontCare
+    io.out(i).bits.crossPageIPFFix := DontCare
   }
 
   //mask initial