未验证 提交 11665d75 编写于 作者: L ljw 提交者: GitHub

Merge pull request #119 from RISCVERS/update-soc-addr

Adapt device address
......@@ -64,7 +64,7 @@ class XSSoc(implicit val p: XSConfig) extends Module with HasSoCParameter {
val addrSpace = List(
(0x40000000L, 0x08000000L), // external devices
(0x48000000L, 0x00010000L) // CLINT
(0x38000000L, 0x00010000L) // CLINT
)
val mmioXbar = Module(new SimpleBusCrossbar1toN(addrSpace))
mmioXbar.io.in <> xsCore.io.mmio
......
......@@ -88,6 +88,22 @@ case class XSConfig
EnableDebug: Boolean = true
)
object AddressSpace extends HasXSParameter {
// (start, size)
// address out of MMIO will be considered as DRAM
def mmio = List(
(0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC
(0x40000000L, 0x40000000L) // external devices
)
def isMMIO(addr: UInt): Bool = mmio.map(range => {
require(isPow2(range._2))
val bits = log2Up(range._2)
(addr ^ range._1.U)(PAddrBits-1, bits) === 0.U
}).reduce(_ || _)
}
class XSCore(implicit val p: XSConfig) extends XSModule {
val io = IO(new Bundle {
val imem = new SimpleBusC
......
......@@ -4,16 +4,11 @@ import chisel3._
import chisel3.util._
import chisel3.util.experimental.BoringUtils
import xiangshan._
import xiangshan.FuType._
import xiangshan.utils._
import xiangshan.backend.regfile.RfWritePort
import utils._
import bus.simplebus._
import noop.AddressSpace
import xiangshan.AddressSpace
import xiangshan.backend._
import xiangshan.backend.brq.BrqPtr
import xiangshan.backend.fu.FunctionUnit._
class StoreQueueEntry extends XSBundle{
......
......@@ -13,8 +13,8 @@ class SimMMIO extends Module {
val devAddrSpace = List(
(0x40600000L, 0x10L), // uart
(0x41000000L, 0x400000L), // vmem
(0x40800000L, 0x8L), // vga ctrl
(0x50000000L, 0x400000L), // vmem
(0x40001000L, 0x8L), // vga ctrl
(0x40000000L, 0x1000L), // flash
(0x40002000L, 0x1000L) // dummy sdcard
)
......
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