omap5.dtsi 27.5 KB
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/*
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 * Based on "omap4.dtsi"
 */

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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/omap.h>
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/ {
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	#address-cells = <2>;
	#size-cells = <2>;
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	compatible = "ti,omap5";
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	interrupt-parent = <&wakeupgen>;
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	chosen { };
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	aliases {
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		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		i2c4 = &i2c5;
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		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
	};

	cpus {
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		#address-cells = <1>;
		#size-cells = <0>;

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		cpu0: cpu@0 {
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			device_type = "cpu";
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			compatible = "arm,cortex-a15";
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			reg = <0x0>;
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			operating-points = <
				/* kHz    uV */
				1000000 1060000
				1500000 1250000
			>;
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			clocks = <&dpll_mpu_ck>;
			clock-names = "cpu";

			clock-latency = <300000>; /* From omap-cpufreq driver */

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			/* cooling options */
			cooling-min-level = <0>;
			cooling-max-level = <2>;
			#cooling-cells = <2>; /* min followed by max */
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		};
		cpu@1 {
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			device_type = "cpu";
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			compatible = "arm,cortex-a15";
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			reg = <0x1>;
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		};
	};

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	thermal-zones {
		#include "omap4-cpu-thermal.dtsi"
		#include "omap5-gpu-thermal.dtsi"
		#include "omap5-core-thermal.dtsi"
	};

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	timer {
		compatible = "arm,armv7-timer";
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		/* PPI secure/nonsecure IRQ */
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
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		interrupt-parent = <&gic>;
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	};

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	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
	};

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	gic: interrupt-controller@48211000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
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		reg = <0 0x48211000 0 0x1000>,
		      <0 0x48212000 0 0x1000>,
		      <0 0x48214000 0 0x2000>,
		      <0 0x48216000 0 0x2000>;
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		interrupt-parent = <&gic>;
	};

	wakeupgen: interrupt-controller@48281000 {
		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
		interrupt-controller;
		#interrupt-cells = <3>;
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		reg = <0 0x48281000 0 0x1000>;
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		interrupt-parent = <&gic>;
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	};

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	/*
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	 * The soc node represents the soc top level view. It is used for IPs
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	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
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			compatible = "ti,omap4-mpu";
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			ti,hwmods = "mpu";
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			sram = <&ocmcram>;
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		};
	};

	/*
	 * XXX: Use a flat representation of the OMAP3 interconnect.
	 * The real OMAP interconnect network is quite complex.
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	 * Since it will not bring real advantage to represent that in DT for
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	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
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		compatible = "ti,omap5-l3-noc", "simple-bus";
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		#address-cells = <1>;
		#size-cells = <1>;
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		ranges = <0 0 0 0xc0000000>;
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		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
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		reg = <0 0x44000000 0 0x2000>,
		      <0 0x44800000 0 0x3000>,
		      <0 0x45000000 0 0x4000>;
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		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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		l4_cfg: l4@4a000000 {
			compatible = "ti,omap5-l4-cfg", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x4a000000 0x22a000>;
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			scm_core: scm@2000 {
				compatible = "ti,omap5-scm-core", "simple-bus";
				reg = <0x2000 0x1000>;
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				#address-cells = <1>;
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				#size-cells = <1>;
				ranges = <0 0x2000 0x800>;

				scm_conf: scm_conf@0 {
					compatible = "syscon";
					reg = <0x0 0x800>;
					#address-cells = <1>;
					#size-cells = <1>;
				};
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			};

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			scm_padconf_core: scm@2800 {
				compatible = "ti,omap5-scm-padconf-core",
					     "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x2800 0x800>;

				omap5_pmx_core: pinmux@40 {
					compatible = "ti,omap5-padconf",
						     "pinctrl-single";
					reg = <0x40 0x01b6>;
					#address-cells = <1>;
					#size-cells = <0>;
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					#pinctrl-cells = <1>;
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					#interrupt-cells = <1>;
					interrupt-controller;
					pinctrl-single,register-width = <16>;
					pinctrl-single,function-mask = <0x7fff>;
				};

				omap5_padconf_global: omap5_padconf_global@5a0 {
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					compatible = "syscon",
						     "simple-bus";
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					reg = <0x5a0 0xec>;
					#address-cells = <1>;
					#size-cells = <1>;
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					ranges = <0 0x5a0 0xec>;
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					pbias_regulator: pbias_regulator@60 {
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						compatible = "ti,pbias-omap5", "ti,pbias-omap";
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						reg = <0x60 0x4>;
						syscon = <&omap5_padconf_global>;
						pbias_mmc_reg: pbias_mmc_omap5 {
							regulator-name = "pbias_mmc_omap5";
							regulator-min-microvolt = <1800000>;
							regulator-max-microvolt = <3000000>;
						};
					};
				};
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			};

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			cm_core_aon: cm_core_aon@4000 {
				compatible = "ti,omap5-cm-core-aon";
				reg = <0x4000 0x2000>;
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				cm_core_aon_clocks: clocks {
					#address-cells = <1>;
					#size-cells = <0>;
				};
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				cm_core_aon_clockdomains: clockdomains {
				};
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			};

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			cm_core: cm_core@8000 {
				compatible = "ti,omap5-cm-core";
				reg = <0x8000 0x3000>;
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				cm_core_clocks: clocks {
					#address-cells = <1>;
					#size-cells = <0>;
				};
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				cm_core_clockdomains: clockdomains {
				};
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			};
		};

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		l4_wkup: l4@4ae00000 {
			compatible = "ti,omap5-l4-wkup", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x4ae00000 0x2b000>;
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			counter32k: counter@4000 {
				compatible = "ti,omap-counter32k";
				reg = <0x4000 0x40>;
				ti,hwmods = "counter_32k";
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			};

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			prm: prm@6000 {
				compatible = "ti,omap5-prm";
				reg = <0x6000 0x3000>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

				prm_clocks: clocks {
					#address-cells = <1>;
					#size-cells = <0>;
				};

				prm_clockdomains: clockdomains {
				};
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			};

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			scrm: scrm@a000 {
				compatible = "ti,omap5-scrm";
				reg = <0xa000 0x2000>;
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				scrm_clocks: clocks {
					#address-cells = <1>;
					#size-cells = <0>;
				};
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				scrm_clockdomains: clockdomains {
				};
			};
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			omap5_pmx_wkup: pinmux@c840 {
				compatible = "ti,omap5-padconf",
					     "pinctrl-single";
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				reg = <0xc840 0x003c>;
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				#address-cells = <1>;
				#size-cells = <0>;
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				#pinctrl-cells = <1>;
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				#interrupt-cells = <1>;
				interrupt-controller;
				pinctrl-single,register-width = <16>;
				pinctrl-single,function-mask = <0x7fff>;
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			};
		};

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		ocmcram: ocmcram@40300000 {
			compatible = "mmio-sram";
			reg = <0x40300000 0x20000>; /* 128k */
		};

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		sdma: dma-controller@4a056000 {
			compatible = "ti,omap4430-sdma";
			reg = <0x4a056000 0x1000>;
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			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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			#dma-cells = <1>;
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			dma-channels = <32>;
			dma-requests = <127>;
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		};

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		gpio1: gpio@4ae10000 {
			compatible = "ti,omap4-gpio";
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			reg = <0x4ae10000 0x200>;
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			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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			ti,hwmods = "gpio1";
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			ti,gpio-always-on;
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			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
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			#interrupt-cells = <2>;
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		};

		gpio2: gpio@48055000 {
			compatible = "ti,omap4-gpio";
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			reg = <0x48055000 0x200>;
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			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
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			#interrupt-cells = <2>;
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		};

		gpio3: gpio@48057000 {
			compatible = "ti,omap4-gpio";
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			reg = <0x48057000 0x200>;
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			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
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			#interrupt-cells = <2>;
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		};

		gpio4: gpio@48059000 {
			compatible = "ti,omap4-gpio";
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			reg = <0x48059000 0x200>;
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			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
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			#interrupt-cells = <2>;
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		};

		gpio5: gpio@4805b000 {
			compatible = "ti,omap4-gpio";
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			reg = <0x4805b000 0x200>;
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			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
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			#interrupt-cells = <2>;
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		};

		gpio6: gpio@4805d000 {
			compatible = "ti,omap4-gpio";
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			reg = <0x4805d000 0x200>;
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			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
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			#interrupt-cells = <2>;
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		};

		gpio7: gpio@48051000 {
			compatible = "ti,omap4-gpio";
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			reg = <0x48051000 0x200>;
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			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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			ti,hwmods = "gpio7";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
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			#interrupt-cells = <2>;
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		};

		gpio8: gpio@48053000 {
			compatible = "ti,omap4-gpio";
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			reg = <0x48053000 0x200>;
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			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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			ti,hwmods = "gpio8";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
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			#interrupt-cells = <2>;
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		};

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		gpmc: gpmc@50000000 {
			compatible = "ti,omap4430-gpmc";
			reg = <0x50000000 0x1000>;
			#address-cells = <2>;
			#size-cells = <1>;
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			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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			dmas = <&sdma 4>;
			dma-names = "rxtx";
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			gpmc,num-cs = <8>;
			gpmc,num-waitpins = <4>;
			ti,hwmods = "gpmc";
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			clocks = <&l3_iclk_div>;
			clock-names = "fck";
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			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
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		};

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		i2c1: i2c@48070000 {
			compatible = "ti,omap4-i2c";
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			reg = <0x48070000 0x100>;
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			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
		};

		i2c2: i2c@48072000 {
			compatible = "ti,omap4-i2c";
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			reg = <0x48072000 0x100>;
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			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
		};

		i2c3: i2c@48060000 {
			compatible = "ti,omap4-i2c";
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			reg = <0x48060000 0x100>;
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			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
		};

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		i2c4: i2c@4807a000 {
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			compatible = "ti,omap4-i2c";
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			reg = <0x4807a000 0x100>;
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			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c4";
		};

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		i2c5: i2c@4807c000 {
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			compatible = "ti,omap4-i2c";
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			reg = <0x4807c000 0x100>;
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			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c5";
		};

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		hwspinlock: spinlock@4a0f6000 {
			compatible = "ti,omap4-hwspinlock";
			reg = <0x4a0f6000 0x1000>;
			ti,hwmods = "spinlock";
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			#hwlock-cells = <1>;
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		};

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		mcspi1: spi@48098000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x48098000 0x200>;
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			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi1";
			ti,spi-num-cs = <4>;
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			dmas = <&sdma 35>,
			       <&sdma 36>,
			       <&sdma 37>,
			       <&sdma 38>,
			       <&sdma 39>,
			       <&sdma 40>,
			       <&sdma 41>,
			       <&sdma 42>;
			dma-names = "tx0", "rx0", "tx1", "rx1",
				    "tx2", "rx2", "tx3", "rx3";
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		};

		mcspi2: spi@4809a000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x4809a000 0x200>;
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			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi2";
			ti,spi-num-cs = <2>;
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			dmas = <&sdma 43>,
			       <&sdma 44>,
			       <&sdma 45>,
			       <&sdma 46>;
			dma-names = "tx0", "rx0", "tx1", "rx1";
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		};

		mcspi3: spi@480b8000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480b8000 0x200>;
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			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi3";
			ti,spi-num-cs = <2>;
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			dmas = <&sdma 15>, <&sdma 16>;
			dma-names = "tx0", "rx0";
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		};

		mcspi4: spi@480ba000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480ba000 0x200>;
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			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi4";
			ti,spi-num-cs = <1>;
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			dmas = <&sdma 70>, <&sdma 71>;
			dma-names = "tx0", "rx0";
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		};

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		uart1: serial@4806a000 {
			compatible = "ti,omap4-uart";
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			reg = <0x4806a000 0x100>;
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			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
		};

		uart2: serial@4806c000 {
			compatible = "ti,omap4-uart";
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			reg = <0x4806c000 0x100>;
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			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
		};

		uart3: serial@48020000 {
			compatible = "ti,omap4-uart";
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			reg = <0x48020000 0x100>;
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			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
		};

		uart4: serial@4806e000 {
			compatible = "ti,omap4-uart";
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			reg = <0x4806e000 0x100>;
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			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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			ti,hwmods = "uart4";
			clock-frequency = <48000000>;
		};

		uart5: serial@48066000 {
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			compatible = "ti,omap4-uart";
			reg = <0x48066000 0x100>;
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			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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			ti,hwmods = "uart5";
			clock-frequency = <48000000>;
		};

		uart6: serial@48068000 {
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			compatible = "ti,omap4-uart";
			reg = <0x48068000 0x100>;
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			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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			ti,hwmods = "uart6";
			clock-frequency = <48000000>;
		};
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		mmc1: mmc@4809c000 {
			compatible = "ti,omap4-hsmmc";
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			reg = <0x4809c000 0x400>;
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			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
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			dmas = <&sdma 61>, <&sdma 62>;
			dma-names = "tx", "rx";
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			pbias-supply = <&pbias_mmc_reg>;
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		};

		mmc2: mmc@480b4000 {
			compatible = "ti,omap4-hsmmc";
581
			reg = <0x480b4000 0x400>;
582
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
583 584
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
585 586
			dmas = <&sdma 47>, <&sdma 48>;
			dma-names = "tx", "rx";
587 588 589 590
		};

		mmc3: mmc@480ad000 {
			compatible = "ti,omap4-hsmmc";
591
			reg = <0x480ad000 0x400>;
592
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
593 594
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
595 596
			dmas = <&sdma 77>, <&sdma 78>;
			dma-names = "tx", "rx";
597 598 599 600
		};

		mmc4: mmc@480d1000 {
			compatible = "ti,omap4-hsmmc";
601
			reg = <0x480d1000 0x400>;
602
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
603 604
			ti,hwmods = "mmc4";
			ti,needs-special-reset;
605 606
			dmas = <&sdma 57>, <&sdma 58>;
			dma-names = "tx", "rx";
607 608 609 610
		};

		mmc5: mmc@480d5000 {
			compatible = "ti,omap4-hsmmc";
611
			reg = <0x480d5000 0x400>;
612
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
613 614
			ti,hwmods = "mmc5";
			ti,needs-special-reset;
615 616
			dmas = <&sdma 59>, <&sdma 60>;
			dma-names = "tx", "rx";
617
		};
618

619 620 621 622 623
		mmu_dsp: mmu@4a066000 {
			compatible = "ti,omap4-iommu";
			reg = <0x4a066000 0x100>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmu_dsp";
624
			#iommu-cells = <0>;
625 626 627 628 629 630 631
		};

		mmu_ipu: mmu@55082000 {
			compatible = "ti,omap4-iommu";
			reg = <0x55082000 0x100>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmu_ipu";
632
			#iommu-cells = <0>;
633 634 635
			ti,iommu-bus-err-back;
		};

636 637
		keypad: keypad@4ae1c000 {
			compatible = "ti,omap4-keypad";
638
			reg = <0x4ae1c000 0x400>;
639 640
			ti,hwmods = "kbd";
		};
641

642 643 644 645 646
		mcpdm: mcpdm@40132000 {
			compatible = "ti,omap4-mcpdm";
			reg = <0x40132000 0x7f>, /* MPU private access */
			      <0x49032000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
647
			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
648
			ti,hwmods = "mcpdm";
649 650 651
			dmas = <&sdma 65>,
			       <&sdma 66>;
			dma-names = "up_link", "dn_link";
652
			status = "disabled";
653 654 655 656 657 658 659
		};

		dmic: dmic@4012e000 {
			compatible = "ti,omap4-dmic";
			reg = <0x4012e000 0x7f>, /* MPU private access */
			      <0x4902e000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
660
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
661
			ti,hwmods = "dmic";
662 663
			dmas = <&sdma 67>;
			dma-names = "up_link";
664
			status = "disabled";
665 666
		};

667 668 669 670 671
		mcbsp1: mcbsp@40122000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40122000 0xff>, /* MPU private access */
			      <0x49022000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
672
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
673 674 675
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp1";
676 677 678
			dmas = <&sdma 33>,
			       <&sdma 34>;
			dma-names = "tx", "rx";
679
			status = "disabled";
680 681 682 683 684 685 686
		};

		mcbsp2: mcbsp@40124000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40124000 0xff>, /* MPU private access */
			      <0x49024000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
687
			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
688 689 690
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp2";
691 692 693
			dmas = <&sdma 17>,
			       <&sdma 18>;
			dma-names = "tx", "rx";
694
			status = "disabled";
695 696 697 698 699 700 701
		};

		mcbsp3: mcbsp@40126000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40126000 0xff>, /* MPU private access */
			      <0x49026000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
702
			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
703 704 705
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp3";
706 707 708
			dmas = <&sdma 19>,
			       <&sdma 20>;
			dma-names = "tx", "rx";
709
			status = "disabled";
710
		};
711

712 713 714 715 716
		mailbox: mailbox@4a0f4000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x4a0f4000 0x200>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mailbox";
717
			#mbox-cells = <1>;
718 719
			ti,mbox-num-users = <3>;
			ti,mbox-num-fifos = <8>;
720 721 722 723 724 725 726 727
			mbox_ipu: mbox_ipu {
				ti,mbox-tx = <0 0 0>;
				ti,mbox-rx = <1 0 0>;
			};
			mbox_dsp: mbox_dsp {
				ti,mbox-tx = <3 0 0>;
				ti,mbox-rx = <2 0 0>;
			};
728 729
		};

730
		timer1: timer@4ae18000 {
731
			compatible = "ti,omap5430-timer";
732
			reg = <0x4ae18000 0x80>;
733
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
734 735 736 737 738
			ti,hwmods = "timer1";
			ti,timer-alwon;
		};

		timer2: timer@48032000 {
739
			compatible = "ti,omap5430-timer";
740
			reg = <0x48032000 0x80>;
741
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
742 743 744 745
			ti,hwmods = "timer2";
		};

		timer3: timer@48034000 {
746
			compatible = "ti,omap5430-timer";
747
			reg = <0x48034000 0x80>;
748
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
749 750 751 752
			ti,hwmods = "timer3";
		};

		timer4: timer@48036000 {
753
			compatible = "ti,omap5430-timer";
754
			reg = <0x48036000 0x80>;
755
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
756 757 758 759
			ti,hwmods = "timer4";
		};

		timer5: timer@40138000 {
760
			compatible = "ti,omap5430-timer";
761 762
			reg = <0x40138000 0x80>,
			      <0x49038000 0x80>;
763
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
764 765
			ti,hwmods = "timer5";
			ti,timer-dsp;
766
			ti,timer-pwm;
767 768 769
		};

		timer6: timer@4013a000 {
770
			compatible = "ti,omap5430-timer";
771 772
			reg = <0x4013a000 0x80>,
			      <0x4903a000 0x80>;
773
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
774 775 776 777 778 779
			ti,hwmods = "timer6";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer7: timer@4013c000 {
780
			compatible = "ti,omap5430-timer";
781 782
			reg = <0x4013c000 0x80>,
			      <0x4903c000 0x80>;
783
			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
784 785 786 787 788
			ti,hwmods = "timer7";
			ti,timer-dsp;
		};

		timer8: timer@4013e000 {
789
			compatible = "ti,omap5430-timer";
790 791
			reg = <0x4013e000 0x80>,
			      <0x4903e000 0x80>;
792
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
793 794 795 796 797 798
			ti,hwmods = "timer8";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer9: timer@4803e000 {
799
			compatible = "ti,omap5430-timer";
800
			reg = <0x4803e000 0x80>;
801
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
802
			ti,hwmods = "timer9";
803
			ti,timer-pwm;
804 805 806
		};

		timer10: timer@48086000 {
807
			compatible = "ti,omap5430-timer";
808
			reg = <0x48086000 0x80>;
809
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
810
			ti,hwmods = "timer10";
811
			ti,timer-pwm;
812 813 814
		};

		timer11: timer@48088000 {
815
			compatible = "ti,omap5430-timer";
816
			reg = <0x48088000 0x80>;
817
			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
818 819 820
			ti,hwmods = "timer11";
			ti,timer-pwm;
		};
821

822 823 824
		wdt2: wdt@4ae14000 {
			compatible = "ti,omap5-wdt", "ti,omap3-wdt";
			reg = <0x4ae14000 0x80>;
825
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
826 827 828
			ti,hwmods = "wd_timer2";
		};

829 830 831 832 833 834 835
		dmm@4e000000 {
			compatible = "ti,omap5-dmm";
			reg = <0x4e000000 0x800>;
			interrupts = <0 113 0x4>;
			ti,hwmods = "dmm";
		};

836
		emif1: emif@4c000000 {
837 838
			compatible	= "ti,emif-4d5";
			ti,hwmods	= "emif1";
839
			ti,no-idle-on-init;
840 841
			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
			reg = <0x4c000000 0x400>;
842
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
843 844 845 846 847
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};

848
		emif2: emif@4d000000 {
849 850
			compatible	= "ti,emif-4d5";
			ti,hwmods	= "emif2";
851
			ti,no-idle-on-init;
852 853
			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
			reg = <0x4d000000 0x400>;
854
			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
855 856 857 858
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};
859

860
		usb3: omap_dwc3@4a020000 {
861 862
			compatible = "ti,dwc3";
			ti,hwmods = "usb_otg_ss";
863
			reg = <0x4a020000 0x10000>;
864
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
865 866 867 868
			#address-cells = <1>;
			#size-cells = <1>;
			utmi-mode = <2>;
			ranges;
869
			dwc3: dwc3@4a030000 {
870
				compatible = "snps,dwc3";
871
				reg = <0x4a030000 0x10000>;
872 873 874 875 876 877
				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "peripheral",
						  "host",
						  "otg";
878 879
				phys = <&usb2_phy>, <&usb3_phy>;
				phy-names = "usb2-phy", "usb3-phy";
880
				dr_mode = "peripheral";
881 882 883
			};
		};

884
		ocp2scp@4a080000 {
885 886 887
			compatible = "ti,omap-ocp2scp";
			#address-cells = <1>;
			#size-cells = <1>;
888
			reg = <0x4a080000 0x20>;
889 890
			ranges;
			ti,hwmods = "ocp2scp1";
891 892 893
			usb2_phy: usb2phy@4a084000 {
				compatible = "ti,omap-usb2";
				reg = <0x4a084000 0x7c>;
894
				syscon-phy-power = <&scm_conf 0x300>;
895 896
				clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
				clock-names = "wkupclk", "refclk";
897
				#phy-cells = <0>;
898 899 900 901 902 903 904 905
			};

			usb3_phy: usb3phy@4a084400 {
				compatible = "ti,omap-usb3";
				reg = <0x4a084400 0x80>,
				      <0x4a084800 0x64>,
				      <0x4a084c00 0x40>;
				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
906
				syscon-phy-power = <&scm_conf 0x370>;
907 908 909 910 911 912
				clocks = <&usb_phy_cm_clk32k>,
					 <&sys_clkin>,
					 <&usb_otg_ss_refclk960m>;
				clock-names =	"wkupclk",
						"sysclk",
						"refclk";
913
				#phy-cells = <0>;
914
			};
915
		};
916 917 918 919 920 921 922 923 924 925 926 927 928 929 930

		usbhstll: usbhstll@4a062000 {
			compatible = "ti,usbhs-tll";
			reg = <0x4a062000 0x1000>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "usb_tll_hs";
		};

		usbhshost: usbhshost@4a064000 {
			compatible = "ti,usbhs-host";
			reg = <0x4a064000 0x800>;
			ti,hwmods = "usb_host_hs";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
931 932 933 934 935 936
			clocks = <&l3init_60m_fclk>,
				 <&xclk60mhsp1_ck>,
				 <&xclk60mhsp2_ck>;
			clock-names = "refclk_60m_int",
				      "refclk_60m_ext_p1",
				      "refclk_60m_ext_p2";
937 938

			usbhsohci: ohci@4a064800 {
939
				compatible = "ti,ohci-omap3";
940 941 942 943 944
				reg = <0x4a064800 0x400>;
				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			};

			usbhsehci: ehci@4a064c00 {
945
				compatible = "ti,ehci-omap";
946 947 948 949
				reg = <0x4a064c00 0x400>;
				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
950

951
		bandgap: bandgap@4a0021e0 {
952 953 954 955 956 957
			reg = <0x4a0021e0 0xc
			       0x4a00232c 0xc
			       0x4a002380 0x2c
			       0x4a0023C0 0x3c>;
			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
			compatible = "ti,omap5430-bandgap";
958 959

			#thermal-sensor-cells = <1>;
960
		};
961 962 963 964 965 966 967 968 969 970 971 972 973 974 975

		/* OCP2SCP3 */
		ocp2scp@4a090000 {
			compatible = "ti,omap-ocp2scp";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x4a090000 0x20>;
			ranges;
			ti,hwmods = "ocp2scp3";
			sata_phy: phy@4a096000 {
				compatible = "ti,phy-pipe3-sata";
				reg = <0x4A096000 0x80>, /* phy_rx */
				      <0x4A096400 0x64>, /* phy_tx */
				      <0x4A096800 0x40>; /* pll_ctrl */
				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
976
				syscon-phy-power = <&scm_conf 0x374>;
977 978
				clocks = <&sys_clkin>, <&sata_ref_clk>;
				clock-names = "sysclk", "refclk";
979 980 981 982 983 984 985 986 987 988 989 990 991 992
				#phy-cells = <0>;
			};
		};

		sata: sata@4a141100 {
			compatible = "snps,dwc-ahci";
			reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&sata_phy>;
			phy-names = "sata-phy";
			clocks = <&sata_ref_clk>;
			ti,hwmods = "sata";
		};

993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012
		dss: dss@58000000 {
			compatible = "ti,omap5-dss";
			reg = <0x58000000 0x80>;
			status = "disabled";
			ti,hwmods = "dss_core";
			clocks = <&dss_dss_clk>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			dispc@58001000 {
				compatible = "ti,omap5-dispc";
				reg = <0x58001000 0x1000>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				ti,hwmods = "dss_dispc";
				clocks = <&dss_dss_clk>;
				clock-names = "fck";
			};

1013 1014 1015 1016 1017 1018 1019 1020 1021
			rfbi: encoder@58002000  {
				compatible = "ti,omap5-rfbi";
				reg = <0x58002000 0x100>;
				status = "disabled";
				ti,hwmods = "dss_rfbi";
				clocks = <&dss_dss_clk>, <&l3_iclk_div>;
				clock-names = "fck", "ick";
			};

1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059
			dsi1: encoder@58004000 {
				compatible = "ti,omap5-dsi";
				reg = <0x58004000 0x200>,
				      <0x58004200 0x40>,
				      <0x58004300 0x40>;
				reg-names = "proto", "phy", "pll";
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
				ti,hwmods = "dss_dsi1";
				clocks = <&dss_dss_clk>, <&dss_sys_clk>;
				clock-names = "fck", "sys_clk";
			};

			dsi2: encoder@58005000 {
				compatible = "ti,omap5-dsi";
				reg = <0x58009000 0x200>,
				      <0x58009200 0x40>,
				      <0x58009300 0x40>;
				reg-names = "proto", "phy", "pll";
				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
				ti,hwmods = "dss_dsi2";
				clocks = <&dss_dss_clk>, <&dss_sys_clk>;
				clock-names = "fck", "sys_clk";
			};

			hdmi: encoder@58060000 {
				compatible = "ti,omap5-hdmi";
				reg = <0x58040000 0x200>,
				      <0x58040200 0x80>,
				      <0x58040300 0x80>,
				      <0x58060000 0x19000>;
				reg-names = "wp", "pll", "phy", "core";
				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
				ti,hwmods = "dss_hdmi";
				clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
				clock-names = "fck", "sys_clk";
1060 1061
				dmas = <&sdma 76>;
				dma-names = "audio_tx";
1062 1063
			};
		};
1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123

		abb_mpu: regulator-abb-mpu {
			compatible = "ti,abb-v2";
			regulator-name = "abb_mpu";
			#address-cells = <0>;
			#size-cells = <0>;
			clocks = <&sys_clkin>;
			ti,settling-time = <50>;
			ti,clock-cycles = <16>;

			reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
			      <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
			reg-names = "base-address", "int-address",
				    "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x80>;
			/* LDOVBBMPU_MUX_CTRL */
			ti,ldovbb-override-mask = <0x400>;
			/* LDOVBBMPU_VSET_OUT */
			ti,ldovbb-vset-mask = <0x1F>;

			/*
			 * NOTE: only FBB mode used but actual vset will
			 * determine final biasing
			 */
			ti,abb_info = <
			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
			1060000		0	0x0	0 0x02000000 0x01F00000
			1250000		0	0x4	0 0x02000000 0x01F00000
			>;
		};

		abb_mm: regulator-abb-mm {
			compatible = "ti,abb-v2";
			regulator-name = "abb_mm";
			#address-cells = <0>;
			#size-cells = <0>;
			clocks = <&sys_clkin>;
			ti,settling-time = <50>;
			ti,clock-cycles = <16>;

			reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
			      <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
			reg-names = "base-address", "int-address",
				    "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x80000000>;
			/* LDOVBBMM_MUX_CTRL */
			ti,ldovbb-override-mask = <0x400>;
			/* LDOVBBMM_VSET_OUT */
			ti,ldovbb-vset-mask = <0x1F>;

			/*
			 * NOTE: only FBB mode used but actual vset will
			 * determine final biasing
			 */
			ti,abb_info = <
			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
			1025000		0	0x0	0 0x02000000 0x01F00000
			1120000		0	0x4	0 0x02000000 0x01F00000
			>;
		};
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	};
};
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&cpu_thermal {
	polling-delay = <500>; /* milliseconds */
};

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/include/ "omap54xx-clocks.dtsi"
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