i915_drv.c 28.1 KB
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/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#include <linux/device.h>
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#include "drmP.h"
#include "drm.h"
#include "i915_drm.h"
#include "i915_drv.h"
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#include "intel_drv.h"
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#include <linux/console.h>
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#include <linux/module.h>
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#include "drm_crtc_helper.h"
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static int i915_modeset __read_mostly = -1;
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module_param_named(modeset, i915_modeset, int, 0400);
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MODULE_PARM_DESC(modeset,
		"Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
		"1=on, -1=force vga console preference [default])");
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unsigned int i915_fbpercrtc __always_unused = 0;
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module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
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int i915_panel_ignore_lid __read_mostly = 0;
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module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
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MODULE_PARM_DESC(panel_ignore_lid,
		"Override lid status (0=autodetect [default], 1=lid open, "
		"-1=lid closed)");
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unsigned int i915_powersave __read_mostly = 1;
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module_param_named(powersave, i915_powersave, int, 0600);
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MODULE_PARM_DESC(powersave,
		"Enable powersavings, fbc, downclocking, etc. (default: true)");
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int i915_semaphores __read_mostly = -1;
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module_param_named(semaphores, i915_semaphores, int, 0600);
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MODULE_PARM_DESC(semaphores,
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		"Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
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int i915_enable_rc6 __read_mostly = -1;
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module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
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MODULE_PARM_DESC(i915_enable_rc6,
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		"Enable power-saving render C-state 6 (default: -1 (use per-chip default)");
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int i915_enable_fbc __read_mostly = -1;
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module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
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MODULE_PARM_DESC(i915_enable_fbc,
		"Enable frame buffer compression for power savings "
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		"(default: -1 (use per-chip default))");
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unsigned int i915_lvds_downclock __read_mostly = 0;
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module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
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MODULE_PARM_DESC(lvds_downclock,
		"Use panel (LVDS/eDP) downclocking for power savings "
		"(default: false)");
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int i915_panel_use_ssc __read_mostly = -1;
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module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
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MODULE_PARM_DESC(lvds_use_ssc,
		"Use Spread Spectrum Clock with panels [LVDS/eDP] "
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		"(default: auto from VBT)");
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int i915_vbt_sdvo_panel_type __read_mostly = -1;
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module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
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MODULE_PARM_DESC(vbt_sdvo_panel_type,
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		"Override/Ignore selection of SDVO panel mode in the VBT "
		"(-2=ignore, -1=auto [default], index in VBT BIOS table)");
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static bool i915_try_reset __read_mostly = true;
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module_param_named(reset, i915_try_reset, bool, 0600);
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MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
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bool i915_enable_hangcheck __read_mostly = true;
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module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
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MODULE_PARM_DESC(enable_hangcheck,
		"Periodically check GPU activity for detecting hangs. "
		"WARNING: Disabling this can cause system wide hangs. "
		"(default: true)");
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bool i915_enable_ppgtt __read_mostly = 1;
module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, bool, 0600);
MODULE_PARM_DESC(i915_enable_ppgtt,
		"Enable PPGTT (default: true)");

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static struct drm_driver driver;
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extern int intel_agp_enabled;
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#define INTEL_VGA_DEVICE(id, info) {		\
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	.class = PCI_BASE_CLASS_DISPLAY << 16,	\
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	.class_mask = 0xff0000,			\
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	.vendor = 0x8086,			\
	.device = id,				\
	.subvendor = PCI_ANY_ID,		\
	.subdevice = PCI_ANY_ID,		\
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	.driver_data = (unsigned long) info }

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static const struct intel_device_info intel_i830_info = {
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	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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};

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static const struct intel_device_info intel_845g_info = {
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	.gen = 2,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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};

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static const struct intel_device_info intel_i85x_info = {
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	.gen = 2, .is_i85x = 1, .is_mobile = 1,
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	.cursor_needs_physical = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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};

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static const struct intel_device_info intel_i865g_info = {
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	.gen = 2,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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};

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static const struct intel_device_info intel_i915g_info = {
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	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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};
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static const struct intel_device_info intel_i915gm_info = {
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	.gen = 3, .is_mobile = 1,
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	.cursor_needs_physical = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.supports_tv = 1,
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};
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static const struct intel_device_info intel_i945g_info = {
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	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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};
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static const struct intel_device_info intel_i945gm_info = {
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	.gen = 3, .is_i945gm = 1, .is_mobile = 1,
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	.has_hotplug = 1, .cursor_needs_physical = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.supports_tv = 1,
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};

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static const struct intel_device_info intel_i965g_info = {
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	.gen = 4, .is_broadwater = 1,
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	.has_hotplug = 1,
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	.has_overlay = 1,
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};

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static const struct intel_device_info intel_i965gm_info = {
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	.gen = 4, .is_crestline = 1,
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	.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
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	.has_overlay = 1,
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	.supports_tv = 1,
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};

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static const struct intel_device_info intel_g33_info = {
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	.gen = 3, .is_g33 = 1,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_overlay = 1,
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};

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static const struct intel_device_info intel_g45_info = {
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	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
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	.has_pipe_cxsr = 1, .has_hotplug = 1,
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	.has_bsd_ring = 1,
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};

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static const struct intel_device_info intel_gm45_info = {
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	.gen = 4, .is_g4x = 1,
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	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
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	.has_pipe_cxsr = 1, .has_hotplug = 1,
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	.supports_tv = 1,
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	.has_bsd_ring = 1,
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};

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static const struct intel_device_info intel_pineview_info = {
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	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_overlay = 1,
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};

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static const struct intel_device_info intel_ironlake_d_info = {
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	.gen = 5,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_bsd_ring = 1,
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};

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static const struct intel_device_info intel_ironlake_m_info = {
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	.gen = 5, .is_mobile = 1,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_fbc = 1,
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	.has_bsd_ring = 1,
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};

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static const struct intel_device_info intel_sandybridge_d_info = {
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	.gen = 6,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_bsd_ring = 1,
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	.has_blt_ring = 1,
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	.has_llc = 1,
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};

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static const struct intel_device_info intel_sandybridge_m_info = {
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	.gen = 6, .is_mobile = 1,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_fbc = 1,
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	.has_bsd_ring = 1,
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	.has_blt_ring = 1,
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	.has_llc = 1,
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};

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static const struct intel_device_info intel_ivybridge_d_info = {
	.is_ivybridge = 1, .gen = 7,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.has_bsd_ring = 1,
	.has_blt_ring = 1,
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	.has_llc = 1,
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};

static const struct intel_device_info intel_ivybridge_m_info = {
	.is_ivybridge = 1, .gen = 7, .is_mobile = 1,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.has_fbc = 0,	/* FBC is not enabled on Ivybridge mobile yet */
	.has_bsd_ring = 1,
	.has_blt_ring = 1,
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	.has_llc = 1,
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};

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static const struct pci_device_id pciidlist[] = {		/* aka */
	INTEL_VGA_DEVICE(0x3577, &intel_i830_info),		/* I830_M */
	INTEL_VGA_DEVICE(0x2562, &intel_845g_info),		/* 845_G */
	INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),		/* I855_GM */
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	INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
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	INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),		/* I865_G */
	INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),		/* I915_G */
	INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),		/* E7221_G */
	INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),		/* I915_GM */
	INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),		/* I945_G */
	INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),		/* I945_GM */
	INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),		/* I945_GME */
	INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),		/* I946_GZ */
	INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),		/* G35_G */
	INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),		/* I965_Q */
	INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),		/* I965_G */
	INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),		/* Q35_G */
	INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),		/* G33_G */
	INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),		/* Q33_G */
	INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),		/* I965_GM */
	INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),		/* I965_GME */
	INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),		/* GM45_G */
	INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),		/* IGD_E_G */
	INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),		/* Q45_G */
	INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),		/* G45_G */
	INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),		/* G41_G */
	INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),		/* B43_G */
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	INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),		/* B43_G.1 */
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	INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
	INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
	INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
	INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
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	INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
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	INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
	INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
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	INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
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	INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
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	INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
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	INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
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	INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
	INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
	INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
	INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
	INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
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	{0, 0, 0}
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};

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#if defined(CONFIG_DRM_I915_KMS)
MODULE_DEVICE_TABLE(pci, pciidlist);
#endif

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#define INTEL_PCH_DEVICE_ID_MASK	0xff00
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#define INTEL_PCH_IBX_DEVICE_ID_TYPE	0x3b00
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#define INTEL_PCH_CPT_DEVICE_ID_TYPE	0x1c00
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#define INTEL_PCH_PPT_DEVICE_ID_TYPE	0x1e00
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void intel_detect_pch(struct drm_device *dev)
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{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct pci_dev *pch;

	/*
	 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
	 * make graphics device passthrough work easy for VMM, that only
	 * need to expose ISA bridge to let driver know the real hardware
	 * underneath. This is a requirement from virtualization team.
	 */
	pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
	if (pch) {
		if (pch->vendor == PCI_VENDOR_ID_INTEL) {
			int id;
			id = pch->device & INTEL_PCH_DEVICE_ID_MASK;

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			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_IBX;
				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
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				dev_priv->pch_type = PCH_CPT;
				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
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			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
				/* PantherPoint is CPT compatible */
				dev_priv->pch_type = PCH_CPT;
				DRM_DEBUG_KMS("Found PatherPoint PCH\n");
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			}
		}
		pci_dev_put(pch);
	}
}

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void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
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{
	int count;

	count = 0;
	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
		udelay(10);

	I915_WRITE_NOTRACE(FORCEWAKE, 1);
	POSTING_READ(FORCEWAKE);

	count = 0;
	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
		udelay(10);
}

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void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
{
	int count;

	count = 0;
	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
		udelay(10);

	I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
	POSTING_READ(FORCEWAKE_MT);

	count = 0;
	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
		udelay(10);
}

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/*
 * Generally this is called implicitly by the register read function. However,
 * if some sequence requires the GT to not power down then this function should
 * be called at the beginning of the sequence followed by a call to
 * gen6_gt_force_wake_put() at the end of the sequence.
 */
void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
{
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	unsigned long irqflags;
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	spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
	if (dev_priv->forcewake_count++ == 0)
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		dev_priv->display.force_wake_get(dev_priv);
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	spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
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}

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static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
{
	u32 gtfifodbg;
	gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
	if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
	     "MMIO read or write has been dropped %x\n", gtfifodbg))
		I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
}

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void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
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{
	I915_WRITE_NOTRACE(FORCEWAKE, 0);
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	/* The below doubles as a POSTING_READ */
	gen6_gt_check_fifodbg(dev_priv);
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}

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void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
{
	I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
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	/* The below doubles as a POSTING_READ */
	gen6_gt_check_fifodbg(dev_priv);
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}

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/*
 * see gen6_gt_force_wake_get()
 */
void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
{
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	unsigned long irqflags;
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	spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
	if (--dev_priv->forcewake_count == 0)
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		dev_priv->display.force_wake_put(dev_priv);
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	spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
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}

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int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
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{
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	int ret = 0;

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	if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
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		int loop = 500;
		u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
		while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
			udelay(10);
			fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
		}
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		if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
			++ret;
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		dev_priv->gt_fifo_count = fifo;
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	}
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	dev_priv->gt_fifo_count--;
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	return ret;
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}

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static int i915_drm_freeze(struct drm_device *dev)
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{
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	struct drm_i915_private *dev_priv = dev->dev_private;

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	drm_kms_helper_poll_disable(dev);

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	pci_save_state(dev->pdev);

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	/* If KMS is active, we do the leavevt stuff here */
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	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
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		int error = i915_gem_idle(dev);
		if (error) {
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			dev_err(&dev->pdev->dev,
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				"GEM idle failed, resume might fail\n");
			return error;
		}
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		drm_irq_uninstall(dev);
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	}

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	i915_save_state(dev);

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	intel_opregion_fini(dev);
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	/* Modeset on resume, not lid events */
	dev_priv->modeset_on_lid = 0;
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	return 0;
471 472
}

473
int i915_suspend(struct drm_device *dev, pm_message_t state)
474 475 476 477 478 479 480 481 482 483 484 485
{
	int error;

	if (!dev || !dev->dev_private) {
		DRM_ERROR("dev: %p\n", dev);
		DRM_ERROR("DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}

	if (state.event == PM_EVENT_PRETHAW)
		return 0;

486 487 488

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
489

490 491 492 493
	error = i915_drm_freeze(dev);
	if (error)
		return error;

494 495 496 497 498
	if (state.event == PM_EVENT_SUSPEND) {
		/* Shut down the device */
		pci_disable_device(dev->pdev);
		pci_set_power_state(dev->pdev, PCI_D3hot);
	}
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	return 0;
}

503
static int i915_drm_thaw(struct drm_device *dev)
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504
{
505
	struct drm_i915_private *dev_priv = dev->dev_private;
506
	int error = 0;
507

508 509 510 511 512 513
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		mutex_lock(&dev->struct_mutex);
		i915_gem_restore_gtt_mappings(dev);
		mutex_unlock(&dev->struct_mutex);
	}

514
	i915_restore_state(dev);
515
	intel_opregion_setup(dev);
516

517 518 519 520 521
	/* KMS EnterVT equivalent */
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		mutex_lock(&dev->struct_mutex);
		dev_priv->mm.suspended = 0;

522
		error = i915_gem_init_hw(dev);
523
		mutex_unlock(&dev->struct_mutex);
524

525 526 527
		if (HAS_PCH_SPLIT(dev))
			ironlake_init_pch_refclk(dev);

528
		drm_mode_config_reset(dev);
529
		drm_irq_install(dev);
530

531 532
		/* Resume the modeset for every activated CRTC */
		drm_helper_resume_force_mode(dev);
533

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534
		if (IS_IRONLAKE_M(dev))
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			ironlake_enable_rc6(dev);
	}
537

538 539
	intel_opregion_init(dev);

540
	dev_priv->modeset_on_lid = 0;
541

542 543 544
	return error;
}

545
int i915_resume(struct drm_device *dev)
546
{
547 548
	int ret;

549 550 551
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

552 553 554 555 556
	if (pci_enable_device(dev->pdev))
		return -EIO;

	pci_set_master(dev->pdev);

557 558 559 560 561 562
	ret = i915_drm_thaw(dev);
	if (ret)
		return ret;

	drm_kms_helper_poll_enable(dev);
	return 0;
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}

565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594
static int i8xx_do_reset(struct drm_device *dev, u8 flags)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (IS_I85X(dev))
		return -ENODEV;

	I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
	POSTING_READ(D_STATE);

	if (IS_I830(dev) || IS_845G(dev)) {
		I915_WRITE(DEBUG_RESET_I830,
			   DEBUG_RESET_DISPLAY |
			   DEBUG_RESET_RENDER |
			   DEBUG_RESET_FULL);
		POSTING_READ(DEBUG_RESET_I830);
		msleep(1);

		I915_WRITE(DEBUG_RESET_I830, 0);
		POSTING_READ(DEBUG_RESET_I830);
	}

	msleep(1);

	I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
	POSTING_READ(D_STATE);

	return 0;
}

595 596 597
static int i965_reset_complete(struct drm_device *dev)
{
	u8 gdrst;
598
	pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
599 600 601
	return gdrst & 0x1;
}

602 603 604 605
static int i965_do_reset(struct drm_device *dev, u8 flags)
{
	u8 gdrst;

606 607 608 609 610
	/*
	 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
	 * well as the reset bit (GR/bit 0).  Setting the GR bit
	 * triggers the reset; when done, the hardware will clear it.
	 */
611 612 613 614 615 616 617 618 619 620 621 622
	pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
	pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);

	return wait_for(i965_reset_complete(dev), 500);
}

static int ironlake_do_reset(struct drm_device *dev, u8 flags)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
	return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
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}

625 626 627
static int gen6_do_reset(struct drm_device *dev, u8 flags)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
628 629
	int	ret;
	unsigned long irqflags;
630

631 632 633
	/* Hold gt_lock across reset to prevent any register access
	 * with forcewake not set correctly
	 */
634
	spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
635 636 637 638 639 640 641 642 643 644 645 646 647

	/* Reset the chip */

	/* GEN6_GDRST is not in the gt power well, no need to check
	 * for fifo space for the write or forcewake the chip for
	 * the read
	 */
	I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);

	/* Spin waiting for the device to ack the reset request */
	ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);

	/* If reset with a user forcewake, try to restore, otherwise turn it off */
648 649
	if (dev_priv->forcewake_count)
		dev_priv->display.force_wake_get(dev_priv);
650 651 652 653 654 655
	else
		dev_priv->display.force_wake_put(dev_priv);

	/* Restore fifo count */
	dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);

656 657
	spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
	return ret;
658 659
}

660
/**
661
 * i915_reset - reset chip after a hang
662 663 664 665 666 667 668 669 670 671 672 673 674 675
 * @dev: drm device to reset
 * @flags: reset domains
 *
 * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 * reset or otherwise an error code.
 *
 * Procedure is fairly simple:
 *   - reset the chip using the reset reg
 *   - re-init context state
 *   - re-init hardware status page
 *   - re-init ring buffer
 *   - re-init interrupt state
 *   - re-init display
 */
676
int i915_reset(struct drm_device *dev, u8 flags)
677 678 679 680 681 682 683
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	/*
	 * We really should only reset the display subsystem if we actually
	 * need to
	 */
	bool need_display = true;
684
	int ret;
685

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	if (!i915_try_reset)
		return 0;

689 690
	if (!mutex_trylock(&dev->struct_mutex))
		return -EBUSY;
691

692
	i915_gem_reset(dev);
693

694
	ret = -ENODEV;
695 696 697
	if (get_seconds() - dev_priv->last_gpu_reset < 5) {
		DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
	} else switch (INTEL_INFO(dev)->gen) {
698
	case 7:
699 700 701
	case 6:
		ret = gen6_do_reset(dev, flags);
		break;
702
	case 5:
703
		ret = ironlake_do_reset(dev, flags);
704 705
		break;
	case 4:
706
		ret = i965_do_reset(dev, flags);
707
		break;
708 709 710
	case 2:
		ret = i8xx_do_reset(dev, flags);
		break;
711
	}
712
	dev_priv->last_gpu_reset = get_seconds();
713
	if (ret) {
714
		DRM_ERROR("Failed to reset chip.\n");
715
		mutex_unlock(&dev->struct_mutex);
716
		return ret;
717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733
	}

	/* Ok, now get things going again... */

	/*
	 * Everything depends on having the GTT running, so we need to start
	 * there.  Fortunately we don't need to do this unless we reset the
	 * chip at a PCI level.
	 *
	 * Next we need to restore the context, but we don't use those
	 * yet either...
	 *
	 * Ring buffer needs to be re-initialized in the KMS case, or if X
	 * was running at the time of the reset (i.e. we weren't VT
	 * switched away).
	 */
	if (drm_core_check_feature(dev, DRIVER_MODESET) ||
734
			!dev_priv->mm.suspended) {
735
		dev_priv->mm.suspended = 0;
736

737 738
		i915_gem_init_swizzling(dev);

739
		dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
740
		if (HAS_BSD(dev))
741
		    dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
742
		if (HAS_BLT(dev))
743
		    dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
744

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		i915_gem_init_ppgtt(dev);

747 748
		mutex_unlock(&dev->struct_mutex);
		drm_irq_uninstall(dev);
749
		drm_mode_config_reset(dev);
750 751 752 753
		drm_irq_install(dev);
		mutex_lock(&dev->struct_mutex);
	}

754 755
	mutex_unlock(&dev->struct_mutex);

756
	/*
757 758 759
	 * Perform a full modeset as on later generations, e.g. Ironlake, we may
	 * need to retrain the display link and cannot just restore the register
	 * values.
760
	 */
761 762 763 764 765
	if (need_display) {
		mutex_lock(&dev->mode_config.mutex);
		drm_helper_resume_force_mode(dev);
		mutex_unlock(&dev->mode_config.mutex);
	}
766 767 768 769 770

	return 0;
}


771 772 773
static int __devinit
i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
774 775 776 777 778 779 780 781
	/* Only bind to function 0 of the device. Early generations
	 * used function 1 as a placeholder for multi-head. This causes
	 * us confusion instead, especially on the systems where both
	 * functions have the same PCI-ID!
	 */
	if (PCI_FUNC(pdev->devfn))
		return -ENODEV;

782
	return drm_get_pci_dev(pdev, ent, &driver);
783 784 785 786 787 788 789 790 791 792
}

static void
i915_pci_remove(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	drm_put_dev(dev);
}

793
static int i915_pm_suspend(struct device *dev)
794
{
795 796 797
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);
	int error;
798

799 800 801 802
	if (!drm_dev || !drm_dev->dev_private) {
		dev_err(dev, "DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}
803

804 805 806
	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

807 808 809
	error = i915_drm_freeze(drm_dev);
	if (error)
		return error;
810

811 812
	pci_disable_device(pdev);
	pci_set_power_state(pdev, PCI_D3hot);
813

814
	return 0;
815 816
}

817
static int i915_pm_resume(struct device *dev)
818
{
819 820 821 822
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);

	return i915_resume(drm_dev);
823 824
}

825
static int i915_pm_freeze(struct device *dev)
826
{
827 828 829 830 831 832 833 834 835
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);

	if (!drm_dev || !drm_dev->dev_private) {
		dev_err(dev, "DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}

	return i915_drm_freeze(drm_dev);
836 837
}

838
static int i915_pm_thaw(struct device *dev)
839
{
840 841 842 843
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);

	return i915_drm_thaw(drm_dev);
844 845
}

846
static int i915_pm_poweroff(struct device *dev)
847
{
848 849 850
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);

851
	return i915_drm_freeze(drm_dev);
852 853
}

854
static const struct dev_pm_ops i915_pm_ops = {
855 856 857 858 859 860
	.suspend = i915_pm_suspend,
	.resume = i915_pm_resume,
	.freeze = i915_pm_freeze,
	.thaw = i915_pm_thaw,
	.poweroff = i915_pm_poweroff,
	.restore = i915_pm_resume,
861 862
};

863 864
static struct vm_operations_struct i915_gem_vm_ops = {
	.fault = i915_gem_fault,
865 866
	.open = drm_gem_vm_open,
	.close = drm_gem_vm_close,
867 868
};

869 870 871 872 873 874 875 876 877 878 879 880 881 882 883
static const struct file_operations i915_driver_fops = {
	.owner = THIS_MODULE,
	.open = drm_open,
	.release = drm_release,
	.unlocked_ioctl = drm_ioctl,
	.mmap = drm_gem_mmap,
	.poll = drm_poll,
	.fasync = drm_fasync,
	.read = drm_read,
#ifdef CONFIG_COMPAT
	.compat_ioctl = i915_compat_ioctl,
#endif
	.llseek = noop_llseek,
};

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static struct drm_driver driver = {
885 886
	/* Don't use MTRRs here; the Xserver or userspace app should
	 * deal with them for Intel hardware.
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	 */
888 889 890
	.driver_features =
	    DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
	    DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
891
	.load = i915_driver_load,
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	.unload = i915_driver_unload,
893
	.open = i915_driver_open,
894 895
	.lastclose = i915_driver_lastclose,
	.preclose = i915_driver_preclose,
896
	.postclose = i915_driver_postclose,
897 898 899 900 901

	/* Used in place of i915_pm_ops for non-DRIVER_MODESET */
	.suspend = i915_suspend,
	.resume = i915_resume,

902
	.device_is_agp = i915_driver_device_is_agp,
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	.reclaim_buffers = drm_core_reclaim_buffers,
904 905
	.master_create = i915_master_create,
	.master_destroy = i915_master_destroy,
906
#if defined(CONFIG_DEBUG_FS)
907 908
	.debugfs_init = i915_debugfs_init,
	.debugfs_cleanup = i915_debugfs_cleanup,
909
#endif
910 911
	.gem_init_object = i915_gem_init_object,
	.gem_free_object = i915_gem_free_object,
912
	.gem_vm_ops = &i915_gem_vm_ops,
913 914 915
	.dumb_create = i915_gem_dumb_create,
	.dumb_map_offset = i915_gem_mmap_gtt,
	.dumb_destroy = i915_gem_dumb_destroy,
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	.ioctls = i915_ioctls,
917
	.fops = &i915_driver_fops,
918 919 920 921 922 923
	.name = DRIVER_NAME,
	.desc = DRIVER_DESC,
	.date = DRIVER_DATE,
	.major = DRIVER_MAJOR,
	.minor = DRIVER_MINOR,
	.patchlevel = DRIVER_PATCHLEVEL,
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};

926 927 928 929 930 931 932 933
static struct pci_driver i915_pci_driver = {
	.name = DRIVER_NAME,
	.id_table = pciidlist,
	.probe = i915_pci_probe,
	.remove = i915_pci_remove,
	.driver.pm = &i915_pm_ops,
};

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static int __init i915_init(void)
{
936 937 938 939 940
	if (!intel_agp_enabled) {
		DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
		return -ENODEV;
	}

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	driver.num_ioctls = i915_max_ioctl;
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	/*
	 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
	 * explicitly disabled with the module pararmeter.
	 *
	 * Otherwise, just follow the parameter (defaulting to off).
	 *
	 * Allow optional vga_text_mode_force boot option to override
	 * the default behavior.
	 */
#if defined(CONFIG_DRM_I915_KMS)
	if (i915_modeset != 0)
		driver.driver_features |= DRIVER_MODESET;
#endif
	if (i915_modeset == 1)
		driver.driver_features |= DRIVER_MODESET;

#ifdef CONFIG_VGA_CONSOLE
	if (vgacon_text_force() && i915_modeset == -1)
		driver.driver_features &= ~DRIVER_MODESET;
#endif

964 965 966
	if (!(driver.driver_features & DRIVER_MODESET))
		driver.get_vblank_timestamp = NULL;

967
	return drm_pci_init(&driver, &i915_pci_driver);
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}

static void __exit i915_exit(void)
{
972
	drm_pci_exit(&driver, &i915_pci_driver);
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973 974 975 976 977
}

module_init(i915_init);
module_exit(i915_exit);

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MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
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MODULE_LICENSE("GPL and additional rights");
981 982 983 984 985

#define __i915_read(x, y) \
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
	u##x val = 0; \
	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
986 987 988 989
		unsigned long irqflags; \
		spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
		if (dev_priv->forcewake_count == 0) \
			dev_priv->display.force_wake_get(dev_priv); \
990
		val = read##y(dev_priv->regs + reg); \
991 992 993
		if (dev_priv->forcewake_count == 0) \
			dev_priv->display.force_wake_put(dev_priv); \
		spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008
	} else { \
		val = read##y(dev_priv->regs + reg); \
	} \
	trace_i915_reg_rw(false, reg, val, sizeof(val)); \
	return val; \
}

__i915_read(8, b)
__i915_read(16, w)
__i915_read(32, l)
__i915_read(64, q)
#undef __i915_read

#define __i915_write(x, y) \
void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1009
	u32 __fifo_ret = 0; \
1010 1011
	trace_i915_reg_rw(true, reg, val, sizeof(val)); \
	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1012
		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1013 1014
	} \
	write##y(val, dev_priv->regs + reg); \
1015 1016 1017
	if (unlikely(__fifo_ret)) { \
		gen6_gt_check_fifodbg(dev_priv); \
	} \
1018 1019 1020 1021 1022 1023
}
__i915_write(8, b)
__i915_write(16, w)
__i915_write(32, l)
__i915_write(64, q)
#undef __i915_write