intel_pm.c 175.1 KB
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/*
 * Copyright © 2012 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eugeni Dodonov <eugeni.dodonov@intel.com>
 *
 */

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#include <linux/cpufreq.h>
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#include "i915_drv.h"
#include "intel_drv.h"
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#include "../../../platform/x86/intel_ips.h"
#include <linux/module.h>
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#include <linux/vgaarb.h>
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#include <drm/i915_powerwell.h>
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#include <linux/pm_runtime.h>
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/**
 * RC6 is a special power stage which allows the GPU to enter an very
 * low-voltage mode when idle, using down to 0V while at this stage.  This
 * stage is entered automatically when the GPU is idle when RC6 support is
 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
 *
 * There are different RC6 modes available in Intel GPU, which differentiate
 * among each other with the latency required to enter and leave RC6 and
 * voltage consumed by the GPU in different states.
 *
 * The combination of the following flags define which states GPU is allowed
 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
 * RC6pp is deepest RC6. Their support by hardware varies according to the
 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
 * which brings the most power savings; deeper states save more power, but
 * require higher latency to switch to and wake up.
 */
#define INTEL_RC6_ENABLE			(1<<0)
#define INTEL_RC6p_ENABLE			(1<<1)
#define INTEL_RC6pp_ENABLE			(1<<2)

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/* FBC, or Frame Buffer Compression, is a technique employed to compress the
 * framebuffer contents in-memory, aiming at reducing the required bandwidth
 * during in-memory transfers and, therefore, reduce the power packet.
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 *
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 * The benefits of FBC are mostly visible with solid backgrounds and
 * variation-less patterns.
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 *
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 * FBC-related functionality can be enabled by the means of the
 * i915.i915_enable_fbc parameter
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 */

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static void i8xx_disable_fbc(struct drm_device *dev)
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{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 fbc_ctl;

	/* Disable compression */
	fbc_ctl = I915_READ(FBC_CONTROL);
	if ((fbc_ctl & FBC_CTL_EN) == 0)
		return;

	fbc_ctl &= ~FBC_CTL_EN;
	I915_WRITE(FBC_CONTROL, fbc_ctl);

	/* Wait for compressing bit to clear */
	if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
		DRM_DEBUG_KMS("FBC idle timed out\n");
		return;
	}

	DRM_DEBUG_KMS("disabled FBC\n");
}

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static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
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{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_framebuffer *fb = crtc->fb;
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
	struct drm_i915_gem_object *obj = intel_fb->obj;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int cfb_pitch;
	int plane, i;
	u32 fbc_ctl, fbc_ctl2;

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	cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
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	if (fb->pitches[0] < cfb_pitch)
		cfb_pitch = fb->pitches[0];

	/* FBC_CTL wants 64B units */
	cfb_pitch = (cfb_pitch / 64) - 1;
	plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;

	/* Clear old tags */
	for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
		I915_WRITE(FBC_TAG + (i * 4), 0);

	/* Set it up... */
	fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
	fbc_ctl2 |= plane;
	I915_WRITE(FBC_CONTROL2, fbc_ctl2);
	I915_WRITE(FBC_FENCE_OFF, crtc->y);

	/* enable it... */
	fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
	if (IS_I945GM(dev))
		fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
	fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
	fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
	fbc_ctl |= obj->fence_reg;
	I915_WRITE(FBC_CONTROL, fbc_ctl);

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	DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
		      cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
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}

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static bool i8xx_fbc_enabled(struct drm_device *dev)
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{
	struct drm_i915_private *dev_priv = dev->dev_private;

	return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
}

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static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
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{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_framebuffer *fb = crtc->fb;
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
	struct drm_i915_gem_object *obj = intel_fb->obj;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
	unsigned long stall_watermark = 200;
	u32 dpfc_ctl;

	dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
	dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
	I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);

	I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
		   (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
		   (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
	I915_WRITE(DPFC_FENCE_YOFF, crtc->y);

	/* enable it... */
	I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);

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	DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
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}

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static void g4x_disable_fbc(struct drm_device *dev)
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{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpfc_ctl;

	/* Disable compression */
	dpfc_ctl = I915_READ(DPFC_CONTROL);
	if (dpfc_ctl & DPFC_CTL_EN) {
		dpfc_ctl &= ~DPFC_CTL_EN;
		I915_WRITE(DPFC_CONTROL, dpfc_ctl);

		DRM_DEBUG_KMS("disabled FBC\n");
	}
}

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static bool g4x_fbc_enabled(struct drm_device *dev)
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{
	struct drm_i915_private *dev_priv = dev->dev_private;

	return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
}

static void sandybridge_blit_fbc_update(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 blt_ecoskpd;

	/* Make sure blitter notifies FBC of writes */
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	/* Blitter is part of Media powerwell on VLV. No impact of
	 * his param in other platforms for now */
	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
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	blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
	blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
		GEN6_BLITTER_LOCK_SHIFT;
	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
	blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
	blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
			 GEN6_BLITTER_LOCK_SHIFT);
	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
	POSTING_READ(GEN6_BLITTER_ECOSKPD);
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	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
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}

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static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
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{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_framebuffer *fb = crtc->fb;
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
	struct drm_i915_gem_object *obj = intel_fb->obj;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
	unsigned long stall_watermark = 200;
	u32 dpfc_ctl;

	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
	dpfc_ctl &= DPFC_RESERVED;
	dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
	/* Set persistent mode for front-buffer rendering, ala X. */
	dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
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	dpfc_ctl |= DPFC_CTL_FENCE_EN;
	if (IS_GEN5(dev))
		dpfc_ctl |= obj->fence_reg;
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	I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);

	I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
		   (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
		   (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
	I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
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	I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
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	/* enable it... */
	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);

	if (IS_GEN6(dev)) {
		I915_WRITE(SNB_DPFC_CTL_SA,
			   SNB_CPU_FENCE_ENABLE | obj->fence_reg);
		I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
		sandybridge_blit_fbc_update(dev);
	}

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	DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
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}

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static void ironlake_disable_fbc(struct drm_device *dev)
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{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpfc_ctl;

	/* Disable compression */
	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
	if (dpfc_ctl & DPFC_CTL_EN) {
		dpfc_ctl &= ~DPFC_CTL_EN;
		I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);

		DRM_DEBUG_KMS("disabled FBC\n");
	}
}

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static bool ironlake_fbc_enabled(struct drm_device *dev)
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{
	struct drm_i915_private *dev_priv = dev->dev_private;

	return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
}

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static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_framebuffer *fb = crtc->fb;
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
	struct drm_i915_gem_object *obj = intel_fb->obj;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

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	I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
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	I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
		   IVB_DPFC_CTL_FENCE_EN |
		   intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);

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	if (IS_IVYBRIDGE(dev)) {
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		/* WaFbcAsynchFlipDisableFbcQueue:ivb */
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		I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
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	} else {
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		/* WaFbcAsynchFlipDisableFbcQueue:hsw */
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		I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
			   HSW_BYPASS_FBC_QUEUE);
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	}
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	I915_WRITE(SNB_DPFC_CTL_SA,
		   SNB_CPU_FENCE_ENABLE | obj->fence_reg);
	I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);

	sandybridge_blit_fbc_update(dev);

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	DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
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}

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bool intel_fbc_enabled(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!dev_priv->display.fbc_enabled)
		return false;

	return dev_priv->display.fbc_enabled(dev);
}

static void intel_fbc_work_fn(struct work_struct *__work)
{
	struct intel_fbc_work *work =
		container_of(to_delayed_work(__work),
			     struct intel_fbc_work, work);
	struct drm_device *dev = work->crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	mutex_lock(&dev->struct_mutex);
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	if (work == dev_priv->fbc.fbc_work) {
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		/* Double check that we haven't switched fb without cancelling
		 * the prior work.
		 */
		if (work->crtc->fb == work->fb) {
			dev_priv->display.enable_fbc(work->crtc,
						     work->interval);

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			dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
			dev_priv->fbc.fb_id = work->crtc->fb->base.id;
			dev_priv->fbc.y = work->crtc->y;
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		}

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		dev_priv->fbc.fbc_work = NULL;
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	}
	mutex_unlock(&dev->struct_mutex);

	kfree(work);
}

static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
{
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	if (dev_priv->fbc.fbc_work == NULL)
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		return;

	DRM_DEBUG_KMS("cancelling pending FBC enable\n");

	/* Synchronisation is provided by struct_mutex and checking of
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	 * dev_priv->fbc.fbc_work, so we can perform the cancellation
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	 * entirely asynchronously.
	 */
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	if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
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		/* tasklet was killed before being run, clean up */
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		kfree(dev_priv->fbc.fbc_work);
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	/* Mark the work as no longer wanted so that if it does
	 * wake-up (because the work was already running and waiting
	 * for our mutex), it will discover that is no longer
	 * necessary to run.
	 */
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	dev_priv->fbc.fbc_work = NULL;
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}

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static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
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{
	struct intel_fbc_work *work;
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!dev_priv->display.enable_fbc)
		return;

	intel_cancel_fbc_work(dev_priv);

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	work = kzalloc(sizeof(*work), GFP_KERNEL);
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	if (work == NULL) {
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		DRM_ERROR("Failed to allocate FBC work structure\n");
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		dev_priv->display.enable_fbc(crtc, interval);
		return;
	}

	work->crtc = crtc;
	work->fb = crtc->fb;
	work->interval = interval;
	INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);

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	dev_priv->fbc.fbc_work = work;
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	/* Delay the actual enabling to let pageflipping cease and the
	 * display to settle before starting the compression. Note that
	 * this delay also serves a second purpose: it allows for a
	 * vblank to pass after disabling the FBC before we attempt
	 * to modify the control registers.
	 *
	 * A more complicated solution would involve tracking vblanks
	 * following the termination of the page-flipping sequence
	 * and indeed performing the enable as a co-routine and not
	 * waiting synchronously upon the vblank.
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	 *
	 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
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	 */
	schedule_delayed_work(&work->work, msecs_to_jiffies(50));
}

void intel_disable_fbc(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	intel_cancel_fbc_work(dev_priv);

	if (!dev_priv->display.disable_fbc)
		return;

	dev_priv->display.disable_fbc(dev);
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	dev_priv->fbc.plane = -1;
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}

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static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
			      enum no_fbc_reason reason)
{
	if (dev_priv->fbc.no_fbc_reason == reason)
		return false;

	dev_priv->fbc.no_fbc_reason = reason;
	return true;
}

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/**
 * intel_update_fbc - enable/disable FBC as needed
 * @dev: the drm_device
 *
 * Set up the framebuffer compression hardware at mode set time.  We
 * enable it if possible:
 *   - plane A only (on pre-965)
 *   - no pixel mulitply/line duplication
 *   - no alpha buffer discard
 *   - no dual wide
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 *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
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 *
 * We can't assume that any compression will take place (worst case),
 * so the compressed buffer has to be the same size as the uncompressed
 * one.  It also must reside (along with the line length buffer) in
 * stolen memory.
 *
 * We need to enable/disable FBC on a global basis.
 */
void intel_update_fbc(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = NULL, *tmp_crtc;
	struct intel_crtc *intel_crtc;
	struct drm_framebuffer *fb;
	struct intel_framebuffer *intel_fb;
	struct drm_i915_gem_object *obj;
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	const struct drm_display_mode *adjusted_mode;
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	unsigned int max_width, max_height;
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	if (!I915_HAS_FBC(dev)) {
		set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
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		return;
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	}
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	if (!i915_powersave) {
		if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
			DRM_DEBUG_KMS("fbc disabled per module param\n");
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		return;
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	}
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	/*
	 * If FBC is already on, we just have to verify that we can
	 * keep it that way...
	 * Need to disable if:
	 *   - more than one pipe is active
	 *   - changing FBC params (stride, fence, mode)
	 *   - new fb is too large to fit in compressed buffer
	 *   - going to an unsupported config (interlace, pixel multiply, etc.)
	 */
	list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
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		if (intel_crtc_active(tmp_crtc) &&
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		    to_intel_crtc(tmp_crtc)->primary_enabled) {
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			if (crtc) {
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				if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
					DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
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				goto out_disable;
			}
			crtc = tmp_crtc;
		}
	}

	if (!crtc || crtc->fb == NULL) {
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		if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
			DRM_DEBUG_KMS("no output, disabling\n");
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		goto out_disable;
	}

	intel_crtc = to_intel_crtc(crtc);
	fb = crtc->fb;
	intel_fb = to_intel_framebuffer(fb);
	obj = intel_fb->obj;
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	adjusted_mode = &intel_crtc->config.adjusted_mode;
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	if (i915_enable_fbc < 0 &&
	    INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
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		if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
			DRM_DEBUG_KMS("disabled per chip default\n");
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		goto out_disable;
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	}
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	if (!i915_enable_fbc) {
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		if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
			DRM_DEBUG_KMS("fbc disabled per module param\n");
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		goto out_disable;
	}
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	if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
	    (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
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		if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
			DRM_DEBUG_KMS("mode incompatible with compression, "
				      "disabling\n");
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		goto out_disable;
	}
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	if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
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		max_width = 4096;
		max_height = 2048;
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	} else {
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		max_width = 2048;
		max_height = 1536;
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	}
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	if (intel_crtc->config.pipe_src_w > max_width ||
	    intel_crtc->config.pipe_src_h > max_height) {
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		if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
			DRM_DEBUG_KMS("mode too large for compression, disabling\n");
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		goto out_disable;
	}
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	if ((INTEL_INFO(dev)->gen < 4 || IS_HASWELL(dev)) &&
	    intel_crtc->plane != PLANE_A) {
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		if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
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			DRM_DEBUG_KMS("plane not A, disabling compression\n");
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		goto out_disable;
	}

	/* The use of a CPU fence is mandatory in order to detect writes
	 * by the CPU to the scanout and trigger updates to the FBC.
	 */
	if (obj->tiling_mode != I915_TILING_X ||
	    obj->fence_reg == I915_FENCE_REG_NONE) {
554 555
		if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
			DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
556 557 558 559 560 561 562
		goto out_disable;
	}

	/* If the kernel debugger is active, always disable compression */
	if (in_dbg_master())
		goto out_disable;

563
	if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
564 565
		if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
			DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
566 567 568
		goto out_disable;
	}

569 570 571 572 573
	/* If the scanout has not changed, don't modify the FBC settings.
	 * Note that we make the fundamental assumption that the fb->obj
	 * cannot be unpinned (and have its GTT offset and fence revoked)
	 * without first being decoupled from the scanout and FBC disabled.
	 */
574 575 576
	if (dev_priv->fbc.plane == intel_crtc->plane &&
	    dev_priv->fbc.fb_id == fb->base.id &&
	    dev_priv->fbc.y == crtc->y)
577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607
		return;

	if (intel_fbc_enabled(dev)) {
		/* We update FBC along two paths, after changing fb/crtc
		 * configuration (modeswitching) and after page-flipping
		 * finishes. For the latter, we know that not only did
		 * we disable the FBC at the start of the page-flip
		 * sequence, but also more than one vblank has passed.
		 *
		 * For the former case of modeswitching, it is possible
		 * to switch between two FBC valid configurations
		 * instantaneously so we do need to disable the FBC
		 * before we can modify its control registers. We also
		 * have to wait for the next vblank for that to take
		 * effect. However, since we delay enabling FBC we can
		 * assume that a vblank has passed since disabling and
		 * that we can safely alter the registers in the deferred
		 * callback.
		 *
		 * In the scenario that we go from a valid to invalid
		 * and then back to valid FBC configuration we have
		 * no strict enforcement that a vblank occurred since
		 * disabling the FBC. However, along all current pipe
		 * disabling paths we do need to wait for a vblank at
		 * some point. And we wait before enabling FBC anyway.
		 */
		DRM_DEBUG_KMS("disabling active FBC for update\n");
		intel_disable_fbc(dev);
	}

	intel_enable_fbc(crtc, 500);
608
	dev_priv->fbc.no_fbc_reason = FBC_OK;
609 610 611 612 613 614 615 616
	return;

out_disable:
	/* Multiple disables should be harmless */
	if (intel_fbc_enabled(dev)) {
		DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
		intel_disable_fbc(dev);
	}
617
	i915_gem_stolen_cleanup_compression(dev);
618 619
}

620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686
static void i915_pineview_get_mem_freq(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	u32 tmp;

	tmp = I915_READ(CLKCFG);

	switch (tmp & CLKCFG_FSB_MASK) {
	case CLKCFG_FSB_533:
		dev_priv->fsb_freq = 533; /* 133*4 */
		break;
	case CLKCFG_FSB_800:
		dev_priv->fsb_freq = 800; /* 200*4 */
		break;
	case CLKCFG_FSB_667:
		dev_priv->fsb_freq =  667; /* 167*4 */
		break;
	case CLKCFG_FSB_400:
		dev_priv->fsb_freq = 400; /* 100*4 */
		break;
	}

	switch (tmp & CLKCFG_MEM_MASK) {
	case CLKCFG_MEM_533:
		dev_priv->mem_freq = 533;
		break;
	case CLKCFG_MEM_667:
		dev_priv->mem_freq = 667;
		break;
	case CLKCFG_MEM_800:
		dev_priv->mem_freq = 800;
		break;
	}

	/* detect pineview DDR3 setting */
	tmp = I915_READ(CSHRDDR3CTL);
	dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
}

static void i915_ironlake_get_mem_freq(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	u16 ddrpll, csipll;

	ddrpll = I915_READ16(DDRMPLL1);
	csipll = I915_READ16(CSIPLL0);

	switch (ddrpll & 0xff) {
	case 0xc:
		dev_priv->mem_freq = 800;
		break;
	case 0x10:
		dev_priv->mem_freq = 1066;
		break;
	case 0x14:
		dev_priv->mem_freq = 1333;
		break;
	case 0x18:
		dev_priv->mem_freq = 1600;
		break;
	default:
		DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
				 ddrpll & 0xff);
		dev_priv->mem_freq = 0;
		break;
	}

687
	dev_priv->ips.r_t = dev_priv->mem_freq;
688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718

	switch (csipll & 0x3ff) {
	case 0x00c:
		dev_priv->fsb_freq = 3200;
		break;
	case 0x00e:
		dev_priv->fsb_freq = 3733;
		break;
	case 0x010:
		dev_priv->fsb_freq = 4266;
		break;
	case 0x012:
		dev_priv->fsb_freq = 4800;
		break;
	case 0x014:
		dev_priv->fsb_freq = 5333;
		break;
	case 0x016:
		dev_priv->fsb_freq = 5866;
		break;
	case 0x018:
		dev_priv->fsb_freq = 6400;
		break;
	default:
		DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
				 csipll & 0x3ff);
		dev_priv->fsb_freq = 0;
		break;
	}

	if (dev_priv->fsb_freq == 3200) {
719
		dev_priv->ips.c_m = 0;
720
	} else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
721
		dev_priv->ips.c_m = 1;
722
	} else {
723
		dev_priv->ips.c_m = 2;
724 725 726
	}
}

727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764
static const struct cxsr_latency cxsr_latency_table[] = {
	{1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
	{1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
	{1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
	{1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
	{1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */

	{1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
	{1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
	{1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
	{1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
	{1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */

	{1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
	{1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
	{1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
	{1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
	{1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */

	{0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
	{0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
	{0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
	{0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
	{0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */

	{0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
	{0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
	{0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
	{0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
	{0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */

	{0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
	{0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
	{0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
	{0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
	{0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
};

765
static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788
							 int is_ddr3,
							 int fsb,
							 int mem)
{
	const struct cxsr_latency *latency;
	int i;

	if (fsb == 0 || mem == 0)
		return NULL;

	for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
		latency = &cxsr_latency_table[i];
		if (is_desktop == latency->is_desktop &&
		    is_ddr3 == latency->is_ddr3 &&
		    fsb == latency->fsb_freq && mem == latency->mem_freq)
			return latency;
	}

	DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");

	return NULL;
}

789
static void pineview_disable_cxsr(struct drm_device *dev)
790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* deactivate cxsr */
	I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
}

/*
 * Latency for FIFO fetches is dependent on several factors:
 *   - memory configuration (speed, channels)
 *   - chipset
 *   - current MCH state
 * It can be fairly high in some situations, so here we assume a fairly
 * pessimal value.  It's a tradeoff between extra memory fetches (if we
 * set this value too high, the FIFO will fetch frequently to stay full)
 * and power consumption (set it too low to save power and we might see
 * FIFO underruns and display "flicker").
 *
 * A value of 5us seems to be a good balance; safe for very low end
 * platforms but not overly aggressive on lower latency configs.
 */
static const int latency_ns = 5000;

813
static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
814 815 816 817 818 819 820 821 822 823 824 825 826 827 828
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dsparb = I915_READ(DSPARB);
	int size;

	size = dsparb & 0x7f;
	if (plane)
		size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;

	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
		      plane ? "B" : "A", size);

	return size;
}

829
static int i85x_get_fifo_size(struct drm_device *dev, int plane)
830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dsparb = I915_READ(DSPARB);
	int size;

	size = dsparb & 0x1ff;
	if (plane)
		size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
	size >>= 1; /* Convert to cachelines */

	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
		      plane ? "B" : "A", size);

	return size;
}

846
static int i845_get_fifo_size(struct drm_device *dev, int plane)
847 848 849 850 851 852 853 854 855 856 857 858 859 860 861
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dsparb = I915_READ(DSPARB);
	int size;

	size = dsparb & 0x7f;
	size >>= 2; /* Convert to cachelines */

	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
		      plane ? "B" : "A",
		      size);

	return size;
}

862
static int i830_get_fifo_size(struct drm_device *dev, int plane)
863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dsparb = I915_READ(DSPARB);
	int size;

	size = dsparb & 0x7f;
	size >>= 1; /* Convert to cachelines */

	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
		      plane ? "B" : "A", size);

	return size;
}

/* Pineview has different values for various configs */
static const struct intel_watermark_params pineview_display_wm = {
	PINEVIEW_DISPLAY_FIFO,
	PINEVIEW_MAX_WM,
	PINEVIEW_DFT_WM,
	PINEVIEW_GUARD_WM,
	PINEVIEW_FIFO_LINE_SIZE
};
static const struct intel_watermark_params pineview_display_hplloff_wm = {
	PINEVIEW_DISPLAY_FIFO,
	PINEVIEW_MAX_WM,
	PINEVIEW_DFT_HPLLOFF_WM,
	PINEVIEW_GUARD_WM,
	PINEVIEW_FIFO_LINE_SIZE
};
static const struct intel_watermark_params pineview_cursor_wm = {
	PINEVIEW_CURSOR_FIFO,
	PINEVIEW_CURSOR_MAX_WM,
	PINEVIEW_CURSOR_DFT_WM,
	PINEVIEW_CURSOR_GUARD_WM,
	PINEVIEW_FIFO_LINE_SIZE,
};
static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
	PINEVIEW_CURSOR_FIFO,
	PINEVIEW_CURSOR_MAX_WM,
	PINEVIEW_CURSOR_DFT_WM,
	PINEVIEW_CURSOR_GUARD_WM,
	PINEVIEW_FIFO_LINE_SIZE
};
static const struct intel_watermark_params g4x_wm_info = {
	G4X_FIFO_SIZE,
	G4X_MAX_WM,
	G4X_MAX_WM,
	2,
	G4X_FIFO_LINE_SIZE,
};
static const struct intel_watermark_params g4x_cursor_wm_info = {
	I965_CURSOR_FIFO,
	I965_CURSOR_MAX_WM,
	I965_CURSOR_DFT_WM,
	2,
	G4X_FIFO_LINE_SIZE,
};
static const struct intel_watermark_params valleyview_wm_info = {
	VALLEYVIEW_FIFO_SIZE,
	VALLEYVIEW_MAX_WM,
	VALLEYVIEW_MAX_WM,
	2,
	G4X_FIFO_LINE_SIZE,
};
static const struct intel_watermark_params valleyview_cursor_wm_info = {
	I965_CURSOR_FIFO,
	VALLEYVIEW_CURSOR_MAX_WM,
	I965_CURSOR_DFT_WM,
	2,
	G4X_FIFO_LINE_SIZE,
};
static const struct intel_watermark_params i965_cursor_wm_info = {
	I965_CURSOR_FIFO,
	I965_CURSOR_MAX_WM,
	I965_CURSOR_DFT_WM,
	2,
	I915_FIFO_LINE_SIZE,
};
static const struct intel_watermark_params i945_wm_info = {
	I945_FIFO_SIZE,
	I915_MAX_WM,
	1,
	2,
	I915_FIFO_LINE_SIZE
};
static const struct intel_watermark_params i915_wm_info = {
	I915_FIFO_SIZE,
	I915_MAX_WM,
	1,
	2,
	I915_FIFO_LINE_SIZE
};
static const struct intel_watermark_params i855_wm_info = {
	I855GM_FIFO_SIZE,
	I915_MAX_WM,
	1,
	2,
	I830_FIFO_LINE_SIZE
};
static const struct intel_watermark_params i830_wm_info = {
	I830_FIFO_SIZE,
	I915_MAX_WM,
	1,
	2,
	I830_FIFO_LINE_SIZE
};

static const struct intel_watermark_params ironlake_display_wm_info = {
	ILK_DISPLAY_FIFO,
	ILK_DISPLAY_MAXWM,
	ILK_DISPLAY_DFTWM,
	2,
	ILK_FIFO_LINE_SIZE
};
static const struct intel_watermark_params ironlake_cursor_wm_info = {
	ILK_CURSOR_FIFO,
	ILK_CURSOR_MAXWM,
	ILK_CURSOR_DFTWM,
	2,
	ILK_FIFO_LINE_SIZE
};
static const struct intel_watermark_params ironlake_display_srwm_info = {
	ILK_DISPLAY_SR_FIFO,
	ILK_DISPLAY_MAX_SRWM,
	ILK_DISPLAY_DFT_SRWM,
	2,
	ILK_FIFO_LINE_SIZE
};
static const struct intel_watermark_params ironlake_cursor_srwm_info = {
	ILK_CURSOR_SR_FIFO,
	ILK_CURSOR_MAX_SRWM,
	ILK_CURSOR_DFT_SRWM,
	2,
	ILK_FIFO_LINE_SIZE
};

static const struct intel_watermark_params sandybridge_display_wm_info = {
	SNB_DISPLAY_FIFO,
	SNB_DISPLAY_MAXWM,
	SNB_DISPLAY_DFTWM,
	2,
	SNB_FIFO_LINE_SIZE
};
static const struct intel_watermark_params sandybridge_cursor_wm_info = {
	SNB_CURSOR_FIFO,
	SNB_CURSOR_MAXWM,
	SNB_CURSOR_DFTWM,
	2,
	SNB_FIFO_LINE_SIZE
};
static const struct intel_watermark_params sandybridge_display_srwm_info = {
	SNB_DISPLAY_SR_FIFO,
	SNB_DISPLAY_MAX_SRWM,
	SNB_DISPLAY_DFT_SRWM,
	2,
	SNB_FIFO_LINE_SIZE
};
static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
	SNB_CURSOR_SR_FIFO,
	SNB_CURSOR_MAX_SRWM,
	SNB_CURSOR_DFT_SRWM,
	2,
	SNB_FIFO_LINE_SIZE
};


/**
 * intel_calculate_wm - calculate watermark level
 * @clock_in_khz: pixel clock
 * @wm: chip FIFO params
 * @pixel_size: display pixel size
 * @latency_ns: memory latency for the platform
 *
 * Calculate the watermark level (the level at which the display plane will
 * start fetching from memory again).  Each chip has a different display
 * FIFO size and allocation, so the caller needs to figure that out and pass
 * in the correct intel_watermark_params structure.
 *
 * As the pixel clock runs, the FIFO will be drained at a rate that depends
 * on the pixel size.  When it reaches the watermark level, it'll start
 * fetching FIFO line sized based chunks from memory until the FIFO fills
 * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 * will occur, and a display engine hang could result.
 */
static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
					const struct intel_watermark_params *wm,
					int fifo_size,
					int pixel_size,
					unsigned long latency_ns)
{
	long entries_required, wm_size;

	/*
	 * Note: we need to make sure we don't overflow for various clock &
	 * latency values.
	 * clocks go from a few thousand to several hundred thousand.
	 * latency is usually a few thousand
	 */
	entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
		1000;
	entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);

	DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);

	wm_size = fifo_size - (entries_required + wm->guard_size);

	DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);

	/* Don't promote wm_size to unsigned... */
	if (wm_size > (long)wm->max_wm)
		wm_size = wm->max_wm;
	if (wm_size <= 0)
		wm_size = wm->default_wm;
	return wm_size;
}

static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
{
	struct drm_crtc *crtc, *enabled = NULL;

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1084
		if (intel_crtc_active(crtc)) {
1085 1086 1087 1088 1089 1090 1091 1092 1093
			if (enabled)
				return NULL;
			enabled = crtc;
		}
	}

	return enabled;
}

1094
static void pineview_update_wm(struct drm_crtc *unused_crtc)
1095
{
1096
	struct drm_device *dev = unused_crtc->dev;
1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	const struct cxsr_latency *latency;
	u32 reg;
	unsigned long wm;

	latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
					 dev_priv->fsb_freq, dev_priv->mem_freq);
	if (!latency) {
		DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
		pineview_disable_cxsr(dev);
		return;
	}

	crtc = single_enabled_crtc(dev);
	if (crtc) {
1113
		const struct drm_display_mode *adjusted_mode;
1114
		int pixel_size = crtc->fb->bits_per_pixel / 8;
1115 1116 1117 1118
		int clock;

		adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
		clock = adjusted_mode->crtc_clock;
1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177

		/* Display SR */
		wm = intel_calculate_wm(clock, &pineview_display_wm,
					pineview_display_wm.fifo_size,
					pixel_size, latency->display_sr);
		reg = I915_READ(DSPFW1);
		reg &= ~DSPFW_SR_MASK;
		reg |= wm << DSPFW_SR_SHIFT;
		I915_WRITE(DSPFW1, reg);
		DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);

		/* cursor SR */
		wm = intel_calculate_wm(clock, &pineview_cursor_wm,
					pineview_display_wm.fifo_size,
					pixel_size, latency->cursor_sr);
		reg = I915_READ(DSPFW3);
		reg &= ~DSPFW_CURSOR_SR_MASK;
		reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
		I915_WRITE(DSPFW3, reg);

		/* Display HPLL off SR */
		wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
					pineview_display_hplloff_wm.fifo_size,
					pixel_size, latency->display_hpll_disable);
		reg = I915_READ(DSPFW3);
		reg &= ~DSPFW_HPLL_SR_MASK;
		reg |= wm & DSPFW_HPLL_SR_MASK;
		I915_WRITE(DSPFW3, reg);

		/* cursor HPLL off SR */
		wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
					pineview_display_hplloff_wm.fifo_size,
					pixel_size, latency->cursor_hpll_disable);
		reg = I915_READ(DSPFW3);
		reg &= ~DSPFW_HPLL_CURSOR_MASK;
		reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
		I915_WRITE(DSPFW3, reg);
		DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);

		/* activate cxsr */
		I915_WRITE(DSPFW3,
			   I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
		DRM_DEBUG_KMS("Self-refresh is enabled\n");
	} else {
		pineview_disable_cxsr(dev);
		DRM_DEBUG_KMS("Self-refresh is disabled\n");
	}
}

static bool g4x_compute_wm0(struct drm_device *dev,
			    int plane,
			    const struct intel_watermark_params *display,
			    int display_latency_ns,
			    const struct intel_watermark_params *cursor,
			    int cursor_latency_ns,
			    int *plane_wm,
			    int *cursor_wm)
{
	struct drm_crtc *crtc;
1178
	const struct drm_display_mode *adjusted_mode;
1179 1180 1181 1182 1183
	int htotal, hdisplay, clock, pixel_size;
	int line_time_us, line_count;
	int entries, tlb_miss;

	crtc = intel_get_crtc_for_plane(dev, plane);
1184
	if (!intel_crtc_active(crtc)) {
1185 1186 1187 1188 1189
		*cursor_wm = cursor->guard_size;
		*plane_wm = display->guard_size;
		return false;
	}

1190
	adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1191
	clock = adjusted_mode->crtc_clock;
1192
	htotal = adjusted_mode->htotal;
1193
	hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263
	pixel_size = crtc->fb->bits_per_pixel / 8;

	/* Use the small buffer method to calculate plane watermark */
	entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
	tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
	if (tlb_miss > 0)
		entries += tlb_miss;
	entries = DIV_ROUND_UP(entries, display->cacheline_size);
	*plane_wm = entries + display->guard_size;
	if (*plane_wm > (int)display->max_wm)
		*plane_wm = display->max_wm;

	/* Use the large buffer method to calculate cursor watermark */
	line_time_us = ((htotal * 1000) / clock);
	line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
	entries = line_count * 64 * pixel_size;
	tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
	if (tlb_miss > 0)
		entries += tlb_miss;
	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
	*cursor_wm = entries + cursor->guard_size;
	if (*cursor_wm > (int)cursor->max_wm)
		*cursor_wm = (int)cursor->max_wm;

	return true;
}

/*
 * Check the wm result.
 *
 * If any calculated watermark values is larger than the maximum value that
 * can be programmed into the associated watermark register, that watermark
 * must be disabled.
 */
static bool g4x_check_srwm(struct drm_device *dev,
			   int display_wm, int cursor_wm,
			   const struct intel_watermark_params *display,
			   const struct intel_watermark_params *cursor)
{
	DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
		      display_wm, cursor_wm);

	if (display_wm > display->max_wm) {
		DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
			      display_wm, display->max_wm);
		return false;
	}

	if (cursor_wm > cursor->max_wm) {
		DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
			      cursor_wm, cursor->max_wm);
		return false;
	}

	if (!(display_wm || cursor_wm)) {
		DRM_DEBUG_KMS("SR latency is 0, disabling\n");
		return false;
	}

	return true;
}

static bool g4x_compute_srwm(struct drm_device *dev,
			     int plane,
			     int latency_ns,
			     const struct intel_watermark_params *display,
			     const struct intel_watermark_params *cursor,
			     int *display_wm, int *cursor_wm)
{
	struct drm_crtc *crtc;
1264
	const struct drm_display_mode *adjusted_mode;
1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276
	int hdisplay, htotal, pixel_size, clock;
	unsigned long line_time_us;
	int line_count, line_size;
	int small, large;
	int entries;

	if (!latency_ns) {
		*display_wm = *cursor_wm = 0;
		return false;
	}

	crtc = intel_get_crtc_for_plane(dev, plane);
1277
	adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1278
	clock = adjusted_mode->crtc_clock;
1279
	htotal = adjusted_mode->htotal;
1280
	hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315
	pixel_size = crtc->fb->bits_per_pixel / 8;

	line_time_us = (htotal * 1000) / clock;
	line_count = (latency_ns / line_time_us + 1000) / 1000;
	line_size = hdisplay * pixel_size;

	/* Use the minimum of the small and large buffer method for primary */
	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
	large = line_count * line_size;

	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
	*display_wm = entries + display->guard_size;

	/* calculate the self-refresh watermark for display cursor */
	entries = line_count * pixel_size * 64;
	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
	*cursor_wm = entries + cursor->guard_size;

	return g4x_check_srwm(dev,
			      *display_wm, *cursor_wm,
			      display, cursor);
}

static bool vlv_compute_drain_latency(struct drm_device *dev,
				     int plane,
				     int *plane_prec_mult,
				     int *plane_dl,
				     int *cursor_prec_mult,
				     int *cursor_dl)
{
	struct drm_crtc *crtc;
	int clock, pixel_size;
	int entries;

	crtc = intel_get_crtc_for_plane(dev, plane);
1316
	if (!intel_crtc_active(crtc))
1317 1318
		return false;

1319
	clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380
	pixel_size = crtc->fb->bits_per_pixel / 8;	/* BPP */

	entries = (clock / 1000) * pixel_size;
	*plane_prec_mult = (entries > 256) ?
		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
	*plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
						     pixel_size);

	entries = (clock / 1000) * 4;	/* BPP is always 4 for cursor */
	*cursor_prec_mult = (entries > 256) ?
		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
	*cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);

	return true;
}

/*
 * Update drain latency registers of memory arbiter
 *
 * Valleyview SoC has a new memory arbiter and needs drain latency registers
 * to be programmed. Each plane has a drain latency multiplier and a drain
 * latency value.
 */

static void vlv_update_drain_latency(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int planea_prec, planea_dl, planeb_prec, planeb_dl;
	int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
	int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
							either 16 or 32 */

	/* For plane A, Cursor A */
	if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
				      &cursor_prec_mult, &cursora_dl)) {
		cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
			DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
		planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
			DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;

		I915_WRITE(VLV_DDL1, cursora_prec |
				(cursora_dl << DDL_CURSORA_SHIFT) |
				planea_prec | planea_dl);
	}

	/* For plane B, Cursor B */
	if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
				      &cursor_prec_mult, &cursorb_dl)) {
		cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
			DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
		planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
			DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;

		I915_WRITE(VLV_DDL2, cursorb_prec |
				(cursorb_dl << DDL_CURSORB_SHIFT) |
				planeb_prec | planeb_dl);
	}
}

#define single_plane_enabled(mask) is_power_of_2(mask)

1381
static void valleyview_update_wm(struct drm_crtc *crtc)
1382
{
1383
	struct drm_device *dev = crtc->dev;
1384 1385 1386 1387
	static const int sr_latency_ns = 12000;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
	int plane_sr, cursor_sr;
1388
	int ignore_plane_sr, ignore_cursor_sr;
1389 1390 1391 1392
	unsigned int enabled = 0;

	vlv_update_drain_latency(dev);

1393
	if (g4x_compute_wm0(dev, PIPE_A,
1394 1395 1396
			    &valleyview_wm_info, latency_ns,
			    &valleyview_cursor_wm_info, latency_ns,
			    &planea_wm, &cursora_wm))
1397
		enabled |= 1 << PIPE_A;
1398

1399
	if (g4x_compute_wm0(dev, PIPE_B,
1400 1401 1402
			    &valleyview_wm_info, latency_ns,
			    &valleyview_cursor_wm_info, latency_ns,
			    &planeb_wm, &cursorb_wm))
1403
		enabled |= 1 << PIPE_B;
1404 1405 1406 1407 1408 1409

	if (single_plane_enabled(enabled) &&
	    g4x_compute_srwm(dev, ffs(enabled) - 1,
			     sr_latency_ns,
			     &valleyview_wm_info,
			     &valleyview_cursor_wm_info,
1410 1411 1412 1413 1414
			     &plane_sr, &ignore_cursor_sr) &&
	    g4x_compute_srwm(dev, ffs(enabled) - 1,
			     2*sr_latency_ns,
			     &valleyview_wm_info,
			     &valleyview_cursor_wm_info,
1415
			     &ignore_plane_sr, &cursor_sr)) {
1416
		I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1417
	} else {
1418 1419
		I915_WRITE(FW_BLC_SELF_VLV,
			   I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1420 1421
		plane_sr = cursor_sr = 0;
	}
1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433

	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
		      planea_wm, cursora_wm,
		      planeb_wm, cursorb_wm,
		      plane_sr, cursor_sr);

	I915_WRITE(DSPFW1,
		   (plane_sr << DSPFW_SR_SHIFT) |
		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
		   planea_wm);
	I915_WRITE(DSPFW2,
1434
		   (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1435 1436
		   (cursora_wm << DSPFW_CURSORA_SHIFT));
	I915_WRITE(DSPFW3,
1437 1438
		   (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
		   (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1439 1440
}

1441
static void g4x_update_wm(struct drm_crtc *crtc)
1442
{
1443
	struct drm_device *dev = crtc->dev;
1444 1445 1446 1447 1448 1449
	static const int sr_latency_ns = 12000;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
	int plane_sr, cursor_sr;
	unsigned int enabled = 0;

1450
	if (g4x_compute_wm0(dev, PIPE_A,
1451 1452 1453
			    &g4x_wm_info, latency_ns,
			    &g4x_cursor_wm_info, latency_ns,
			    &planea_wm, &cursora_wm))
1454
		enabled |= 1 << PIPE_A;
1455

1456
	if (g4x_compute_wm0(dev, PIPE_B,
1457 1458 1459
			    &g4x_wm_info, latency_ns,
			    &g4x_cursor_wm_info, latency_ns,
			    &planeb_wm, &cursorb_wm))
1460
		enabled |= 1 << PIPE_B;
1461 1462 1463 1464 1465 1466

	if (single_plane_enabled(enabled) &&
	    g4x_compute_srwm(dev, ffs(enabled) - 1,
			     sr_latency_ns,
			     &g4x_wm_info,
			     &g4x_cursor_wm_info,
1467
			     &plane_sr, &cursor_sr)) {
1468
		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1469
	} else {
1470 1471
		I915_WRITE(FW_BLC_SELF,
			   I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1472 1473
		plane_sr = cursor_sr = 0;
	}
1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485

	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
		      planea_wm, cursora_wm,
		      planeb_wm, cursorb_wm,
		      plane_sr, cursor_sr);

	I915_WRITE(DSPFW1,
		   (plane_sr << DSPFW_SR_SHIFT) |
		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
		   planea_wm);
	I915_WRITE(DSPFW2,
1486
		   (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1487 1488 1489
		   (cursora_wm << DSPFW_CURSORA_SHIFT));
	/* HPLL off in SR has some issues on G4x... disable it */
	I915_WRITE(DSPFW3,
1490
		   (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1491 1492 1493
		   (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
}

1494
static void i965_update_wm(struct drm_crtc *unused_crtc)
1495
{
1496
	struct drm_device *dev = unused_crtc->dev;
1497 1498 1499 1500 1501 1502 1503 1504 1505 1506
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	int srwm = 1;
	int cursor_sr = 16;

	/* Calc sr entries for one plane configs */
	crtc = single_enabled_crtc(dev);
	if (crtc) {
		/* self-refresh has much higher latency */
		static const int sr_latency_ns = 12000;
1507 1508
		const struct drm_display_mode *adjusted_mode =
			&to_intel_crtc(crtc)->config.adjusted_mode;
1509
		int clock = adjusted_mode->crtc_clock;
1510
		int htotal = adjusted_mode->htotal;
1511
		int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561
		int pixel_size = crtc->fb->bits_per_pixel / 8;
		unsigned long line_time_us;
		int entries;

		line_time_us = ((htotal * 1000) / clock);

		/* Use ns/us then divide to preserve precision */
		entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
			pixel_size * hdisplay;
		entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
		srwm = I965_FIFO_SIZE - entries;
		if (srwm < 0)
			srwm = 1;
		srwm &= 0x1ff;
		DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
			      entries, srwm);

		entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
			pixel_size * 64;
		entries = DIV_ROUND_UP(entries,
					  i965_cursor_wm_info.cacheline_size);
		cursor_sr = i965_cursor_wm_info.fifo_size -
			(entries + i965_cursor_wm_info.guard_size);

		if (cursor_sr > i965_cursor_wm_info.max_wm)
			cursor_sr = i965_cursor_wm_info.max_wm;

		DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
			      "cursor %d\n", srwm, cursor_sr);

		if (IS_CRESTLINE(dev))
			I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
	} else {
		/* Turn off self refresh if both pipes are enabled */
		if (IS_CRESTLINE(dev))
			I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
				   & ~FW_BLC_SELF_EN);
	}

	DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
		      srwm);

	/* 965 has limitations... */
	I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
		   (8 << 16) | (8 << 8) | (8 << 0));
	I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
	/* update cursor SR watermark */
	I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
}

1562
static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1563
{
1564
	struct drm_device *dev = unused_crtc->dev;
1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582
	struct drm_i915_private *dev_priv = dev->dev_private;
	const struct intel_watermark_params *wm_info;
	uint32_t fwater_lo;
	uint32_t fwater_hi;
	int cwm, srwm = 1;
	int fifo_size;
	int planea_wm, planeb_wm;
	struct drm_crtc *crtc, *enabled = NULL;

	if (IS_I945GM(dev))
		wm_info = &i945_wm_info;
	else if (!IS_GEN2(dev))
		wm_info = &i915_wm_info;
	else
		wm_info = &i855_wm_info;

	fifo_size = dev_priv->display.get_fifo_size(dev, 0);
	crtc = intel_get_crtc_for_plane(dev, 0);
1583
	if (intel_crtc_active(crtc)) {
1584
		const struct drm_display_mode *adjusted_mode;
1585 1586 1587 1588
		int cpp = crtc->fb->bits_per_pixel / 8;
		if (IS_GEN2(dev))
			cpp = 4;

1589 1590
		adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
		planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1591
					       wm_info, fifo_size, cpp,
1592 1593 1594 1595 1596 1597 1598
					       latency_ns);
		enabled = crtc;
	} else
		planea_wm = fifo_size - wm_info->guard_size;

	fifo_size = dev_priv->display.get_fifo_size(dev, 1);
	crtc = intel_get_crtc_for_plane(dev, 1);
1599
	if (intel_crtc_active(crtc)) {
1600
		const struct drm_display_mode *adjusted_mode;
1601 1602 1603 1604
		int cpp = crtc->fb->bits_per_pixel / 8;
		if (IS_GEN2(dev))
			cpp = 4;

1605 1606
		adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
		planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1607
					       wm_info, fifo_size, cpp,
1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632
					       latency_ns);
		if (enabled == NULL)
			enabled = crtc;
		else
			enabled = NULL;
	} else
		planeb_wm = fifo_size - wm_info->guard_size;

	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);

	/*
	 * Overlay gets an aggressive default since video jitter is bad.
	 */
	cwm = 2;

	/* Play safe and disable self-refresh before adjusting watermarks. */
	if (IS_I945G(dev) || IS_I945GM(dev))
		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
	else if (IS_I915GM(dev))
		I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);

	/* Calc sr entries for one plane configs */
	if (HAS_FW_BLC(dev) && enabled) {
		/* self-refresh has much higher latency */
		static const int sr_latency_ns = 6000;
1633 1634
		const struct drm_display_mode *adjusted_mode =
			&to_intel_crtc(enabled)->config.adjusted_mode;
1635
		int clock = adjusted_mode->crtc_clock;
1636
		int htotal = adjusted_mode->htotal;
1637
		int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685
		int pixel_size = enabled->fb->bits_per_pixel / 8;
		unsigned long line_time_us;
		int entries;

		line_time_us = (htotal * 1000) / clock;

		/* Use ns/us then divide to preserve precision */
		entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
			pixel_size * hdisplay;
		entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
		DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
		srwm = wm_info->fifo_size - entries;
		if (srwm < 0)
			srwm = 1;

		if (IS_I945G(dev) || IS_I945GM(dev))
			I915_WRITE(FW_BLC_SELF,
				   FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
		else if (IS_I915GM(dev))
			I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
	}

	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
		      planea_wm, planeb_wm, cwm, srwm);

	fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
	fwater_hi = (cwm & 0x1f);

	/* Set request length to 8 cachelines per fetch */
	fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
	fwater_hi = fwater_hi | (1 << 8);

	I915_WRITE(FW_BLC, fwater_lo);
	I915_WRITE(FW_BLC2, fwater_hi);

	if (HAS_FW_BLC(dev)) {
		if (enabled) {
			if (IS_I945G(dev) || IS_I945GM(dev))
				I915_WRITE(FW_BLC_SELF,
					   FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
			else if (IS_I915GM(dev))
				I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
			DRM_DEBUG_KMS("memory self refresh enabled\n");
		} else
			DRM_DEBUG_KMS("memory self refresh disabled\n");
	}
}

1686
static void i830_update_wm(struct drm_crtc *unused_crtc)
1687
{
1688
	struct drm_device *dev = unused_crtc->dev;
1689 1690
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
1691
	const struct drm_display_mode *adjusted_mode;
1692 1693 1694 1695 1696 1697 1698
	uint32_t fwater_lo;
	int planea_wm;

	crtc = single_enabled_crtc(dev);
	if (crtc == NULL)
		return;

1699 1700
	adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
	planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1701
				       &i830_wm_info,
1702
				       dev_priv->display.get_fifo_size(dev, 0),
1703
				       4, latency_ns);
1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736
	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
	fwater_lo |= (3<<8) | planea_wm;

	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);

	I915_WRITE(FW_BLC, fwater_lo);
}

/*
 * Check the wm result.
 *
 * If any calculated watermark values is larger than the maximum value that
 * can be programmed into the associated watermark register, that watermark
 * must be disabled.
 */
static bool ironlake_check_srwm(struct drm_device *dev, int level,
				int fbc_wm, int display_wm, int cursor_wm,
				const struct intel_watermark_params *display,
				const struct intel_watermark_params *cursor)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
		      " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);

	if (fbc_wm > SNB_FBC_MAX_SRWM) {
		DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
			      fbc_wm, SNB_FBC_MAX_SRWM, level);

		/* fbc has it's own way to disable FBC WM */
		I915_WRITE(DISP_ARB_CTL,
			   I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
		return false;
1737 1738 1739 1740
	} else if (INTEL_INFO(dev)->gen >= 6) {
		/* enable FBC WM (except on ILK, where it must remain off) */
		I915_WRITE(DISP_ARB_CTL,
			   I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772
	}

	if (display_wm > display->max_wm) {
		DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
			      display_wm, SNB_DISPLAY_MAX_SRWM, level);
		return false;
	}

	if (cursor_wm > cursor->max_wm) {
		DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
			      cursor_wm, SNB_CURSOR_MAX_SRWM, level);
		return false;
	}

	if (!(fbc_wm || display_wm || cursor_wm)) {
		DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
		return false;
	}

	return true;
}

/*
 * Compute watermark values of WM[1-3],
 */
static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
				  int latency_ns,
				  const struct intel_watermark_params *display,
				  const struct intel_watermark_params *cursor,
				  int *fbc_wm, int *display_wm, int *cursor_wm)
{
	struct drm_crtc *crtc;
1773
	const struct drm_display_mode *adjusted_mode;
1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785
	unsigned long line_time_us;
	int hdisplay, htotal, pixel_size, clock;
	int line_count, line_size;
	int small, large;
	int entries;

	if (!latency_ns) {
		*fbc_wm = *display_wm = *cursor_wm = 0;
		return false;
	}

	crtc = intel_get_crtc_for_plane(dev, plane);
1786
	adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1787
	clock = adjusted_mode->crtc_clock;
1788
	htotal = adjusted_mode->htotal;
1789
	hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818
	pixel_size = crtc->fb->bits_per_pixel / 8;

	line_time_us = (htotal * 1000) / clock;
	line_count = (latency_ns / line_time_us + 1000) / 1000;
	line_size = hdisplay * pixel_size;

	/* Use the minimum of the small and large buffer method for primary */
	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
	large = line_count * line_size;

	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
	*display_wm = entries + display->guard_size;

	/*
	 * Spec says:
	 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
	 */
	*fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;

	/* calculate the self-refresh watermark for display cursor */
	entries = line_count * pixel_size * 64;
	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
	*cursor_wm = entries + cursor->guard_size;

	return ironlake_check_srwm(dev, level,
				   *fbc_wm, *display_wm, *cursor_wm,
				   display, cursor);
}

1819
static void ironlake_update_wm(struct drm_crtc *crtc)
1820
{
1821
	struct drm_device *dev = crtc->dev;
1822 1823 1824 1825 1826
	struct drm_i915_private *dev_priv = dev->dev_private;
	int fbc_wm, plane_wm, cursor_wm;
	unsigned int enabled;

	enabled = 0;
1827
	if (g4x_compute_wm0(dev, PIPE_A,
1828
			    &ironlake_display_wm_info,
1829
			    dev_priv->wm.pri_latency[0] * 100,
1830
			    &ironlake_cursor_wm_info,
1831
			    dev_priv->wm.cur_latency[0] * 100,
1832 1833 1834 1835 1836 1837
			    &plane_wm, &cursor_wm)) {
		I915_WRITE(WM0_PIPEA_ILK,
			   (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
		DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
			      " plane %d, " "cursor: %d\n",
			      plane_wm, cursor_wm);
1838
		enabled |= 1 << PIPE_A;
1839 1840
	}

1841
	if (g4x_compute_wm0(dev, PIPE_B,
1842
			    &ironlake_display_wm_info,
1843
			    dev_priv->wm.pri_latency[0] * 100,
1844
			    &ironlake_cursor_wm_info,
1845
			    dev_priv->wm.cur_latency[0] * 100,
1846 1847 1848 1849 1850 1851
			    &plane_wm, &cursor_wm)) {
		I915_WRITE(WM0_PIPEB_ILK,
			   (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
		DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
			      " plane %d, cursor: %d\n",
			      plane_wm, cursor_wm);
1852
		enabled |= 1 << PIPE_B;
1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868
	}

	/*
	 * Calculate and update the self-refresh watermark only when one
	 * display plane is used.
	 */
	I915_WRITE(WM3_LP_ILK, 0);
	I915_WRITE(WM2_LP_ILK, 0);
	I915_WRITE(WM1_LP_ILK, 0);

	if (!single_plane_enabled(enabled))
		return;
	enabled = ffs(enabled) - 1;

	/* WM1 */
	if (!ironlake_compute_srwm(dev, 1, enabled,
1869
				   dev_priv->wm.pri_latency[1] * 500,
1870 1871 1872 1873 1874 1875 1876
				   &ironlake_display_srwm_info,
				   &ironlake_cursor_srwm_info,
				   &fbc_wm, &plane_wm, &cursor_wm))
		return;

	I915_WRITE(WM1_LP_ILK,
		   WM1_LP_SR_EN |
1877
		   (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1878 1879 1880 1881 1882 1883
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
		   (plane_wm << WM1_LP_SR_SHIFT) |
		   cursor_wm);

	/* WM2 */
	if (!ironlake_compute_srwm(dev, 2, enabled,
1884
				   dev_priv->wm.pri_latency[2] * 500,
1885 1886 1887 1888 1889 1890 1891
				   &ironlake_display_srwm_info,
				   &ironlake_cursor_srwm_info,
				   &fbc_wm, &plane_wm, &cursor_wm))
		return;

	I915_WRITE(WM2_LP_ILK,
		   WM2_LP_EN |
1892
		   (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1893 1894 1895 1896 1897 1898 1899 1900 1901 1902
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
		   (plane_wm << WM1_LP_SR_SHIFT) |
		   cursor_wm);

	/*
	 * WM3 is unsupported on ILK, probably because we don't have latency
	 * data for that power state
	 */
}

1903
static void sandybridge_update_wm(struct drm_crtc *crtc)
1904
{
1905
	struct drm_device *dev = crtc->dev;
1906
	struct drm_i915_private *dev_priv = dev->dev_private;
1907
	int latency = dev_priv->wm.pri_latency[0] * 100;	/* In unit 0.1us */
1908 1909 1910 1911 1912
	u32 val;
	int fbc_wm, plane_wm, cursor_wm;
	unsigned int enabled;

	enabled = 0;
1913
	if (g4x_compute_wm0(dev, PIPE_A,
1914 1915 1916 1917 1918 1919 1920 1921 1922 1923
			    &sandybridge_display_wm_info, latency,
			    &sandybridge_cursor_wm_info, latency,
			    &plane_wm, &cursor_wm)) {
		val = I915_READ(WM0_PIPEA_ILK);
		val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
		I915_WRITE(WM0_PIPEA_ILK, val |
			   ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
		DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
			      " plane %d, " "cursor: %d\n",
			      plane_wm, cursor_wm);
1924
		enabled |= 1 << PIPE_A;
1925 1926
	}

1927
	if (g4x_compute_wm0(dev, PIPE_B,
1928 1929 1930 1931 1932 1933 1934 1935 1936 1937
			    &sandybridge_display_wm_info, latency,
			    &sandybridge_cursor_wm_info, latency,
			    &plane_wm, &cursor_wm)) {
		val = I915_READ(WM0_PIPEB_ILK);
		val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
		I915_WRITE(WM0_PIPEB_ILK, val |
			   ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
		DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
			      " plane %d, cursor: %d\n",
			      plane_wm, cursor_wm);
1938
		enabled |= 1 << PIPE_B;
1939 1940
	}

1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961
	/*
	 * Calculate and update the self-refresh watermark only when one
	 * display plane is used.
	 *
	 * SNB support 3 levels of watermark.
	 *
	 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
	 * and disabled in the descending order
	 *
	 */
	I915_WRITE(WM3_LP_ILK, 0);
	I915_WRITE(WM2_LP_ILK, 0);
	I915_WRITE(WM1_LP_ILK, 0);

	if (!single_plane_enabled(enabled) ||
	    dev_priv->sprite_scaling_enabled)
		return;
	enabled = ffs(enabled) - 1;

	/* WM1 */
	if (!ironlake_compute_srwm(dev, 1, enabled,
1962
				   dev_priv->wm.pri_latency[1] * 500,
1963 1964 1965 1966 1967 1968 1969
				   &sandybridge_display_srwm_info,
				   &sandybridge_cursor_srwm_info,
				   &fbc_wm, &plane_wm, &cursor_wm))
		return;

	I915_WRITE(WM1_LP_ILK,
		   WM1_LP_SR_EN |
1970
		   (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1971 1972 1973 1974 1975 1976
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
		   (plane_wm << WM1_LP_SR_SHIFT) |
		   cursor_wm);

	/* WM2 */
	if (!ironlake_compute_srwm(dev, 2, enabled,
1977
				   dev_priv->wm.pri_latency[2] * 500,
1978 1979 1980 1981 1982 1983 1984
				   &sandybridge_display_srwm_info,
				   &sandybridge_cursor_srwm_info,
				   &fbc_wm, &plane_wm, &cursor_wm))
		return;

	I915_WRITE(WM2_LP_ILK,
		   WM2_LP_EN |
1985
		   (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1986 1987 1988 1989 1990 1991
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
		   (plane_wm << WM1_LP_SR_SHIFT) |
		   cursor_wm);

	/* WM3 */
	if (!ironlake_compute_srwm(dev, 3, enabled,
1992
				   dev_priv->wm.pri_latency[3] * 500,
1993 1994 1995 1996 1997 1998 1999
				   &sandybridge_display_srwm_info,
				   &sandybridge_cursor_srwm_info,
				   &fbc_wm, &plane_wm, &cursor_wm))
		return;

	I915_WRITE(WM3_LP_ILK,
		   WM3_LP_EN |
2000
		   (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2001 2002 2003 2004 2005
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
		   (plane_wm << WM1_LP_SR_SHIFT) |
		   cursor_wm);
}

2006
static void ivybridge_update_wm(struct drm_crtc *crtc)
2007
{
2008
	struct drm_device *dev = crtc->dev;
2009
	struct drm_i915_private *dev_priv = dev->dev_private;
2010
	int latency = dev_priv->wm.pri_latency[0] * 100;	/* In unit 0.1us */
2011 2012 2013 2014 2015 2016
	u32 val;
	int fbc_wm, plane_wm, cursor_wm;
	int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
	unsigned int enabled;

	enabled = 0;
2017
	if (g4x_compute_wm0(dev, PIPE_A,
2018 2019 2020 2021 2022 2023 2024 2025 2026 2027
			    &sandybridge_display_wm_info, latency,
			    &sandybridge_cursor_wm_info, latency,
			    &plane_wm, &cursor_wm)) {
		val = I915_READ(WM0_PIPEA_ILK);
		val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
		I915_WRITE(WM0_PIPEA_ILK, val |
			   ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
		DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
			      " plane %d, " "cursor: %d\n",
			      plane_wm, cursor_wm);
2028
		enabled |= 1 << PIPE_A;
2029 2030
	}

2031
	if (g4x_compute_wm0(dev, PIPE_B,
2032 2033 2034 2035 2036 2037 2038 2039 2040 2041
			    &sandybridge_display_wm_info, latency,
			    &sandybridge_cursor_wm_info, latency,
			    &plane_wm, &cursor_wm)) {
		val = I915_READ(WM0_PIPEB_ILK);
		val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
		I915_WRITE(WM0_PIPEB_ILK, val |
			   ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
		DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
			      " plane %d, cursor: %d\n",
			      plane_wm, cursor_wm);
2042
		enabled |= 1 << PIPE_B;
2043 2044
	}

2045
	if (g4x_compute_wm0(dev, PIPE_C,
2046 2047 2048 2049 2050 2051 2052 2053 2054 2055
			    &sandybridge_display_wm_info, latency,
			    &sandybridge_cursor_wm_info, latency,
			    &plane_wm, &cursor_wm)) {
		val = I915_READ(WM0_PIPEC_IVB);
		val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
		I915_WRITE(WM0_PIPEC_IVB, val |
			   ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
		DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
			      " plane %d, cursor: %d\n",
			      plane_wm, cursor_wm);
2056
		enabled |= 1 << PIPE_C;
2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079
	}

	/*
	 * Calculate and update the self-refresh watermark only when one
	 * display plane is used.
	 *
	 * SNB support 3 levels of watermark.
	 *
	 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
	 * and disabled in the descending order
	 *
	 */
	I915_WRITE(WM3_LP_ILK, 0);
	I915_WRITE(WM2_LP_ILK, 0);
	I915_WRITE(WM1_LP_ILK, 0);

	if (!single_plane_enabled(enabled) ||
	    dev_priv->sprite_scaling_enabled)
		return;
	enabled = ffs(enabled) - 1;

	/* WM1 */
	if (!ironlake_compute_srwm(dev, 1, enabled,
2080
				   dev_priv->wm.pri_latency[1] * 500,
2081 2082 2083 2084 2085 2086 2087
				   &sandybridge_display_srwm_info,
				   &sandybridge_cursor_srwm_info,
				   &fbc_wm, &plane_wm, &cursor_wm))
		return;

	I915_WRITE(WM1_LP_ILK,
		   WM1_LP_SR_EN |
2088
		   (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
2089 2090 2091 2092 2093 2094
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
		   (plane_wm << WM1_LP_SR_SHIFT) |
		   cursor_wm);

	/* WM2 */
	if (!ironlake_compute_srwm(dev, 2, enabled,
2095
				   dev_priv->wm.pri_latency[2] * 500,
2096 2097 2098 2099 2100 2101 2102
				   &sandybridge_display_srwm_info,
				   &sandybridge_cursor_srwm_info,
				   &fbc_wm, &plane_wm, &cursor_wm))
		return;

	I915_WRITE(WM2_LP_ILK,
		   WM2_LP_EN |
2103
		   (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
2104 2105 2106 2107
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
		   (plane_wm << WM1_LP_SR_SHIFT) |
		   cursor_wm);

2108
	/* WM3, note we have to correct the cursor latency */
2109
	if (!ironlake_compute_srwm(dev, 3, enabled,
2110
				   dev_priv->wm.pri_latency[3] * 500,
2111 2112
				   &sandybridge_display_srwm_info,
				   &sandybridge_cursor_srwm_info,
2113 2114
				   &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
	    !ironlake_compute_srwm(dev, 3, enabled,
2115
				   dev_priv->wm.cur_latency[3] * 500,
2116 2117 2118
				   &sandybridge_display_srwm_info,
				   &sandybridge_cursor_srwm_info,
				   &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2119 2120 2121 2122
		return;

	I915_WRITE(WM3_LP_ILK,
		   WM3_LP_EN |
2123
		   (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2124 2125 2126 2127 2128
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
		   (plane_wm << WM1_LP_SR_SHIFT) |
		   cursor_wm);
}

2129 2130
static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
				    struct drm_crtc *crtc)
2131 2132
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133
	uint32_t pixel_rate;
2134

2135
	pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
2136 2137 2138 2139

	/* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
	 * adjust the pixel_rate here. */

2140
	if (intel_crtc->config.pch_pfit.enabled) {
2141
		uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2142
		uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
2143

2144 2145
		pipe_w = intel_crtc->config.pipe_src_w;
		pipe_h = intel_crtc->config.pipe_src_h;
2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159
		pfit_w = (pfit_size >> 16) & 0xFFFF;
		pfit_h = pfit_size & 0xFFFF;
		if (pipe_w < pfit_w)
			pipe_w = pfit_w;
		if (pipe_h < pfit_h)
			pipe_h = pfit_h;

		pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
				     pfit_w * pfit_h);
	}

	return pixel_rate;
}

2160
/* latency must be in 0.1us units. */
2161
static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2162 2163 2164 2165
			       uint32_t latency)
{
	uint64_t ret;

2166 2167 2168
	if (WARN(latency == 0, "Latency value missing\n"))
		return UINT_MAX;

2169 2170 2171 2172 2173 2174
	ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
	ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;

	return ret;
}

2175
/* latency must be in 0.1us units. */
2176
static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2177 2178 2179 2180 2181
			       uint32_t horiz_pixels, uint8_t bytes_per_pixel,
			       uint32_t latency)
{
	uint32_t ret;

2182 2183 2184
	if (WARN(latency == 0, "Latency value missing\n"))
		return UINT_MAX;

2185 2186 2187 2188 2189 2190
	ret = (latency * pixel_rate) / (pipe_htotal * 10000);
	ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
	ret = DIV_ROUND_UP(ret, 64) + 2;
	return ret;
}

2191
static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2192 2193 2194 2195 2196
			   uint8_t bytes_per_pixel)
{
	return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
}

2197 2198 2199 2200
struct hsw_pipe_wm_parameters {
	bool active;
	uint32_t pipe_htotal;
	uint32_t pixel_rate;
2201 2202 2203
	struct intel_plane_wm_parameters pri;
	struct intel_plane_wm_parameters spr;
	struct intel_plane_wm_parameters cur;
2204 2205
};

2206 2207 2208 2209 2210 2211 2212
struct hsw_wm_maximums {
	uint16_t pri;
	uint16_t spr;
	uint16_t cur;
	uint16_t fbc;
};

2213 2214 2215 2216 2217 2218 2219
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

2220 2221 2222 2223
/*
 * For both WM_PIPE and WM_LP.
 * mem_value must be in 0.1us units.
 */
2224
static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
2225 2226
				   uint32_t mem_value,
				   bool is_lp)
2227
{
2228 2229
	uint32_t method1, method2;

2230
	if (!params->active || !params->pri.enabled)
2231 2232
		return 0;

2233
	method1 = ilk_wm_method1(params->pixel_rate,
2234
				 params->pri.bytes_per_pixel,
2235 2236 2237 2238 2239
				 mem_value);

	if (!is_lp)
		return method1;

2240
	method2 = ilk_wm_method2(params->pixel_rate,
2241
				 params->pipe_htotal,
2242 2243
				 params->pri.horiz_pixels,
				 params->pri.bytes_per_pixel,
2244 2245 2246
				 mem_value);

	return min(method1, method2);
2247 2248
}

2249 2250 2251 2252
/*
 * For both WM_PIPE and WM_LP.
 * mem_value must be in 0.1us units.
 */
2253
static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
2254 2255 2256 2257
				   uint32_t mem_value)
{
	uint32_t method1, method2;

2258
	if (!params->active || !params->spr.enabled)
2259 2260
		return 0;

2261
	method1 = ilk_wm_method1(params->pixel_rate,
2262
				 params->spr.bytes_per_pixel,
2263
				 mem_value);
2264
	method2 = ilk_wm_method2(params->pixel_rate,
2265
				 params->pipe_htotal,
2266 2267
				 params->spr.horiz_pixels,
				 params->spr.bytes_per_pixel,
2268 2269 2270 2271
				 mem_value);
	return min(method1, method2);
}

2272 2273 2274 2275
/*
 * For both WM_PIPE and WM_LP.
 * mem_value must be in 0.1us units.
 */
2276
static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
2277 2278
				   uint32_t mem_value)
{
2279
	if (!params->active || !params->cur.enabled)
2280 2281
		return 0;

2282
	return ilk_wm_method2(params->pixel_rate,
2283
			      params->pipe_htotal,
2284 2285
			      params->cur.horiz_pixels,
			      params->cur.bytes_per_pixel,
2286 2287 2288
			      mem_value);
}

2289
/* Only for WM_LP. */
2290
static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
2291
				   uint32_t pri_val)
2292
{
2293
	if (!params->active || !params->pri.enabled)
2294 2295
		return 0;

2296
	return ilk_wm_fbc(pri_val,
2297 2298
			  params->pri.horiz_pixels,
			  params->pri.bytes_per_pixel);
2299 2300
}

2301 2302
static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
{
2303 2304 2305
	if (INTEL_INFO(dev)->gen >= 8)
		return 3072;
	else if (INTEL_INFO(dev)->gen >= 7)
2306 2307 2308 2309 2310 2311 2312 2313
		return 768;
	else
		return 512;
}

/* Calculate the maximum primary/sprite plane watermark */
static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
				     int level,
2314
				     const struct intel_wm_config *config,
2315 2316 2317 2318 2319 2320 2321
				     enum intel_ddb_partitioning ddb_partitioning,
				     bool is_sprite)
{
	unsigned int fifo_size = ilk_display_fifo_size(dev);
	unsigned int max;

	/* if sprites aren't enabled, sprites get nothing */
2322
	if (is_sprite && !config->sprites_enabled)
2323 2324 2325
		return 0;

	/* HSW allows LP1+ watermarks even with multiple pipes */
2326
	if (level == 0 || config->num_pipes_active > 1) {
2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337
		fifo_size /= INTEL_INFO(dev)->num_pipes;

		/*
		 * For some reason the non self refresh
		 * FIFO size is only half of the self
		 * refresh FIFO size on ILK/SNB.
		 */
		if (INTEL_INFO(dev)->gen <= 6)
			fifo_size /= 2;
	}

2338
	if (config->sprites_enabled) {
2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349
		/* level 0 is always calculated with 1:1 split */
		if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
			if (is_sprite)
				fifo_size *= 5;
			fifo_size /= 6;
		} else {
			fifo_size /= 2;
		}
	}

	/* clamp to max that the registers can hold */
2350 2351 2352
	if (INTEL_INFO(dev)->gen >= 8)
		max = level == 0 ? 255 : 2047;
	else if (INTEL_INFO(dev)->gen >= 7)
2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366
		/* IVB/HSW primary/sprite plane watermarks */
		max = level == 0 ? 127 : 1023;
	else if (!is_sprite)
		/* ILK/SNB primary plane watermarks */
		max = level == 0 ? 127 : 511;
	else
		/* ILK/SNB sprite plane watermarks */
		max = level == 0 ? 63 : 255;

	return min(fifo_size, max);
}

/* Calculate the maximum cursor plane watermark */
static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2367 2368
				      int level,
				      const struct intel_wm_config *config)
2369 2370
{
	/* HSW LP1+ watermarks w/ multiple pipes */
2371
	if (level > 0 && config->num_pipes_active > 1)
2372 2373 2374 2375 2376 2377 2378 2379 2380 2381
		return 64;

	/* otherwise just report max that registers can hold */
	if (INTEL_INFO(dev)->gen >= 7)
		return level == 0 ? 63 : 255;
	else
		return level == 0 ? 31 : 63;
}

/* Calculate the maximum FBC watermark */
2382
static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
2383 2384
{
	/* max that registers can hold */
2385 2386 2387 2388
	if (INTEL_INFO(dev)->gen >= 8)
		return 31;
	else
		return 15;
2389 2390
}

2391 2392 2393 2394 2395
static void ilk_compute_wm_maximums(struct drm_device *dev,
				    int level,
				    const struct intel_wm_config *config,
				    enum intel_ddb_partitioning ddb_partitioning,
				    struct hsw_wm_maximums *max)
2396
{
2397 2398 2399
	max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
	max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
	max->cur = ilk_cursor_wm_max(dev, level, config);
2400
	max->fbc = ilk_fbc_wm_max(dev);
2401 2402
}

2403 2404 2405
static bool ilk_validate_wm_level(int level,
				  const struct hsw_wm_maximums *max,
				  struct intel_wm_level *result)
2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443
{
	bool ret;

	/* already determined to be invalid? */
	if (!result->enable)
		return false;

	result->enable = result->pri_val <= max->pri &&
			 result->spr_val <= max->spr &&
			 result->cur_val <= max->cur;

	ret = result->enable;

	/*
	 * HACK until we can pre-compute everything,
	 * and thus fail gracefully if LP0 watermarks
	 * are exceeded...
	 */
	if (level == 0 && !result->enable) {
		if (result->pri_val > max->pri)
			DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
				      level, result->pri_val, max->pri);
		if (result->spr_val > max->spr)
			DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
				      level, result->spr_val, max->spr);
		if (result->cur_val > max->cur)
			DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
				      level, result->cur_val, max->cur);

		result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
		result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
		result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
		result->enable = true;
	}

	return ret;
}

2444 2445
static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
				 int level,
2446
				 const struct hsw_pipe_wm_parameters *p,
2447
				 struct intel_wm_level *result)
2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466
{
	uint16_t pri_latency = dev_priv->wm.pri_latency[level];
	uint16_t spr_latency = dev_priv->wm.spr_latency[level];
	uint16_t cur_latency = dev_priv->wm.cur_latency[level];

	/* WM1+ latency values stored in 0.5us units */
	if (level > 0) {
		pri_latency *= 5;
		spr_latency *= 5;
		cur_latency *= 5;
	}

	result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
	result->spr_val = ilk_compute_spr_wm(p, spr_latency);
	result->cur_val = ilk_compute_cur_wm(p, cur_latency);
	result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
	result->enable = true;
}

2467 2468
static uint32_t
hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2469 2470
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2471 2472
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2473
	u32 linetime, ips_linetime;
2474

2475 2476
	if (!intel_crtc_active(crtc))
		return 0;
2477

2478 2479 2480
	/* The WM are computed with base on how long it takes to fill a single
	 * row at the given clock rate, multiplied by 8.
	 * */
2481 2482 2483
	linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
	ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
					 intel_ddi_get_cdclk_freq(dev_priv));
2484

2485 2486
	return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
	       PIPE_WM_LINETIME_TIME(linetime);
2487 2488
}

2489 2490 2491 2492 2493 2494 2495 2496 2497 2498
static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (IS_HASWELL(dev)) {
		uint64_t sskpd = I915_READ64(MCH_SSKPD);

		wm[0] = (sskpd >> 56) & 0xFF;
		if (wm[0] == 0)
			wm[0] = sskpd & 0xF;
2499 2500 2501 2502
		wm[1] = (sskpd >> 4) & 0xFF;
		wm[2] = (sskpd >> 12) & 0xFF;
		wm[3] = (sskpd >> 20) & 0x1FF;
		wm[4] = (sskpd >> 32) & 0x1FF;
2503 2504 2505 2506 2507 2508 2509
	} else if (INTEL_INFO(dev)->gen >= 6) {
		uint32_t sskpd = I915_READ(MCH_SSKPD);

		wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
		wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
		wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
		wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2510 2511 2512 2513 2514 2515 2516
	} else if (INTEL_INFO(dev)->gen >= 5) {
		uint32_t mltr = I915_READ(MLTR_ILK);

		/* ILK primary LP0 latency is 700 ns */
		wm[0] = 7;
		wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
		wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2517 2518 2519
	}
}

2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537
static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
{
	/* ILK sprite LP0 latency is 1300 ns */
	if (INTEL_INFO(dev)->gen == 5)
		wm[0] = 13;
}

static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
{
	/* ILK cursor LP0 latency is 1300 ns */
	if (INTEL_INFO(dev)->gen == 5)
		wm[0] = 13;

	/* WaDoubleCursorLP3Latency:ivb */
	if (IS_IVYBRIDGE(dev))
		wm[3] *= 2;
}

2538
static int ilk_wm_max_level(const struct drm_device *dev)
2539 2540 2541
{
	/* how many WM levels are we expecting */
	if (IS_HASWELL(dev))
2542
		return 4;
2543
	else if (INTEL_INFO(dev)->gen >= 6)
2544
		return 3;
2545
	else
2546 2547 2548 2549 2550 2551 2552 2553
		return 2;
}

static void intel_print_wm_latency(struct drm_device *dev,
				   const char *name,
				   const uint16_t wm[5])
{
	int level, max_level = ilk_wm_max_level(dev);
2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573

	for (level = 0; level <= max_level; level++) {
		unsigned int latency = wm[level];

		if (latency == 0) {
			DRM_ERROR("%s WM%d latency not provided\n",
				  name, level);
			continue;
		}

		/* WM1+ latency values in 0.5us units */
		if (level > 0)
			latency *= 5;

		DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
			      name, level, wm[level],
			      latency / 10, latency % 10);
	}
}

2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586
static void intel_setup_wm_latency(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	intel_read_wm_latency(dev, dev_priv->wm.pri_latency);

	memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
	       sizeof(dev_priv->wm.pri_latency));
	memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
	       sizeof(dev_priv->wm.pri_latency));

	intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
	intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2587 2588 2589 2590

	intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
	intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
	intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2591 2592
}

2593 2594
static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
				      struct hsw_pipe_wm_parameters *p,
2595
				      struct intel_wm_config *config)
2596
{
2597 2598 2599 2600
	struct drm_device *dev = crtc->dev;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	enum pipe pipe = intel_crtc->pipe;
	struct drm_plane *plane;
2601

2602 2603
	p->active = intel_crtc_active(crtc);
	if (p->active) {
2604
		p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2605
		p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2606 2607
		p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
		p->cur.bytes_per_pixel = 4;
2608
		p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2609 2610 2611 2612
		p->cur.horiz_pixels = 64;
		/* TODO: for now, assume primary and cursor planes are always enabled. */
		p->pri.enabled = true;
		p->cur.enabled = true;
2613 2614
	}

2615
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2616
		config->num_pipes_active += intel_crtc_active(crtc);
2617

2618 2619 2620
	list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
		struct intel_plane *intel_plane = to_intel_plane(plane);

2621 2622
		if (intel_plane->pipe == pipe)
			p->spr = intel_plane->wm;
2623

2624 2625
		config->sprites_enabled |= intel_plane->wm.enabled;
		config->sprites_scaled |= intel_plane->wm.scaled;
2626
	}
2627 2628
}

2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645
/* Compute new watermarks for the pipe */
static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
				  const struct hsw_pipe_wm_parameters *params,
				  struct intel_pipe_wm *pipe_wm)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int level, max_level = ilk_wm_max_level(dev);
	/* LP0 watermark maximums depend on this pipe alone */
	struct intel_wm_config config = {
		.num_pipes_active = 1,
		.sprites_enabled = params->spr.enabled,
		.sprites_scaled = params->spr.scaled,
	};
	struct hsw_wm_maximums max;

	/* LP0 watermarks always use 1/2 DDB partitioning */
2646
	ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2647 2648 2649 2650 2651 2652 2653 2654

	for (level = 0; level <= max_level; level++)
		ilk_compute_wm_level(dev_priv, level, params,
				     &pipe_wm->wm[level]);

	pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);

	/* At least LP0 must be valid */
2655
	return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699
}

/*
 * Merge the watermarks from all active pipes for a specific level.
 */
static void ilk_merge_wm_level(struct drm_device *dev,
			       int level,
			       struct intel_wm_level *ret_wm)
{
	const struct intel_crtc *intel_crtc;

	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
		const struct intel_wm_level *wm =
			&intel_crtc->wm.active.wm[level];

		if (!wm->enable)
			return;

		ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
		ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
		ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
		ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
	}

	ret_wm->enable = true;
}

/*
 * Merge all low power watermarks for all active pipes.
 */
static void ilk_wm_merge(struct drm_device *dev,
			 const struct hsw_wm_maximums *max,
			 struct intel_pipe_wm *merged)
{
	int level, max_level = ilk_wm_max_level(dev);

	merged->fbc_wm_enabled = true;

	/* merge each WM1+ level */
	for (level = 1; level <= max_level; level++) {
		struct intel_wm_level *wm = &merged->wm[level];

		ilk_merge_wm_level(dev, level, wm);

2700
		if (!ilk_validate_wm_level(level, max, wm))
2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713
			break;

		/*
		 * The spec says it is preferred to disable
		 * FBC WMs instead of disabling a WM level.
		 */
		if (wm->fbc_val > max->fbc) {
			merged->fbc_wm_enabled = false;
			wm->fbc_val = 0;
		}
	}
}

2714 2715 2716 2717 2718 2719
static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
{
	/* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
	return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
}

2720
static void hsw_compute_wm_results(struct drm_device *dev,
2721
				   const struct intel_pipe_wm *merged,
2722
				   enum intel_ddb_partitioning partitioning,
2723 2724
				   struct hsw_wm_values *results)
{
2725 2726
	struct intel_crtc *intel_crtc;
	int level, wm_lp;
2727

2728
	results->enable_fbc_wm = merged->fbc_wm_enabled;
2729
	results->partitioning = partitioning;
2730

2731
	/* LP1+ register values */
2732
	for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2733
		const struct intel_wm_level *r;
2734

2735
		level = ilk_wm_lp_to_level(wm_lp, merged);
2736

2737
		r = &merged->wm[level];
2738
		if (!r->enable)
2739 2740
			break;

2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752
		results->wm_lp[wm_lp - 1] = WM3_LP_EN |
			((level * 2) << WM1_LP_LATENCY_SHIFT) |
			(r->pri_val << WM1_LP_SR_SHIFT) |
			r->cur_val;

		if (INTEL_INFO(dev)->gen >= 8)
			results->wm_lp[wm_lp - 1] |=
				r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
		else
			results->wm_lp[wm_lp - 1] |=
				r->fbc_val << WM1_LP_FBC_SHIFT;

2753 2754
		results->wm_lp_spr[wm_lp - 1] = r->spr_val;
	}
2755

2756 2757 2758 2759 2760 2761 2762 2763 2764 2765
	/* LP0 register values */
	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
		enum pipe pipe = intel_crtc->pipe;
		const struct intel_wm_level *r =
			&intel_crtc->wm.active.wm[0];

		if (WARN_ON(!r->enable))
			continue;

		results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2766

2767 2768 2769 2770
		results->wm_pipe[pipe] =
			(r->pri_val << WM0_PIPE_PLANE_SHIFT) |
			(r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
			r->cur_val;
2771 2772 2773
	}
}

2774 2775
/* Find the result with the highest level enabled. Check for enable_fbc_wm in
 * case both are at the same level. Prefer r1 in case they're the same. */
2776 2777 2778
static struct intel_pipe_wm *hsw_find_best_result(struct drm_device *dev,
						  struct intel_pipe_wm *r1,
						  struct intel_pipe_wm *r2)
2779
{
2780 2781
	int level, max_level = ilk_wm_max_level(dev);
	int level1 = 0, level2 = 0;
2782

2783 2784 2785 2786 2787
	for (level = 1; level <= max_level; level++) {
		if (r1->wm[level].enable)
			level1 = level;
		if (r2->wm[level].enable)
			level2 = level;
2788 2789
	}

2790 2791
	if (level1 == level2) {
		if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2792 2793 2794
			return r2;
		else
			return r1;
2795
	} else if (level1 > level2) {
2796 2797 2798 2799 2800 2801
		return r1;
	} else {
		return r2;
	}
}

2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861
/* dirty bits used to track which watermarks need changes */
#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
#define WM_DIRTY_FBC (1 << 24)
#define WM_DIRTY_DDB (1 << 25)

static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
					 const struct hsw_wm_values *old,
					 const struct hsw_wm_values *new)
{
	unsigned int dirty = 0;
	enum pipe pipe;
	int wm_lp;

	for_each_pipe(pipe) {
		if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
			dirty |= WM_DIRTY_LINETIME(pipe);
			/* Must disable LP1+ watermarks too */
			dirty |= WM_DIRTY_LP_ALL;
		}

		if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
			dirty |= WM_DIRTY_PIPE(pipe);
			/* Must disable LP1+ watermarks too */
			dirty |= WM_DIRTY_LP_ALL;
		}
	}

	if (old->enable_fbc_wm != new->enable_fbc_wm) {
		dirty |= WM_DIRTY_FBC;
		/* Must disable LP1+ watermarks too */
		dirty |= WM_DIRTY_LP_ALL;
	}

	if (old->partitioning != new->partitioning) {
		dirty |= WM_DIRTY_DDB;
		/* Must disable LP1+ watermarks too */
		dirty |= WM_DIRTY_LP_ALL;
	}

	/* LP1+ watermarks already deemed dirty, no need to continue */
	if (dirty & WM_DIRTY_LP_ALL)
		return dirty;

	/* Find the lowest numbered LP1+ watermark in need of an update... */
	for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
		if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
		    old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
			break;
	}

	/* ...and mark it and all higher numbered LP1+ watermarks as dirty */
	for (; wm_lp <= 3; wm_lp++)
		dirty |= WM_DIRTY_LP(wm_lp);

	return dirty;
}

2862 2863 2864 2865 2866
/*
 * The spec says we shouldn't write when we don't need, because every write
 * causes WMs to be re-evaluated, expending some power.
 */
static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2867
				struct hsw_wm_values *results)
2868
{
2869
	struct hsw_wm_values *previous = &dev_priv->wm.hw;
2870
	unsigned int dirty;
2871 2872
	uint32_t val;

2873
	dirty = ilk_compute_wm_dirty(dev_priv->dev, previous, results);
2874
	if (!dirty)
2875 2876
		return;

2877
	if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != 0)
2878
		I915_WRITE(WM3_LP_ILK, 0);
2879
	if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != 0)
2880
		I915_WRITE(WM2_LP_ILK, 0);
2881
	if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != 0)
2882 2883
		I915_WRITE(WM1_LP_ILK, 0);

2884
	if (dirty & WM_DIRTY_PIPE(PIPE_A))
2885
		I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2886
	if (dirty & WM_DIRTY_PIPE(PIPE_B))
2887
		I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2888
	if (dirty & WM_DIRTY_PIPE(PIPE_C))
2889 2890
		I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);

2891
	if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2892
		I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2893
	if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2894
		I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2895
	if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2896 2897
		I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);

2898
	if (dirty & WM_DIRTY_DDB) {
2899
		val = I915_READ(WM_MISC);
2900
		if (results->partitioning == INTEL_DDB_PART_1_2)
2901 2902 2903 2904
			val &= ~WM_MISC_DATA_PARTITION_5_6;
		else
			val |= WM_MISC_DATA_PARTITION_5_6;
		I915_WRITE(WM_MISC, val);
2905 2906
	}

2907
	if (dirty & WM_DIRTY_FBC) {
2908 2909 2910 2911 2912 2913 2914 2915
		val = I915_READ(DISP_ARB_CTL);
		if (results->enable_fbc_wm)
			val &= ~DISP_FBC_WM_DIS;
		else
			val |= DISP_FBC_WM_DIS;
		I915_WRITE(DISP_ARB_CTL, val);
	}

2916
	if (dirty & WM_DIRTY_LP(1) && previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2917
		I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2918
	if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2919
		I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2920
	if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2921 2922
		I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);

2923
	if (dirty & WM_DIRTY_LP(1) && results->wm_lp[0] != 0)
2924
		I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2925
	if (dirty & WM_DIRTY_LP(2) && results->wm_lp[1] != 0)
2926
		I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2927
	if (dirty & WM_DIRTY_LP(3) && results->wm_lp[2] != 0)
2928
		I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2929 2930

	dev_priv->wm.hw = *results;
2931 2932
}

2933
static void haswell_update_wm(struct drm_crtc *crtc)
2934
{
2935
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2936
	struct drm_device *dev = crtc->dev;
2937
	struct drm_i915_private *dev_priv = dev->dev_private;
2938
	struct hsw_wm_maximums max;
2939
	struct hsw_pipe_wm_parameters params = {};
2940
	struct hsw_wm_values results = {};
2941
	enum intel_ddb_partitioning partitioning;
2942
	struct intel_pipe_wm pipe_wm = {};
2943
	struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2944
	struct intel_wm_config config = {};
2945

2946
	hsw_compute_wm_parameters(crtc, &params, &config);
2947 2948 2949 2950 2951

	intel_compute_pipe_wm(crtc, &params, &pipe_wm);

	if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
		return;
2952

2953
	intel_crtc->wm.active = pipe_wm;
2954

2955
	ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2956 2957 2958
	ilk_wm_merge(dev, &max, &lp_wm_1_2);

	/* 5/6 split only in single pipe config on IVB+ */
2959 2960
	if (INTEL_INFO(dev)->gen >= 7 &&
	    config.num_pipes_active == 1 && config.sprites_enabled) {
2961
		ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2962
		ilk_wm_merge(dev, &max, &lp_wm_5_6);
2963

2964
		best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2965
	} else {
2966
		best_lp_wm = &lp_wm_1_2;
2967 2968
	}

2969
	partitioning = (best_lp_wm == &lp_wm_1_2) ?
2970
		       INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2971

2972 2973 2974
	hsw_compute_wm_results(dev, best_lp_wm, partitioning, &results);

	hsw_write_wm_values(dev_priv, &results);
2975 2976
}

2977 2978
static void haswell_update_sprite_wm(struct drm_plane *plane,
				     struct drm_crtc *crtc,
2979
				     uint32_t sprite_width, int pixel_size,
2980
				     bool enabled, bool scaled)
2981
{
2982
	struct intel_plane *intel_plane = to_intel_plane(plane);
2983

2984 2985 2986 2987
	intel_plane->wm.enabled = enabled;
	intel_plane->wm.scaled = scaled;
	intel_plane->wm.horiz_pixels = sprite_width;
	intel_plane->wm.bytes_per_pixel = pixel_size;
2988

2989
	haswell_update_wm(crtc);
2990 2991
}

2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002
static bool
sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
			      uint32_t sprite_width, int pixel_size,
			      const struct intel_watermark_params *display,
			      int display_latency_ns, int *sprite_wm)
{
	struct drm_crtc *crtc;
	int clock;
	int entries, tlb_miss;

	crtc = intel_get_crtc_for_plane(dev, plane);
3003
	if (!intel_crtc_active(crtc)) {
3004 3005 3006 3007
		*sprite_wm = display->guard_size;
		return false;
	}

3008
	clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042

	/* Use the small buffer method to calculate the sprite watermark */
	entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
	tlb_miss = display->fifo_size*display->cacheline_size -
		sprite_width * 8;
	if (tlb_miss > 0)
		entries += tlb_miss;
	entries = DIV_ROUND_UP(entries, display->cacheline_size);
	*sprite_wm = entries + display->guard_size;
	if (*sprite_wm > (int)display->max_wm)
		*sprite_wm = display->max_wm;

	return true;
}

static bool
sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
				uint32_t sprite_width, int pixel_size,
				const struct intel_watermark_params *display,
				int latency_ns, int *sprite_wm)
{
	struct drm_crtc *crtc;
	unsigned long line_time_us;
	int clock;
	int line_count, line_size;
	int small, large;
	int entries;

	if (!latency_ns) {
		*sprite_wm = 0;
		return false;
	}

	crtc = intel_get_crtc_for_plane(dev, plane);
3043
	clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067
	if (!clock) {
		*sprite_wm = 0;
		return false;
	}

	line_time_us = (sprite_width * 1000) / clock;
	if (!line_time_us) {
		*sprite_wm = 0;
		return false;
	}

	line_count = (latency_ns / line_time_us + 1000) / 1000;
	line_size = sprite_width * pixel_size;

	/* Use the minimum of the small and large buffer method for primary */
	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
	large = line_count * line_size;

	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
	*sprite_wm = entries + display->guard_size;

	return *sprite_wm > 0x3ff ? false : true;
}

3068 3069
static void sandybridge_update_sprite_wm(struct drm_plane *plane,
					 struct drm_crtc *crtc,
3070
					 uint32_t sprite_width, int pixel_size,
3071
					 bool enabled, bool scaled)
3072
{
3073
	struct drm_device *dev = plane->dev;
3074
	struct drm_i915_private *dev_priv = dev->dev_private;
3075
	int pipe = to_intel_plane(plane)->pipe;
3076
	int latency = dev_priv->wm.spr_latency[0] * 100;	/* In unit 0.1us */
3077 3078 3079 3080
	u32 val;
	int sprite_wm, reg;
	int ret;

3081
	if (!enabled)
3082 3083
		return;

3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101
	switch (pipe) {
	case 0:
		reg = WM0_PIPEA_ILK;
		break;
	case 1:
		reg = WM0_PIPEB_ILK;
		break;
	case 2:
		reg = WM0_PIPEC_IVB;
		break;
	default:
		return; /* bad pipe */
	}

	ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
					    &sandybridge_display_wm_info,
					    latency, &sprite_wm);
	if (!ret) {
3102 3103
		DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
			      pipe_name(pipe));
3104 3105 3106 3107 3108 3109
		return;
	}

	val = I915_READ(reg);
	val &= ~WM0_PIPE_SPRITE_MASK;
	I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
3110
	DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
3111 3112 3113 3114 3115


	ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
					      pixel_size,
					      &sandybridge_display_srwm_info,
3116
					      dev_priv->wm.spr_latency[1] * 500,
3117 3118
					      &sprite_wm);
	if (!ret) {
3119 3120
		DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
			      pipe_name(pipe));
3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131
		return;
	}
	I915_WRITE(WM1S_LP_ILK, sprite_wm);

	/* Only IVB has two more LP watermarks for sprite */
	if (!IS_IVYBRIDGE(dev))
		return;

	ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
					      pixel_size,
					      &sandybridge_display_srwm_info,
3132
					      dev_priv->wm.spr_latency[2] * 500,
3133 3134
					      &sprite_wm);
	if (!ret) {
3135 3136
		DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
			      pipe_name(pipe));
3137 3138 3139 3140 3141 3142 3143
		return;
	}
	I915_WRITE(WM2S_LP_IVB, sprite_wm);

	ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
					      pixel_size,
					      &sandybridge_display_srwm_info,
3144
					      dev_priv->wm.spr_latency[3] * 500,
3145 3146
					      &sprite_wm);
	if (!ret) {
3147 3148
		DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
			      pipe_name(pipe));
3149 3150 3151 3152 3153
		return;
	}
	I915_WRITE(WM3S_LP_IVB, sprite_wm);
}

3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221
static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct hsw_wm_values *hw = &dev_priv->wm.hw;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_pipe_wm *active = &intel_crtc->wm.active;
	enum pipe pipe = intel_crtc->pipe;
	static const unsigned int wm0_pipe_reg[] = {
		[PIPE_A] = WM0_PIPEA_ILK,
		[PIPE_B] = WM0_PIPEB_ILK,
		[PIPE_C] = WM0_PIPEC_IVB,
	};

	hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
	hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));

	if (intel_crtc_active(crtc)) {
		u32 tmp = hw->wm_pipe[pipe];

		/*
		 * For active pipes LP0 watermark is marked as
		 * enabled, and LP1+ watermaks as disabled since
		 * we can't really reverse compute them in case
		 * multiple pipes are active.
		 */
		active->wm[0].enable = true;
		active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
		active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
		active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
		active->linetime = hw->wm_linetime[pipe];
	} else {
		int level, max_level = ilk_wm_max_level(dev);

		/*
		 * For inactive pipes, all watermark levels
		 * should be marked as enabled but zeroed,
		 * which is what we'd compute them to.
		 */
		for (level = 0; level <= max_level; level++)
			active->wm[level].enable = true;
	}
}

void ilk_wm_get_hw_state(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct hsw_wm_values *hw = &dev_priv->wm.hw;
	struct drm_crtc *crtc;

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
		ilk_pipe_wm_get_hw_state(crtc);

	hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
	hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
	hw->wm_lp[2] = I915_READ(WM3_LP_ILK);

	hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
	hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
	hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);

	hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
		INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;

	hw->enable_fbc_wm =
		!(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
}

3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253
/**
 * intel_update_watermarks - update FIFO watermark values based on current modes
 *
 * Calculate watermark values for the various WM regs based on current mode
 * and plane configuration.
 *
 * There are several cases to deal with here:
 *   - normal (i.e. non-self-refresh)
 *   - self-refresh (SR) mode
 *   - lines are large relative to FIFO size (buffer can hold up to 2)
 *   - lines are small relative to FIFO size (buffer can hold more than 2
 *     lines), so need to account for TLB latency
 *
 *   The normal calculation is:
 *     watermark = dotclock * bytes per pixel * latency
 *   where latency is platform & configuration dependent (we assume pessimal
 *   values here).
 *
 *   The SR calculation is:
 *     watermark = (trunc(latency/line time)+1) * surface width *
 *       bytes per pixel
 *   where
 *     line time = htotal / dotclock
 *     surface width = hdisplay for normal plane and 64 for cursor
 *   and latency is assumed to be high, as above.
 *
 * The final value programmed to the register should always be rounded up,
 * and include an extra 2 entries to account for clock crossings.
 *
 * We don't use the sprite, so we can ignore that.  And on Crestline we have
 * to set the non-SR watermarks to 8.
 */
3254
void intel_update_watermarks(struct drm_crtc *crtc)
3255
{
3256
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3257 3258

	if (dev_priv->display.update_wm)
3259
		dev_priv->display.update_wm(crtc);
3260 3261
}

3262 3263
void intel_update_sprite_watermarks(struct drm_plane *plane,
				    struct drm_crtc *crtc,
3264
				    uint32_t sprite_width, int pixel_size,
3265
				    bool enabled, bool scaled)
3266
{
3267
	struct drm_i915_private *dev_priv = plane->dev->dev_private;
3268 3269

	if (dev_priv->display.update_sprite_wm)
3270
		dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
3271
						   pixel_size, enabled, scaled);
3272 3273
}

3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287
static struct drm_i915_gem_object *
intel_alloc_context_page(struct drm_device *dev)
{
	struct drm_i915_gem_object *ctx;
	int ret;

	WARN_ON(!mutex_is_locked(&dev->struct_mutex));

	ctx = i915_gem_alloc_object(dev, 4096);
	if (!ctx) {
		DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
		return NULL;
	}

B
Ben Widawsky 已提交
3288
	ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308
	if (ret) {
		DRM_ERROR("failed to pin power context: %d\n", ret);
		goto err_unref;
	}

	ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
	if (ret) {
		DRM_ERROR("failed to set-domain on power context: %d\n", ret);
		goto err_unpin;
	}

	return ctx;

err_unpin:
	i915_gem_object_unpin(ctx);
err_unref:
	drm_gem_object_unreference(&ctx->base);
	return NULL;
}

3309 3310 3311 3312 3313 3314 3315 3316 3317
/**
 * Lock protecting IPS related data structures
 */
DEFINE_SPINLOCK(mchdev_lock);

/* Global for IPS driver to get at the current i915 device. Protected by
 * mchdev_lock. */
static struct drm_i915_private *i915_mch_dev;

3318 3319 3320 3321 3322
bool ironlake_set_drps(struct drm_device *dev, u8 val)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u16 rgvswctl;

3323 3324
	assert_spin_locked(&mchdev_lock);

3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341
	rgvswctl = I915_READ16(MEMSWCTL);
	if (rgvswctl & MEMCTL_CMD_STS) {
		DRM_DEBUG("gpu busy, RCS change rejected\n");
		return false; /* still busy with another command */
	}

	rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
		(val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
	I915_WRITE16(MEMSWCTL, rgvswctl);
	POSTING_READ16(MEMSWCTL);

	rgvswctl |= MEMCTL_CMD_STS;
	I915_WRITE16(MEMSWCTL, rgvswctl);

	return true;
}

3342
static void ironlake_enable_drps(struct drm_device *dev)
3343 3344 3345 3346 3347
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 rgvmodectl = I915_READ(MEMMODECTL);
	u8 fmax, fmin, fstart, vstart;

3348 3349
	spin_lock_irq(&mchdev_lock);

3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372
	/* Enable temp reporting */
	I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
	I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);

	/* 100ms RC evaluation intervals */
	I915_WRITE(RCUPEI, 100000);
	I915_WRITE(RCDNEI, 100000);

	/* Set max/min thresholds to 90ms and 80ms respectively */
	I915_WRITE(RCBMAXAVG, 90000);
	I915_WRITE(RCBMINAVG, 80000);

	I915_WRITE(MEMIHYST, 1);

	/* Set up min, max, and cur for interrupt handling */
	fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
	fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
	fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
		MEMMODE_FSTART_SHIFT;

	vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
		PXVFREQ_PX_SHIFT;

3373 3374
	dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
	dev_priv->ips.fstart = fstart;
3375

3376 3377 3378
	dev_priv->ips.max_delay = fstart;
	dev_priv->ips.min_delay = fmin;
	dev_priv->ips.cur_delay = fstart;
3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394

	DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
			 fmax, fmin, fstart);

	I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);

	/*
	 * Interrupts will be enabled in ironlake_irq_postinstall
	 */

	I915_WRITE(VIDSTART, vstart);
	POSTING_READ(VIDSTART);

	rgvmodectl |= MEMMODE_SWMODE_EN;
	I915_WRITE(MEMMODECTL, rgvmodectl);

3395
	if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3396
		DRM_ERROR("stuck trying to change perf mode\n");
3397
	mdelay(1);
3398 3399 3400

	ironlake_set_drps(dev, fstart);

3401
	dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3402
		I915_READ(0x112e0);
3403 3404 3405
	dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
	dev_priv->ips.last_count2 = I915_READ(0x112f4);
	getrawmonotonic(&dev_priv->ips.last_time2);
3406 3407

	spin_unlock_irq(&mchdev_lock);
3408 3409
}

3410
static void ironlake_disable_drps(struct drm_device *dev)
3411 3412
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3413 3414 3415 3416 3417
	u16 rgvswctl;

	spin_lock_irq(&mchdev_lock);

	rgvswctl = I915_READ16(MEMSWCTL);
3418 3419 3420 3421 3422 3423 3424 3425 3426

	/* Ack interrupts, disable EFC interrupt */
	I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
	I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
	I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
	I915_WRITE(DEIIR, DE_PCU_EVENT);
	I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);

	/* Go back to the starting frequency */
3427
	ironlake_set_drps(dev, dev_priv->ips.fstart);
3428
	mdelay(1);
3429 3430
	rgvswctl |= MEMCTL_CMD_STS;
	I915_WRITE(MEMSWCTL, rgvswctl);
3431
	mdelay(1);
3432

3433
	spin_unlock_irq(&mchdev_lock);
3434 3435
}

3436 3437 3438 3439 3440
/* There's a funny hw issue where the hw returns all 0 when reading from
 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
 * ourselves, instead of doing a rmw cycle (which might result in us clearing
 * all limits and the gpu stuck at whatever frequency it is at atm).
 */
3441
static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3442
{
3443
	u32 limits;
3444

3445 3446 3447 3448 3449 3450
	/* Only set the down limit when we've reached the lowest level to avoid
	 * getting more interrupts, otherwise leave this clear. This prevents a
	 * race in the hw when coming out of rc6: There's a tiny window where
	 * the hw runs at the minimal clock before selecting the desired
	 * frequency, if the down threshold expires in that window we will not
	 * receive a down interrupt. */
3451 3452
	limits = dev_priv->rps.max_delay << 24;
	if (val <= dev_priv->rps.min_delay)
3453
		limits |= dev_priv->rps.min_delay << 16;
3454 3455 3456 3457

	return limits;
}

3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549
static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
{
	int new_power;

	new_power = dev_priv->rps.power;
	switch (dev_priv->rps.power) {
	case LOW_POWER:
		if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
			new_power = BETWEEN;
		break;

	case BETWEEN:
		if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
			new_power = LOW_POWER;
		else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
			new_power = HIGH_POWER;
		break;

	case HIGH_POWER:
		if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
			new_power = BETWEEN;
		break;
	}
	/* Max/min bins are special */
	if (val == dev_priv->rps.min_delay)
		new_power = LOW_POWER;
	if (val == dev_priv->rps.max_delay)
		new_power = HIGH_POWER;
	if (new_power == dev_priv->rps.power)
		return;

	/* Note the units here are not exactly 1us, but 1280ns. */
	switch (new_power) {
	case LOW_POWER:
		/* Upclock if more than 95% busy over 16ms */
		I915_WRITE(GEN6_RP_UP_EI, 12500);
		I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);

		/* Downclock if less than 85% busy over 32ms */
		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);

		I915_WRITE(GEN6_RP_CONTROL,
			   GEN6_RP_MEDIA_TURBO |
			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
			   GEN6_RP_MEDIA_IS_GFX |
			   GEN6_RP_ENABLE |
			   GEN6_RP_UP_BUSY_AVG |
			   GEN6_RP_DOWN_IDLE_AVG);
		break;

	case BETWEEN:
		/* Upclock if more than 90% busy over 13ms */
		I915_WRITE(GEN6_RP_UP_EI, 10250);
		I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);

		/* Downclock if less than 75% busy over 32ms */
		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);

		I915_WRITE(GEN6_RP_CONTROL,
			   GEN6_RP_MEDIA_TURBO |
			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
			   GEN6_RP_MEDIA_IS_GFX |
			   GEN6_RP_ENABLE |
			   GEN6_RP_UP_BUSY_AVG |
			   GEN6_RP_DOWN_IDLE_AVG);
		break;

	case HIGH_POWER:
		/* Upclock if more than 85% busy over 10ms */
		I915_WRITE(GEN6_RP_UP_EI, 8000);
		I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);

		/* Downclock if less than 60% busy over 32ms */
		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);

		I915_WRITE(GEN6_RP_CONTROL,
			   GEN6_RP_MEDIA_TURBO |
			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
			   GEN6_RP_MEDIA_IS_GFX |
			   GEN6_RP_ENABLE |
			   GEN6_RP_UP_BUSY_AVG |
			   GEN6_RP_DOWN_IDLE_AVG);
		break;
	}

	dev_priv->rps.power = new_power;
	dev_priv->rps.last_adj = 0;
}

3550 3551 3552
void gen6_set_rps(struct drm_device *dev, u8 val)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3553

3554
	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3555 3556
	WARN_ON(val > dev_priv->rps.max_delay);
	WARN_ON(val < dev_priv->rps.min_delay);
3557

3558
	if (val == dev_priv->rps.cur_delay)
3559 3560
		return;

3561 3562
	gen6_set_rps_thresholds(dev_priv, val);

3563 3564 3565 3566 3567 3568 3569 3570
	if (IS_HASWELL(dev))
		I915_WRITE(GEN6_RPNSWREQ,
			   HSW_FREQUENCY(val));
	else
		I915_WRITE(GEN6_RPNSWREQ,
			   GEN6_FREQUENCY(val) |
			   GEN6_OFFSET(0) |
			   GEN6_AGGRESSIVE_TURBO);
3571 3572 3573 3574

	/* Make sure we continue to get interrupts
	 * until we hit the minimum or maximum frequencies.
	 */
3575 3576
	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
		   gen6_rps_limits(dev_priv, val));
3577

3578 3579
	POSTING_READ(GEN6_RPNSWREQ);

3580
	dev_priv->rps.cur_delay = val;
3581 3582

	trace_intel_gpu_freq_change(val * 50);
3583 3584
}

3585 3586 3587
void gen6_rps_idle(struct drm_i915_private *dev_priv)
{
	mutex_lock(&dev_priv->rps.hw_lock);
3588 3589 3590 3591 3592 3593 3594
	if (dev_priv->rps.enabled) {
		if (dev_priv->info->is_valleyview)
			valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
		else
			gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
		dev_priv->rps.last_adj = 0;
	}
3595 3596 3597 3598 3599 3600
	mutex_unlock(&dev_priv->rps.hw_lock);
}

void gen6_rps_boost(struct drm_i915_private *dev_priv)
{
	mutex_lock(&dev_priv->rps.hw_lock);
3601 3602 3603 3604 3605 3606 3607
	if (dev_priv->rps.enabled) {
		if (dev_priv->info->is_valleyview)
			valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
		else
			gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
		dev_priv->rps.last_adj = 0;
	}
3608 3609 3610
	mutex_unlock(&dev_priv->rps.hw_lock);
}

3611 3612 3613
void valleyview_set_rps(struct drm_device *dev, u8 val)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3614

3615 3616 3617 3618
	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
	WARN_ON(val > dev_priv->rps.max_delay);
	WARN_ON(val < dev_priv->rps.min_delay);

3619
	DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3620
			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
3621
			 dev_priv->rps.cur_delay,
3622
			 vlv_gpu_freq(dev_priv, val), val);
3623 3624 3625 3626

	if (val == dev_priv->rps.cur_delay)
		return;

3627
	vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3628

3629
	dev_priv->rps.cur_delay = val;
3630

3631
	trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3632 3633
}

3634
static void gen6_disable_rps_interrupts(struct drm_device *dev)
3635 3636 3637 3638
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3639
	I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3640 3641 3642 3643 3644
	/* Complete PM interrupt masking here doesn't race with the rps work
	 * item again unmasking PM interrupts because that is using a different
	 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
	 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */

3645
	spin_lock_irq(&dev_priv->irq_lock);
3646
	dev_priv->rps.pm_iir = 0;
3647
	spin_unlock_irq(&dev_priv->irq_lock);
3648

3649
	I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3650 3651
}

3652
static void gen6_disable_rps(struct drm_device *dev)
3653 3654 3655 3656
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(GEN6_RC_CONTROL, 0);
3657
	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3658

3659 3660 3661 3662 3663 3664 3665 3666
	gen6_disable_rps_interrupts(dev);
}

static void valleyview_disable_rps(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(GEN6_RC_CONTROL, 0);
3667

3668
	gen6_disable_rps_interrupts(dev);
3669 3670 3671 3672 3673

	if (dev_priv->vlv_pctx) {
		drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
		dev_priv->vlv_pctx = NULL;
	}
3674 3675
}

B
Ben Widawsky 已提交
3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689
static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
{
	if (IS_GEN6(dev))
		DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");

	if (IS_HASWELL(dev))
		DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");

	DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
			(mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
			(mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
			(mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
}

3690 3691
int intel_enable_rc6(const struct drm_device *dev)
{
3692 3693 3694 3695
	/* No RC6 before Ironlake */
	if (INTEL_INFO(dev)->gen < 5)
		return 0;

3696
	/* Respect the kernel parameter if it is set */
3697 3698 3699
	if (i915_enable_rc6 >= 0)
		return i915_enable_rc6;

3700 3701 3702
	/* Disable RC6 on Ironlake */
	if (INTEL_INFO(dev)->gen == 5)
		return 0;
3703

B
Ben Widawsky 已提交
3704
	if (IS_HASWELL(dev))
3705
		return INTEL_RC6_ENABLE;
3706

3707
	/* snb/ivb have more than one rc6 state. */
B
Ben Widawsky 已提交
3708
	if (INTEL_INFO(dev)->gen == 6)
3709
		return INTEL_RC6_ENABLE;
3710

3711 3712 3713
	return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
}

3714 3715 3716
static void gen6_enable_rps_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3717
	u32 enabled_intrs;
3718 3719

	spin_lock_irq(&dev_priv->irq_lock);
3720
	WARN_ON(dev_priv->rps.pm_iir);
P
Paulo Zanoni 已提交
3721
	snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3722 3723
	I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
	spin_unlock_irq(&dev_priv->irq_lock);
3724

3725
	/* only unmask PM interrupts we need. Mask all others. */
3726 3727 3728 3729 3730 3731 3732 3733 3734
	enabled_intrs = GEN6_PM_RPS_EVENTS;

	/* IVB and SNB hard hangs on looping batchbuffer
	 * if GEN6_PM_UP_EI_EXPIRED is masked.
	 */
	if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
		enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;

	I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3735 3736
}

3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748
static void gen8_enable_rps(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_ring_buffer *ring;
	uint32_t rc6_mask = 0, rp_state_cap;
	int unused;

	/* 1a: Software RC state - RC0 */
	I915_WRITE(GEN6_RC_STATE, 0);

	/* 1c & 1d: Get forcewake during program sequence. Although the driver
	 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3749
	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805

	/* 2a: Disable RC states. */
	I915_WRITE(GEN6_RC_CONTROL, 0);

	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);

	/* 2b: Program RC6 thresholds.*/
	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
	for_each_ring(ring, dev_priv, unused)
		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
	I915_WRITE(GEN6_RC_SLEEP, 0);
	I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */

	/* 3: Enable RC6 */
	if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
	DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
	I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
			GEN6_RC_CTL_EI_MODE(1) |
			rc6_mask);

	/* 4 Program defaults and thresholds for RPS*/
	I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
	I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
	/* NB: Docs say 1s, and 1000000 - which aren't equivalent */
	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */

	/* Docs recommend 900MHz, and 300 MHz respectively */
	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
		   dev_priv->rps.max_delay << 24 |
		   dev_priv->rps.min_delay << 16);

	I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
	I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
	I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */

	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);

	/* 5: Enable RPS */
	I915_WRITE(GEN6_RP_CONTROL,
		   GEN6_RP_MEDIA_TURBO |
		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
		   GEN6_RP_MEDIA_IS_GFX |
		   GEN6_RP_ENABLE |
		   GEN6_RP_UP_BUSY_AVG |
		   GEN6_RP_DOWN_IDLE_AVG);

	/* 6: Ring frequency + overclocking (our driver does this later */

	gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);

	gen6_enable_rps_interrupts(dev);

3806
	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3807 3808
}

3809
static void gen6_enable_rps(struct drm_device *dev)
3810
{
3811
	struct drm_i915_private *dev_priv = dev->dev_private;
3812
	struct intel_ring_buffer *ring;
3813 3814
	u32 rp_state_cap;
	u32 gt_perf_status;
3815
	u32 rc6vids, pcu_mbox, rc6_mask = 0;
3816 3817
	u32 gtfifodbg;
	int rc6_mode;
B
Ben Widawsky 已提交
3818
	int i, ret;
3819

3820
	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3821

3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835
	/* Here begins a magic sequence of register writes to enable
	 * auto-downclocking.
	 *
	 * Perhaps there might be some value in exposing these to
	 * userspace...
	 */
	I915_WRITE(GEN6_RC_STATE, 0);

	/* Clear the DBG now so we don't confuse earlier errors */
	if ((gtfifodbg = I915_READ(GTFIFODBG))) {
		DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
		I915_WRITE(GTFIFODBG, gtfifodbg);
	}

3836
	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3837

3838 3839 3840
	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);

3841 3842
	/* In units of 50MHz */
	dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3843 3844 3845 3846
	dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
	dev_priv->rps.rp1_delay = (rp_state_cap >>  8) & 0xff;
	dev_priv->rps.rp0_delay = (rp_state_cap >>  0) & 0xff;
	dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
3847
	dev_priv->rps.cur_delay = 0;
3848

3849 3850 3851 3852 3853 3854 3855 3856 3857
	/* disable the counters and set deterministic thresholds */
	I915_WRITE(GEN6_RC_CONTROL, 0);

	I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
	I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);

3858 3859
	for_each_ring(ring, dev_priv, i)
		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3860 3861 3862

	I915_WRITE(GEN6_RC_SLEEP, 0);
	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3863
	if (IS_IVYBRIDGE(dev))
3864 3865 3866
		I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
	else
		I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3867
	I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3868 3869
	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */

3870
	/* Check if we are enabling RC6 */
3871 3872 3873 3874
	rc6_mode = intel_enable_rc6(dev_priv->dev);
	if (rc6_mode & INTEL_RC6_ENABLE)
		rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;

3875 3876 3877 3878
	/* We don't use those on Haswell */
	if (!IS_HASWELL(dev)) {
		if (rc6_mode & INTEL_RC6p_ENABLE)
			rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3879

3880 3881 3882
		if (rc6_mode & INTEL_RC6pp_ENABLE)
			rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
	}
3883

B
Ben Widawsky 已提交
3884
	intel_print_rc6_info(dev, rc6_mask);
3885 3886 3887 3888 3889 3890

	I915_WRITE(GEN6_RC_CONTROL,
		   rc6_mask |
		   GEN6_RC_CTL_EI_MODE(1) |
		   GEN6_RC_CTL_HW_ENABLE);

3891 3892
	/* Power down if completely idle for over 50ms */
	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3893 3894
	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);

B
Ben Widawsky 已提交
3895
	ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3896
	if (!ret) {
B
Ben Widawsky 已提交
3897 3898
		pcu_mbox = 0;
		ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3899
		if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3900
			DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3901 3902
					 (dev_priv->rps.max_delay & 0xff) * 50,
					 (pcu_mbox & 0xff) * 50);
3903
			dev_priv->rps.hw_max = pcu_mbox & 0xff;
B
Ben Widawsky 已提交
3904 3905 3906
		}
	} else {
		DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3907 3908
	}

3909 3910
	dev_priv->rps.power = HIGH_POWER; /* force a reset */
	gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3911

3912
	gen6_enable_rps_interrupts(dev);
3913

3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927
	rc6vids = 0;
	ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
	if (IS_GEN6(dev) && ret) {
		DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
	} else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
		DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
			  GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
		rc6vids &= 0xffff00;
		rc6vids |= GEN6_ENCODE_RC6_VID(450);
		ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
		if (ret)
			DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
	}

3928
	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3929 3930
}

3931
void gen6_update_ring_freq(struct drm_device *dev)
3932
{
3933
	struct drm_i915_private *dev_priv = dev->dev_private;
3934
	int min_freq = 15;
3935 3936
	unsigned int gpu_freq;
	unsigned int max_ia_freq, min_ring_freq;
3937
	int scaling_factor = 180;
3938
	struct cpufreq_policy *policy;
3939

3940
	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3941

3942 3943 3944 3945 3946 3947 3948 3949 3950
	policy = cpufreq_cpu_get(0);
	if (policy) {
		max_ia_freq = policy->cpuinfo.max_freq;
		cpufreq_cpu_put(policy);
	} else {
		/*
		 * Default to measured freq if none found, PCU will ensure we
		 * don't go over
		 */
3951
		max_ia_freq = tsc_khz;
3952
	}
3953 3954 3955 3956

	/* Convert from kHz to MHz */
	max_ia_freq /= 1000;

3957
	min_ring_freq = I915_READ(DCLK) & 0xf;
3958 3959
	/* convert DDR frequency from units of 266.6MHz to bandwidth */
	min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3960

3961 3962 3963 3964 3965
	/*
	 * For each potential GPU frequency, load a ring frequency we'd like
	 * to use for memory access.  We do this by specifying the IA frequency
	 * the PCU should use as a reference to determine the ring frequency.
	 */
3966
	for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3967
	     gpu_freq--) {
3968
		int diff = dev_priv->rps.max_delay - gpu_freq;
3969 3970
		unsigned int ia_freq = 0, ring_freq = 0;

3971 3972 3973 3974
		if (INTEL_INFO(dev)->gen >= 8) {
			/* max(2 * GT, DDR). NB: GT is 50MHz units */
			ring_freq = max(min_ring_freq, gpu_freq);
		} else if (IS_HASWELL(dev)) {
3975
			ring_freq = mult_frac(gpu_freq, 5, 4);
3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991
			ring_freq = max(min_ring_freq, ring_freq);
			/* leave ia_freq as the default, chosen by cpufreq */
		} else {
			/* On older processors, there is no separate ring
			 * clock domain, so in order to boost the bandwidth
			 * of the ring, we need to upclock the CPU (ia_freq).
			 *
			 * For GPU frequencies less than 750MHz,
			 * just use the lowest ring freq.
			 */
			if (gpu_freq < min_freq)
				ia_freq = 800;
			else
				ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
			ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
		}
3992

B
Ben Widawsky 已提交
3993 3994
		sandybridge_pcode_write(dev_priv,
					GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3995 3996 3997
					ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
					ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
					gpu_freq);
3998 3999 4000
	}
}

4001 4002 4003 4004
int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
{
	u32 val, rp0;

4005
	val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017

	rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
	/* Clamp to max */
	rp0 = min_t(u32, rp0, 0xea);

	return rp0;
}

static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
{
	u32 val, rpe;

4018
	val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
4019
	rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
4020
	val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
4021 4022 4023 4024 4025 4026 4027
	rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;

	return rpe;
}

int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
{
4028
	return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
4029 4030
}

4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046
static void valleyview_setup_pctx(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *pctx;
	unsigned long pctx_paddr;
	u32 pcbr;
	int pctx_size = 24*1024;

	pcbr = I915_READ(VLV_PCBR);
	if (pcbr) {
		/* BIOS set it up already, grab the pre-alloc'd space */
		int pcbr_offset;

		pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
		pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
								      pcbr_offset,
4047
								      I915_GTT_OFFSET_NONE,
4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072
								      pctx_size);
		goto out;
	}

	/*
	 * From the Gunit register HAS:
	 * The Gfx driver is expected to program this register and ensure
	 * proper allocation within Gfx stolen memory.  For example, this
	 * register should be programmed such than the PCBR range does not
	 * overlap with other ranges, such as the frame buffer, protected
	 * memory, or any other relevant ranges.
	 */
	pctx = i915_gem_object_create_stolen(dev, pctx_size);
	if (!pctx) {
		DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
		return;
	}

	pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
	I915_WRITE(VLV_PCBR, pctx_paddr);

out:
	dev_priv->vlv_pctx = pctx;
}

4073 4074 4075 4076
static void valleyview_enable_rps(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_ring_buffer *ring;
4077
	u32 gtfifodbg, val, rc6_mode = 0;
4078 4079 4080 4081 4082
	int i;

	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

	if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4083 4084
		DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
				 gtfifodbg);
4085 4086 4087
		I915_WRITE(GTFIFODBG, gtfifodbg);
	}

4088 4089
	valleyview_setup_pctx(dev);

4090 4091
	/* If VLV, Forcewake all wells, else re-direct to regular path */
	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114

	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
	I915_WRITE(GEN6_RP_UP_EI, 66000);
	I915_WRITE(GEN6_RP_DOWN_EI, 350000);

	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);

	I915_WRITE(GEN6_RP_CONTROL,
		   GEN6_RP_MEDIA_TURBO |
		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
		   GEN6_RP_MEDIA_IS_GFX |
		   GEN6_RP_ENABLE |
		   GEN6_RP_UP_BUSY_AVG |
		   GEN6_RP_DOWN_IDLE_CONT);

	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);

	for_each_ring(ring, dev_priv, i)
		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);

4115
	I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4116 4117

	/* allows RC6 residency counter to work */
4118 4119 4120 4121
	I915_WRITE(VLV_COUNTER_CONTROL,
		   _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
				      VLV_MEDIA_RC6_COUNT_EN |
				      VLV_RENDER_RC6_COUNT_EN));
4122
	if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4123
		rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
B
Ben Widawsky 已提交
4124 4125 4126

	intel_print_rc6_info(dev, rc6_mode);

4127
	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4128

4129
	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4130 4131 4132 4133 4134

	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);

	dev_priv->rps.cur_delay = (val >> 8) & 0xff;
4135
	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4136
			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
4137
			 dev_priv->rps.cur_delay);
4138 4139 4140

	dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
	dev_priv->rps.hw_max = dev_priv->rps.max_delay;
4141
	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4142
			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay),
4143
			 dev_priv->rps.max_delay);
4144

4145 4146
	dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4147
			 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
4148
			 dev_priv->rps.rpe_delay);
4149

4150 4151
	dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4152
			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay),
4153
			 dev_priv->rps.min_delay);
4154

4155
	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4156
			 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
4157
			 dev_priv->rps.rpe_delay);
4158

4159
	valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
4160

4161
	gen6_enable_rps_interrupts(dev);
4162

4163
	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4164 4165
}

4166
void ironlake_teardown_rc6(struct drm_device *dev)
4167 4168 4169
{
	struct drm_i915_private *dev_priv = dev->dev_private;

4170 4171 4172 4173
	if (dev_priv->ips.renderctx) {
		i915_gem_object_unpin(dev_priv->ips.renderctx);
		drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
		dev_priv->ips.renderctx = NULL;
4174 4175
	}

4176 4177 4178 4179
	if (dev_priv->ips.pwrctx) {
		i915_gem_object_unpin(dev_priv->ips.pwrctx);
		drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
		dev_priv->ips.pwrctx = NULL;
4180 4181 4182
	}
}

4183
static void ironlake_disable_rc6(struct drm_device *dev)
4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (I915_READ(PWRCTXA)) {
		/* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
		I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
		wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
			 50);

		I915_WRITE(PWRCTXA, 0);
		POSTING_READ(PWRCTXA);

		I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
		POSTING_READ(RSTDBYCTL);
	}
}

static int ironlake_setup_rc6(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

4205 4206 4207
	if (dev_priv->ips.renderctx == NULL)
		dev_priv->ips.renderctx = intel_alloc_context_page(dev);
	if (!dev_priv->ips.renderctx)
4208 4209
		return -ENOMEM;

4210 4211 4212
	if (dev_priv->ips.pwrctx == NULL)
		dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
	if (!dev_priv->ips.pwrctx) {
4213 4214 4215 4216 4217 4218 4219
		ironlake_teardown_rc6(dev);
		return -ENOMEM;
	}

	return 0;
}

4220
static void ironlake_enable_rc6(struct drm_device *dev)
4221 4222
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4223
	struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
4224
	bool was_interruptible;
4225 4226 4227 4228 4229 4230 4231 4232
	int ret;

	/* rc6 disabled by default due to repeated reports of hanging during
	 * boot and resume.
	 */
	if (!intel_enable_rc6(dev))
		return;

4233 4234
	WARN_ON(!mutex_is_locked(&dev->struct_mutex));

4235
	ret = ironlake_setup_rc6(dev);
4236
	if (ret)
4237 4238
		return;

4239 4240 4241
	was_interruptible = dev_priv->mm.interruptible;
	dev_priv->mm.interruptible = false;

4242 4243 4244 4245
	/*
	 * GPU can automatically power down the render unit if given a page
	 * to save state.
	 */
4246
	ret = intel_ring_begin(ring, 6);
4247 4248
	if (ret) {
		ironlake_teardown_rc6(dev);
4249
		dev_priv->mm.interruptible = was_interruptible;
4250 4251 4252
		return;
	}

4253 4254
	intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
	intel_ring_emit(ring, MI_SET_CONTEXT);
4255
	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4256 4257 4258 4259 4260 4261 4262 4263
			MI_MM_SPACE_GTT |
			MI_SAVE_EXT_STATE_EN |
			MI_RESTORE_EXT_STATE_EN |
			MI_RESTORE_INHIBIT);
	intel_ring_emit(ring, MI_SUSPEND_FLUSH);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_emit(ring, MI_FLUSH);
	intel_ring_advance(ring);
4264 4265 4266 4267 4268 4269

	/*
	 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
	 * does an implicit flush, combined with MI_FLUSH above, it should be
	 * safe to assume that renderctx is valid
	 */
4270 4271
	ret = intel_ring_idle(ring);
	dev_priv->mm.interruptible = was_interruptible;
4272
	if (ret) {
4273
		DRM_ERROR("failed to enable ironlake power savings\n");
4274 4275 4276 4277
		ironlake_teardown_rc6(dev);
		return;
	}

4278
	I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4279
	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
B
Ben Widawsky 已提交
4280 4281

	intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
4282 4283
}

4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298
static unsigned long intel_pxfreq(u32 vidfreq)
{
	unsigned long freq;
	int div = (vidfreq & 0x3f0000) >> 16;
	int post = (vidfreq & 0x3000) >> 12;
	int pre = (vidfreq & 0x7);

	if (!pre)
		return 0;

	freq = ((div * 133333) / ((1<<post) * pre));

	return freq;
}

4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312
static const struct cparams {
	u16 i;
	u16 t;
	u16 m;
	u16 c;
} cparams[] = {
	{ 1, 1333, 301, 28664 },
	{ 1, 1066, 294, 24460 },
	{ 1, 800, 294, 25192 },
	{ 0, 1333, 276, 27605 },
	{ 0, 1066, 276, 27605 },
	{ 0, 800, 231, 23784 },
};

4313
static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4314 4315 4316 4317 4318 4319
{
	u64 total_count, diff, ret;
	u32 count1, count2, count3, m = 0, c = 0;
	unsigned long now = jiffies_to_msecs(jiffies), diff1;
	int i;

4320 4321
	assert_spin_locked(&mchdev_lock);

4322
	diff1 = now - dev_priv->ips.last_time1;
4323 4324 4325 4326 4327 4328 4329

	/* Prevent division-by-zero if we are asking too fast.
	 * Also, we don't get interesting results if we are polling
	 * faster than once in 10ms, so just return the saved value
	 * in such cases.
	 */
	if (diff1 <= 10)
4330
		return dev_priv->ips.chipset_power;
4331 4332 4333 4334 4335 4336 4337 4338

	count1 = I915_READ(DMIEC);
	count2 = I915_READ(DDREC);
	count3 = I915_READ(CSIEC);

	total_count = count1 + count2 + count3;

	/* FIXME: handle per-counter overflow */
4339 4340
	if (total_count < dev_priv->ips.last_count1) {
		diff = ~0UL - dev_priv->ips.last_count1;
4341 4342
		diff += total_count;
	} else {
4343
		diff = total_count - dev_priv->ips.last_count1;
4344 4345 4346
	}

	for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4347 4348
		if (cparams[i].i == dev_priv->ips.c_m &&
		    cparams[i].t == dev_priv->ips.r_t) {
4349 4350 4351 4352 4353 4354 4355 4356 4357 4358
			m = cparams[i].m;
			c = cparams[i].c;
			break;
		}
	}

	diff = div_u64(diff, diff1);
	ret = ((m * diff) + c);
	ret = div_u64(ret, 10);

4359 4360
	dev_priv->ips.last_count1 = total_count;
	dev_priv->ips.last_time1 = now;
4361

4362
	dev_priv->ips.chipset_power = ret;
4363 4364 4365 4366

	return ret;
}

4367 4368 4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381 4382
unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
{
	unsigned long val;

	if (dev_priv->info->gen != 5)
		return 0;

	spin_lock_irq(&mchdev_lock);

	val = __i915_chipset_val(dev_priv);

	spin_unlock_irq(&mchdev_lock);

	return val;
}

4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460 4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509 4510 4511 4512 4513 4514 4515 4516 4517 4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538
unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
{
	unsigned long m, x, b;
	u32 tsfs;

	tsfs = I915_READ(TSFS);

	m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
	x = I915_READ8(TR1);

	b = tsfs & TSFS_INTR_MASK;

	return ((m * x) / 127) - b;
}

static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
{
	static const struct v_table {
		u16 vd; /* in .1 mil */
		u16 vm; /* in .1 mil */
	} v_table[] = {
		{ 0, 0, },
		{ 375, 0, },
		{ 500, 0, },
		{ 625, 0, },
		{ 750, 0, },
		{ 875, 0, },
		{ 1000, 0, },
		{ 1125, 0, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4125, 3000, },
		{ 4250, 3125, },
		{ 4375, 3250, },
		{ 4500, 3375, },
		{ 4625, 3500, },
		{ 4750, 3625, },
		{ 4875, 3750, },
		{ 5000, 3875, },
		{ 5125, 4000, },
		{ 5250, 4125, },
		{ 5375, 4250, },
		{ 5500, 4375, },
		{ 5625, 4500, },
		{ 5750, 4625, },
		{ 5875, 4750, },
		{ 6000, 4875, },
		{ 6125, 5000, },
		{ 6250, 5125, },
		{ 6375, 5250, },
		{ 6500, 5375, },
		{ 6625, 5500, },
		{ 6750, 5625, },
		{ 6875, 5750, },
		{ 7000, 5875, },
		{ 7125, 6000, },
		{ 7250, 6125, },
		{ 7375, 6250, },
		{ 7500, 6375, },
		{ 7625, 6500, },
		{ 7750, 6625, },
		{ 7875, 6750, },
		{ 8000, 6875, },
		{ 8125, 7000, },
		{ 8250, 7125, },
		{ 8375, 7250, },
		{ 8500, 7375, },
		{ 8625, 7500, },
		{ 8750, 7625, },
		{ 8875, 7750, },
		{ 9000, 7875, },
		{ 9125, 8000, },
		{ 9250, 8125, },
		{ 9375, 8250, },
		{ 9500, 8375, },
		{ 9625, 8500, },
		{ 9750, 8625, },
		{ 9875, 8750, },
		{ 10000, 8875, },
		{ 10125, 9000, },
		{ 10250, 9125, },
		{ 10375, 9250, },
		{ 10500, 9375, },
		{ 10625, 9500, },
		{ 10750, 9625, },
		{ 10875, 9750, },
		{ 11000, 9875, },
		{ 11125, 10000, },
		{ 11250, 10125, },
		{ 11375, 10250, },
		{ 11500, 10375, },
		{ 11625, 10500, },
		{ 11750, 10625, },
		{ 11875, 10750, },
		{ 12000, 10875, },
		{ 12125, 11000, },
		{ 12250, 11125, },
		{ 12375, 11250, },
		{ 12500, 11375, },
		{ 12625, 11500, },
		{ 12750, 11625, },
		{ 12875, 11750, },
		{ 13000, 11875, },
		{ 13125, 12000, },
		{ 13250, 12125, },
		{ 13375, 12250, },
		{ 13500, 12375, },
		{ 13625, 12500, },
		{ 13750, 12625, },
		{ 13875, 12750, },
		{ 14000, 12875, },
		{ 14125, 13000, },
		{ 14250, 13125, },
		{ 14375, 13250, },
		{ 14500, 13375, },
		{ 14625, 13500, },
		{ 14750, 13625, },
		{ 14875, 13750, },
		{ 15000, 13875, },
		{ 15125, 14000, },
		{ 15250, 14125, },
		{ 15375, 14250, },
		{ 15500, 14375, },
		{ 15625, 14500, },
		{ 15750, 14625, },
		{ 15875, 14750, },
		{ 16000, 14875, },
		{ 16125, 15000, },
	};
	if (dev_priv->info->is_mobile)
		return v_table[pxvid].vm;
	else
		return v_table[pxvid].vd;
}

4539
static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4540 4541 4542 4543 4544 4545
{
	struct timespec now, diff1;
	u64 diff;
	unsigned long diffms;
	u32 count;

4546
	assert_spin_locked(&mchdev_lock);
4547 4548

	getrawmonotonic(&now);
4549
	diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4550 4551 4552 4553 4554 4555 4556 4557

	/* Don't divide by 0 */
	diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
	if (!diffms)
		return;

	count = I915_READ(GFXEC);

4558 4559
	if (count < dev_priv->ips.last_count2) {
		diff = ~0UL - dev_priv->ips.last_count2;
4560 4561
		diff += count;
	} else {
4562
		diff = count - dev_priv->ips.last_count2;
4563 4564
	}

4565 4566
	dev_priv->ips.last_count2 = count;
	dev_priv->ips.last_time2 = now;
4567 4568 4569 4570

	/* More magic constants... */
	diff = diff * 1181;
	diff = div_u64(diff, diffms * 10);
4571
	dev_priv->ips.gfx_power = diff;
4572 4573
}

4574 4575 4576 4577 4578
void i915_update_gfx_val(struct drm_i915_private *dev_priv)
{
	if (dev_priv->info->gen != 5)
		return;

4579
	spin_lock_irq(&mchdev_lock);
4580 4581 4582

	__i915_update_gfx_val(dev_priv);

4583
	spin_unlock_irq(&mchdev_lock);
4584 4585
}

4586
static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4587 4588 4589 4590
{
	unsigned long t, corr, state1, corr2, state2;
	u32 pxvid, ext_v;

4591 4592
	assert_spin_locked(&mchdev_lock);

4593
	pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4594 4595 4596 4597 4598 4599 4600 4601 4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612
	pxvid = (pxvid >> 24) & 0x7f;
	ext_v = pvid_to_extvid(dev_priv, pxvid);

	state1 = ext_v;

	t = i915_mch_val(dev_priv);

	/* Revel in the empirically derived constants */

	/* Correction factor in 1/100000 units */
	if (t > 80)
		corr = ((t * 2349) + 135940);
	else if (t >= 50)
		corr = ((t * 964) + 29317);
	else /* < 50 */
		corr = ((t * 301) + 1004);

	corr = corr * ((150142 * state1) / 10000 - 78642);
	corr /= 100000;
4613
	corr2 = (corr * dev_priv->ips.corr);
4614 4615 4616 4617

	state2 = (corr2 * state1) / 10000;
	state2 /= 100; /* convert to mW */

4618
	__i915_update_gfx_val(dev_priv);
4619

4620
	return dev_priv->ips.gfx_power + state2;
4621 4622
}

4623 4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638
unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
{
	unsigned long val;

	if (dev_priv->info->gen != 5)
		return 0;

	spin_lock_irq(&mchdev_lock);

	val = __i915_gfx_val(dev_priv);

	spin_unlock_irq(&mchdev_lock);

	return val;
}

4639 4640 4641 4642 4643 4644 4645 4646 4647 4648 4649
/**
 * i915_read_mch_val - return value for IPS use
 *
 * Calculate and return a value for the IPS driver to use when deciding whether
 * we have thermal and power headroom to increase CPU or GPU power budget.
 */
unsigned long i915_read_mch_val(void)
{
	struct drm_i915_private *dev_priv;
	unsigned long chipset_val, graphics_val, ret = 0;

4650
	spin_lock_irq(&mchdev_lock);
4651 4652 4653 4654
	if (!i915_mch_dev)
		goto out_unlock;
	dev_priv = i915_mch_dev;

4655 4656
	chipset_val = __i915_chipset_val(dev_priv);
	graphics_val = __i915_gfx_val(dev_priv);
4657 4658 4659 4660

	ret = chipset_val + graphics_val;

out_unlock:
4661
	spin_unlock_irq(&mchdev_lock);
4662 4663 4664 4665 4666 4667 4668 4669 4670 4671 4672 4673 4674 4675 4676

	return ret;
}
EXPORT_SYMBOL_GPL(i915_read_mch_val);

/**
 * i915_gpu_raise - raise GPU frequency limit
 *
 * Raise the limit; IPS indicates we have thermal headroom.
 */
bool i915_gpu_raise(void)
{
	struct drm_i915_private *dev_priv;
	bool ret = true;

4677
	spin_lock_irq(&mchdev_lock);
4678 4679 4680 4681 4682 4683
	if (!i915_mch_dev) {
		ret = false;
		goto out_unlock;
	}
	dev_priv = i915_mch_dev;

4684 4685
	if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
		dev_priv->ips.max_delay--;
4686 4687

out_unlock:
4688
	spin_unlock_irq(&mchdev_lock);
4689 4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702 4703 4704

	return ret;
}
EXPORT_SYMBOL_GPL(i915_gpu_raise);

/**
 * i915_gpu_lower - lower GPU frequency limit
 *
 * IPS indicates we're close to a thermal limit, so throttle back the GPU
 * frequency maximum.
 */
bool i915_gpu_lower(void)
{
	struct drm_i915_private *dev_priv;
	bool ret = true;

4705
	spin_lock_irq(&mchdev_lock);
4706 4707 4708 4709 4710 4711
	if (!i915_mch_dev) {
		ret = false;
		goto out_unlock;
	}
	dev_priv = i915_mch_dev;

4712 4713
	if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
		dev_priv->ips.max_delay++;
4714 4715

out_unlock:
4716
	spin_unlock_irq(&mchdev_lock);
4717 4718 4719 4720 4721 4722 4723 4724 4725 4726 4727 4728 4729

	return ret;
}
EXPORT_SYMBOL_GPL(i915_gpu_lower);

/**
 * i915_gpu_busy - indicate GPU business to IPS
 *
 * Tell the IPS driver whether or not the GPU is busy.
 */
bool i915_gpu_busy(void)
{
	struct drm_i915_private *dev_priv;
4730
	struct intel_ring_buffer *ring;
4731
	bool ret = false;
4732
	int i;
4733

4734
	spin_lock_irq(&mchdev_lock);
4735 4736 4737 4738
	if (!i915_mch_dev)
		goto out_unlock;
	dev_priv = i915_mch_dev;

4739 4740
	for_each_ring(ring, dev_priv, i)
		ret |= !list_empty(&ring->request_list);
4741 4742

out_unlock:
4743
	spin_unlock_irq(&mchdev_lock);
4744 4745 4746 4747 4748 4749 4750 4751 4752 4753 4754 4755 4756 4757 4758 4759

	return ret;
}
EXPORT_SYMBOL_GPL(i915_gpu_busy);

/**
 * i915_gpu_turbo_disable - disable graphics turbo
 *
 * Disable graphics turbo by resetting the max frequency and setting the
 * current frequency to the default.
 */
bool i915_gpu_turbo_disable(void)
{
	struct drm_i915_private *dev_priv;
	bool ret = true;

4760
	spin_lock_irq(&mchdev_lock);
4761 4762 4763 4764 4765 4766
	if (!i915_mch_dev) {
		ret = false;
		goto out_unlock;
	}
	dev_priv = i915_mch_dev;

4767
	dev_priv->ips.max_delay = dev_priv->ips.fstart;
4768

4769
	if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4770 4771 4772
		ret = false;

out_unlock:
4773
	spin_unlock_irq(&mchdev_lock);
4774 4775 4776 4777 4778 4779 4780 4781 4782 4783 4784 4785 4786 4787 4788 4789 4790 4791 4792 4793 4794 4795 4796 4797 4798 4799 4800

	return ret;
}
EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);

/**
 * Tells the intel_ips driver that the i915 driver is now loaded, if
 * IPS got loaded first.
 *
 * This awkward dance is so that neither module has to depend on the
 * other in order for IPS to do the appropriate communication of
 * GPU turbo limits to i915.
 */
static void
ips_ping_for_i915_load(void)
{
	void (*link)(void);

	link = symbol_get(ips_link_to_i915_driver);
	if (link) {
		link();
		symbol_put(ips_link_to_i915_driver);
	}
}

void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
{
4801 4802
	/* We only register the i915 ips part with intel-ips once everything is
	 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4803
	spin_lock_irq(&mchdev_lock);
4804
	i915_mch_dev = dev_priv;
4805
	spin_unlock_irq(&mchdev_lock);
4806 4807 4808 4809 4810 4811

	ips_ping_for_i915_load();
}

void intel_gpu_ips_teardown(void)
{
4812
	spin_lock_irq(&mchdev_lock);
4813
	i915_mch_dev = NULL;
4814
	spin_unlock_irq(&mchdev_lock);
4815
}
4816
static void intel_init_emon(struct drm_device *dev)
4817 4818 4819 4820 4821 4822 4823 4824 4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848 4849 4850 4851 4852 4853 4854 4855 4856 4857 4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880 4881 4882 4883
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 lcfuse;
	u8 pxw[16];
	int i;

	/* Disable to program */
	I915_WRITE(ECR, 0);
	POSTING_READ(ECR);

	/* Program energy weights for various events */
	I915_WRITE(SDEW, 0x15040d00);
	I915_WRITE(CSIEW0, 0x007f0000);
	I915_WRITE(CSIEW1, 0x1e220004);
	I915_WRITE(CSIEW2, 0x04000004);

	for (i = 0; i < 5; i++)
		I915_WRITE(PEW + (i * 4), 0);
	for (i = 0; i < 3; i++)
		I915_WRITE(DEW + (i * 4), 0);

	/* Program P-state weights to account for frequency power adjustment */
	for (i = 0; i < 16; i++) {
		u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
		unsigned long freq = intel_pxfreq(pxvidfreq);
		unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
			PXVFREQ_PX_SHIFT;
		unsigned long val;

		val = vid * vid;
		val *= (freq / 1000);
		val *= 255;
		val /= (127*127*900);
		if (val > 0xff)
			DRM_ERROR("bad pxval: %ld\n", val);
		pxw[i] = val;
	}
	/* Render standby states get 0 weight */
	pxw[14] = 0;
	pxw[15] = 0;

	for (i = 0; i < 4; i++) {
		u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
			(pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
		I915_WRITE(PXW + (i * 4), val);
	}

	/* Adjust magic regs to magic values (more experimental results) */
	I915_WRITE(OGW0, 0);
	I915_WRITE(OGW1, 0);
	I915_WRITE(EG0, 0x00007f00);
	I915_WRITE(EG1, 0x0000000e);
	I915_WRITE(EG2, 0x000e0000);
	I915_WRITE(EG3, 0x68000300);
	I915_WRITE(EG4, 0x42000000);
	I915_WRITE(EG5, 0x00140031);
	I915_WRITE(EG6, 0);
	I915_WRITE(EG7, 0);

	for (i = 0; i < 8; i++)
		I915_WRITE(PXWL + (i * 4), 0);

	/* Enable PMON + select events */
	I915_WRITE(ECR, 0x80000019);

	lcfuse = I915_READ(LCFUSE02);

4884
	dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4885 4886
}

4887 4888
void intel_disable_gt_powersave(struct drm_device *dev)
{
4889 4890
	struct drm_i915_private *dev_priv = dev->dev_private;

4891 4892 4893
	/* Interrupts should be disabled already to avoid re-arming. */
	WARN_ON(dev->irq_enabled);

4894
	if (IS_IRONLAKE_M(dev)) {
4895
		ironlake_disable_drps(dev);
4896
		ironlake_disable_rc6(dev);
4897
	} else if (INTEL_INFO(dev)->gen >= 6) {
4898
		cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4899
		cancel_work_sync(&dev_priv->rps.work);
4900
		mutex_lock(&dev_priv->rps.hw_lock);
4901 4902 4903 4904
		if (IS_VALLEYVIEW(dev))
			valleyview_disable_rps(dev);
		else
			gen6_disable_rps(dev);
4905
		dev_priv->rps.enabled = false;
4906
		mutex_unlock(&dev_priv->rps.hw_lock);
4907
	}
4908 4909
}

4910 4911 4912 4913 4914 4915 4916
static void intel_gen6_powersave_work(struct work_struct *work)
{
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private,
			     rps.delayed_resume_work.work);
	struct drm_device *dev = dev_priv->dev;

4917
	mutex_lock(&dev_priv->rps.hw_lock);
4918 4919 4920

	if (IS_VALLEYVIEW(dev)) {
		valleyview_enable_rps(dev);
4921 4922 4923
	} else if (IS_BROADWELL(dev)) {
		gen8_enable_rps(dev);
		gen6_update_ring_freq(dev);
4924 4925 4926 4927
	} else {
		gen6_enable_rps(dev);
		gen6_update_ring_freq(dev);
	}
4928
	dev_priv->rps.enabled = true;
4929
	mutex_unlock(&dev_priv->rps.hw_lock);
4930 4931
}

4932 4933
void intel_enable_gt_powersave(struct drm_device *dev)
{
4934 4935
	struct drm_i915_private *dev_priv = dev->dev_private;

4936 4937 4938 4939
	if (IS_IRONLAKE_M(dev)) {
		ironlake_enable_drps(dev);
		ironlake_enable_rc6(dev);
		intel_init_emon(dev);
4940
	} else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4941 4942 4943 4944 4945 4946 4947
		/*
		 * PCU communication is slow and this doesn't need to be
		 * done at any specific time, so do this out of our fast path
		 * to make resume and init faster.
		 */
		schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
				      round_jiffies_up_relative(HZ));
4948 4949 4950
	}
}

4951 4952 4953 4954 4955 4956 4957 4958 4959 4960 4961 4962
static void ibx_init_clock_gating(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	/*
	 * On Ibex Peak and Cougar Point, we need to disable clock
	 * gating for the panel power sequencer or it will fail to
	 * start up when no ports are active.
	 */
	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
}

4963 4964 4965 4966 4967 4968 4969 4970 4971
static void g4x_disable_trickle_feed(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe;

	for_each_pipe(pipe) {
		I915_WRITE(DSPCNTR(pipe),
			   I915_READ(DSPCNTR(pipe)) |
			   DISPPLANE_TRICKLE_FEED_DISABLE);
4972
		intel_flush_primary_plane(dev_priv, pipe);
4973 4974 4975
	}
}

4976
static void ironlake_init_clock_gating(struct drm_device *dev)
4977 4978
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4979
	uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4980

4981 4982 4983 4984
	/*
	 * Required for FBC
	 * WaFbcDisableDpfcClockGating:ilk
	 */
4985 4986 4987
	dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
		   ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4988 4989 4990 4991 4992 4993 4994 4995 4996 4997 4998 4999 5000 5001 5002 5003 5004

	I915_WRITE(PCH_3DCGDIS0,
		   MARIUNIT_CLOCK_GATE_DISABLE |
		   SVSMUNIT_CLOCK_GATE_DISABLE);
	I915_WRITE(PCH_3DCGDIS1,
		   VFMUNIT_CLOCK_GATE_DISABLE);

	/*
	 * According to the spec the following bits should be set in
	 * order to enable memory self-refresh
	 * The bit 22/21 of 0x42004
	 * The bit 5 of 0x42020
	 * The bit 15 of 0x45000
	 */
	I915_WRITE(ILK_DISPLAY_CHICKEN2,
		   (I915_READ(ILK_DISPLAY_CHICKEN2) |
		    ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5005
	dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
5006 5007 5008 5009 5010 5011 5012 5013 5014 5015 5016 5017 5018 5019 5020
	I915_WRITE(DISP_ARB_CTL,
		   (I915_READ(DISP_ARB_CTL) |
		    DISP_FBC_WM_DIS));
	I915_WRITE(WM3_LP_ILK, 0);
	I915_WRITE(WM2_LP_ILK, 0);
	I915_WRITE(WM1_LP_ILK, 0);

	/*
	 * Based on the document from hardware guys the following bits
	 * should be set unconditionally in order to enable FBC.
	 * The bit 22 of 0x42000
	 * The bit 22 of 0x42004
	 * The bit 7,8,9 of 0x42020.
	 */
	if (IS_IRONLAKE_M(dev)) {
5021
		/* WaFbcAsynchFlipDisableFbcQueue:ilk */
5022 5023 5024 5025 5026 5027 5028 5029
		I915_WRITE(ILK_DISPLAY_CHICKEN1,
			   I915_READ(ILK_DISPLAY_CHICKEN1) |
			   ILK_FBCQ_DIS);
		I915_WRITE(ILK_DISPLAY_CHICKEN2,
			   I915_READ(ILK_DISPLAY_CHICKEN2) |
			   ILK_DPARB_GATE);
	}

5030 5031
	I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);

5032 5033 5034 5035 5036 5037
	I915_WRITE(ILK_DISPLAY_CHICKEN2,
		   I915_READ(ILK_DISPLAY_CHICKEN2) |
		   ILK_ELPIN_409_SELECT);
	I915_WRITE(_3D_CHICKEN2,
		   _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
		   _3D_CHICKEN2_WM_READ_PIPELINED);
5038

5039
	/* WaDisableRenderCachePipelinedFlush:ilk */
5040 5041
	I915_WRITE(CACHE_MODE_0,
		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5042

5043
	g4x_disable_trickle_feed(dev);
5044

5045 5046 5047 5048 5049 5050 5051
	ibx_init_clock_gating(dev);
}

static void cpt_init_clock_gating(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe;
5052
	uint32_t val;
5053 5054 5055 5056 5057 5058

	/*
	 * On Ibex Peak and Cougar Point, we need to disable clock
	 * gating for the panel power sequencer or it will fail to
	 * start up when no ports are active.
	 */
5059 5060 5061
	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
		   PCH_DPLUNIT_CLOCK_GATE_DISABLE |
		   PCH_CPUNIT_CLOCK_GATE_DISABLE);
5062 5063
	I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
		   DPLS_EDP_PPS_FIX_DIS);
5064 5065 5066
	/* The below fixes the weird display corruption, a few pixels shifted
	 * downward, on (only) LVDS of some HP laptops with IVY.
	 */
5067
	for_each_pipe(pipe) {
5068 5069 5070
		val = I915_READ(TRANS_CHICKEN2(pipe));
		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
		val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5071
		if (dev_priv->vbt.fdi_rx_polarity_inverted)
5072
			val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
5073 5074 5075
		val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
		val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
		val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
5076 5077
		I915_WRITE(TRANS_CHICKEN2(pipe), val);
	}
5078 5079 5080 5081 5082
	/* WADP0ClockGatingDisable */
	for_each_pipe(pipe) {
		I915_WRITE(TRANS_CHICKEN1(pipe),
			   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
	}
5083 5084
}

5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097
static void gen6_check_mch_setup(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t tmp;

	tmp = I915_READ(MCH_SSKPD);
	if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
		DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
		DRM_INFO("This can cause pipe underruns and display issues.\n");
		DRM_INFO("Please upgrade your BIOS to fix this.\n");
	}
}

5098
static void gen6_init_clock_gating(struct drm_device *dev)
5099 5100
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5101
	uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
5102

5103
	I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5104 5105 5106 5107 5108

	I915_WRITE(ILK_DISPLAY_CHICKEN2,
		   I915_READ(ILK_DISPLAY_CHICKEN2) |
		   ILK_ELPIN_409_SELECT);

5109
	/* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5110 5111 5112
	I915_WRITE(_3D_CHICKEN,
		   _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));

5113
	/* WaSetupGtModeTdRowDispatch:snb */
5114 5115 5116 5117
	if (IS_SNB_GT1(dev))
		I915_WRITE(GEN6_GT_MODE,
			   _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));

5118 5119 5120 5121 5122
	I915_WRITE(WM3_LP_ILK, 0);
	I915_WRITE(WM2_LP_ILK, 0);
	I915_WRITE(WM1_LP_ILK, 0);

	I915_WRITE(CACHE_MODE_0,
5123
		   _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
5124 5125 5126 5127 5128 5129 5130 5131 5132 5133 5134 5135 5136 5137 5138

	I915_WRITE(GEN6_UCGCTL1,
		   I915_READ(GEN6_UCGCTL1) |
		   GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
		   GEN6_CSUNIT_CLOCK_GATE_DISABLE);

	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
	 * gating disable must be set.  Failure to set it results in
	 * flickering pixels due to Z write ordering failures after
	 * some amount of runtime in the Mesa "fire" demo, and Unigine
	 * Sanctuary and Tropics, and apparently anything else with
	 * alpha test or pixel discard.
	 *
	 * According to the spec, bit 11 (RCCUNIT) must also be set,
	 * but we didn't debug actual testcases to find it out.
5139
	 *
5140 5141
	 * Also apply WaDisableVDSUnitClockGating:snb and
	 * WaDisableRCPBUnitClockGating:snb.
5142 5143
	 */
	I915_WRITE(GEN6_UCGCTL2,
5144
		   GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5145 5146 5147 5148
		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);

	/* Bspec says we need to always set all mask bits. */
5149 5150
	I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
		   _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
5151 5152 5153 5154 5155 5156 5157 5158 5159

	/*
	 * According to the spec the following bits should be
	 * set in order to enable memory self-refresh and fbc:
	 * The bit21 and bit22 of 0x42000
	 * The bit21 and bit22 of 0x42004
	 * The bit5 and bit7 of 0x42020
	 * The bit14 of 0x70180
	 * The bit14 of 0x71180
5160 5161
	 *
	 * WaFbcAsynchFlipDisableFbcQueue:snb
5162 5163 5164 5165 5166 5167 5168
	 */
	I915_WRITE(ILK_DISPLAY_CHICKEN1,
		   I915_READ(ILK_DISPLAY_CHICKEN1) |
		   ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
	I915_WRITE(ILK_DISPLAY_CHICKEN2,
		   I915_READ(ILK_DISPLAY_CHICKEN2) |
		   ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5169 5170 5171 5172
	I915_WRITE(ILK_DSPCLK_GATE_D,
		   I915_READ(ILK_DSPCLK_GATE_D) |
		   ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5173

5174
	g4x_disable_trickle_feed(dev);
B
Ben Widawsky 已提交
5175 5176 5177 5178 5179

	/* The default value should be 0x200 according to docs, but the two
	 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
	I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
	I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
5180 5181

	cpt_init_clock_gating(dev);
5182 5183

	gen6_check_mch_setup(dev);
5184 5185 5186 5187 5188 5189 5190 5191 5192 5193 5194
}

static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
{
	uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);

	reg &= ~GEN7_FF_SCHED_MASK;
	reg |= GEN7_FF_TS_SCHED_HW;
	reg |= GEN7_FF_VS_SCHED_HW;
	reg |= GEN7_FF_DS_SCHED_HW;

5195 5196 5197
	if (IS_HASWELL(dev_priv->dev))
		reg &= ~GEN7_FF_VS_REF_CNT_FFME;

5198 5199 5200
	I915_WRITE(GEN7_FF_THREAD_MODE, reg);
}

5201 5202 5203 5204 5205 5206 5207 5208 5209 5210 5211 5212
static void lpt_init_clock_gating(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	/*
	 * TODO: this bit should only be enabled when really needed, then
	 * disabled when not needed anymore in order to save power.
	 */
	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
		I915_WRITE(SOUTH_DSPCLK_GATE_D,
			   I915_READ(SOUTH_DSPCLK_GATE_D) |
			   PCH_LP_PARTITION_LEVEL_DISABLE);
5213 5214 5215 5216 5217

	/* WADPOClockGatingDisable:hsw */
	I915_WRITE(_TRANSA_CHICKEN1,
		   I915_READ(_TRANSA_CHICKEN1) |
		   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5218 5219
}

5220 5221 5222 5223 5224 5225 5226 5227 5228 5229 5230 5231
static void lpt_suspend_hw(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
		uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);

		val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
	}
}

B
Ben Widawsky 已提交
5232 5233 5234
static void gen8_init_clock_gating(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5235
	enum pipe i;
B
Ben Widawsky 已提交
5236 5237 5238 5239

	I915_WRITE(WM3_LP_ILK, 0);
	I915_WRITE(WM2_LP_ILK, 0);
	I915_WRITE(WM1_LP_ILK, 0);
5240 5241 5242 5243

	/* FIXME(BDW): Check all the w/a, some might only apply to
	 * pre-production hw. */

5244 5245 5246 5247
	WARN(!i915_preliminary_hw_support,
	     "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
	I915_WRITE(HALF_SLICE_CHICKEN3,
		   _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
5248 5249
	I915_WRITE(HALF_SLICE_CHICKEN3,
		   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5250 5251
	I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));

5252 5253 5254
	I915_WRITE(_3D_CHICKEN3,
		   _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));

5255 5256 5257
	I915_WRITE(COMMON_SLICE_CHICKEN2,
		   _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));

5258 5259 5260
	I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
		   _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));

5261 5262
	/* WaSwitchSolVfFArbitrationPriority */
	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5263 5264 5265 5266 5267 5268 5269 5270 5271 5272 5273

	/* WaPsrDPAMaskVBlankInSRD */
	I915_WRITE(CHICKEN_PAR1_1,
		   I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);

	/* WaPsrDPRSUnmaskVBlankInSRD */
	for_each_pipe(i) {
		I915_WRITE(CHICKEN_PIPESL_1(i),
			   I915_READ(CHICKEN_PIPESL_1(i) |
				     DPRS_MASK_VBLANK_SRD));
	}
B
Ben Widawsky 已提交
5274 5275
}

5276 5277 5278 5279 5280 5281 5282 5283 5284
static void haswell_init_clock_gating(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(WM3_LP_ILK, 0);
	I915_WRITE(WM2_LP_ILK, 0);
	I915_WRITE(WM1_LP_ILK, 0);

	/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5285
	 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
5286 5287 5288
	 */
	I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);

5289
	/* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
5290 5291 5292
	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);

5293
	/* WaApplyL3ControlAndL3ChickenMode:hsw */
5294 5295 5296 5297 5298
	I915_WRITE(GEN7_L3CNTLREG1,
			GEN7_WA_FOR_GEN7_L3_CONTROL);
	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
			GEN7_WA_L3_CHICKEN_MODE);

5299 5300 5301 5302 5303
	/* L3 caching of data atomics doesn't work -- disable it. */
	I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
	I915_WRITE(HSW_ROW_CHICKEN3,
		   _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));

5304
	/* This is required by WaCatErrorRejectionIssue:hsw */
5305 5306 5307 5308
	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);

5309
	/* WaVSRefCountFullforceMissDisable:hsw */
5310 5311
	gen7_setup_fixed_func_scheduler(dev_priv);

5312
	/* WaDisable4x2SubspanOptimization:hsw */
5313 5314
	I915_WRITE(CACHE_MODE_1,
		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5315

5316
	/* WaSwitchSolVfFArbitrationPriority:hsw */
5317 5318
	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);

5319 5320 5321
	/* WaRsPkgCStateDisplayPMReq:hsw */
	I915_WRITE(CHICKEN_PAR1_1,
		   I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5322

5323
	lpt_init_clock_gating(dev);
5324 5325
}

5326
static void ivybridge_init_clock_gating(struct drm_device *dev)
5327 5328
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5329
	uint32_t snpcr;
5330 5331 5332 5333 5334

	I915_WRITE(WM3_LP_ILK, 0);
	I915_WRITE(WM2_LP_ILK, 0);
	I915_WRITE(WM1_LP_ILK, 0);

5335
	I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5336

5337
	/* WaDisableEarlyCull:ivb */
5338 5339 5340
	I915_WRITE(_3D_CHICKEN3,
		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));

5341
	/* WaDisableBackToBackFlipFix:ivb */
5342 5343 5344 5345
	I915_WRITE(IVB_CHICKEN3,
		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
		   CHICKEN3_DGMG_DONE_FIX_DISABLE);

5346
	/* WaDisablePSDDualDispatchEnable:ivb */
5347 5348 5349 5350 5351 5352 5353
	if (IS_IVB_GT1(dev))
		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
	else
		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));

5354
	/* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5355 5356 5357
	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);

5358
	/* WaApplyL3ControlAndL3ChickenMode:ivb */
5359 5360 5361
	I915_WRITE(GEN7_L3CNTLREG1,
			GEN7_WA_FOR_GEN7_L3_CONTROL);
	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5362 5363 5364 5365 5366 5367 5368 5369
		   GEN7_WA_L3_CHICKEN_MODE);
	if (IS_IVB_GT1(dev))
		I915_WRITE(GEN7_ROW_CHICKEN2,
			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
	else
		I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));

5370

5371
	/* WaForceL3Serialization:ivb */
5372 5373 5374
	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);

5375 5376 5377 5378 5379 5380 5381 5382 5383 5384 5385
	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
	 * gating disable must be set.  Failure to set it results in
	 * flickering pixels due to Z write ordering failures after
	 * some amount of runtime in the Mesa "fire" demo, and Unigine
	 * Sanctuary and Tropics, and apparently anything else with
	 * alpha test or pixel discard.
	 *
	 * According to the spec, bit 11 (RCCUNIT) must also be set,
	 * but we didn't debug actual testcases to find it out.
	 *
	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5386
	 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5387 5388 5389 5390 5391
	 */
	I915_WRITE(GEN6_UCGCTL2,
		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);

5392
	/* This is required by WaCatErrorRejectionIssue:ivb */
5393 5394 5395 5396
	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);

5397
	g4x_disable_trickle_feed(dev);
5398

5399
	/* WaVSRefCountFullforceMissDisable:ivb */
5400
	gen7_setup_fixed_func_scheduler(dev_priv);
5401

5402
	/* WaDisable4x2SubspanOptimization:ivb */
5403 5404
	I915_WRITE(CACHE_MODE_1,
		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5405 5406 5407 5408 5409

	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
	snpcr &= ~GEN6_MBC_SNPCR_MASK;
	snpcr |= GEN6_MBC_SNPCR_MED;
	I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5410

5411 5412
	if (!HAS_PCH_NOP(dev))
		cpt_init_clock_gating(dev);
5413 5414

	gen6_check_mch_setup(dev);
5415 5416
}

5417
static void valleyview_init_clock_gating(struct drm_device *dev)
5418 5419
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5420 5421 5422 5423 5424 5425 5426 5427 5428
	u32 val;

	mutex_lock(&dev_priv->rps.hw_lock);
	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
	mutex_unlock(&dev_priv->rps.hw_lock);
	switch ((val >> 6) & 3) {
	case 0:
		dev_priv->mem_freq = 800;
		break;
5429
	case 1:
5430 5431
		dev_priv->mem_freq = 1066;
		break;
5432
	case 2:
5433 5434
		dev_priv->mem_freq = 1333;
		break;
5435
	case 3:
5436
		dev_priv->mem_freq = 1333;
5437
		break;
5438 5439
	}
	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5440

5441
	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5442

5443
	/* WaDisableEarlyCull:vlv */
5444 5445 5446
	I915_WRITE(_3D_CHICKEN3,
		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));

5447
	/* WaDisableBackToBackFlipFix:vlv */
5448 5449 5450 5451
	I915_WRITE(IVB_CHICKEN3,
		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
		   CHICKEN3_DGMG_DONE_FIX_DISABLE);

5452
	/* WaDisablePSDDualDispatchEnable:vlv */
5453
	I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5454 5455
		   _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
				      GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5456

5457
	/* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
5458 5459 5460
	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);

5461
	/* WaApplyL3ControlAndL3ChickenMode:vlv */
5462
	I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
5463 5464
	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);

5465
	/* WaForceL3Serialization:vlv */
5466 5467 5468
	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);

5469
	/* WaDisableDopClockGating:vlv */
5470 5471 5472
	I915_WRITE(GEN7_ROW_CHICKEN2,
		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));

5473
	/* This is required by WaCatErrorRejectionIssue:vlv */
5474 5475 5476 5477
	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);

5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488
	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
	 * gating disable must be set.  Failure to set it results in
	 * flickering pixels due to Z write ordering failures after
	 * some amount of runtime in the Mesa "fire" demo, and Unigine
	 * Sanctuary and Tropics, and apparently anything else with
	 * alpha test or pixel discard.
	 *
	 * According to the spec, bit 11 (RCCUNIT) must also be set,
	 * but we didn't debug actual testcases to find it out.
	 *
	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5489
	 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5490
	 *
5491 5492
	 * Also apply WaDisableVDSUnitClockGating:vlv and
	 * WaDisableRCPBUnitClockGating:vlv.
5493 5494 5495
	 */
	I915_WRITE(GEN6_UCGCTL2,
		   GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5496
		   GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
5497 5498 5499 5500
		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);

5501 5502
	I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);

5503
	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5504

5505 5506
	I915_WRITE(CACHE_MODE_1,
		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5507

5508
	/*
5509
	 * WaDisableVLVClockGating_VBIIssue:vlv
5510 5511 5512
	 * Disable clock gating on th GCFG unit to prevent a delay
	 * in the reporting of vblank events.
	 */
5513 5514 5515 5516 5517 5518 5519 5520 5521 5522
	I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);

	/* Conservative clock gating settings for now */
	I915_WRITE(0x9400, 0xffffffff);
	I915_WRITE(0x9404, 0xffffffff);
	I915_WRITE(0x9408, 0xffffffff);
	I915_WRITE(0x940c, 0xffffffff);
	I915_WRITE(0x9410, 0xffffffff);
	I915_WRITE(0x9414, 0xffffffff);
	I915_WRITE(0x9418, 0xffffffff);
5523 5524
}

5525
static void g4x_init_clock_gating(struct drm_device *dev)
5526 5527 5528 5529 5530 5531 5532 5533 5534 5535 5536 5537 5538 5539 5540
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dspclk_gate;

	I915_WRITE(RENCLK_GATE_D1, 0);
	I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
		   GS_UNIT_CLOCK_GATE_DISABLE |
		   CL_UNIT_CLOCK_GATE_DISABLE);
	I915_WRITE(RAMCLK_GATE_D, 0);
	dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
		OVRUNIT_CLOCK_GATE_DISABLE |
		OVCUNIT_CLOCK_GATE_DISABLE;
	if (IS_GM45(dev))
		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
	I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5541 5542 5543 5544

	/* WaDisableRenderCachePipelinedFlush */
	I915_WRITE(CACHE_MODE_0,
		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5545

5546
	g4x_disable_trickle_feed(dev);
5547 5548
}

5549
static void crestline_init_clock_gating(struct drm_device *dev)
5550 5551 5552 5553 5554 5555 5556 5557
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
	I915_WRITE(RENCLK_GATE_D2, 0);
	I915_WRITE(DSPCLK_GATE_D, 0);
	I915_WRITE(RAMCLK_GATE_D, 0);
	I915_WRITE16(DEUC, 0);
5558 5559
	I915_WRITE(MI_ARB_STATE,
		   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5560 5561
}

5562
static void broadwater_init_clock_gating(struct drm_device *dev)
5563 5564 5565 5566 5567 5568 5569 5570 5571
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
		   I965_RCC_CLOCK_GATE_DISABLE |
		   I965_RCPB_CLOCK_GATE_DISABLE |
		   I965_ISC_CLOCK_GATE_DISABLE |
		   I965_FBC_CLOCK_GATE_DISABLE);
	I915_WRITE(RENCLK_GATE_D2, 0);
5572 5573
	I915_WRITE(MI_ARB_STATE,
		   _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5574 5575
}

5576
static void gen3_init_clock_gating(struct drm_device *dev)
5577 5578 5579 5580 5581 5582 5583
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dstate = I915_READ(D_STATE);

	dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
		DSTATE_DOT_CLOCK_GATING;
	I915_WRITE(D_STATE, dstate);
5584 5585 5586

	if (IS_PINEVIEW(dev))
		I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5587 5588 5589

	/* IIR "flip pending" means done if this bit is set */
	I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5590 5591
}

5592
static void i85x_init_clock_gating(struct drm_device *dev)
5593 5594 5595 5596 5597 5598
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
}

5599
static void i830_init_clock_gating(struct drm_device *dev)
5600 5601 5602 5603 5604 5605 5606 5607 5608 5609 5610 5611 5612
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
}

void intel_init_clock_gating(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	dev_priv->display.init_clock_gating(dev);
}

5613 5614 5615 5616 5617 5618
void intel_suspend_hw(struct drm_device *dev)
{
	if (HAS_PCH_LPT(dev))
		lpt_suspend_hw(dev);
}

5619 5620 5621 5622 5623 5624 5625 5626 5627 5628 5629 5630 5631
#define for_each_power_well(i, power_well, domain_mask, power_domains)	\
	for (i = 0;							\
	     i < (power_domains)->power_well_count &&			\
		 ((power_well) = &(power_domains)->power_wells[i]);	\
	     i++)							\
		if ((power_well)->domains & (domain_mask))

#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
	for (i = (power_domains)->power_well_count - 1;			 \
	     i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
	     i--)							 \
		if ((power_well)->domains & (domain_mask))

5632 5633 5634 5635 5636
/**
 * We should only use the power well if we explicitly asked the hardware to
 * enable it, so check if it's enabled and also check if we've requested it to
 * be enabled.
 */
5637 5638 5639 5640 5641 5642 5643 5644 5645
static bool hsw_power_well_enabled(struct drm_device *dev,
				   struct i915_power_well *power_well)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	return I915_READ(HSW_PWR_WELL_DRIVER) ==
		     (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
}

5646 5647 5648 5649 5650 5651 5652 5653 5654 5655 5656
bool intel_display_power_enabled_sw(struct drm_device *dev,
				    enum intel_display_power_domain domain)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct i915_power_domains *power_domains;

	power_domains = &dev_priv->power_domains;

	return power_domains->domain_use_count[domain];
}

5657 5658
bool intel_display_power_enabled(struct drm_device *dev,
				 enum intel_display_power_domain domain)
5659 5660
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5661 5662 5663 5664
	struct i915_power_domains *power_domains;
	struct i915_power_well *power_well;
	bool is_enabled;
	int i;
5665

5666 5667 5668 5669 5670 5671
	power_domains = &dev_priv->power_domains;

	is_enabled = true;

	mutex_lock(&power_domains->lock);
	for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5672 5673 5674
		if (power_well->always_on)
			continue;

5675 5676 5677 5678 5679 5680 5681 5682
		if (!power_well->is_enabled(dev, power_well)) {
			is_enabled = false;
			break;
		}
	}
	mutex_unlock(&power_domains->lock);

	return is_enabled;
5683 5684
}

5685 5686 5687 5688 5689
static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	unsigned long irqflags;

5690 5691 5692 5693 5694 5695 5696 5697 5698 5699 5700 5701 5702 5703
	/*
	 * After we re-enable the power well, if we touch VGA register 0x3d5
	 * we'll get unclaimed register interrupts. This stops after we write
	 * anything to the VGA MSR register. The vgacon module uses this
	 * register all the time, so if we unbind our driver and, as a
	 * consequence, bind vgacon, we'll get stuck in an infinite loop at
	 * console_unlock(). So make here we touch the VGA MSR register, making
	 * sure vgacon can keep working normally without triggering interrupts
	 * and error messages.
	 */
	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
	outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);

5704 5705 5706 5707 5708 5709 5710 5711 5712 5713 5714 5715 5716 5717 5718 5719 5720 5721 5722 5723 5724 5725 5726 5727 5728 5729 5730 5731 5732 5733 5734 5735 5736 5737 5738 5739 5740
	if (IS_BROADWELL(dev)) {
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
			   dev_priv->de_irq_mask[PIPE_B]);
		I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
			   ~dev_priv->de_irq_mask[PIPE_B] |
			   GEN8_PIPE_VBLANK);
		I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
			   dev_priv->de_irq_mask[PIPE_C]);
		I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
			   ~dev_priv->de_irq_mask[PIPE_C] |
			   GEN8_PIPE_VBLANK);
		POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
	}
}

static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	enum pipe p;
	unsigned long irqflags;

	/*
	 * After this, the registers on the pipes that are part of the power
	 * well will become zero, so we have to adjust our counters according to
	 * that.
	 *
	 * FIXME: Should we do this in general in drm_vblank_post_modeset?
	 */
	spin_lock_irqsave(&dev->vbl_lock, irqflags);
	for_each_pipe(p)
		if (p != PIPE_A)
			dev->vblank[p].last = 0;
	spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
}

5741 5742
static void hsw_set_power_well(struct drm_device *dev,
			       struct i915_power_well *power_well, bool enable)
5743 5744
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5745 5746
	bool is_enabled, enable_requested;
	uint32_t tmp;
5747

5748 5749
	WARN_ON(dev_priv->pc8.enabled);

5750
	tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5751 5752
	is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
	enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5753

5754 5755
	if (enable) {
		if (!enable_requested)
5756 5757
			I915_WRITE(HSW_PWR_WELL_DRIVER,
				   HSW_PWR_WELL_ENABLE_REQUEST);
5758

5759 5760 5761
		if (!is_enabled) {
			DRM_DEBUG_KMS("Enabling power well\n");
			if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5762
				      HSW_PWR_WELL_STATE_ENABLED), 20))
5763 5764
				DRM_ERROR("Timeout enabling power well\n");
		}
5765

5766
		hsw_power_well_post_enable(dev_priv);
5767 5768 5769
	} else {
		if (enable_requested) {
			I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5770
			POSTING_READ(HSW_PWR_WELL_DRIVER);
5771
			DRM_DEBUG_KMS("Requesting to disable the power well\n");
5772

5773
			hsw_power_well_post_disable(dev_priv);
5774 5775
		}
	}
5776
}
5777

5778 5779
static void __intel_power_well_get(struct drm_device *dev,
				   struct i915_power_well *power_well)
5780
{
5781 5782 5783 5784
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!power_well->count++ && power_well->set) {
		hsw_disable_package_c8(dev_priv);
5785
		power_well->set(dev, power_well, true);
5786
	}
5787 5788
}

5789 5790
static void __intel_power_well_put(struct drm_device *dev,
				   struct i915_power_well *power_well)
5791
{
5792 5793
	struct drm_i915_private *dev_priv = dev->dev_private;

5794
	WARN_ON(!power_well->count);
5795

5796 5797
	if (!--power_well->count && power_well->set &&
	    i915_disable_power_well) {
5798
		power_well->set(dev, power_well, false);
5799 5800
		hsw_enable_package_c8(dev_priv);
	}
5801 5802
}

5803 5804 5805 5806
void intel_display_power_get(struct drm_device *dev,
			     enum intel_display_power_domain domain)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5807
	struct i915_power_domains *power_domains;
5808 5809
	struct i915_power_well *power_well;
	int i;
5810

5811 5812 5813
	power_domains = &dev_priv->power_domains;

	mutex_lock(&power_domains->lock);
5814

5815 5816
	for_each_power_well(i, power_well, BIT(domain), power_domains)
		__intel_power_well_get(dev, power_well);
5817

5818 5819
	power_domains->domain_use_count[domain]++;

5820
	mutex_unlock(&power_domains->lock);
5821 5822 5823 5824 5825 5826
}

void intel_display_power_put(struct drm_device *dev,
			     enum intel_display_power_domain domain)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5827
	struct i915_power_domains *power_domains;
5828 5829
	struct i915_power_well *power_well;
	int i;
5830

5831 5832 5833
	power_domains = &dev_priv->power_domains;

	mutex_lock(&power_domains->lock);
5834 5835 5836

	WARN_ON(!power_domains->domain_use_count[domain]);
	power_domains->domain_use_count[domain]--;
5837 5838 5839

	for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
		__intel_power_well_put(dev, power_well);
5840

5841
	mutex_unlock(&power_domains->lock);
5842 5843
}

5844
static struct i915_power_domains *hsw_pwr;
5845 5846 5847 5848

/* Display audio driver power well request */
void i915_request_power_well(void)
{
5849 5850
	struct drm_i915_private *dev_priv;

5851 5852 5853
	if (WARN_ON(!hsw_pwr))
		return;

5854 5855
	dev_priv = container_of(hsw_pwr, struct drm_i915_private,
				power_domains);
I
Imre Deak 已提交
5856
	intel_display_power_get(dev_priv->dev, POWER_DOMAIN_AUDIO);
5857 5858 5859 5860 5861 5862
}
EXPORT_SYMBOL_GPL(i915_request_power_well);

/* Display audio driver power well release */
void i915_release_power_well(void)
{
5863 5864
	struct drm_i915_private *dev_priv;

5865 5866 5867
	if (WARN_ON(!hsw_pwr))
		return;

5868 5869
	dev_priv = container_of(hsw_pwr, struct drm_i915_private,
				power_domains);
I
Imre Deak 已提交
5870
	intel_display_power_put(dev_priv->dev, POWER_DOMAIN_AUDIO);
5871 5872 5873
}
EXPORT_SYMBOL_GPL(i915_release_power_well);

5874 5875 5876 5877 5878 5879 5880 5881
static struct i915_power_well i9xx_always_on_power_well[] = {
	{
		.name = "always-on",
		.always_on = 1,
		.domains = POWER_DOMAIN_MASK,
	},
};

5882
static struct i915_power_well hsw_power_wells[] = {
5883 5884 5885 5886 5887
	{
		.name = "always-on",
		.always_on = 1,
		.domains = HSW_ALWAYS_ON_POWER_DOMAINS,
	},
5888 5889 5890 5891 5892 5893 5894 5895 5896
	{
		.name = "display",
		.domains = POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS,
		.is_enabled = hsw_power_well_enabled,
		.set = hsw_set_power_well,
	},
};

static struct i915_power_well bdw_power_wells[] = {
5897 5898 5899 5900 5901
	{
		.name = "always-on",
		.always_on = 1,
		.domains = BDW_ALWAYS_ON_POWER_DOMAINS,
	},
5902 5903 5904 5905 5906 5907 5908 5909 5910 5911 5912 5913 5914
	{
		.name = "display",
		.domains = POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS,
		.is_enabled = hsw_power_well_enabled,
		.set = hsw_set_power_well,
	},
};

#define set_power_wells(power_domains, __power_wells) ({		\
	(power_domains)->power_wells = (__power_wells);			\
	(power_domains)->power_well_count = ARRAY_SIZE(__power_wells);	\
})

5915
int intel_power_domains_init(struct drm_device *dev)
5916 5917
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5918
	struct i915_power_domains *power_domains = &dev_priv->power_domains;
5919

5920
	mutex_init(&power_domains->lock);
5921

5922 5923 5924 5925 5926 5927 5928 5929 5930 5931 5932
	/*
	 * The enabling order will be from lower to higher indexed wells,
	 * the disabling order is reversed.
	 */
	if (IS_HASWELL(dev)) {
		set_power_wells(power_domains, hsw_power_wells);
		hsw_pwr = power_domains;
	} else if (IS_BROADWELL(dev)) {
		set_power_wells(power_domains, bdw_power_wells);
		hsw_pwr = power_domains;
	} else {
5933
		set_power_wells(power_domains, i9xx_always_on_power_well);
5934
	}
5935 5936 5937 5938

	return 0;
}

5939
void intel_power_domains_remove(struct drm_device *dev)
5940 5941 5942 5943
{
	hsw_pwr = NULL;
}

5944
static void intel_power_domains_resume(struct drm_device *dev)
5945 5946
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5947 5948
	struct i915_power_domains *power_domains = &dev_priv->power_domains;
	struct i915_power_well *power_well;
5949
	int i;
5950

5951
	mutex_lock(&power_domains->lock);
5952 5953 5954 5955
	for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
		if (power_well->set)
			power_well->set(dev, power_well, power_well->count > 0);
	}
5956
	mutex_unlock(&power_domains->lock);
5957 5958
}

5959 5960 5961 5962 5963
/*
 * Starting with Haswell, we have a "Power Down Well" that can be turned off
 * when not needed anymore. We have 4 registers that can request the power well
 * to be enabled, and it will only be disabled if none of the registers is
 * requesting it to be enabled.
5964
 */
5965
void intel_power_domains_init_hw(struct drm_device *dev)
5966 5967 5968
{
	struct drm_i915_private *dev_priv = dev->dev_private;

5969
	/* For now, we need the power well to be always enabled. */
5970
	intel_display_set_init_power(dev, true);
5971
	intel_power_domains_resume(dev);
5972

5973 5974 5975
	if (!(IS_HASWELL(dev) || IS_BROADWELL(dev)))
		return;

5976 5977
	/* We're taking over the BIOS, so clear any requests made by it since
	 * the driver is in charge now. */
5978
	if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5979
		I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5980 5981
}

5982 5983 5984 5985 5986 5987 5988 5989 5990 5991 5992
/* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
{
	hsw_disable_package_c8(dev_priv);
}

void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
{
	hsw_enable_package_c8(dev_priv);
}

5993 5994 5995 5996 5997 5998 5999 6000 6001 6002 6003 6004 6005 6006 6007 6008 6009 6010 6011 6012 6013 6014 6015 6016 6017 6018 6019 6020 6021 6022 6023 6024 6025 6026 6027 6028 6029 6030 6031 6032 6033 6034 6035 6036 6037 6038 6039 6040 6041 6042 6043 6044 6045 6046
void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	struct device *device = &dev->pdev->dev;

	if (!HAS_RUNTIME_PM(dev))
		return;

	pm_runtime_get_sync(device);
	WARN(dev_priv->pm.suspended, "Device still suspended.\n");
}

void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	struct device *device = &dev->pdev->dev;

	if (!HAS_RUNTIME_PM(dev))
		return;

	pm_runtime_mark_last_busy(device);
	pm_runtime_put_autosuspend(device);
}

void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	struct device *device = &dev->pdev->dev;

	dev_priv->pm.suspended = false;

	if (!HAS_RUNTIME_PM(dev))
		return;

	pm_runtime_set_active(device);

	pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
	pm_runtime_mark_last_busy(device);
	pm_runtime_use_autosuspend(device);
}

void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	struct device *device = &dev->pdev->dev;

	if (!HAS_RUNTIME_PM(dev))
		return;

	/* Make sure we're not suspended first. */
	pm_runtime_get_sync(device);
	pm_runtime_disable(device);
}

6047 6048 6049 6050 6051 6052
/* Set up chip specific power management-related functions */
void intel_init_pm(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (I915_HAS_FBC(dev)) {
6053
		if (INTEL_INFO(dev)->gen >= 7) {
6054
			dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6055 6056 6057 6058 6059
			dev_priv->display.enable_fbc = gen7_enable_fbc;
			dev_priv->display.disable_fbc = ironlake_disable_fbc;
		} else if (INTEL_INFO(dev)->gen >= 5) {
			dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
			dev_priv->display.enable_fbc = ironlake_enable_fbc;
6060 6061 6062 6063 6064
			dev_priv->display.disable_fbc = ironlake_disable_fbc;
		} else if (IS_GM45(dev)) {
			dev_priv->display.fbc_enabled = g4x_fbc_enabled;
			dev_priv->display.enable_fbc = g4x_enable_fbc;
			dev_priv->display.disable_fbc = g4x_disable_fbc;
6065
		} else {
6066 6067 6068 6069 6070 6071
			dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
			dev_priv->display.enable_fbc = i8xx_enable_fbc;
			dev_priv->display.disable_fbc = i8xx_disable_fbc;
		}
	}

6072 6073 6074 6075 6076 6077
	/* For cxsr */
	if (IS_PINEVIEW(dev))
		i915_pineview_get_mem_freq(dev);
	else if (IS_GEN5(dev))
		i915_ironlake_get_mem_freq(dev);

6078 6079
	/* For FIFO watermark updates */
	if (HAS_PCH_SPLIT(dev)) {
6080 6081
		intel_setup_wm_latency(dev);

6082
		if (IS_GEN5(dev)) {
6083 6084 6085
			if (dev_priv->wm.pri_latency[1] &&
			    dev_priv->wm.spr_latency[1] &&
			    dev_priv->wm.cur_latency[1])
6086 6087 6088 6089 6090 6091 6092 6093
				dev_priv->display.update_wm = ironlake_update_wm;
			else {
				DRM_DEBUG_KMS("Failed to get proper latency. "
					      "Disable CxSR\n");
				dev_priv->display.update_wm = NULL;
			}
			dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
		} else if (IS_GEN6(dev)) {
6094 6095 6096
			if (dev_priv->wm.pri_latency[0] &&
			    dev_priv->wm.spr_latency[0] &&
			    dev_priv->wm.cur_latency[0]) {
6097 6098 6099 6100 6101 6102 6103 6104 6105
				dev_priv->display.update_wm = sandybridge_update_wm;
				dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
			} else {
				DRM_DEBUG_KMS("Failed to read display plane latency. "
					      "Disable CxSR\n");
				dev_priv->display.update_wm = NULL;
			}
			dev_priv->display.init_clock_gating = gen6_init_clock_gating;
		} else if (IS_IVYBRIDGE(dev)) {
6106 6107 6108
			if (dev_priv->wm.pri_latency[0] &&
			    dev_priv->wm.spr_latency[0] &&
			    dev_priv->wm.cur_latency[0]) {
6109
				dev_priv->display.update_wm = ivybridge_update_wm;
6110 6111 6112 6113 6114 6115 6116
				dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
			} else {
				DRM_DEBUG_KMS("Failed to read display plane latency. "
					      "Disable CxSR\n");
				dev_priv->display.update_wm = NULL;
			}
			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6117
		} else if (IS_HASWELL(dev)) {
6118 6119 6120
			if (dev_priv->wm.pri_latency[0] &&
			    dev_priv->wm.spr_latency[0] &&
			    dev_priv->wm.cur_latency[0]) {
6121
				dev_priv->display.update_wm = haswell_update_wm;
6122 6123
				dev_priv->display.update_sprite_wm =
					haswell_update_sprite_wm;
6124 6125 6126 6127 6128
			} else {
				DRM_DEBUG_KMS("Failed to read display plane latency. "
					      "Disable CxSR\n");
				dev_priv->display.update_wm = NULL;
			}
6129
			dev_priv->display.init_clock_gating = haswell_init_clock_gating;
B
Ben Widawsky 已提交
6130 6131
		} else if (INTEL_INFO(dev)->gen == 8) {
			dev_priv->display.init_clock_gating = gen8_init_clock_gating;
6132 6133 6134 6135 6136 6137 6138 6139 6140 6141 6142 6143 6144 6145 6146 6147 6148 6149 6150 6151 6152 6153 6154 6155 6156 6157 6158 6159 6160 6161 6162 6163 6164 6165 6166 6167 6168 6169 6170 6171 6172 6173 6174 6175 6176 6177 6178 6179 6180 6181 6182 6183 6184
		} else
			dev_priv->display.update_wm = NULL;
	} else if (IS_VALLEYVIEW(dev)) {
		dev_priv->display.update_wm = valleyview_update_wm;
		dev_priv->display.init_clock_gating =
			valleyview_init_clock_gating;
	} else if (IS_PINEVIEW(dev)) {
		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
					    dev_priv->is_ddr3,
					    dev_priv->fsb_freq,
					    dev_priv->mem_freq)) {
			DRM_INFO("failed to find known CxSR latency "
				 "(found ddr%s fsb freq %d, mem freq %d), "
				 "disabling CxSR\n",
				 (dev_priv->is_ddr3 == 1) ? "3" : "2",
				 dev_priv->fsb_freq, dev_priv->mem_freq);
			/* Disable CxSR and never update its watermark again */
			pineview_disable_cxsr(dev);
			dev_priv->display.update_wm = NULL;
		} else
			dev_priv->display.update_wm = pineview_update_wm;
		dev_priv->display.init_clock_gating = gen3_init_clock_gating;
	} else if (IS_G4X(dev)) {
		dev_priv->display.update_wm = g4x_update_wm;
		dev_priv->display.init_clock_gating = g4x_init_clock_gating;
	} else if (IS_GEN4(dev)) {
		dev_priv->display.update_wm = i965_update_wm;
		if (IS_CRESTLINE(dev))
			dev_priv->display.init_clock_gating = crestline_init_clock_gating;
		else if (IS_BROADWATER(dev))
			dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
	} else if (IS_GEN3(dev)) {
		dev_priv->display.update_wm = i9xx_update_wm;
		dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
		dev_priv->display.init_clock_gating = gen3_init_clock_gating;
	} else if (IS_I865G(dev)) {
		dev_priv->display.update_wm = i830_update_wm;
		dev_priv->display.init_clock_gating = i85x_init_clock_gating;
		dev_priv->display.get_fifo_size = i830_get_fifo_size;
	} else if (IS_I85X(dev)) {
		dev_priv->display.update_wm = i9xx_update_wm;
		dev_priv->display.get_fifo_size = i85x_get_fifo_size;
		dev_priv->display.init_clock_gating = i85x_init_clock_gating;
	} else {
		dev_priv->display.update_wm = i830_update_wm;
		dev_priv->display.init_clock_gating = i830_init_clock_gating;
		if (IS_845G(dev))
			dev_priv->display.get_fifo_size = i845_get_fifo_size;
		else
			dev_priv->display.get_fifo_size = i830_get_fifo_size;
	}
}

B
Ben Widawsky 已提交
6185 6186
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
{
6187
	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
B
Ben Widawsky 已提交
6188 6189 6190 6191 6192 6193 6194 6195 6196 6197 6198 6199 6200 6201 6202 6203 6204 6205 6206 6207 6208 6209 6210

	if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
		DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
		return -EAGAIN;
	}

	I915_WRITE(GEN6_PCODE_DATA, *val);
	I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);

	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
		     500)) {
		DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
		return -ETIMEDOUT;
	}

	*val = I915_READ(GEN6_PCODE_DATA);
	I915_WRITE(GEN6_PCODE_DATA, 0);

	return 0;
}

int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
{
6211
	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
B
Ben Widawsky 已提交
6212 6213 6214 6215 6216 6217 6218 6219 6220 6221 6222 6223 6224 6225 6226 6227 6228 6229 6230

	if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
		DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
		return -EAGAIN;
	}

	I915_WRITE(GEN6_PCODE_DATA, val);
	I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);

	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
		     500)) {
		DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
		return -ETIMEDOUT;
	}

	I915_WRITE(GEN6_PCODE_DATA, 0);

	return 0;
}
6231

6232
int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6233
{
6234
	int div;
6235

6236
	/* 4 x czclk */
6237
	switch (dev_priv->mem_freq) {
6238
	case 800:
6239
		div = 10;
6240 6241
		break;
	case 1066:
6242
		div = 12;
6243 6244
		break;
	case 1333:
6245
		div = 16;
6246 6247 6248 6249 6250
		break;
	default:
		return -1;
	}

6251
	return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
6252 6253
}

6254
int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6255
{
6256
	int mul;
6257

6258
	/* 4 x czclk */
6259
	switch (dev_priv->mem_freq) {
6260
	case 800:
6261
		mul = 10;
6262 6263
		break;
	case 1066:
6264
		mul = 12;
6265 6266
		break;
	case 1333:
6267
		mul = 16;
6268 6269 6270 6271 6272
		break;
	default:
		return -1;
	}

6273
	return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
6274 6275
}

6276 6277 6278 6279 6280 6281 6282
void intel_pm_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
			  intel_gen6_powersave_work);
}