perf_event.c 54.3 KB
Newer Older
I
Ingo Molnar 已提交
1
/*
2
 * Performance events x86 architecture code
I
Ingo Molnar 已提交
3
 *
4 5 6 7 8
 *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
 *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
 *  Copyright (C) 2009 Jaswinder Singh Rajput
 *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
 *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9
 *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10
 *  Copyright (C) 2009 Google, Inc., Stephane Eranian
I
Ingo Molnar 已提交
11 12 13 14
 *
 *  For licencing details see kernel-base/COPYING
 */

15
#include <linux/perf_event.h>
I
Ingo Molnar 已提交
16 17 18 19
#include <linux/capability.h>
#include <linux/notifier.h>
#include <linux/hardirq.h>
#include <linux/kprobes.h>
20
#include <linux/module.h>
I
Ingo Molnar 已提交
21 22
#include <linux/kdebug.h>
#include <linux/sched.h>
23
#include <linux/uaccess.h>
24
#include <linux/slab.h>
25
#include <linux/cpu.h>
26
#include <linux/bitops.h>
27
#include <linux/device.h>
I
Ingo Molnar 已提交
28 29

#include <asm/apic.h>
30
#include <asm/stacktrace.h>
P
Peter Zijlstra 已提交
31
#include <asm/nmi.h>
32
#include <asm/smp.h>
33
#include <asm/alternative.h>
34
#include <asm/mmu_context.h>
A
Andy Lutomirski 已提交
35
#include <asm/tlbflush.h>
36
#include <asm/timer.h>
37 38
#include <asm/desc.h>
#include <asm/ldt.h>
I
Ingo Molnar 已提交
39

40 41 42
#include "perf_event.h"

struct x86_pmu x86_pmu __read_mostly;
43

44
DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
45 46
	.enabled = 1,
};
I
Ingo Molnar 已提交
47

48 49
struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE;

50
u64 __read_mostly hw_cache_event_ids
51 52 53
				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];
54
u64 __read_mostly hw_cache_extra_regs
55 56 57
				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];
58

59
/*
60 61
 * Propagate event elapsed time into the generic event.
 * Can only be executed on the CPU where the event is active.
62 63
 * Returns the delta events processed.
 */
64
u64 x86_perf_event_update(struct perf_event *event)
65
{
66
	struct hw_perf_event *hwc = &event->hw;
67
	int shift = 64 - x86_pmu.cntval_bits;
68
	u64 prev_raw_count, new_raw_count;
69
	int idx = hwc->idx;
70
	s64 delta;
71

72
	if (idx == INTEL_PMC_IDX_FIXED_BTS)
73 74
		return 0;

75
	/*
76
	 * Careful: an NMI might modify the previous event value.
77 78 79
	 *
	 * Our tactic to handle this is to first atomically read and
	 * exchange a new raw count - then add that new-prev delta
80
	 * count to the generic event atomically:
81 82
	 */
again:
83
	prev_raw_count = local64_read(&hwc->prev_count);
84
	rdpmcl(hwc->event_base_rdpmc, new_raw_count);
85

86
	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
87 88 89 90 91 92
					new_raw_count) != prev_raw_count)
		goto again;

	/*
	 * Now we have the new raw value and have updated the prev
	 * timestamp already. We can now calculate the elapsed delta
93
	 * (event-)time and add that to the generic event.
94 95
	 *
	 * Careful, not all hw sign-extends above the physical width
96
	 * of the count.
97
	 */
98 99
	delta = (new_raw_count << shift) - (prev_raw_count << shift);
	delta >>= shift;
100

101 102
	local64_add(delta, &event->count);
	local64_sub(delta, &hwc->period_left);
103 104

	return new_raw_count;
105 106
}

107 108 109 110 111
/*
 * Find and validate any extra registers to set up.
 */
static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
{
112
	struct hw_perf_event_extra *reg;
113 114
	struct extra_reg *er;

115
	reg = &event->hw.extra_reg;
116 117 118 119 120 121 122 123 124

	if (!x86_pmu.extra_regs)
		return 0;

	for (er = x86_pmu.extra_regs; er->msr; er++) {
		if (er->event != (config & er->config_mask))
			continue;
		if (event->attr.config1 & ~er->valid_mask)
			return -EINVAL;
125 126 127
		/* Check if the extra msrs can be safely accessed*/
		if (!er->extra_msr_access)
			return -ENXIO;
128 129 130 131

		reg->idx = er->idx;
		reg->config = event->attr.config1;
		reg->reg = er->msr;
132 133 134 135 136
		break;
	}
	return 0;
}

137
static atomic_t active_events;
138
static atomic_t pmc_refcount;
P
Peter Zijlstra 已提交
139 140
static DEFINE_MUTEX(pmc_reserve_mutex);

141 142
#ifdef CONFIG_X86_LOCAL_APIC

P
Peter Zijlstra 已提交
143 144 145 146
static bool reserve_pmc_hardware(void)
{
	int i;

147
	for (i = 0; i < x86_pmu.num_counters; i++) {
148
		if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
P
Peter Zijlstra 已提交
149 150 151
			goto perfctr_fail;
	}

152
	for (i = 0; i < x86_pmu.num_counters; i++) {
153
		if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
P
Peter Zijlstra 已提交
154 155 156 157 158 159 160
			goto eventsel_fail;
	}

	return true;

eventsel_fail:
	for (i--; i >= 0; i--)
161
		release_evntsel_nmi(x86_pmu_config_addr(i));
P
Peter Zijlstra 已提交
162

163
	i = x86_pmu.num_counters;
P
Peter Zijlstra 已提交
164 165 166

perfctr_fail:
	for (i--; i >= 0; i--)
167
		release_perfctr_nmi(x86_pmu_event_addr(i));
P
Peter Zijlstra 已提交
168 169 170 171 172 173 174 175

	return false;
}

static void release_pmc_hardware(void)
{
	int i;

176
	for (i = 0; i < x86_pmu.num_counters; i++) {
177 178
		release_perfctr_nmi(x86_pmu_event_addr(i));
		release_evntsel_nmi(x86_pmu_config_addr(i));
P
Peter Zijlstra 已提交
179 180 181
	}
}

182 183 184 185 186 187 188
#else

static bool reserve_pmc_hardware(void) { return true; }
static void release_pmc_hardware(void) {}

#endif

189 190
static bool check_hw_exists(void)
{
191 192 193
	u64 val, val_fail, val_new= ~0;
	int i, reg, reg_fail, ret = 0;
	int bios_fail = 0;
194
	int reg_safe = -1;
195

196 197 198 199 200
	/*
	 * Check to see if the BIOS enabled any of the counters, if so
	 * complain and bail.
	 */
	for (i = 0; i < x86_pmu.num_counters; i++) {
201
		reg = x86_pmu_config_addr(i);
202 203 204
		ret = rdmsrl_safe(reg, &val);
		if (ret)
			goto msr_fail;
205 206 207 208
		if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
			bios_fail = 1;
			val_fail = val;
			reg_fail = reg;
209 210
		} else {
			reg_safe = i;
211
		}
212 213 214 215 216 217 218 219
	}

	if (x86_pmu.num_counters_fixed) {
		reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
		ret = rdmsrl_safe(reg, &val);
		if (ret)
			goto msr_fail;
		for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
220 221 222 223 224
			if (val & (0x03 << i*4)) {
				bios_fail = 1;
				val_fail = val;
				reg_fail = reg;
			}
225 226 227
		}
	}

228 229 230 231 232 233 234 235 236 237 238
	/*
	 * If all the counters are enabled, the below test will always
	 * fail.  The tools will also become useless in this scenario.
	 * Just fail and disable the hardware counters.
	 */

	if (reg_safe == -1) {
		reg = reg_safe;
		goto msr_fail;
	}

239
	/*
240 241 242
	 * Read the current value, change it and read it back to see if it
	 * matches, this is needed to detect certain hardware emulators
	 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
243
	 */
244
	reg = x86_pmu_event_addr(reg_safe);
245 246 247
	if (rdmsrl_safe(reg, &val))
		goto msr_fail;
	val ^= 0xffffUL;
248 249
	ret = wrmsrl_safe(reg, val);
	ret |= rdmsrl_safe(reg, &val_new);
250
	if (ret || val != val_new)
251
		goto msr_fail;
252

253 254 255
	/*
	 * We still allow the PMU driver to operate:
	 */
256 257 258 259
	if (bios_fail) {
		printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
		printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
	}
260 261

	return true;
262 263 264

msr_fail:
	printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
265 266 267
	printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
		boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR,
		reg, val_new);
268

269
	return false;
270 271
}

272
static void hw_perf_event_destroy(struct perf_event *event)
P
Peter Zijlstra 已提交
273
{
274
	x86_release_hardware();
275
	atomic_dec(&active_events);
P
Peter Zijlstra 已提交
276 277
}

278 279 280 281 282 283 284 285
void hw_perf_lbr_event_destroy(struct perf_event *event)
{
	hw_perf_event_destroy(event);

	/* undo the lbr/bts event accounting */
	x86_del_exclusive(x86_lbr_exclusive_lbr);
}

286 287 288 289 290
static inline int x86_pmu_initialized(void)
{
	return x86_pmu.handle_irq != NULL;
}

291
static inline int
292
set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
293
{
294
	struct perf_event_attr *attr = &event->attr;
295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320
	unsigned int cache_type, cache_op, cache_result;
	u64 config, val;

	config = attr->config;

	cache_type = (config >>  0) & 0xff;
	if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
		return -EINVAL;

	cache_op = (config >>  8) & 0xff;
	if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
		return -EINVAL;

	cache_result = (config >> 16) & 0xff;
	if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
		return -EINVAL;

	val = hw_cache_event_ids[cache_type][cache_op][cache_result];

	if (val == 0)
		return -ENOENT;

	if (val == -1)
		return -EINVAL;

	hwc->config |= val;
321 322
	attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
	return x86_pmu_extra_regs(val, event);
323 324
}

325 326 327 328
int x86_reserve_hardware(void)
{
	int err = 0;

329
	if (!atomic_inc_not_zero(&pmc_refcount)) {
330
		mutex_lock(&pmc_reserve_mutex);
331
		if (atomic_read(&pmc_refcount) == 0) {
332 333 334 335 336 337
			if (!reserve_pmc_hardware())
				err = -EBUSY;
			else
				reserve_ds_buffers();
		}
		if (!err)
338
			atomic_inc(&pmc_refcount);
339 340 341 342 343 344 345 346
		mutex_unlock(&pmc_reserve_mutex);
	}

	return err;
}

void x86_release_hardware(void)
{
347
	if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
348 349 350 351 352 353
		release_pmc_hardware();
		release_ds_buffers();
		mutex_unlock(&pmc_reserve_mutex);
	}
}

354 355 356 357 358 359
/*
 * Check if we can create event of a certain type (that no conflicting events
 * are present).
 */
int x86_add_exclusive(unsigned int what)
{
360
	int i;
361

362 363 364 365 366 367 368 369
	if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
		mutex_lock(&pmc_reserve_mutex);
		for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
			if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
				goto fail_unlock;
		}
		atomic_inc(&x86_pmu.lbr_exclusive[what]);
		mutex_unlock(&pmc_reserve_mutex);
370
	}
371

372 373
	atomic_inc(&active_events);
	return 0;
374

375
fail_unlock:
376
	mutex_unlock(&pmc_reserve_mutex);
377
	return -EBUSY;
378 379 380 381 382
}

void x86_del_exclusive(unsigned int what)
{
	atomic_dec(&x86_pmu.lbr_exclusive[what]);
383
	atomic_dec(&active_events);
384 385
}

386
int x86_setup_perfctr(struct perf_event *event)
387 388 389 390 391
{
	struct perf_event_attr *attr = &event->attr;
	struct hw_perf_event *hwc = &event->hw;
	u64 config;

392
	if (!is_sampling_event(event)) {
393 394
		hwc->sample_period = x86_pmu.max_period;
		hwc->last_period = hwc->sample_period;
395
		local64_set(&hwc->period_left, hwc->sample_period);
396 397 398
	}

	if (attr->type == PERF_TYPE_RAW)
399
		return x86_pmu_extra_regs(event->attr.config, event);
400 401

	if (attr->type == PERF_TYPE_HW_CACHE)
402
		return set_ext_hw_attr(hwc, event);
403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420

	if (attr->config >= x86_pmu.max_events)
		return -EINVAL;

	/*
	 * The generic map:
	 */
	config = x86_pmu.event_map(attr->config);

	if (config == 0)
		return -ENOENT;

	if (config == -1LL)
		return -EINVAL;

	/*
	 * Branch tracing:
	 */
P
Peter Zijlstra 已提交
421 422
	if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
	    !attr->freq && hwc->sample_period == 1) {
423
		/* BTS is not supported by this architecture. */
424
		if (!x86_pmu.bts_active)
425 426 427 428 429
			return -EOPNOTSUPP;

		/* BTS is currently only allowed for user-mode. */
		if (!attr->exclude_kernel)
			return -EOPNOTSUPP;
430 431 432 433 434 435

		/* disallow bts if conflicting events are present */
		if (x86_add_exclusive(x86_lbr_exclusive_lbr))
			return -EBUSY;

		event->destroy = hw_perf_lbr_event_destroy;
436 437 438 439 440 441
	}

	hwc->config |= config;

	return 0;
}
442

443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472
/*
 * check that branch_sample_type is compatible with
 * settings needed for precise_ip > 1 which implies
 * using the LBR to capture ALL taken branches at the
 * priv levels of the measurement
 */
static inline int precise_br_compat(struct perf_event *event)
{
	u64 m = event->attr.branch_sample_type;
	u64 b = 0;

	/* must capture all branches */
	if (!(m & PERF_SAMPLE_BRANCH_ANY))
		return 0;

	m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;

	if (!event->attr.exclude_user)
		b |= PERF_SAMPLE_BRANCH_USER;

	if (!event->attr.exclude_kernel)
		b |= PERF_SAMPLE_BRANCH_KERNEL;

	/*
	 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
	 */

	return m == b;
}

473
int x86_pmu_hw_config(struct perf_event *event)
474
{
P
Peter Zijlstra 已提交
475 476 477 478
	if (event->attr.precise_ip) {
		int precise = 0;

		/* Support for constant skid */
479
		if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
P
Peter Zijlstra 已提交
480 481
			precise++;

482
			/* Support for IP fixup */
A
Andi Kleen 已提交
483
			if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
484 485
				precise++;
		}
P
Peter Zijlstra 已提交
486 487 488

		if (event->attr.precise_ip > precise)
			return -EOPNOTSUPP;
489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517
	}
	/*
	 * check that PEBS LBR correction does not conflict with
	 * whatever the user is asking with attr->branch_sample_type
	 */
	if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
		u64 *br_type = &event->attr.branch_sample_type;

		if (has_branch_stack(event)) {
			if (!precise_br_compat(event))
				return -EOPNOTSUPP;

			/* branch_sample_type is compatible */

		} else {
			/*
			 * user did not specify  branch_sample_type
			 *
			 * For PEBS fixups, we capture all
			 * the branches at the priv level of the
			 * event.
			 */
			*br_type = PERF_SAMPLE_BRANCH_ANY;

			if (!event->attr.exclude_user)
				*br_type |= PERF_SAMPLE_BRANCH_USER;

			if (!event->attr.exclude_kernel)
				*br_type |= PERF_SAMPLE_BRANCH_KERNEL;
518
		}
P
Peter Zijlstra 已提交
519 520
	}

521 522 523
	if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
		event->attach_state |= PERF_ATTACH_TASK_DATA;

524 525 526 527
	/*
	 * Generate PMC IRQs:
	 * (keep 'enabled' bit clear for now)
	 */
528
	event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
529 530 531 532

	/*
	 * Count user and OS events unless requested not to
	 */
533 534 535 536
	if (!event->attr.exclude_user)
		event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
	if (!event->attr.exclude_kernel)
		event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
537

538 539
	if (event->attr.type == PERF_TYPE_RAW)
		event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
540

541 542 543 544 545 546
	if (event->attr.sample_period && x86_pmu.limit_period) {
		if (x86_pmu.limit_period(event, event->attr.sample_period) >
				event->attr.sample_period)
			return -EINVAL;
	}

547
	return x86_setup_perfctr(event);
548 549
}

I
Ingo Molnar 已提交
550
/*
551
 * Setup the hardware configuration for a given attr_type
I
Ingo Molnar 已提交
552
 */
553
static int __x86_pmu_event_init(struct perf_event *event)
I
Ingo Molnar 已提交
554
{
P
Peter Zijlstra 已提交
555
	int err;
I
Ingo Molnar 已提交
556

557 558
	if (!x86_pmu_initialized())
		return -ENODEV;
I
Ingo Molnar 已提交
559

560
	err = x86_reserve_hardware();
P
Peter Zijlstra 已提交
561 562 563
	if (err)
		return err;

564
	atomic_inc(&active_events);
565
	event->destroy = hw_perf_event_destroy;
566

567 568 569
	event->hw.idx = -1;
	event->hw.last_cpu = -1;
	event->hw.last_tag = ~0ULL;
570

571 572
	/* mark unused */
	event->hw.extra_reg.idx = EXTRA_REG_NONE;
573 574
	event->hw.branch_reg.idx = EXTRA_REG_NONE;

575
	return x86_pmu.hw_config(event);
576 577
}

578
void x86_pmu_disable_all(void)
579
{
580
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
581 582
	int idx;

583
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
584 585
		u64 val;

586
		if (!test_bit(idx, cpuc->active_mask))
587
			continue;
588
		rdmsrl(x86_pmu_config_addr(idx), val);
589
		if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
590
			continue;
591
		val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
592
		wrmsrl(x86_pmu_config_addr(idx), val);
593 594 595
	}
}

P
Peter Zijlstra 已提交
596
static void x86_pmu_disable(struct pmu *pmu)
597
{
598
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
599

600
	if (!x86_pmu_initialized())
601
		return;
602

603 604 605 606 607 608
	if (!cpuc->enabled)
		return;

	cpuc->n_added = 0;
	cpuc->enabled = 0;
	barrier();
609 610

	x86_pmu.disable_all();
611
}
I
Ingo Molnar 已提交
612

613
void x86_pmu_enable_all(int added)
614
{
615
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
616 617
	int idx;

618
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
619
		struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
620

621
		if (!test_bit(idx, cpuc->active_mask))
622
			continue;
623

624
		__x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
625 626 627
	}
}

P
Peter Zijlstra 已提交
628
static struct pmu pmu;
629 630 631 632 633 634

static inline int is_x86_event(struct perf_event *event)
{
	return event->pmu == &pmu;
}

635 636 637 638 639 640 641 642 643 644 645 646
/*
 * Event scheduler state:
 *
 * Assign events iterating over all events and counters, beginning
 * with events with least weights first. Keep the current iterator
 * state in struct sched_state.
 */
struct sched_state {
	int	weight;
	int	event;		/* event index */
	int	counter;	/* counter index */
	int	unassigned;	/* number of events to be assigned left */
647
	int	nr_gp;		/* number of GP counters used */
648 649 650
	unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
};

651 652 653
/* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
#define	SCHED_STATES_MAX	2

654 655 656
struct perf_sched {
	int			max_weight;
	int			max_events;
657 658
	int			max_gp;
	int			saved_states;
659
	struct event_constraint	**constraints;
660
	struct sched_state	state;
661
	struct sched_state	saved[SCHED_STATES_MAX];
662 663 664 665 666
};

/*
 * Initialize interator that runs through all events and counters.
 */
667
static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
668
			    int num, int wmin, int wmax, int gpmax)
669 670 671 672 673 674
{
	int idx;

	memset(sched, 0, sizeof(*sched));
	sched->max_events	= num;
	sched->max_weight	= wmax;
675
	sched->max_gp		= gpmax;
676
	sched->constraints	= constraints;
677 678

	for (idx = 0; idx < num; idx++) {
679
		if (constraints[idx]->weight == wmin)
680 681 682 683 684 685 686 687
			break;
	}

	sched->state.event	= idx;		/* start with min weight */
	sched->state.weight	= wmin;
	sched->state.unassigned	= num;
}

688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710
static void perf_sched_save_state(struct perf_sched *sched)
{
	if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
		return;

	sched->saved[sched->saved_states] = sched->state;
	sched->saved_states++;
}

static bool perf_sched_restore_state(struct perf_sched *sched)
{
	if (!sched->saved_states)
		return false;

	sched->saved_states--;
	sched->state = sched->saved[sched->saved_states];

	/* continue with next counter: */
	clear_bit(sched->state.counter++, sched->state.used);

	return true;
}

711 712 713 714
/*
 * Select a counter for the current event to schedule. Return true on
 * success.
 */
715
static bool __perf_sched_find_counter(struct perf_sched *sched)
716 717 718 719 720 721 722 723 724 725
{
	struct event_constraint *c;
	int idx;

	if (!sched->state.unassigned)
		return false;

	if (sched->state.event >= sched->max_events)
		return false;

726
	c = sched->constraints[sched->state.event];
727
	/* Prefer fixed purpose counters */
728 729
	if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
		idx = INTEL_PMC_IDX_FIXED;
730
		for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
731 732 733 734
			if (!__test_and_set_bit(idx, sched->state.used))
				goto done;
		}
	}
735

736 737
	/* Grab the first unused counter starting with idx */
	idx = sched->state.counter;
738
	for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
739 740 741 742
		if (!__test_and_set_bit(idx, sched->state.used)) {
			if (sched->state.nr_gp++ >= sched->max_gp)
				return false;

743
			goto done;
744
		}
745 746
	}

747 748 749 750
	return false;

done:
	sched->state.counter = idx;
751

752 753 754 755 756 757 758 759 760 761 762 763 764
	if (c->overlap)
		perf_sched_save_state(sched);

	return true;
}

static bool perf_sched_find_counter(struct perf_sched *sched)
{
	while (!__perf_sched_find_counter(sched)) {
		if (!perf_sched_restore_state(sched))
			return false;
	}

765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788
	return true;
}

/*
 * Go through all unassigned events and find the next one to schedule.
 * Take events with the least weight first. Return true on success.
 */
static bool perf_sched_next_event(struct perf_sched *sched)
{
	struct event_constraint *c;

	if (!sched->state.unassigned || !--sched->state.unassigned)
		return false;

	do {
		/* next event */
		sched->state.event++;
		if (sched->state.event >= sched->max_events) {
			/* next weight */
			sched->state.event = 0;
			sched->state.weight++;
			if (sched->state.weight > sched->max_weight)
				return false;
		}
789
		c = sched->constraints[sched->state.event];
790 791 792 793 794 795 796 797 798 799
	} while (c->weight != sched->state.weight);

	sched->state.counter = 0;	/* start with first counter */

	return true;
}

/*
 * Assign a counter for each event.
 */
800
int perf_assign_events(struct event_constraint **constraints, int n,
801
			int wmin, int wmax, int gpmax, int *assign)
802 803 804
{
	struct perf_sched sched;

805
	perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
806 807 808 809 810 811 812 813 814 815

	do {
		if (!perf_sched_find_counter(&sched))
			break;	/* failed */
		if (assign)
			assign[sched.state.event] = sched.state.counter;
	} while (perf_sched_next_event(&sched));

	return sched.state.unassigned;
}
816
EXPORT_SYMBOL_GPL(perf_assign_events);
817

818
int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
819
{
820
	struct event_constraint *c;
821
	unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
822
	struct perf_event *e;
823
	int i, wmin, wmax, unsched = 0;
824 825 826 827
	struct hw_perf_event *hwc;

	bitmap_zero(used_mask, X86_PMC_IDX_MAX);

828 829 830
	if (x86_pmu.start_scheduling)
		x86_pmu.start_scheduling(cpuc);

831
	for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
832
		cpuc->event_constraint[i] = NULL;
833
		c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
834
		cpuc->event_constraint[i] = c;
835

836 837
		wmin = min(wmin, c->weight);
		wmax = max(wmax, c->weight);
838 839
	}

840 841 842
	/*
	 * fastpath, try to reuse previous register
	 */
843
	for (i = 0; i < n; i++) {
844
		hwc = &cpuc->event_list[i]->hw;
845
		c = cpuc->event_constraint[i];
846 847 848 849 850 851

		/* never assigned */
		if (hwc->idx == -1)
			break;

		/* constraint still honored */
852
		if (!test_bit(hwc->idx, c->idxmsk))
853 854 855 856 857 858
			break;

		/* not already used */
		if (test_bit(hwc->idx, used_mask))
			break;

P
Peter Zijlstra 已提交
859
		__set_bit(hwc->idx, used_mask);
860 861 862 863
		if (assign)
			assign[i] = hwc->idx;
	}

864
	/* slow path */
865
	if (i != n) {
866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881
		int gpmax = x86_pmu.num_counters;

		/*
		 * Do not allow scheduling of more than half the available
		 * generic counters.
		 *
		 * This helps avoid counter starvation of sibling thread by
		 * ensuring at most half the counters cannot be in exclusive
		 * mode. There is no designated counters for the limits. Any
		 * N/2 counters can be used. This helps with events with
		 * specific counter constraints.
		 */
		if (is_ht_workaround_enabled() && !cpuc->is_fake &&
		    READ_ONCE(cpuc->excl_cntrs->exclusive_present))
			gpmax /= 2;

882
		unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
883
					     wmax, gpmax, assign);
884
	}
885

886
	/*
887 888 889 890 891 892 893 894
	 * In case of success (unsched = 0), mark events as committed,
	 * so we do not put_constraint() in case new events are added
	 * and fail to be scheduled
	 *
	 * We invoke the lower level commit callback to lock the resource
	 *
	 * We do not need to do all of this in case we are called to
	 * validate an event group (assign == NULL)
895
	 */
896
	if (!unsched && assign) {
897 898 899
		for (i = 0; i < n; i++) {
			e = cpuc->event_list[i];
			e->hw.flags |= PERF_X86_EVENT_COMMITTED;
900
			if (x86_pmu.commit_scheduling)
901
				x86_pmu.commit_scheduling(cpuc, i, assign[i]);
902
		}
903
	} else {
904
		for (i = 0; i < n; i++) {
905 906 907 908 909 910 911 912
			e = cpuc->event_list[i];
			/*
			 * do not put_constraint() on comitted events,
			 * because they are good to go
			 */
			if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
				continue;

913 914 915
			/*
			 * release events that failed scheduling
			 */
916
			if (x86_pmu.put_event_constraints)
917
				x86_pmu.put_event_constraints(cpuc, e);
918 919
		}
	}
920 921 922 923

	if (x86_pmu.stop_scheduling)
		x86_pmu.stop_scheduling(cpuc);

924
	return unsched ? -EINVAL : 0;
925 926 927 928 929 930 931 932 933 934 935
}

/*
 * dogrp: true if must collect siblings events (group)
 * returns total number of events and error code
 */
static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
{
	struct perf_event *event;
	int n, max_count;

936
	max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
937 938 939 940 941 942

	/* current number of events already accepted */
	n = cpuc->n_events;

	if (is_x86_event(leader)) {
		if (n >= max_count)
943
			return -EINVAL;
944 945 946 947 948 949 950 951
		cpuc->event_list[n] = leader;
		n++;
	}
	if (!dogrp)
		return n;

	list_for_each_entry(event, &leader->sibling_list, group_entry) {
		if (!is_x86_event(event) ||
952
		    event->state <= PERF_EVENT_STATE_OFF)
953 954 955
			continue;

		if (n >= max_count)
956
			return -EINVAL;
957 958 959 960 961 962 963 964

		cpuc->event_list[n] = event;
		n++;
	}
	return n;
}

static inline void x86_assign_hw_event(struct perf_event *event,
965
				struct cpu_hw_events *cpuc, int i)
966
{
967 968 969 970 971
	struct hw_perf_event *hwc = &event->hw;

	hwc->idx = cpuc->assign[i];
	hwc->last_cpu = smp_processor_id();
	hwc->last_tag = ++cpuc->tags[i];
972

973
	if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
974 975
		hwc->config_base = 0;
		hwc->event_base	= 0;
976
	} else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
977
		hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
978 979
		hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
		hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
980
	} else {
981 982
		hwc->config_base = x86_pmu_config_addr(hwc->idx);
		hwc->event_base  = x86_pmu_event_addr(hwc->idx);
983
		hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
984 985 986
	}
}

987 988 989 990 991 992 993 994 995
static inline int match_prev_assignment(struct hw_perf_event *hwc,
					struct cpu_hw_events *cpuc,
					int i)
{
	return hwc->idx == cpuc->assign[i] &&
		hwc->last_cpu == smp_processor_id() &&
		hwc->last_tag == cpuc->tags[i];
}

P
Peter Zijlstra 已提交
996
static void x86_pmu_start(struct perf_event *event, int flags);
997

P
Peter Zijlstra 已提交
998
static void x86_pmu_enable(struct pmu *pmu)
999
{
1000
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1001 1002
	struct perf_event *event;
	struct hw_perf_event *hwc;
1003
	int i, added = cpuc->n_added;
1004

1005
	if (!x86_pmu_initialized())
1006
		return;
1007 1008 1009 1010

	if (cpuc->enabled)
		return;

1011
	if (cpuc->n_added) {
1012
		int n_running = cpuc->n_events - cpuc->n_added;
1013 1014 1015 1016 1017 1018
		/*
		 * apply assignment obtained either from
		 * hw_perf_group_sched_in() or x86_pmu_enable()
		 *
		 * step1: save events moving to new counters
		 */
1019
		for (i = 0; i < n_running; i++) {
1020 1021 1022
			event = cpuc->event_list[i];
			hwc = &event->hw;

1023 1024 1025 1026 1027 1028 1029 1030
			/*
			 * we can avoid reprogramming counter if:
			 * - assigned same counter as last time
			 * - running on same CPU as last time
			 * - no other event has used the counter since
			 */
			if (hwc->idx == -1 ||
			    match_prev_assignment(hwc, cpuc, i))
1031 1032
				continue;

P
Peter Zijlstra 已提交
1033 1034 1035 1036 1037 1038 1039 1040
			/*
			 * Ensure we don't accidentally enable a stopped
			 * counter simply because we rescheduled.
			 */
			if (hwc->state & PERF_HES_STOPPED)
				hwc->state |= PERF_HES_ARCH;

			x86_pmu_stop(event, PERF_EF_UPDATE);
1041 1042
		}

1043 1044 1045
		/*
		 * step2: reprogram moved events into new counters
		 */
1046 1047 1048 1049
		for (i = 0; i < cpuc->n_events; i++) {
			event = cpuc->event_list[i];
			hwc = &event->hw;

1050
			if (!match_prev_assignment(hwc, cpuc, i))
1051
				x86_assign_hw_event(event, cpuc, i);
1052 1053
			else if (i < n_running)
				continue;
1054

P
Peter Zijlstra 已提交
1055 1056 1057 1058
			if (hwc->state & PERF_HES_ARCH)
				continue;

			x86_pmu_start(event, PERF_EF_RELOAD);
1059 1060 1061 1062
		}
		cpuc->n_added = 0;
		perf_events_lapic_init();
	}
1063 1064 1065 1066

	cpuc->enabled = 1;
	barrier();

1067
	x86_pmu.enable_all(added);
1068 1069
}

1070
static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
I
Ingo Molnar 已提交
1071

1072 1073
/*
 * Set the next IRQ period, based on the hwc->period_left value.
1074
 * To be called with the event disabled in hw:
1075
 */
1076
int x86_perf_event_set_period(struct perf_event *event)
I
Ingo Molnar 已提交
1077
{
1078
	struct hw_perf_event *hwc = &event->hw;
1079
	s64 left = local64_read(&hwc->period_left);
1080
	s64 period = hwc->sample_period;
1081
	int ret = 0, idx = hwc->idx;
1082

1083
	if (idx == INTEL_PMC_IDX_FIXED_BTS)
1084 1085
		return 0;

1086
	/*
1087
	 * If we are way outside a reasonable range then just skip forward:
1088 1089 1090
	 */
	if (unlikely(left <= -period)) {
		left = period;
1091
		local64_set(&hwc->period_left, left);
1092
		hwc->last_period = period;
1093
		ret = 1;
1094 1095 1096 1097
	}

	if (unlikely(left <= 0)) {
		left += period;
1098
		local64_set(&hwc->period_left, left);
1099
		hwc->last_period = period;
1100
		ret = 1;
1101
	}
1102
	/*
1103
	 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1104 1105 1106
	 */
	if (unlikely(left < 2))
		left = 2;
I
Ingo Molnar 已提交
1107

1108 1109 1110
	if (left > x86_pmu.max_period)
		left = x86_pmu.max_period;

1111 1112 1113
	if (x86_pmu.limit_period)
		left = x86_pmu.limit_period(event, left);

1114
	per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1115

1116 1117 1118 1119 1120 1121 1122
	if (!(hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) ||
	    local64_read(&hwc->prev_count) != (u64)-left) {
		/*
		 * The hw event starts counting from this event offset,
		 * mark it to be able to extra future deltas:
		 */
		local64_set(&hwc->prev_count, (u64)-left);
1123

1124 1125
		wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
	}
1126 1127 1128 1129 1130 1131 1132

	/*
	 * Due to erratum on certan cpu we need
	 * a second write to be sure the register
	 * is updated properly
	 */
	if (x86_pmu.perfctr_second_write) {
1133
		wrmsrl(hwc->event_base,
1134
			(u64)(-left) & x86_pmu.cntval_mask);
1135
	}
1136

1137
	perf_event_update_userpage(event);
1138

1139
	return ret;
1140 1141
}

1142
void x86_pmu_enable_event(struct perf_event *event)
1143
{
T
Tejun Heo 已提交
1144
	if (__this_cpu_read(cpu_hw_events.enabled))
1145 1146
		__x86_pmu_enable_event(&event->hw,
				       ARCH_PERFMON_EVENTSEL_ENABLE);
I
Ingo Molnar 已提交
1147 1148
}

1149
/*
P
Peter Zijlstra 已提交
1150
 * Add a single event to the PMU.
1151 1152 1153
 *
 * The event is added to the group of enabled events
 * but only if it can be scehduled with existing events.
1154
 */
P
Peter Zijlstra 已提交
1155
static int x86_pmu_add(struct perf_event *event, int flags)
1156
{
1157
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1158 1159 1160
	struct hw_perf_event *hwc;
	int assign[X86_PMC_IDX_MAX];
	int n, n0, ret;
1161

1162
	hwc = &event->hw;
1163

1164
	n0 = cpuc->n_events;
1165 1166 1167
	ret = n = collect_events(cpuc, event, false);
	if (ret < 0)
		goto out;
1168

P
Peter Zijlstra 已提交
1169 1170 1171 1172
	hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
	if (!(flags & PERF_EF_START))
		hwc->state |= PERF_HES_ARCH;

1173 1174
	/*
	 * If group events scheduling transaction was started,
L
Lucas De Marchi 已提交
1175
	 * skip the schedulability test here, it will be performed
1176
	 * at commit time (->commit_txn) as a whole.
1177
	 */
1178
	if (cpuc->group_flag & PERF_EVENT_TXN)
1179
		goto done_collect;
1180

1181
	ret = x86_pmu.schedule_events(cpuc, n, assign);
1182
	if (ret)
1183
		goto out;
1184 1185 1186 1187 1188
	/*
	 * copy new assignment, now we know it is possible
	 * will be used by hw_perf_enable()
	 */
	memcpy(cpuc->assign, assign, n*sizeof(int));
1189

1190
done_collect:
1191 1192 1193 1194
	/*
	 * Commit the collect_events() state. See x86_pmu_del() and
	 * x86_pmu_*_txn().
	 */
1195
	cpuc->n_events = n;
1196
	cpuc->n_added += n - n0;
1197
	cpuc->n_txn += n - n0;
1198

1199 1200 1201
	ret = 0;
out:
	return ret;
I
Ingo Molnar 已提交
1202 1203
}

P
Peter Zijlstra 已提交
1204
static void x86_pmu_start(struct perf_event *event, int flags)
1205
{
1206
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
P
Peter Zijlstra 已提交
1207 1208
	int idx = event->hw.idx;

P
Peter Zijlstra 已提交
1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220
	if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
		return;

	if (WARN_ON_ONCE(idx == -1))
		return;

	if (flags & PERF_EF_RELOAD) {
		WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
		x86_perf_event_set_period(event);
	}

	event->hw.state = 0;
1221

P
Peter Zijlstra 已提交
1222 1223
	cpuc->events[idx] = event;
	__set_bit(idx, cpuc->active_mask);
1224
	__set_bit(idx, cpuc->running);
1225
	x86_pmu.enable(event);
P
Peter Zijlstra 已提交
1226
	perf_event_update_userpage(event);
1227 1228
}

1229
void perf_event_print_debug(void)
I
Ingo Molnar 已提交
1230
{
1231
	u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
A
Andi Kleen 已提交
1232
	u64 pebs, debugctl;
1233
	struct cpu_hw_events *cpuc;
1234
	unsigned long flags;
1235 1236
	int cpu, idx;

1237
	if (!x86_pmu.num_counters)
1238
		return;
I
Ingo Molnar 已提交
1239

1240
	local_irq_save(flags);
I
Ingo Molnar 已提交
1241 1242

	cpu = smp_processor_id();
1243
	cpuc = &per_cpu(cpu_hw_events, cpu);
I
Ingo Molnar 已提交
1244

1245
	if (x86_pmu.version >= 2) {
1246 1247 1248 1249 1250 1251 1252 1253 1254 1255
		rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
		rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
		rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
		rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);

		pr_info("\n");
		pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
		pr_info("CPU#%d: status:     %016llx\n", cpu, status);
		pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
		pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1256 1257 1258 1259
		if (x86_pmu.pebs_constraints) {
			rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
			pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
		}
A
Andi Kleen 已提交
1260 1261 1262 1263
		if (x86_pmu.lbr_nr) {
			rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
			pr_info("CPU#%d: debugctl:   %016llx\n", cpu, debugctl);
		}
1264
	}
1265
	pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
I
Ingo Molnar 已提交
1266

1267
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1268 1269
		rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
		rdmsrl(x86_pmu_event_addr(idx), pmc_count);
I
Ingo Molnar 已提交
1270

1271
		prev_left = per_cpu(pmc_prev_left[idx], cpu);
I
Ingo Molnar 已提交
1272

1273
		pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
I
Ingo Molnar 已提交
1274
			cpu, idx, pmc_ctrl);
1275
		pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
I
Ingo Molnar 已提交
1276
			cpu, idx, pmc_count);
1277
		pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1278
			cpu, idx, prev_left);
I
Ingo Molnar 已提交
1279
	}
1280
	for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1281 1282
		rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);

1283
		pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1284 1285
			cpu, idx, pmc_count);
	}
1286
	local_irq_restore(flags);
I
Ingo Molnar 已提交
1287 1288
}

1289
void x86_pmu_stop(struct perf_event *event, int flags)
I
Ingo Molnar 已提交
1290
{
1291
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1292
	struct hw_perf_event *hwc = &event->hw;
I
Ingo Molnar 已提交
1293

P
Peter Zijlstra 已提交
1294 1295 1296 1297 1298 1299
	if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
		x86_pmu.disable(event);
		cpuc->events[hwc->idx] = NULL;
		WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
		hwc->state |= PERF_HES_STOPPED;
	}
1300

P
Peter Zijlstra 已提交
1301 1302 1303 1304 1305 1306 1307 1308
	if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
		/*
		 * Drain the remaining delta count out of a event
		 * that we are disabling:
		 */
		x86_perf_event_update(event);
		hwc->state |= PERF_HES_UPTODATE;
	}
1309 1310
}

P
Peter Zijlstra 已提交
1311
static void x86_pmu_del(struct perf_event *event, int flags)
1312
{
1313
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1314 1315
	int i;

1316 1317 1318 1319 1320
	/*
	 * event is descheduled
	 */
	event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;

1321 1322 1323 1324
	/*
	 * If we're called during a txn, we don't need to do anything.
	 * The events never got scheduled and ->cancel_txn will truncate
	 * the event_list.
1325 1326 1327
	 *
	 * XXX assumes any ->del() called during a TXN will only be on
	 * an event added during that same TXN.
1328
	 */
1329
	if (cpuc->group_flag & PERF_EVENT_TXN)
1330 1331
		return;

1332 1333 1334
	/*
	 * Not a TXN, therefore cleanup properly.
	 */
P
Peter Zijlstra 已提交
1335
	x86_pmu_stop(event, PERF_EF_UPDATE);
1336

1337
	for (i = 0; i < cpuc->n_events; i++) {
1338 1339 1340
		if (event == cpuc->event_list[i])
			break;
	}
1341

1342 1343
	if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
		return;
P
Peter Zijlstra 已提交
1344

1345 1346 1347
	/* If we have a newly added event; make sure to decrease n_added. */
	if (i >= cpuc->n_events - cpuc->n_added)
		--cpuc->n_added;
1348

1349 1350 1351 1352
	if (x86_pmu.put_event_constraints)
		x86_pmu.put_event_constraints(cpuc, event);

	/* Delete the array entry. */
1353
	while (++i < cpuc->n_events) {
1354
		cpuc->event_list[i-1] = cpuc->event_list[i];
1355 1356
		cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
	}
1357
	--cpuc->n_events;
1358

1359
	perf_event_update_userpage(event);
I
Ingo Molnar 已提交
1360 1361
}

1362
int x86_pmu_handle_irq(struct pt_regs *regs)
1363
{
1364
	struct perf_sample_data data;
1365 1366
	struct cpu_hw_events *cpuc;
	struct perf_event *event;
V
Vince Weaver 已提交
1367
	int idx, handled = 0;
1368 1369
	u64 val;

1370
	cpuc = this_cpu_ptr(&cpu_hw_events);
1371

1372 1373 1374 1375 1376 1377 1378 1379 1380 1381
	/*
	 * Some chipsets need to unmask the LVTPC in a particular spot
	 * inside the nmi handler.  As a result, the unmasking was pushed
	 * into all the nmi handlers.
	 *
	 * This generic handler doesn't seem to have any issues where the
	 * unmasking occurs so it was left at the top.
	 */
	apic_write(APIC_LVTPC, APIC_DM_NMI);

1382
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1383 1384 1385 1386 1387 1388 1389 1390
		if (!test_bit(idx, cpuc->active_mask)) {
			/*
			 * Though we deactivated the counter some cpus
			 * might still deliver spurious interrupts still
			 * in flight. Catch them:
			 */
			if (__test_and_clear_bit(idx, cpuc->running))
				handled++;
1391
			continue;
1392
		}
1393

1394
		event = cpuc->events[idx];
1395

1396
		val = x86_perf_event_update(event);
1397
		if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1398
			continue;
1399

1400
		/*
1401
		 * event overflow
1402
		 */
1403
		handled++;
1404
		perf_sample_data_init(&data, 0, event->hw.last_period);
1405

1406
		if (!x86_perf_event_set_period(event))
1407 1408
			continue;

1409
		if (perf_event_overflow(event, &data, regs))
P
Peter Zijlstra 已提交
1410
			x86_pmu_stop(event, 0);
1411
	}
1412

1413 1414 1415
	if (handled)
		inc_irq_stat(apic_perf_irqs);

1416 1417
	return handled;
}
1418

1419
void perf_events_lapic_init(void)
I
Ingo Molnar 已提交
1420
{
1421
	if (!x86_pmu.apic || !x86_pmu_initialized())
I
Ingo Molnar 已提交
1422
		return;
1423

I
Ingo Molnar 已提交
1424
	/*
1425
	 * Always use NMI for PMU
I
Ingo Molnar 已提交
1426
	 */
1427
	apic_write(APIC_LVTPC, APIC_DM_NMI);
I
Ingo Molnar 已提交
1428 1429
}

1430
static int
1431
perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
I
Ingo Molnar 已提交
1432
{
1433 1434
	u64 start_clock;
	u64 finish_clock;
P
Peter Zijlstra 已提交
1435
	int ret;
1436

1437 1438 1439 1440
	/*
	 * All PMUs/events that share this PMI handler should make sure to
	 * increment active_events for their events.
	 */
1441
	if (!atomic_read(&active_events))
1442
		return NMI_DONE;
1443

P
Peter Zijlstra 已提交
1444
	start_clock = sched_clock();
1445
	ret = x86_pmu.handle_irq(regs);
P
Peter Zijlstra 已提交
1446
	finish_clock = sched_clock();
1447 1448 1449 1450

	perf_sample_event_took(finish_clock - start_clock);

	return ret;
I
Ingo Molnar 已提交
1451
}
1452
NOKPROBE_SYMBOL(perf_event_nmi_handler);
I
Ingo Molnar 已提交
1453

1454 1455
struct event_constraint emptyconstraint;
struct event_constraint unconstrained;
1456

1457
static int
1458 1459 1460
x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
{
	unsigned int cpu = (long)hcpu;
1461
	struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1462
	int i, ret = NOTIFY_OK;
1463 1464 1465

	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_UP_PREPARE:
1466 1467
		for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
			cpuc->kfree_on_online[i] = NULL;
1468
		if (x86_pmu.cpu_prepare)
1469
			ret = x86_pmu.cpu_prepare(cpu);
1470 1471 1472 1473 1474 1475 1476
		break;

	case CPU_STARTING:
		if (x86_pmu.cpu_starting)
			x86_pmu.cpu_starting(cpu);
		break;

1477
	case CPU_ONLINE:
1478 1479 1480 1481
		for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
			kfree(cpuc->kfree_on_online[i]);
			cpuc->kfree_on_online[i] = NULL;
		}
1482 1483
		break;

1484 1485 1486 1487 1488
	case CPU_DYING:
		if (x86_pmu.cpu_dying)
			x86_pmu.cpu_dying(cpu);
		break;

1489
	case CPU_UP_CANCELED:
1490 1491 1492 1493 1494 1495 1496 1497 1498
	case CPU_DEAD:
		if (x86_pmu.cpu_dead)
			x86_pmu.cpu_dead(cpu);
		break;

	default:
		break;
	}

1499
	return ret;
1500 1501
}

1502 1503 1504 1505 1506 1507 1508 1509
static void __init pmu_check_apic(void)
{
	if (cpu_has_apic)
		return;

	x86_pmu.apic = 0;
	pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
	pr_info("no hardware sampling interrupt available.\n");
1510 1511 1512 1513 1514 1515 1516 1517 1518

	/*
	 * If we have a PMU initialized but no APIC
	 * interrupts, we cannot sample hardware
	 * events (user-space has to fall back and
	 * sample via a hrtimer based software event):
	 */
	pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;

1519 1520
}

1521 1522 1523 1524 1525
static struct attribute_group x86_pmu_format_group = {
	.name = "format",
	.attrs = NULL,
};

1526 1527 1528 1529 1530 1531
/*
 * Remove all undefined events (x86_pmu.event_map(id) == 0)
 * out of events_attr attributes.
 */
static void __init filter_events(struct attribute **attrs)
{
1532 1533
	struct device_attribute *d;
	struct perf_pmu_events_attr *pmu_attr;
1534 1535 1536
	int i, j;

	for (i = 0; attrs[i]; i++) {
1537 1538 1539 1540 1541
		d = (struct device_attribute *)attrs[i];
		pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
		/* str trumps id */
		if (pmu_attr->event_str)
			continue;
1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552
		if (x86_pmu.event_map(i))
			continue;

		for (j = i; attrs[j]; j++)
			attrs[j] = attrs[j + 1];

		/* Check the shifted attr. */
		i--;
	}
}

1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578
/* Merge two pointer arrays */
static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
{
	struct attribute **new;
	int j, i;

	for (j = 0; a[j]; j++)
		;
	for (i = 0; b[i]; i++)
		j++;
	j++;

	new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
	if (!new)
		return NULL;

	j = 0;
	for (i = 0; a[i]; i++)
		new[j++] = a[i];
	for (i = 0; b[i]; i++)
		new[j++] = b[i];
	new[j] = NULL;

	return new;
}

1579
ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1580 1581 1582 1583 1584 1585
			  char *page)
{
	struct perf_pmu_events_attr *pmu_attr = \
		container_of(attr, struct perf_pmu_events_attr, attr);
	u64 config = x86_pmu.event_map(pmu_attr->id);

1586 1587 1588
	/* string trumps id */
	if (pmu_attr->event_str)
		return sprintf(page, "%s", pmu_attr->event_str);
1589

1590 1591
	return x86_pmu.events_sysfs_show(page, config);
}
1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605

EVENT_ATTR(cpu-cycles,			CPU_CYCLES		);
EVENT_ATTR(instructions,		INSTRUCTIONS		);
EVENT_ATTR(cache-references,		CACHE_REFERENCES	);
EVENT_ATTR(cache-misses, 		CACHE_MISSES		);
EVENT_ATTR(branch-instructions,		BRANCH_INSTRUCTIONS	);
EVENT_ATTR(branch-misses,		BRANCH_MISSES		);
EVENT_ATTR(bus-cycles,			BUS_CYCLES		);
EVENT_ATTR(stalled-cycles-frontend,	STALLED_CYCLES_FRONTEND	);
EVENT_ATTR(stalled-cycles-backend,	STALLED_CYCLES_BACKEND	);
EVENT_ATTR(ref-cycles,			REF_CPU_CYCLES		);

static struct attribute *empty_attrs;

P
Peter Huewe 已提交
1606
static struct attribute *events_attr[] = {
1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624
	EVENT_PTR(CPU_CYCLES),
	EVENT_PTR(INSTRUCTIONS),
	EVENT_PTR(CACHE_REFERENCES),
	EVENT_PTR(CACHE_MISSES),
	EVENT_PTR(BRANCH_INSTRUCTIONS),
	EVENT_PTR(BRANCH_MISSES),
	EVENT_PTR(BUS_CYCLES),
	EVENT_PTR(STALLED_CYCLES_FRONTEND),
	EVENT_PTR(STALLED_CYCLES_BACKEND),
	EVENT_PTR(REF_CPU_CYCLES),
	NULL,
};

static struct attribute_group x86_pmu_events_group = {
	.name = "events",
	.attrs = events_attr,
};

1625
ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663
{
	u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
	u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
	bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
	bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
	bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
	bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
	ssize_t ret;

	/*
	* We have whole page size to spend and just little data
	* to write, so we can safely use sprintf.
	*/
	ret = sprintf(page, "event=0x%02llx", event);

	if (umask)
		ret += sprintf(page + ret, ",umask=0x%02llx", umask);

	if (edge)
		ret += sprintf(page + ret, ",edge");

	if (pc)
		ret += sprintf(page + ret, ",pc");

	if (any)
		ret += sprintf(page + ret, ",any");

	if (inv)
		ret += sprintf(page + ret, ",inv");

	if (cmask)
		ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);

	ret += sprintf(page + ret, "\n");

	return ret;
}

1664
static int __init init_hw_perf_events(void)
1665
{
1666
	struct x86_pmu_quirk *quirk;
1667 1668
	int err;

1669
	pr_info("Performance Events: ");
1670

1671 1672
	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_INTEL:
1673
		err = intel_pmu_init();
1674
		break;
1675
	case X86_VENDOR_AMD:
1676
		err = amd_pmu_init();
1677
		break;
1678
	default:
1679
		err = -ENOTSUPP;
1680
	}
1681
	if (err != 0) {
1682
		pr_cont("no PMU driver, software events only.\n");
1683
		return 0;
1684
	}
1685

1686 1687
	pmu_check_apic();

1688
	/* sanity check that the hardware exists or is emulated */
1689
	if (!check_hw_exists())
1690
		return 0;
1691

1692
	pr_cont("%s PMU driver.\n", x86_pmu.name);
1693

1694 1695
	x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */

1696 1697
	for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
		quirk->func();
1698

1699 1700
	if (!x86_pmu.intel_ctrl)
		x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
I
Ingo Molnar 已提交
1701

1702
	perf_events_lapic_init();
1703
	register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1704

1705
	unconstrained = (struct event_constraint)
1706
		__EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1707
				   0, x86_pmu.num_counters, 0, 0);
1708

1709
	x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1710

1711 1712 1713
	if (x86_pmu.event_attrs)
		x86_pmu_events_group.attrs = x86_pmu.event_attrs;

1714 1715
	if (!x86_pmu.events_sysfs_show)
		x86_pmu_events_group.attrs = &empty_attrs;
1716 1717
	else
		filter_events(x86_pmu_events_group.attrs);
1718

1719 1720 1721 1722 1723 1724 1725 1726
	if (x86_pmu.cpu_events) {
		struct attribute **tmp;

		tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
		if (!WARN_ON(!tmp))
			x86_pmu_events_group.attrs = tmp;
	}

I
Ingo Molnar 已提交
1727
	pr_info("... version:                %d\n",     x86_pmu.version);
1728 1729 1730
	pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
	pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
	pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
I
Ingo Molnar 已提交
1731
	pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1732
	pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1733
	pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1734

P
Peter Zijlstra 已提交
1735
	perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1736
	perf_cpu_notifier(x86_pmu_notifier);
1737 1738

	return 0;
I
Ingo Molnar 已提交
1739
}
1740
early_initcall(init_hw_perf_events);
I
Ingo Molnar 已提交
1741

1742
static inline void x86_pmu_read(struct perf_event *event)
1743
{
1744
	x86_perf_event_update(event);
1745 1746
}

1747 1748 1749 1750 1751
/*
 * Start group events scheduling transaction
 * Set the flag to make pmu::enable() not perform the
 * schedulability test, it will be performed at commit time
 */
P
Peter Zijlstra 已提交
1752
static void x86_pmu_start_txn(struct pmu *pmu)
1753
{
P
Peter Zijlstra 已提交
1754
	perf_pmu_disable(pmu);
T
Tejun Heo 已提交
1755 1756
	__this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
	__this_cpu_write(cpu_hw_events.n_txn, 0);
1757 1758 1759 1760 1761 1762 1763
}

/*
 * Stop group events scheduling transaction
 * Clear the flag and pmu::enable() will perform the
 * schedulability test.
 */
P
Peter Zijlstra 已提交
1764
static void x86_pmu_cancel_txn(struct pmu *pmu)
1765
{
T
Tejun Heo 已提交
1766
	__this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1767
	/*
1768 1769
	 * Truncate collected array by the number of events added in this
	 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1770
	 */
T
Tejun Heo 已提交
1771 1772
	__this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
	__this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
P
Peter Zijlstra 已提交
1773
	perf_pmu_enable(pmu);
1774 1775 1776 1777 1778 1779
}

/*
 * Commit group events scheduling transaction
 * Perform the group schedulability test as a whole
 * Return 0 if success
1780 1781
 *
 * Does not cancel the transaction on failure; expects the caller to do this.
1782
 */
P
Peter Zijlstra 已提交
1783
static int x86_pmu_commit_txn(struct pmu *pmu)
1784
{
1785
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803
	int assign[X86_PMC_IDX_MAX];
	int n, ret;

	n = cpuc->n_events;

	if (!x86_pmu_initialized())
		return -EAGAIN;

	ret = x86_pmu.schedule_events(cpuc, n, assign);
	if (ret)
		return ret;

	/*
	 * copy new assignment, now we know it is possible
	 * will be used by hw_perf_enable()
	 */
	memcpy(cpuc->assign, assign, n*sizeof(int));

1804
	cpuc->group_flag &= ~PERF_EVENT_TXN;
P
Peter Zijlstra 已提交
1805
	perf_pmu_enable(pmu);
1806 1807
	return 0;
}
1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836
/*
 * a fake_cpuc is used to validate event groups. Due to
 * the extra reg logic, we need to also allocate a fake
 * per_core and per_cpu structure. Otherwise, group events
 * using extra reg may conflict without the kernel being
 * able to catch this when the last event gets added to
 * the group.
 */
static void free_fake_cpuc(struct cpu_hw_events *cpuc)
{
	kfree(cpuc->shared_regs);
	kfree(cpuc);
}

static struct cpu_hw_events *allocate_fake_cpuc(void)
{
	struct cpu_hw_events *cpuc;
	int cpu = raw_smp_processor_id();

	cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
	if (!cpuc)
		return ERR_PTR(-ENOMEM);

	/* only needed, if we have extra_regs */
	if (x86_pmu.extra_regs) {
		cpuc->shared_regs = allocate_shared_regs(cpu);
		if (!cpuc->shared_regs)
			goto error;
	}
1837
	cpuc->is_fake = 1;
1838 1839 1840 1841 1842
	return cpuc;
error:
	free_fake_cpuc(cpuc);
	return ERR_PTR(-ENOMEM);
}
1843

1844 1845 1846 1847 1848 1849 1850 1851 1852
/*
 * validate that we can schedule this event
 */
static int validate_event(struct perf_event *event)
{
	struct cpu_hw_events *fake_cpuc;
	struct event_constraint *c;
	int ret = 0;

1853 1854 1855
	fake_cpuc = allocate_fake_cpuc();
	if (IS_ERR(fake_cpuc))
		return PTR_ERR(fake_cpuc);
1856

1857
	c = x86_pmu.get_event_constraints(fake_cpuc, -1, event);
1858 1859

	if (!c || !c->weight)
1860
		ret = -EINVAL;
1861 1862 1863 1864

	if (x86_pmu.put_event_constraints)
		x86_pmu.put_event_constraints(fake_cpuc, event);

1865
	free_fake_cpuc(fake_cpuc);
1866 1867 1868 1869

	return ret;
}

1870 1871 1872 1873
/*
 * validate a single event group
 *
 * validation include:
1874 1875 1876
 *	- check events are compatible which each other
 *	- events do not compete for the same counter
 *	- number of events <= number of counters
1877 1878 1879 1880
 *
 * validation ensures the group can be loaded onto the
 * PMU if it was the only group available.
 */
1881 1882
static int validate_group(struct perf_event *event)
{
1883
	struct perf_event *leader = event->group_leader;
1884
	struct cpu_hw_events *fake_cpuc;
1885
	int ret = -EINVAL, n;
1886

1887 1888 1889
	fake_cpuc = allocate_fake_cpuc();
	if (IS_ERR(fake_cpuc))
		return PTR_ERR(fake_cpuc);
1890 1891 1892 1893 1894 1895
	/*
	 * the event is not yet connected with its
	 * siblings therefore we must first collect
	 * existing siblings, then add the new event
	 * before we can simulate the scheduling
	 */
1896
	n = collect_events(fake_cpuc, leader, true);
1897
	if (n < 0)
1898
		goto out;
1899

1900 1901
	fake_cpuc->n_events = n;
	n = collect_events(fake_cpuc, event, false);
1902
	if (n < 0)
1903
		goto out;
1904

1905
	fake_cpuc->n_events = n;
1906

1907
	ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1908 1909

out:
1910
	free_fake_cpuc(fake_cpuc);
1911
	return ret;
1912 1913
}

1914
static int x86_pmu_event_init(struct perf_event *event)
I
Ingo Molnar 已提交
1915
{
P
Peter Zijlstra 已提交
1916
	struct pmu *tmp;
I
Ingo Molnar 已提交
1917 1918
	int err;

1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929
	switch (event->attr.type) {
	case PERF_TYPE_RAW:
	case PERF_TYPE_HARDWARE:
	case PERF_TYPE_HW_CACHE:
		break;

	default:
		return -ENOENT;
	}

	err = __x86_pmu_event_init(event);
1930
	if (!err) {
1931 1932 1933 1934 1935 1936 1937 1938
		/*
		 * we temporarily connect event to its pmu
		 * such that validate_group() can classify
		 * it as an x86 event using is_x86_event()
		 */
		tmp = event->pmu;
		event->pmu = &pmu;

1939 1940
		if (event->group_leader != event)
			err = validate_group(event);
1941 1942
		else
			err = validate_event(event);
1943 1944

		event->pmu = tmp;
1945
	}
1946
	if (err) {
1947 1948
		if (event->destroy)
			event->destroy(event);
1949
	}
I
Ingo Molnar 已提交
1950

1951 1952 1953
	if (ACCESS_ONCE(x86_pmu.attr_rdpmc))
		event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;

1954
	return err;
I
Ingo Molnar 已提交
1955
}
1956

1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983
static void refresh_pce(void *ignored)
{
	if (current->mm)
		load_mm_cr4(current->mm);
}

static void x86_pmu_event_mapped(struct perf_event *event)
{
	if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
		return;

	if (atomic_inc_return(&current->mm->context.perf_rdpmc_allowed) == 1)
		on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
}

static void x86_pmu_event_unmapped(struct perf_event *event)
{
	if (!current->mm)
		return;

	if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
		return;

	if (atomic_dec_and_test(&current->mm->context.perf_rdpmc_allowed))
		on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
}

1984 1985 1986 1987
static int x86_pmu_event_idx(struct perf_event *event)
{
	int idx = event->hw.idx;

1988
	if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
1989 1990
		return 0;

1991 1992
	if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
		idx -= INTEL_PMC_IDX_FIXED;
1993 1994 1995 1996 1997 1998
		idx |= 1 << 30;
	}

	return idx + 1;
}

1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009
static ssize_t get_attr_rdpmc(struct device *cdev,
			      struct device_attribute *attr,
			      char *buf)
{
	return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
}

static ssize_t set_attr_rdpmc(struct device *cdev,
			      struct device_attribute *attr,
			      const char *buf, size_t count)
{
2010 2011 2012 2013 2014 2015
	unsigned long val;
	ssize_t ret;

	ret = kstrtoul(buf, 0, &val);
	if (ret)
		return ret;
2016

2017 2018 2019
	if (val > 2)
		return -EINVAL;

2020 2021
	if (x86_pmu.attr_rdpmc_broken)
		return -ENOTSUPP;
2022

2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037
	if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) {
		/*
		 * Changing into or out of always available, aka
		 * perf-event-bypassing mode.  This path is extremely slow,
		 * but only root can trigger it, so it's okay.
		 */
		if (val == 2)
			static_key_slow_inc(&rdpmc_always_available);
		else
			static_key_slow_dec(&rdpmc_always_available);
		on_each_cpu(refresh_pce, NULL, 1);
	}

	x86_pmu.attr_rdpmc = val;

2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053
	return count;
}

static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);

static struct attribute *x86_pmu_attrs[] = {
	&dev_attr_rdpmc.attr,
	NULL,
};

static struct attribute_group x86_pmu_attr_group = {
	.attrs = x86_pmu_attrs,
};

static const struct attribute_group *x86_pmu_attr_groups[] = {
	&x86_pmu_attr_group,
2054
	&x86_pmu_format_group,
2055
	&x86_pmu_events_group,
2056 2057 2058
	NULL,
};

2059
static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2060
{
2061 2062
	if (x86_pmu.sched_task)
		x86_pmu.sched_task(ctx, sched_in);
2063 2064
}

2065 2066 2067 2068 2069 2070 2071
void perf_check_microcode(void)
{
	if (x86_pmu.check_microcode)
		x86_pmu.check_microcode();
}
EXPORT_SYMBOL_GPL(perf_check_microcode);

2072
static struct pmu pmu = {
2073 2074
	.pmu_enable		= x86_pmu_enable,
	.pmu_disable		= x86_pmu_disable,
P
Peter Zijlstra 已提交
2075

2076
	.attr_groups		= x86_pmu_attr_groups,
2077

2078
	.event_init		= x86_pmu_event_init,
P
Peter Zijlstra 已提交
2079

2080 2081 2082
	.event_mapped		= x86_pmu_event_mapped,
	.event_unmapped		= x86_pmu_event_unmapped,

2083 2084 2085 2086 2087
	.add			= x86_pmu_add,
	.del			= x86_pmu_del,
	.start			= x86_pmu_start,
	.stop			= x86_pmu_stop,
	.read			= x86_pmu_read,
P
Peter Zijlstra 已提交
2088

2089 2090 2091
	.start_txn		= x86_pmu_start_txn,
	.cancel_txn		= x86_pmu_cancel_txn,
	.commit_txn		= x86_pmu_commit_txn,
2092

2093
	.event_idx		= x86_pmu_event_idx,
2094
	.sched_task		= x86_pmu_sched_task,
2095
	.task_ctx_size          = sizeof(struct x86_perf_task_context),
2096 2097
};

2098 2099
void arch_perf_update_userpage(struct perf_event *event,
			       struct perf_event_mmap_page *userpg, u64 now)
2100
{
2101 2102
	struct cyc2ns_data *data;

2103 2104
	userpg->cap_user_time = 0;
	userpg->cap_user_time_zero = 0;
2105 2106
	userpg->cap_user_rdpmc =
		!!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2107 2108
	userpg->pmc_width = x86_pmu.cntval_bits;

2109
	if (!sched_clock_stable())
2110 2111
		return;

2112 2113
	data = cyc2ns_read_begin();

2114 2115 2116 2117
	/*
	 * Internal timekeeping for enabled/running/stopped times
	 * is always in the local_clock domain.
	 */
2118
	userpg->cap_user_time = 1;
2119 2120 2121
	userpg->time_mult = data->cyc2ns_mul;
	userpg->time_shift = data->cyc2ns_shift;
	userpg->time_offset = data->cyc2ns_offset - now;
2122

2123 2124 2125 2126 2127 2128 2129 2130
	/*
	 * cap_user_time_zero doesn't make sense when we're using a different
	 * time base for the records.
	 */
	if (event->clock == &local_clock) {
		userpg->cap_user_time_zero = 1;
		userpg->time_zero = data->cyc2ns_offset;
	}
2131 2132

	cyc2ns_read_end(data);
2133 2134
}

2135 2136 2137 2138 2139 2140
/*
 * callchain support
 */

static int backtrace_stack(void *data, char *name)
{
2141
	return 0;
2142 2143 2144 2145 2146 2147
}

static void backtrace_address(void *data, unsigned long addr, int reliable)
{
	struct perf_callchain_entry *entry = data;

2148
	perf_callchain_store(entry, addr);
2149 2150 2151 2152 2153
}

static const struct stacktrace_ops backtrace_ops = {
	.stack			= backtrace_stack,
	.address		= backtrace_address,
2154
	.walk_stack		= print_context_stack_bp,
2155 2156
};

2157 2158
void
perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
2159
{
2160 2161
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
		/* TODO: We don't support guest os callchain now */
2162
		return;
2163 2164
	}

2165
	perf_callchain_store(entry, regs->ip);
2166

2167
	dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
2168 2169
}

2170 2171 2172 2173 2174 2175
static inline int
valid_user_frame(const void __user *fp, unsigned long size)
{
	return (__range_not_ok(fp, size, TASK_SIZE) == 0);
}

2176 2177 2178 2179 2180 2181
static unsigned long get_segment_base(unsigned int segment)
{
	struct desc_struct *desc;
	int idx = segment >> 3;

	if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2182 2183
		struct ldt_struct *ldt;

2184 2185 2186
		if (idx > LDT_ENTRIES)
			return 0;

2187 2188 2189
		/* IRQs are off, so this synchronizes with smp_store_release */
		ldt = lockless_dereference(current->active_mm->context.ldt);
		if (!ldt || idx > ldt->size)
2190 2191
			return 0;

2192
		desc = &ldt->entries[idx];
2193 2194 2195 2196
	} else {
		if (idx > GDT_ENTRIES)
			return 0;

2197
		desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2198 2199
	}

2200
	return get_desc_base(desc);
2201 2202
}

2203
#ifdef CONFIG_COMPAT
H
H. Peter Anvin 已提交
2204 2205 2206

#include <asm/compat.h>

2207 2208
static inline int
perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2209
{
2210
	/* 32-bit process in 64-bit kernel. */
2211
	unsigned long ss_base, cs_base;
2212 2213
	struct stack_frame_ia32 frame;
	const void __user *fp;
2214

2215 2216 2217
	if (!test_thread_flag(TIF_IA32))
		return 0;

2218 2219 2220 2221
	cs_base = get_segment_base(regs->cs);
	ss_base = get_segment_base(regs->ss);

	fp = compat_ptr(ss_base + regs->bp);
2222 2223 2224 2225 2226 2227
	while (entry->nr < PERF_MAX_STACK_DEPTH) {
		unsigned long bytes;
		frame.next_frame     = 0;
		frame.return_address = 0;

		bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2228
		if (bytes != 0)
2229
			break;
2230

2231 2232 2233
		if (!valid_user_frame(fp, sizeof(frame)))
			break;

2234 2235
		perf_callchain_store(entry, cs_base + frame.return_address);
		fp = compat_ptr(ss_base + frame.next_frame);
2236 2237
	}
	return 1;
2238
}
2239 2240 2241 2242 2243 2244 2245
#else
static inline int
perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
{
    return 0;
}
#endif
2246

2247 2248
void
perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
2249 2250 2251 2252
{
	struct stack_frame frame;
	const void __user *fp;

2253 2254
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
		/* TODO: We don't support guest os callchain now */
2255
		return;
2256
	}
2257

2258 2259 2260 2261 2262 2263
	/*
	 * We don't know what to do with VM86 stacks.. ignore them for now.
	 */
	if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
		return;

2264
	fp = (void __user *)regs->bp;
2265

2266
	perf_callchain_store(entry, regs->ip);
2267

2268 2269 2270
	if (!current->mm)
		return;

2271 2272 2273
	if (perf_callchain_user32(regs, entry))
		return;

2274
	while (entry->nr < PERF_MAX_STACK_DEPTH) {
2275
		unsigned long bytes;
2276
		frame.next_frame	     = NULL;
2277 2278
		frame.return_address = 0;

2279
		bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2280
		if (bytes != 0)
2281 2282
			break;

2283 2284 2285
		if (!valid_user_frame(fp, sizeof(frame)))
			break;

2286
		perf_callchain_store(entry, frame.return_address);
2287
		fp = frame.next_frame;
2288 2289 2290
	}
}

2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304
/*
 * Deal with code segment offsets for the various execution modes:
 *
 *   VM86 - the good olde 16 bit days, where the linear address is
 *          20 bits and we use regs->ip + 0x10 * regs->cs.
 *
 *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
 *          to figure out what the 32bit base address is.
 *
 *    X32 - has TIF_X32 set, but is running in x86_64
 *
 * X86_64 - CS,DS,SS,ES are all zero based.
 */
static unsigned long code_segment_base(struct pt_regs *regs)
2305
{
2306 2307 2308 2309 2310 2311
	/*
	 * For IA32 we look at the GDT/LDT segment base to convert the
	 * effective IP to a linear address.
	 */

#ifdef CONFIG_X86_32
2312 2313 2314 2315 2316 2317 2318
	/*
	 * If we are in VM86 mode, add the segment offset to convert to a
	 * linear address.
	 */
	if (regs->flags & X86_VM_MASK)
		return 0x10 * regs->cs;

2319
	if (user_mode(regs) && regs->cs != __USER_CS)
2320 2321
		return get_segment_base(regs->cs);
#else
2322 2323 2324
	if (user_mode(regs) && !user_64bit_mode(regs) &&
	    regs->cs != __USER32_CS)
		return get_segment_base(regs->cs);
2325 2326 2327
#endif
	return 0;
}
2328

2329 2330
unsigned long perf_instruction_pointer(struct pt_regs *regs)
{
2331
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2332
		return perf_guest_cbs->get_guest_ip();
2333

2334
	return regs->ip + code_segment_base(regs);
2335 2336 2337 2338 2339
}

unsigned long perf_misc_flags(struct pt_regs *regs)
{
	int misc = 0;
2340

2341
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2342 2343 2344 2345 2346
		if (perf_guest_cbs->is_user_mode())
			misc |= PERF_RECORD_MISC_GUEST_USER;
		else
			misc |= PERF_RECORD_MISC_GUEST_KERNEL;
	} else {
2347
		if (user_mode(regs))
2348 2349 2350 2351 2352
			misc |= PERF_RECORD_MISC_USER;
		else
			misc |= PERF_RECORD_MISC_KERNEL;
	}

2353
	if (regs->flags & PERF_EFLAGS_EXACT)
P
Peter Zijlstra 已提交
2354
		misc |= PERF_RECORD_MISC_EXACT_IP;
2355 2356 2357

	return misc;
}
2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369

void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
{
	cap->version		= x86_pmu.version;
	cap->num_counters_gp	= x86_pmu.num_counters;
	cap->num_counters_fixed	= x86_pmu.num_counters_fixed;
	cap->bit_width_gp	= x86_pmu.cntval_bits;
	cap->bit_width_fixed	= x86_pmu.cntval_bits;
	cap->events_mask	= (unsigned int)x86_pmu.events_maskl;
	cap->events_mask_len	= x86_pmu.events_mask_len;
}
EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);