pci.c 68.9 KB
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/*
 * QEMU PCI bus manager
 *
 * Copyright (c) 2004 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
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#include "hw/hw.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci/pci_host.h"
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#include "monitor/monitor.h"
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#include "net/net.h"
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#include "sysemu/sysemu.h"
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#include "hw/loader.h"
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#include "qemu/range.h"
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#include "qmp-commands.h"
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#include "hw/pci/msi.h"
#include "hw/pci/msix.h"
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#include "exec/address-spaces.h"
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#include "hw/hotplug.h"
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//#define DEBUG_PCI
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#ifdef DEBUG_PCI
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# define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)
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#else
# define PCI_DPRINTF(format, ...)       do { } while (0)
#endif
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static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
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static char *pcibus_get_dev_path(DeviceState *dev);
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static char *pcibus_get_fw_dev_path(DeviceState *dev);
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static void pcibus_reset(BusState *qbus);
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static void pci_bus_finalize(Object *obj);
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static Property pci_props[] = {
    DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
    DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
    DEFINE_PROP_UINT32("rombar",  PCIDevice, rom_bar, 1),
    DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
                    QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
    DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
                    QEMU_PCI_CAP_SERR_BITNR, true),
    DEFINE_PROP_END_OF_LIST()
};

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static void pci_bus_class_init(ObjectClass *klass, void *data)
{
    BusClass *k = BUS_CLASS(klass);

    k->print_dev = pcibus_dev_print;
    k->get_dev_path = pcibus_get_dev_path;
    k->get_fw_dev_path = pcibus_get_fw_dev_path;
    k->reset = pcibus_reset;
}

static const TypeInfo pci_bus_info = {
    .name = TYPE_PCI_BUS,
    .parent = TYPE_BUS,
    .instance_size = sizeof(PCIBus),
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    .instance_finalize = pci_bus_finalize,
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    .class_init = pci_bus_class_init,
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};
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static const TypeInfo pcie_bus_info = {
    .name = TYPE_PCIE_BUS,
    .parent = TYPE_PCI_BUS,
};

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static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
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static void pci_update_mappings(PCIDevice *d);
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static void pci_irq_handler(void *opaque, int irq_num, int level);
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static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
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static void pci_del_option_rom(PCIDevice *pdev);
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static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
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static QLIST_HEAD(, PCIHostState) pci_host_bridges;
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static const VMStateDescription vmstate_pcibus = {
    .name = "PCIBUS",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_INT32_EQUAL(nirq, PCIBus),
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        VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static int pci_bar(PCIDevice *d, int reg)
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{
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    uint8_t type;

    if (reg != PCI_ROM_SLOT)
        return PCI_BASE_ADDRESS_0 + reg * 4;

    type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
    return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
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}

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static inline int pci_irq_state(PCIDevice *d, int irq_num)
{
	return (d->irq_state >> irq_num) & 0x1;
}

static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
{
	d->irq_state &= ~(0x1 << irq_num);
	d->irq_state |= level << irq_num;
}

static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
{
    PCIBus *bus;
    for (;;) {
        bus = pci_dev->bus;
        irq_num = bus->map_irq(pci_dev, irq_num);
        if (bus->set_irq)
            break;
        pci_dev = bus->parent_dev;
    }
    bus->irq_count[irq_num] += change;
    bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
}

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int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
{
    assert(irq_num >= 0);
    assert(irq_num < bus->nirq);
    return !!bus->irq_count[irq_num];
}

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/* Update interrupt status bit in config space on interrupt
 * state change. */
static void pci_update_irq_status(PCIDevice *dev)
{
    if (dev->irq_state) {
        dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
    } else {
        dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
    }
}

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void pci_device_deassert_intx(PCIDevice *dev)
{
    int i;
    for (i = 0; i < PCI_NUM_PINS; ++i) {
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        pci_irq_handler(dev, i, 0);
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    }
}

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static void pci_do_device_reset(PCIDevice *dev)
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{
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    int r;
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    dev->irq_state = 0;
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    pci_update_irq_status(dev);
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    pci_device_deassert_intx(dev);
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    /* Clear all writable bits */
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    pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
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                                 pci_get_word(dev->wmask + PCI_COMMAND) |
                                 pci_get_word(dev->w1cmask + PCI_COMMAND));
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    pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
                                 pci_get_word(dev->wmask + PCI_STATUS) |
                                 pci_get_word(dev->w1cmask + PCI_STATUS));
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    dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
    dev->config[PCI_INTERRUPT_LINE] = 0x0;
    for (r = 0; r < PCI_NUM_REGIONS; ++r) {
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        PCIIORegion *region = &dev->io_regions[r];
        if (!region->size) {
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            continue;
        }
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        if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
            region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
            pci_set_quad(dev->config + pci_bar(dev, r), region->type);
        } else {
            pci_set_long(dev->config + pci_bar(dev, r), region->type);
        }
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    }
    pci_update_mappings(dev);
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    msi_reset(dev);
    msix_reset(dev);
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}

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/*
 * This function is called on #RST and FLR.
 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
 */
void pci_device_reset(PCIDevice *dev)
{
    qdev_reset_all(&dev->qdev);
    pci_do_device_reset(dev);
}

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/*
 * Trigger pci bus reset under a given bus.
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 * Called via qbus_reset_all on RST# assert, after the devices
 * have been reset qdev_reset_all-ed already.
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 */
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static void pcibus_reset(BusState *qbus)
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{
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    PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
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    int i;

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    for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
        if (bus->devices[i]) {
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            pci_do_device_reset(bus->devices[i]);
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        }
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    }
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    for (i = 0; i < bus->nirq; i++) {
        assert(bus->irq_count[i] == 0);
    }
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}

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static void pci_host_bus_register(PCIBus *bus, DeviceState *parent)
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{
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    PCIHostState *host_bridge = PCI_HOST_BRIDGE(parent);

    QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
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}

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PCIBus *pci_find_primary_bus(void)
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{
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    PCIBus *primary_bus = NULL;
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    PCIHostState *host;
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    QLIST_FOREACH(host, &pci_host_bridges, next) {
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        if (primary_bus) {
            /* We have multiple root buses, refuse to select a primary */
            return NULL;
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        }
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        primary_bus = host->bus;
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    }

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    return primary_bus;
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}

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PCIBus *pci_device_root_bus(const PCIDevice *d)
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{
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    PCIBus *bus = d->bus;
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    while ((d = bus->parent_dev) != NULL) {
        bus = d->bus;
    }

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    return bus;
}

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const char *pci_root_bus_path(PCIDevice *dev)
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{
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    PCIBus *rootbus = pci_device_root_bus(dev);
    PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
    PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
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    assert(!rootbus->parent_dev);
    assert(host_bridge->bus == rootbus);

    if (hc->root_bus_path) {
        return (*hc->root_bus_path)(host_bridge, rootbus);
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    }

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    return rootbus->qbus.name;
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}

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static void pci_bus_init(PCIBus *bus, DeviceState *parent,
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                         const char *name,
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                         MemoryRegion *address_space_mem,
                         MemoryRegion *address_space_io,
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                         uint8_t devfn_min)
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{
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    assert(PCI_FUNC(devfn_min) == 0);
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    bus->devfn_min = devfn_min;
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    bus->address_space_mem = address_space_mem;
    bus->address_space_io = address_space_io;
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    /* host bridge */
    QLIST_INIT(&bus->child);
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    pci_host_bus_register(bus, parent);
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    vmstate_register(NULL, -1, &vmstate_pcibus, bus);
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}

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bool pci_bus_is_express(PCIBus *bus)
{
    return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
}

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bool pci_bus_is_root(PCIBus *bus)
{
    return !bus->parent_dev;
}

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void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
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                         const char *name,
                         MemoryRegion *address_space_mem,
                         MemoryRegion *address_space_io,
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                         uint8_t devfn_min, const char *typename)
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{
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    qbus_create_inplace(bus, bus_size, typename, parent, name);
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    pci_bus_init(bus, parent, name, address_space_mem,
                 address_space_io, devfn_min);
}

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PCIBus *pci_bus_new(DeviceState *parent, const char *name,
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                    MemoryRegion *address_space_mem,
                    MemoryRegion *address_space_io,
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                    uint8_t devfn_min, const char *typename)
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{
    PCIBus *bus;

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    bus = PCI_BUS(qbus_create(typename, parent, name));
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    pci_bus_init(bus, parent, name, address_space_mem,
                 address_space_io, devfn_min);
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    return bus;
}

void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
                  void *irq_opaque, int nirq)
{
    bus->set_irq = set_irq;
    bus->map_irq = map_irq;
    bus->irq_opaque = irq_opaque;
    bus->nirq = nirq;
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    bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
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}

PCIBus *pci_register_bus(DeviceState *parent, const char *name,
                         pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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                         void *irq_opaque,
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                         MemoryRegion *address_space_mem,
                         MemoryRegion *address_space_io,
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                         uint8_t devfn_min, int nirq, const char *typename)
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{
    PCIBus *bus;

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    bus = pci_bus_new(parent, name, address_space_mem,
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                      address_space_io, devfn_min, typename);
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    pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
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    return bus;
}
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int pci_bus_num(PCIBus *s)
{
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    if (pci_bus_is_root(s))
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        return 0;       /* pci host bridge */
    return s->parent_dev->config[PCI_SECONDARY_BUS];
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}

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static void pci_bus_finalize(Object *obj)
{
    PCIBus *bus = PCI_BUS(obj);
    vmstate_unregister(NULL, &vmstate_pcibus, bus);
}

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static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
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{
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    PCIDevice *s = container_of(pv, PCIDevice, config);
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    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
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    uint8_t *config;
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    int i;

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    assert(size == pci_config_size(s));
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    config = g_malloc(size);
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    qemu_get_buffer(f, config, size);
    for (i = 0; i < size; ++i) {
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        if ((config[i] ^ s->config[i]) &
            s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
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            g_free(config);
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            return -EINVAL;
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        }
    }
    memcpy(s->config, config, size);
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    pci_update_mappings(s);
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    if (pc->is_bridge) {
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        PCIBridge *b = PCI_BRIDGE(s);
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        pci_bridge_update_mappings(b);
    }
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    memory_region_set_enabled(&s->bus_master_enable_region,
                              pci_get_word(s->config + PCI_COMMAND)
                              & PCI_COMMAND_MASTER);

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    g_free(config);
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    return 0;
}

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/* just put buffer */
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static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
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{
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    const uint8_t **v = pv;
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    assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
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    qemu_put_buffer(f, *v, size);
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}

static VMStateInfo vmstate_info_pci_config = {
    .name = "pci config",
    .get  = get_pci_config_device,
    .put  = put_pci_config_device,
};

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static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
{
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    PCIDevice *s = container_of(pv, PCIDevice, irq_state);
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    uint32_t irq_state[PCI_NUM_PINS];
    int i;
    for (i = 0; i < PCI_NUM_PINS; ++i) {
        irq_state[i] = qemu_get_be32(f);
        if (irq_state[i] != 0x1 && irq_state[i] != 0) {
            fprintf(stderr, "irq state %d: must be 0 or 1.\n",
                    irq_state[i]);
            return -EINVAL;
        }
    }

    for (i = 0; i < PCI_NUM_PINS; ++i) {
        pci_set_irq_state(s, i, irq_state[i]);
    }

    return 0;
}

static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
{
    int i;
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    PCIDevice *s = container_of(pv, PCIDevice, irq_state);
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    for (i = 0; i < PCI_NUM_PINS; ++i) {
        qemu_put_be32(f, pci_irq_state(s, i));
    }
}

static VMStateInfo vmstate_info_pci_irq_state = {
    .name = "pci irq state",
    .get  = get_pci_irq_state,
    .put  = put_pci_irq_state,
};

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const VMStateDescription vmstate_pci_device = {
    .name = "PCIDevice",
    .version_id = 2,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_INT32_LE(version_id, PCIDevice),
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        VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
                                   vmstate_info_pci_config,
                                   PCI_CONFIG_SPACE_SIZE),
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        VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
				   vmstate_info_pci_irq_state,
				   PCI_NUM_PINS * sizeof(int32_t)),
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        VMSTATE_END_OF_LIST()
    }
};

const VMStateDescription vmstate_pcie_device = {
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    .name = "PCIEDevice",
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    .version_id = 2,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_INT32_LE(version_id, PCIDevice),
        VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
                                   vmstate_info_pci_config,
                                   PCIE_CONFIG_SPACE_SIZE),
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        VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
				   vmstate_info_pci_irq_state,
				   PCI_NUM_PINS * sizeof(int32_t)),
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        VMSTATE_END_OF_LIST()
    }
};

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static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
{
    return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
}

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void pci_device_save(PCIDevice *s, QEMUFile *f)
{
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    /* Clear interrupt status bit: it is implicit
     * in irq_state which we are saving.
     * This makes us compatible with old devices
     * which never set or clear this bit. */
    s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
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    vmstate_save_state(f, pci_get_vmstate(s), s);
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    /* Restore the interrupt status bit. */
    pci_update_irq_status(s);
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}

int pci_device_load(PCIDevice *s, QEMUFile *f)
{
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    int ret;
    ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
    /* Restore the interrupt status bit. */
    pci_update_irq_status(s);
    return ret;
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}

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static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
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{
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    pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
                 pci_default_sub_vendor_id);
    pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
                 pci_default_sub_device_id);
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}

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/*
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 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
 *       [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
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 */
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int pci_parse_devaddr(const char *addr, int *domp, int *busp,
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                      unsigned int *slotp, unsigned int *funcp)
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{
    const char *p;
    char *e;
    unsigned long val;
    unsigned long dom = 0, bus = 0;
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    unsigned int slot = 0;
    unsigned int func = 0;
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    p = addr;
    val = strtoul(p, &e, 16);
    if (e == p)
	return -1;
    if (*e == ':') {
	bus = val;
	p = e + 1;
	val = strtoul(p, &e, 16);
	if (e == p)
	    return -1;
	if (*e == ':') {
	    dom = bus;
	    bus = val;
	    p = e + 1;
	    val = strtoul(p, &e, 16);
	    if (e == p)
		return -1;
	}
    }

    slot = val;

567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582
    if (funcp != NULL) {
        if (*e != '.')
            return -1;

        p = e + 1;
        val = strtoul(p, &e, 16);
        if (e == p)
            return -1;

        func = val;
    }

    /* if funcp == NULL func is 0 */
    if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
	return -1;

583 584 585 586 587 588
    if (*e)
	return -1;

    *domp = dom;
    *busp = bus;
    *slotp = slot;
589 590
    if (funcp != NULL)
        *funcp = func;
591 592 593
    return 0;
}

594
PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, const char *devaddr)
595 596 597 598
{
    int dom, bus;
    unsigned slot;

599 600
    assert(!root->parent_dev);

D
David Gibson 已提交
601 602 603 604 605
    if (!root) {
        fprintf(stderr, "No primary PCI bus\n");
        return NULL;
    }

606 607
    if (!devaddr) {
        *devfnp = -1;
D
David Gibson 已提交
608
        return pci_find_bus_nr(root, 0);
609 610
    }

611
    if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
612 613 614
        return NULL;
    }

D
David Gibson 已提交
615 616 617 618 619
    if (dom != 0) {
        fprintf(stderr, "No support for non-zero PCI domains\n");
        return NULL;
    }

620
    *devfnp = PCI_DEVFN(slot, 0);
D
David Gibson 已提交
621
    return pci_find_bus_nr(root, bus);
622 623
}

624 625 626 627 628 629 630 631 632 633 634 635
static void pci_init_cmask(PCIDevice *dev)
{
    pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
    pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
    dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
    dev->cmask[PCI_REVISION_ID] = 0xff;
    dev->cmask[PCI_CLASS_PROG] = 0xff;
    pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
    dev->cmask[PCI_HEADER_TYPE] = 0xff;
    dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
}

636 637
static void pci_init_wmask(PCIDevice *dev)
{
I
Isaku Yamahata 已提交
638 639
    int config_size = pci_config_size(dev);

640 641
    dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
    dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
I
Isaku Yamahata 已提交
642
    pci_set_word(dev->wmask + PCI_COMMAND,
643 644
                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
                 PCI_COMMAND_INTX_DISABLE);
645 646 647
    if (dev->cap_present & QEMU_PCI_CAP_SERR) {
        pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
    }
648 649 650

    memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
           config_size - PCI_CONFIG_HEADER_SIZE);
651 652
}

653 654 655
static void pci_init_w1cmask(PCIDevice *dev)
{
    /*
656
     * Note: It's okay to set w1cmask even for readonly bits as
657 658 659 660 661 662 663 664
     * long as their value is hardwired to 0.
     */
    pci_set_word(dev->w1cmask + PCI_STATUS,
                 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
}

665
static void pci_init_mask_bridge(PCIDevice *d)
666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685
{
    /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
       PCI_SEC_LETENCY_TIMER */
    memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);

    /* base and limit */
    d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
    d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
    pci_set_word(d->wmask + PCI_MEMORY_BASE,
                 PCI_MEMORY_RANGE_MASK & 0xffff);
    pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
                 PCI_MEMORY_RANGE_MASK & 0xffff);
    pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
                 PCI_PREF_RANGE_MASK & 0xffff);
    pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
                 PCI_PREF_RANGE_MASK & 0xffff);

    /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
    memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);

686
    /* Supported memory and i/o types */
M
Michael S. Tsirkin 已提交
687 688
    d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
    d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
689 690 691 692 693
    pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
                               PCI_PREF_RANGE_TYPE_64);
    pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
                               PCI_PREF_RANGE_TYPE_64);

694 695 696 697
    /*
     * TODO: Bridges default to 10-bit VGA decoding but we currently only
     * implement 16-bit decoding (no alias support).
     */
698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713
    pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
                 PCI_BRIDGE_CTL_PARITY |
                 PCI_BRIDGE_CTL_SERR |
                 PCI_BRIDGE_CTL_ISA |
                 PCI_BRIDGE_CTL_VGA |
                 PCI_BRIDGE_CTL_VGA_16BIT |
                 PCI_BRIDGE_CTL_MASTER_ABORT |
                 PCI_BRIDGE_CTL_BUS_RESET |
                 PCI_BRIDGE_CTL_FAST_BACK |
                 PCI_BRIDGE_CTL_DISCARD |
                 PCI_BRIDGE_CTL_SEC_DISCARD |
                 PCI_BRIDGE_CTL_DISCARD_SERR);
    /* Below does not do anything as we never set this bit, put here for
     * completeness. */
    pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
                 PCI_BRIDGE_CTL_DISCARD_STATUS);
714
    d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
715
    d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
716 717
    pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
                               PCI_PREF_RANGE_TYPE_MASK);
718 719
    pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
                               PCI_PREF_RANGE_TYPE_MASK);
720 721
}

722 723 724 725 726 727 728 729 730 731
static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
{
    uint8_t slot = PCI_SLOT(dev->devfn);
    uint8_t func;

    if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
        dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
    }

    /*
S
Stefan Weil 已提交
732
     * multifunction bit is interpreted in two ways as follows.
733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769
     *   - all functions must set the bit to 1.
     *     Example: Intel X53
     *   - function 0 must set the bit, but the rest function (> 0)
     *     is allowed to leave the bit to 0.
     *     Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
     *
     * So OS (at least Linux) checks the bit of only function 0,
     * and doesn't see the bit of function > 0.
     *
     * The below check allows both interpretation.
     */
    if (PCI_FUNC(dev->devfn)) {
        PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
        if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
            /* function 0 should set multifunction bit */
            error_report("PCI: single function device can't be populated "
                         "in function %x.%x", slot, PCI_FUNC(dev->devfn));
            return -1;
        }
        return 0;
    }

    if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
        return 0;
    }
    /* function 0 indicates single function, so function > 0 must be NULL */
    for (func = 1; func < PCI_FUNC_MAX; ++func) {
        if (bus->devices[PCI_DEVFN(slot, func)]) {
            error_report("PCI: %x.0 indicates single function, "
                         "but %x.%x is already populated.",
                         slot, slot, func);
            return -1;
        }
    }
    return 0;
}

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Isaku Yamahata 已提交
770 771 772 773
static void pci_config_alloc(PCIDevice *pci_dev)
{
    int config_size = pci_config_size(pci_dev);

774 775 776 777 778
    pci_dev->config = g_malloc0(config_size);
    pci_dev->cmask = g_malloc0(config_size);
    pci_dev->wmask = g_malloc0(config_size);
    pci_dev->w1cmask = g_malloc0(config_size);
    pci_dev->used = g_malloc0(config_size);
I
Isaku Yamahata 已提交
779 780 781 782
}

static void pci_config_free(PCIDevice *pci_dev)
{
783 784 785 786 787
    g_free(pci_dev->config);
    g_free(pci_dev->cmask);
    g_free(pci_dev->wmask);
    g_free(pci_dev->w1cmask);
    g_free(pci_dev->used);
I
Isaku Yamahata 已提交
788 789
}

790 791 792 793 794 795 796 797 798
static void do_pci_unregister_device(PCIDevice *pci_dev)
{
    pci_dev->bus->devices[pci_dev->devfn] = NULL;
    pci_config_free(pci_dev);

    address_space_destroy(&pci_dev->bus_master_as);
    memory_region_destroy(&pci_dev->bus_master_enable_region);
}

B
bellard 已提交
799
/* -1 for devfn means auto assign */
P
Paul Brook 已提交
800
static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
801
                                         const char *name, int devfn)
B
bellard 已提交
802
{
803 804 805
    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
    PCIConfigReadFunc *config_read = pc->config_read;
    PCIConfigWriteFunc *config_write = pc->config_write;
806
    AddressSpace *dma_as;
807

B
bellard 已提交
808
    if (devfn < 0) {
809
        for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
810
            devfn += PCI_FUNC_MAX) {
811
            if (!bus->devices[devfn])
B
bellard 已提交
812 813
                goto found;
        }
814
        error_report("PCI: no slot/function available for %s, all in use", name);
815
        return NULL;
B
bellard 已提交
816
    found: ;
817
    } else if (bus->devices[devfn]) {
818 819
        error_report("PCI: slot %d function %d not available for %s, in use by %s",
                     PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
820
        return NULL;
B
bellard 已提交
821
    }
822

823
    pci_dev->bus = bus;
824
    dma_as = pci_device_iommu_address_space(pci_dev);
825

826 827
    memory_region_init_alias(&pci_dev->bus_master_enable_region,
                             OBJECT(pci_dev), "bus master",
828 829
                             dma_as->root, 0, memory_region_size(dma_as->root));
    memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
830 831
    address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region,
                       name);
832

B
bellard 已提交
833 834
    pci_dev->devfn = devfn;
    pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
835
    pci_dev->irq_state = 0;
I
Isaku Yamahata 已提交
836
    pci_config_alloc(pci_dev);
837

838 839 840 841
    pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
    pci_config_set_device_id(pci_dev->config, pc->device_id);
    pci_config_set_revision(pci_dev->config, pc->revision);
    pci_config_set_class(pci_dev->config, pc->class_id);
842

843 844
    if (!pc->is_bridge) {
        if (pc->subsystem_vendor_id || pc->subsystem_id) {
845
            pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
846
                         pc->subsystem_vendor_id);
847
            pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
848
                         pc->subsystem_id);
849 850 851 852 853
        } else {
            pci_set_default_subsystem_id(pci_dev);
        }
    } else {
        /* subsystem_vendor_id/subsystem_id are only for header type 0 */
854 855
        assert(!pc->subsystem_vendor_id);
        assert(!pc->subsystem_id);
856
    }
857
    pci_init_cmask(pci_dev);
858
    pci_init_wmask(pci_dev);
859
    pci_init_w1cmask(pci_dev);
860
    if (pc->is_bridge) {
861
        pci_init_mask_bridge(pci_dev);
862
    }
863
    if (pci_init_multifunction(bus, pci_dev)) {
864
        do_pci_unregister_device(pci_dev);
865 866
        return NULL;
    }
867 868 869 870 871

    if (!config_read)
        config_read = pci_default_read_config;
    if (!config_write)
        config_write = pci_default_write_config;
B
bellard 已提交
872 873
    pci_dev->config_read = config_read;
    pci_dev->config_write = config_write;
874
    bus->devices[devfn] = pci_dev;
J
Juan Quintela 已提交
875
    pci_dev->version_id = 2; /* Current pci device vmstate version */
B
bellard 已提交
876 877 878
    return pci_dev;
}

879 880 881 882 883 884 885
static void pci_unregister_io_regions(PCIDevice *pci_dev)
{
    PCIIORegion *r;
    int i;

    for(i = 0; i < PCI_NUM_REGIONS; i++) {
        r = &pci_dev->io_regions[i];
886
        if (!r->size || r->addr == PCI_BAR_UNMAPPED)
887
            continue;
888
        memory_region_del_subregion(r->address_space, r->memory);
889
    }
A
Alex Williamson 已提交
890 891

    pci_unregister_vga(pci_dev);
892 893
}

894
static int pci_unregister_device(DeviceState *dev)
895
{
896 897
    PCIDevice *pci_dev = PCI_DEVICE(dev);
    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
898 899

    pci_unregister_io_regions(pci_dev);
900
    pci_del_option_rom(pci_dev);
901

902 903 904
    if (pc->exit) {
        pc->exit(pci_dev);
    }
905

906
    do_pci_unregister_device(pci_dev);
907 908 909
    return 0;
}

910 911
void pci_register_bar(PCIDevice *pci_dev, int region_num,
                      uint8_t type, MemoryRegion *memory)
B
bellard 已提交
912 913
{
    PCIIORegion *r;
P
pbrook 已提交
914
    uint32_t addr;
915
    uint64_t wmask;
A
Avi Kivity 已提交
916
    pcibus_t size = memory_region_size(memory);
917

918 919
    assert(region_num >= 0);
    assert(region_num < PCI_NUM_REGIONS);
920 921
    if (size & (size-1)) {
        fprintf(stderr, "ERROR: PCI region size must be pow2 "
922
                    "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
923 924 925
        exit(1);
    }

B
bellard 已提交
926
    r = &pci_dev->io_regions[region_num];
927
    r->addr = PCI_BAR_UNMAPPED;
B
bellard 已提交
928 929
    r->size = size;
    r->type = type;
930
    r->memory = NULL;
931 932

    wmask = ~(size - 1);
933
    addr = pci_bar(pci_dev, region_num);
P
pbrook 已提交
934
    if (region_num == PCI_ROM_SLOT) {
S
Stefan Weil 已提交
935
        /* ROM enable bit is writable */
936
        wmask |= PCI_ROM_ADDRESS_ENABLE;
P
pbrook 已提交
937
    }
938
    pci_set_long(pci_dev->config + addr, type);
I
Isaku Yamahata 已提交
939 940 941 942 943 944 945 946
    if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
        r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
        pci_set_quad(pci_dev->wmask + addr, wmask);
        pci_set_quad(pci_dev->cmask + addr, ~0ULL);
    } else {
        pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
        pci_set_long(pci_dev->cmask + addr, 0xffffffff);
    }
947
    pci_dev->io_regions[region_num].memory = memory;
948
    pci_dev->io_regions[region_num].address_space
A
Avi Kivity 已提交
949
        = type & PCI_BASE_ADDRESS_SPACE_IO
950 951
        ? pci_dev->bus->address_space_io
        : pci_dev->bus->address_space_mem;
952 953
}

A
Alex Williamson 已提交
954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010
static void pci_update_vga(PCIDevice *pci_dev)
{
    uint16_t cmd;

    if (!pci_dev->has_vga) {
        return;
    }

    cmd = pci_get_word(pci_dev->config + PCI_COMMAND);

    memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
                              cmd & PCI_COMMAND_MEMORY);
    memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
                              cmd & PCI_COMMAND_IO);
    memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
                              cmd & PCI_COMMAND_IO);
}

void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
                      MemoryRegion *io_lo, MemoryRegion *io_hi)
{
    assert(!pci_dev->has_vga);

    assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
    pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
    memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem,
                                        QEMU_PCI_VGA_MEM_BASE, mem, 1);

    assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
    pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
    memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
                                        QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);

    assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
    pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
    memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
                                        QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
    pci_dev->has_vga = true;

    pci_update_vga(pci_dev);
}

void pci_unregister_vga(PCIDevice *pci_dev)
{
    if (!pci_dev->has_vga) {
        return;
    }

    memory_region_del_subregion(pci_dev->bus->address_space_mem,
                                pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
    memory_region_del_subregion(pci_dev->bus->address_space_io,
                                pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
    memory_region_del_subregion(pci_dev->bus->address_space_io,
                                pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
    pci_dev->has_vga = false;
}

1011 1012 1013 1014 1015
pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
{
    return pci_dev->io_regions[region_num].addr;
}

1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028
static pcibus_t pci_bar_address(PCIDevice *d,
				int reg, uint8_t type, pcibus_t size)
{
    pcibus_t new_addr, last_addr;
    int bar = pci_bar(d, reg);
    uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);

    if (type & PCI_BASE_ADDRESS_SPACE_IO) {
        if (!(cmd & PCI_COMMAND_IO)) {
            return PCI_BAR_UNMAPPED;
        }
        new_addr = pci_get_long(d->config + bar) & ~(size - 1);
        last_addr = new_addr + size - 1;
1029 1030 1031 1032
        /* Check if 32 bit BAR wraps around explicitly.
         * TODO: make priorities correct and remove this work around.
         */
        if (last_addr <= new_addr || new_addr == 0 || last_addr >= UINT32_MAX) {
1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075
            return PCI_BAR_UNMAPPED;
        }
        return new_addr;
    }

    if (!(cmd & PCI_COMMAND_MEMORY)) {
        return PCI_BAR_UNMAPPED;
    }
    if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
        new_addr = pci_get_quad(d->config + bar);
    } else {
        new_addr = pci_get_long(d->config + bar);
    }
    /* the ROM slot has a specific enable bit */
    if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
        return PCI_BAR_UNMAPPED;
    }
    new_addr &= ~(size - 1);
    last_addr = new_addr + size - 1;
    /* NOTE: we do not support wrapping */
    /* XXX: as we cannot support really dynamic
       mappings, we handle specific values as invalid
       mappings. */
    if (last_addr <= new_addr || new_addr == 0 ||
        last_addr == PCI_BAR_UNMAPPED) {
        return PCI_BAR_UNMAPPED;
    }

    /* Now pcibus_t is 64bit.
     * Check if 32 bit BAR wraps around explicitly.
     * Without this, PC ide doesn't work well.
     * TODO: remove this work around.
     */
    if  (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
        return PCI_BAR_UNMAPPED;
    }

    /*
     * OS is allowed to set BAR beyond its addressable
     * bits. For example, 32 bit OS can set 64bit bar
     * to >4G. Check it. TODO: we might need to support
     * it in the future for e.g. PAE.
     */
A
Avi Kivity 已提交
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    if (last_addr >= HWADDR_MAX) {
1077 1078 1079 1080 1081 1082
        return PCI_BAR_UNMAPPED;
    }

    return new_addr;
}

1083 1084 1085
static void pci_update_mappings(PCIDevice *d)
{
    PCIIORegion *r;
1086
    int i;
1087
    pcibus_t new_addr;
1088

1089
    for(i = 0; i < PCI_NUM_REGIONS; i++) {
1090
        r = &d->io_regions[i];
1091 1092

        /* this region isn't registered */
1093
        if (!r->size)
1094 1095
            continue;

1096
        new_addr = pci_bar_address(d, i, r->type, r->size);
1097 1098

        /* This bar isn't changed */
1099
        if (new_addr == r->addr)
1100 1101 1102 1103
            continue;

        /* now do the real mapping */
        if (r->addr != PCI_BAR_UNMAPPED) {
1104
            memory_region_del_subregion(r->address_space, r->memory);
1105
        }
1106 1107
        r->addr = new_addr;
        if (r->addr != PCI_BAR_UNMAPPED) {
1108 1109
            memory_region_add_subregion_overlap(r->address_space,
                                                r->addr, r->memory, 1);
1110
        }
1111
    }
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1112 1113

    pci_update_vga(d);
1114 1115
}

1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134
static inline int pci_irq_disabled(PCIDevice *d)
{
    return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
}

/* Called after interrupt disabled field update in config space,
 * assert/deassert interrupts if necessary.
 * Gets original interrupt disable bit value (before update). */
static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
{
    int i, disabled = pci_irq_disabled(d);
    if (disabled == was_irq_disabled)
        return;
    for (i = 0; i < PCI_NUM_PINS; ++i) {
        int state = pci_irq_state(d, i);
        pci_change_irq_level(d, i, disabled ? -state : state);
    }
}

1135
uint32_t pci_default_read_config(PCIDevice *d,
1136
                                 uint32_t address, int len)
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1137
{
1138
    uint32_t val = 0;
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1139

1140 1141
    memcpy(&val, d->config + address, len);
    return le32_to_cpu(val);
1142 1143
}

1144
void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1145
{
1146
    int i, was_irq_disabled = pci_irq_disabled(d);
1147

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1148
    for (i = 0; i < l; val >>= 8, ++i) {
1149
        uint8_t wmask = d->wmask[addr + i];
1150 1151
        uint8_t w1cmask = d->w1cmask[addr + i];
        assert(!(wmask & w1cmask));
1152
        d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1153
        d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1154
    }
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    if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1156 1157
        ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
        ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
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1158
        range_covers_byte(addr, l, PCI_COMMAND))
1159
        pci_update_mappings(d);
1160

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1161
    if (range_covers_byte(addr, l, PCI_COMMAND)) {
1162
        pci_update_irq_disabled(d, was_irq_disabled);
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1163 1164 1165 1166
        memory_region_set_enabled(&d->bus_master_enable_region,
                                  pci_get_word(d->config + PCI_COMMAND)
                                    & PCI_COMMAND_MASTER);
    }
1167 1168 1169

    msi_write_config(d, addr, val, l);
    msix_write_config(d, addr, val, l);
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}

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/***********************************************************/
/* generic PCI irq support */
1174

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/* 0 <= irq_num <= 3. level must be 0 or 1 */
1176
static void pci_irq_handler(void *opaque, int irq_num, int level)
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{
1178
    PCIDevice *pci_dev = opaque;
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    int change;
1180

1181
    change = level - pci_irq_state(pci_dev, irq_num);
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1182 1183
    if (!change)
        return;
1184

1185
    pci_set_irq_state(pci_dev, irq_num, level);
1186
    pci_update_irq_status(pci_dev);
1187 1188
    if (pci_irq_disabled(pci_dev))
        return;
1189
    pci_change_irq_level(pci_dev, irq_num, change);
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}

1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209
static inline int pci_intx(PCIDevice *pci_dev)
{
    return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
}

qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
{
    int intx = pci_intx(pci_dev);

    return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
}

void pci_set_irq(PCIDevice *pci_dev, int level)
{
    int intx = pci_intx(pci_dev);
    pci_irq_handler(pci_dev, intx, level);
}

1210 1211 1212
/* Special hooks used by device assignment */
void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
{
1213
    assert(pci_bus_is_root(bus));
1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225
    bus->route_intx_to_irq = route_intx_to_irq;
}

PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
{
    PCIBus *bus;

    do {
         bus = dev->bus;
         pin = bus->map_irq(dev, pin);
         dev = bus->parent_dev;
    } while (dev);
1226 1227

    if (!bus->route_intx_to_irq) {
1228
        error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1229 1230 1231 1232
                     object_get_typename(OBJECT(bus->qbus.parent)));
        return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
    }

1233
    return bus->route_intx_to_irq(bus->irq_opaque, pin);
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}

1236 1237 1238 1239 1240
bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
{
    return old->mode != new->mode || old->irq != new->irq;
}

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1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251
void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
{
    PCIDevice *dev;
    PCIBus *sec;
    int i;

    for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
        dev = bus->devices[i];
        if (dev && dev->intx_routing_notifier) {
            dev->intx_routing_notifier(dev);
        }
1252 1253 1254 1255
    }

    QLIST_FOREACH(sec, &bus->child, sibling) {
        pci_bus_fire_intx_routing_notifier(sec);
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1256 1257 1258 1259 1260 1261 1262
    }
}

void pci_device_set_intx_routing_notifier(PCIDevice *dev,
                                          PCIINTxRoutingNotifier notifier)
{
    dev->intx_routing_notifier = notifier;
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}

1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282
/*
 * PCI-to-PCI bridge specification
 * 9.1: Interrupt routing. Table 9-1
 *
 * the PCI Express Base Specification, Revision 2.1
 * 2.2.8.1: INTx interrutp signaling - Rules
 *          the Implementation Note
 *          Table 2-20
 */
/*
 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
 * 0-origin unlike PCI interrupt pin register.
 */
int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
{
    return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
}

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1283 1284
/***********************************************************/
/* monitor info on PCI */
1285

1286 1287 1288
typedef struct {
    uint16_t class;
    const char *desc;
1289 1290
    const char *fw_name;
    uint16_t fw_ign_bits;
1291 1292
} pci_class_desc;

1293
static const pci_class_desc pci_class_descriptions[] =
1294
{
1295 1296 1297 1298 1299 1300
    { 0x0001, "VGA controller", "display"},
    { 0x0100, "SCSI controller", "scsi"},
    { 0x0101, "IDE controller", "ide"},
    { 0x0102, "Floppy controller", "fdc"},
    { 0x0103, "IPI controller", "ipi"},
    { 0x0104, "RAID controller", "raid"},
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1301 1302 1303
    { 0x0106, "SATA controller"},
    { 0x0107, "SAS controller"},
    { 0x0180, "Storage controller"},
1304 1305 1306 1307
    { 0x0200, "Ethernet controller", "ethernet"},
    { 0x0201, "Token Ring controller", "token-ring"},
    { 0x0202, "FDDI controller", "fddi"},
    { 0x0203, "ATM controller", "atm"},
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    { 0x0280, "Network controller"},
1309
    { 0x0300, "VGA controller", "display", 0x00ff},
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1310 1311 1312
    { 0x0301, "XGA controller"},
    { 0x0302, "3D controller"},
    { 0x0380, "Display controller"},
1313 1314
    { 0x0400, "Video controller", "video"},
    { 0x0401, "Audio controller", "sound"},
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1315
    { 0x0402, "Phone"},
1316
    { 0x0403, "Audio controller", "sound"},
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1317
    { 0x0480, "Multimedia controller"},
1318 1319
    { 0x0500, "RAM controller", "memory"},
    { 0x0501, "Flash controller", "flash"},
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1320
    { 0x0580, "Memory controller"},
1321 1322 1323 1324
    { 0x0600, "Host bridge", "host"},
    { 0x0601, "ISA bridge", "isa"},
    { 0x0602, "EISA bridge", "eisa"},
    { 0x0603, "MC bridge", "mca"},
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    { 0x0604, "PCI bridge", "pci-bridge"},
1326 1327 1328
    { 0x0605, "PCMCIA bridge", "pcmcia"},
    { 0x0606, "NUBUS bridge", "nubus"},
    { 0x0607, "CARDBUS bridge", "cardbus"},
T
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1329 1330
    { 0x0608, "RACEWAY bridge"},
    { 0x0680, "Bridge"},
1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346
    { 0x0700, "Serial port", "serial"},
    { 0x0701, "Parallel port", "parallel"},
    { 0x0800, "Interrupt controller", "interrupt-controller"},
    { 0x0801, "DMA controller", "dma-controller"},
    { 0x0802, "Timer", "timer"},
    { 0x0803, "RTC", "rtc"},
    { 0x0900, "Keyboard", "keyboard"},
    { 0x0901, "Pen", "pen"},
    { 0x0902, "Mouse", "mouse"},
    { 0x0A00, "Dock station", "dock", 0x00ff},
    { 0x0B00, "i386 cpu", "cpu", 0x00ff},
    { 0x0c00, "Fireware contorller", "fireware"},
    { 0x0c01, "Access bus controller", "access-bus"},
    { 0x0c02, "SSA controller", "ssa"},
    { 0x0c03, "USB controller", "usb"},
    { 0x0c04, "Fibre channel controller", "fibre-channel"},
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1347
    { 0x0c05, "SMBus"},
1348 1349 1350
    { 0, NULL}
};

1351
static void pci_for_each_device_under_bus(PCIBus *bus,
1352 1353 1354
                                          void (*fn)(PCIBus *b, PCIDevice *d,
                                                     void *opaque),
                                          void *opaque)
1355
{
1356 1357
    PCIDevice *d;
    int devfn;
1358

1359 1360 1361
    for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
        d = bus->devices[devfn];
        if (d) {
1362
            fn(bus, d, opaque);
1363 1364 1365 1366 1367
        }
    }
}

void pci_for_each_device(PCIBus *bus, int bus_num,
1368 1369
                         void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
                         void *opaque)
1370
{
1371
    bus = pci_find_bus_nr(bus, bus_num);
1372 1373

    if (bus) {
1374
        pci_for_each_device_under_bus(bus, fn, opaque);
1375 1376 1377
    }
}

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1378
static const pci_class_desc *get_class_desc(int class)
1379
{
L
Luiz Capitulino 已提交
1380
    const pci_class_desc *desc;
1381

L
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1382 1383 1384
    desc = pci_class_descriptions;
    while (desc->desc && class != desc->class) {
        desc++;
1385
    }
1386

L
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1387 1388
    return desc;
}
I
Isaku Yamahata 已提交
1389

L
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1390
static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
1391

L
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1392 1393 1394 1395
static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
{
    PciMemoryRegionList *head = NULL, *cur_item = NULL;
    int i;
1396

L
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1397 1398 1399 1400 1401 1402
    for (i = 0; i < PCI_NUM_REGIONS; i++) {
        const PCIIORegion *r = &dev->io_regions[i];
        PciMemoryRegionList *region;

        if (!r->size) {
            continue;
P
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1403
        }
1404

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1405 1406
        region = g_malloc0(sizeof(*region));
        region->value = g_malloc0(sizeof(*region->value));
1407

L
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1408 1409 1410 1411 1412 1413 1414 1415
        if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
            region->value->type = g_strdup("io");
        } else {
            region->value->type = g_strdup("memory");
            region->value->has_prefetch = true;
            region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
            region->value->has_mem_type_64 = true;
            region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
1416
        }
1417

L
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1418 1419 1420
        region->value->bar = i;
        region->value->address = r->addr;
        region->value->size = r->size;
1421

L
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1422 1423 1424 1425 1426 1427
        /* XXX: waiting for the qapi to support GSList */
        if (!cur_item) {
            head = cur_item = region;
        } else {
            cur_item->next = region;
            cur_item = region;
1428
        }
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1429
    }
1430

L
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1431
    return head;
1432 1433
}

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1434 1435
static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
                                           int bus_num)
1436
{
L
Luiz Capitulino 已提交
1437
    PciBridgeInfo *info;
1438

L
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1439
    info = g_malloc0(sizeof(*info));
1440

L
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1441 1442 1443
    info->bus.number = dev->config[PCI_PRIMARY_BUS];
    info->bus.secondary = dev->config[PCI_SECONDARY_BUS];
    info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS];
1444

L
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1445 1446 1447
    info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range));
    info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
    info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
1448

L
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1449 1450 1451
    info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range));
    info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
    info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1452

L
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1453 1454 1455
    info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range));
    info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
    info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1456

L
Luiz Capitulino 已提交
1457
    if (dev->config[PCI_SECONDARY_BUS] != 0) {
1458
        PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
L
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1459 1460 1461 1462
        if (child_bus) {
            info->has_devices = true;
            info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
        }
1463 1464
    }

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1465
    return info;
1466 1467
}

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1468 1469
static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
                                           int bus_num)
1470
{
L
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1471 1472
    const pci_class_desc *desc;
    PciDeviceInfo *info;
1473
    uint8_t type;
L
Luiz Capitulino 已提交
1474
    int class;
1475

L
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1476 1477 1478 1479 1480 1481
    info = g_malloc0(sizeof(*info));
    info->bus = bus_num;
    info->slot = PCI_SLOT(dev->devfn);
    info->function = PCI_FUNC(dev->devfn);

    class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1482
    info->class_info.q_class = class;
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1483 1484 1485 1486 1487 1488 1489 1490 1491 1492
    desc = get_class_desc(class);
    if (desc->desc) {
        info->class_info.has_desc = true;
        info->class_info.desc = g_strdup(desc->desc);
    }

    info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
    info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID);
    info->regions = qmp_query_pci_regions(dev);
    info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
1493 1494

    if (dev->config[PCI_INTERRUPT_PIN] != 0) {
L
Luiz Capitulino 已提交
1495 1496
        info->has_irq = true;
        info->irq = dev->config[PCI_INTERRUPT_LINE];
1497 1498
    }

1499 1500
    type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
    if (type == PCI_HEADER_TYPE_BRIDGE) {
L
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1501 1502
        info->has_pci_bridge = true;
        info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
1503 1504
    }

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1505
    return info;
1506 1507
}

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1508
static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
1509
{
L
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1510
    PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
1511
    PCIDevice *dev;
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1512
    int devfn;
1513 1514 1515 1516

    for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
        dev = bus->devices[devfn];
        if (dev) {
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1517 1518 1519 1520 1521 1522 1523 1524 1525 1526
            info = g_malloc0(sizeof(*info));
            info->value = qmp_query_pci_device(dev, bus, bus_num);

            /* XXX: waiting for the qapi to support GSList */
            if (!cur_item) {
                head = cur_item = info;
            } else {
                cur_item->next = info;
                cur_item = info;
            }
1527
        }
1528
    }
1529

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1530
    return head;
1531 1532
}

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1533
static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1534
{
L
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1535 1536
    PciInfo *info = NULL;

1537
    bus = pci_find_bus_nr(bus, bus_num);
P
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1538
    if (bus) {
L
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1539 1540 1541
        info = g_malloc0(sizeof(*info));
        info->bus = bus_num;
        info->devices = qmp_query_pci_devices(bus, bus_num);
B
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1542
    }
1543

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1544
    return info;
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1545 1546
}

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1547
PciInfoList *qmp_query_pci(Error **errp)
B
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1548
{
L
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1549
    PciInfoList *info, *head = NULL, *cur_item = NULL;
1550
    PCIHostState *host_bridge;
1551

1552
    QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
L
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1553
        info = g_malloc0(sizeof(*info));
1554
        info->value = qmp_query_pci_bus(host_bridge->bus, 0);
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1555 1556 1557 1558 1559 1560 1561

        /* XXX: waiting for the qapi to support GSList */
        if (!cur_item) {
            head = cur_item = info;
        } else {
            cur_item->next = info;
            cur_item = info;
1562
        }
1563
    }
1564

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1565
    return head;
B
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1566
}
1567

1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579
static const char * const pci_nic_models[] = {
    "ne2k_pci",
    "i82551",
    "i82557b",
    "i82559er",
    "rtl8139",
    "e1000",
    "pcnet",
    "virtio",
    NULL
};

P
Paul Brook 已提交
1580 1581 1582 1583 1584 1585 1586 1587
static const char * const pci_nic_names[] = {
    "ne2k_pci",
    "i82551",
    "i82557b",
    "i82559er",
    "rtl8139",
    "e1000",
    "pcnet",
P
Paul Brook 已提交
1588
    "virtio-net-pci",
1589 1590 1591
    NULL
};

1592
/* Initialize a PCI NIC.  */
1593
/* FIXME callers should check for failure, but don't */
1594 1595
PCIDevice *pci_nic_init(NICInfo *nd, PCIBus *rootbus,
                        const char *default_model,
1596
                        const char *default_devaddr)
1597
{
1598
    const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1599 1600
    PCIBus *bus;
    int devfn;
1601
    PCIDevice *pci_dev;
P
Paul Brook 已提交
1602
    DeviceState *dev;
1603 1604
    int i;

1605 1606 1607 1608
    i = qemu_find_nic_model(nd, pci_nic_models, default_model);
    if (i < 0)
        return NULL;

1609
    bus = pci_get_bus_devfn(&devfn, rootbus, devaddr);
1610
    if (!bus) {
1611 1612
        error_report("Invalid PCI device address %s for device %s",
                     devaddr, pci_nic_names[i]);
1613 1614 1615
        return NULL;
    }

1616
    pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1617
    dev = &pci_dev->qdev;
G
Gerd Hoffmann 已提交
1618
    qdev_set_nic_properties(dev, nd);
1619 1620
    if (qdev_init(dev) < 0)
        return NULL;
1621
    return pci_dev;
1622 1623
}

1624 1625
PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
                               const char *default_model,
1626 1627 1628 1629 1630 1631 1632
                               const char *default_devaddr)
{
    PCIDevice *res;

    if (qemu_show_nic_models(nd->model, pci_nic_models))
        exit(0);

1633
    res = pci_nic_init(nd, rootbus, default_model, default_devaddr);
1634 1635 1636 1637 1638
    if (!res)
        exit(1);
    return res;
}

1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656
PCIDevice *pci_vga_init(PCIBus *bus)
{
    switch (vga_interface_type) {
    case VGA_CIRRUS:
        return pci_create_simple(bus, -1, "cirrus-vga");
    case VGA_QXL:
        return pci_create_simple(bus, -1, "qxl-vga");
    case VGA_STD:
        return pci_create_simple(bus, -1, "VGA");
    case VGA_VMWARE:
        return pci_create_simple(bus, -1, "vmware-svga");
    case VGA_NONE:
    default: /* Other non-PCI types. Checking for unsupported types is already
                done in vl.c. */
        return NULL;
    }
}

1657 1658 1659 1660 1661 1662 1663 1664 1665 1666
/* Whether a given bus number is in range of the secondary
 * bus of the given bridge device. */
static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
{
    return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
             PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
        dev->config[PCI_SECONDARY_BUS] < bus_num &&
        bus_num <= dev->config[PCI_SUBORDINATE_BUS];
}

1667
static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
1668
{
I
Isaku Yamahata 已提交
1669
    PCIBus *sec;
1670

I
Isaku Yamahata 已提交
1671
    if (!bus) {
1672
        return NULL;
I
Isaku Yamahata 已提交
1673
    }
1674

1675 1676 1677 1678
    if (pci_bus_num(bus) == bus_num) {
        return bus;
    }

1679
    /* Consider all bus numbers in range for the host pci bridge. */
1680
    if (!pci_bus_is_root(bus) &&
1681 1682 1683 1684
        !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
        return NULL;
    }

1685
    /* try child bus */
1686 1687
    for (; bus; bus = sec) {
        QLIST_FOREACH(sec, &bus->child, sibling) {
1688
            assert(!pci_bus_is_root(sec));
1689 1690 1691 1692 1693
            if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
                return sec;
            }
            if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
                break;
B
Blue Swirl 已提交
1694
            }
1695 1696 1697 1698
        }
    }

    return NULL;
1699 1700
}

1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728
void pci_for_each_bus_depth_first(PCIBus *bus,
                                  void *(*begin)(PCIBus *bus, void *parent_state),
                                  void (*end)(PCIBus *bus, void *state),
                                  void *parent_state)
{
    PCIBus *sec;
    void *state;

    if (!bus) {
        return;
    }

    if (begin) {
        state = begin(bus, parent_state);
    } else {
        state = parent_state;
    }

    QLIST_FOREACH(sec, &bus->child, sibling) {
        pci_for_each_bus_depth_first(sec, begin, end, state);
    }

    if (end) {
        end(bus, state);
    }
}


1729
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1730
{
1731
    bus = pci_find_bus_nr(bus, bus_num);
1732 1733 1734 1735

    if (!bus)
        return NULL;

1736
    return bus->devices[devfn];
1737 1738
}

A
Anthony Liguori 已提交
1739
static int pci_qdev_init(DeviceState *qdev)
P
Paul Brook 已提交
1740 1741
{
    PCIDevice *pci_dev = (PCIDevice *)qdev;
1742
    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
P
Paul Brook 已提交
1743
    PCIBus *bus;
1744
    int rc;
1745
    bool is_default_rom;
P
Paul Brook 已提交
1746

I
Isaku Yamahata 已提交
1747
    /* initialize cap_present for pci_is_express() and pci_config_size() */
1748
    if (pc->is_express) {
I
Isaku Yamahata 已提交
1749 1750 1751
        pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
    }

A
Andreas Färber 已提交
1752
    bus = PCI_BUS(qdev_get_parent_bus(qdev));
A
Anthony Liguori 已提交
1753 1754 1755
    pci_dev = do_pci_register_device(pci_dev, bus,
                                     object_get_typename(OBJECT(qdev)),
                                     pci_dev->devfn);
1756 1757
    if (pci_dev == NULL)
        return -1;
1758

1759 1760
    if (pc->init) {
        rc = pc->init(pci_dev);
1761 1762 1763 1764
        if (rc != 0) {
            do_pci_unregister_device(pci_dev);
            return rc;
        }
1765
    }
1766 1767

    /* rom loading */
1768
    is_default_rom = false;
1769 1770
    if (pci_dev->romfile == NULL && pc->romfile != NULL) {
        pci_dev->romfile = g_strdup(pc->romfile);
1771 1772 1773
        is_default_rom = true;
    }
    pci_add_option_rom(pci_dev, is_default_rom);
1774

G
Gerd Hoffmann 已提交
1775 1776 1777
    return 0;
}

1778 1779
PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
                                    const char *name)
P
Paul Brook 已提交
1780 1781 1782
{
    DeviceState *dev;

P
Paul Brook 已提交
1783
    dev = qdev_create(&bus->qbus, name);
1784
    qdev_prop_set_int32(dev, "addr", devfn);
1785
    qdev_prop_set_bit(dev, "multifunction", multifunction);
1786
    return PCI_DEVICE(dev);
1787
}
P
Paul Brook 已提交
1788

1789 1790 1791
PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
                                           bool multifunction,
                                           const char *name)
1792
{
1793
    PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
M
Markus Armbruster 已提交
1794
    qdev_init_nofail(&dev->qdev);
1795
    return dev;
P
Paul Brook 已提交
1796
}
1797

1798 1799 1800 1801 1802 1803 1804 1805 1806 1807
PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
{
    return pci_create_multifunction(bus, devfn, false, name);
}

PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
{
    return pci_create_simple_multifunction(bus, devfn, false, name);
}

1808
static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
1809 1810 1811
{
    int offset = PCI_CONFIG_HEADER_SIZE;
    int i;
1812
    for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
1813 1814 1815 1816
        if (pdev->used[i])
            offset = i + 1;
        else if (i - offset + 1 == size)
            return offset;
1817
    }
1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838
    return 0;
}

static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
                                        uint8_t *prev_p)
{
    uint8_t next, prev;

    if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
        return 0;

    for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
         prev = next + PCI_CAP_LIST_NEXT)
        if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
            break;

    if (prev_p)
        *prev_p = prev;
    return next;
}

1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857
static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
{
    uint8_t next, prev, found = 0;

    if (!(pdev->used[offset])) {
        return 0;
    }

    assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);

    for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
         prev = next + PCI_CAP_LIST_NEXT) {
        if (next <= offset && next > found) {
            found = next;
        }
    }
    return found;
}

1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913
/* Patch the PCI vendor and device ids in a PCI rom image if necessary.
   This is needed for an option rom which is used for more than one device. */
static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
{
    uint16_t vendor_id;
    uint16_t device_id;
    uint16_t rom_vendor_id;
    uint16_t rom_device_id;
    uint16_t rom_magic;
    uint16_t pcir_offset;
    uint8_t checksum;

    /* Words in rom data are little endian (like in PCI configuration),
       so they can be read / written with pci_get_word / pci_set_word. */

    /* Only a valid rom will be patched. */
    rom_magic = pci_get_word(ptr);
    if (rom_magic != 0xaa55) {
        PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
        return;
    }
    pcir_offset = pci_get_word(ptr + 0x18);
    if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
        PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
        return;
    }

    vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
    device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
    rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
    rom_device_id = pci_get_word(ptr + pcir_offset + 6);

    PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
                vendor_id, device_id, rom_vendor_id, rom_device_id);

    checksum = ptr[6];

    if (vendor_id != rom_vendor_id) {
        /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
        checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
        checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
        PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
        ptr[6] = checksum;
        pci_set_word(ptr + pcir_offset + 4, vendor_id);
    }

    if (device_id != rom_device_id) {
        /* Patch device id and checksum (at offset 6 for etherboot roms). */
        checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
        checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
        PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
        ptr[6] = checksum;
        pci_set_word(ptr + pcir_offset + 6, device_id);
    }
}

1914
/* Add an option rom for the device */
1915
static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1916 1917 1918 1919
{
    int size;
    char *path;
    void *ptr;
1920
    char name[32];
A
Anthony Liguori 已提交
1921
    const VMStateDescription *vmsd;
1922

1923 1924 1925 1926 1927
    if (!pdev->romfile)
        return 0;
    if (strlen(pdev->romfile) == 0)
        return 0;

1928 1929 1930 1931 1932 1933 1934 1935 1936
    if (!pdev->rom_bar) {
        /*
         * Load rom via fw_cfg instead of creating a rom bar,
         * for 0.11 compatibility.
         */
        int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
        if (class == 0x0300) {
            rom_add_vga(pdev->romfile);
        } else {
G
Gleb Natapov 已提交
1937
            rom_add_option(pdev->romfile, -1);
1938 1939 1940 1941
        }
        return 0;
    }

1942
    path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1943
    if (path == NULL) {
1944
        path = g_strdup(pdev->romfile);
1945 1946 1947
    }

    size = get_image_size(path);
1948
    if (size < 0) {
1949
        error_report("%s: failed to find romfile \"%s\"",
S
Stefan Hajnoczi 已提交
1950 1951 1952 1953 1954 1955
                     __func__, pdev->romfile);
        g_free(path);
        return -1;
    } else if (size == 0) {
        error_report("%s: ignoring empty romfile \"%s\"",
                     __func__, pdev->romfile);
1956
        g_free(path);
1957 1958
        return -1;
    }
1959 1960 1961 1962
    if (size & (size - 1)) {
        size = 1 << qemu_fls(size);
    }

A
Anthony Liguori 已提交
1963 1964 1965 1966 1967
    vmsd = qdev_get_vmsd(DEVICE(pdev));

    if (vmsd) {
        snprintf(name, sizeof(name), "%s.rom", vmsd->name);
    } else {
1968
        snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
A
Anthony Liguori 已提交
1969
    }
A
Avi Kivity 已提交
1970
    pdev->has_rom = true;
1971
    memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size);
1972
    vmstate_register_ram(&pdev->rom, &pdev->qdev);
A
Avi Kivity 已提交
1973
    ptr = memory_region_get_ram_ptr(&pdev->rom);
1974
    load_image(path, ptr);
1975
    g_free(path);
1976

1977 1978 1979 1980 1981
    if (is_default_rom) {
        /* Only the default rom images will be patched (if needed). */
        pci_patch_ids(pdev, ptr, size);
    }

1982
    pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
1983 1984 1985 1986

    return 0;
}

1987 1988
static void pci_del_option_rom(PCIDevice *pdev)
{
A
Avi Kivity 已提交
1989
    if (!pdev->has_rom)
1990 1991
        return;

1992
    vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
A
Avi Kivity 已提交
1993 1994
    memory_region_destroy(&pdev->rom);
    pdev->has_rom = false;
1995 1996
}

1997 1998 1999 2000 2001 2002 2003 2004 2005
/*
 * if !offset
 * Reserve space and add capability to the linked list in pci config space
 *
 * if offset = 0,
 * Find and reserve space and add capability to the linked list
 * in pci config space */
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
                       uint8_t offset, uint8_t size)
2006
{
2007
    uint8_t *config;
2008 2009
    int i, overlapping_cap;

2010 2011 2012 2013 2014
    if (!offset) {
        offset = pci_find_space(pdev, size);
        if (!offset) {
            return -ENOSPC;
        }
2015 2016 2017 2018 2019 2020 2021 2022
    } else {
        /* Verify that capabilities don't overlap.  Note: device assignment
         * depends on this check to verify that the device is not broken.
         * Should never trigger for emulated devices, but it's helpful
         * for debugging these. */
        for (i = offset; i < offset + size; i++) {
            overlapping_cap = pci_find_capability_at_offset(pdev, i);
            if (overlapping_cap) {
2023
                fprintf(stderr, "ERROR: %s:%02x:%02x.%x "
2024 2025
                        "Attempt to add PCI capability %x at offset "
                        "%x overlaps existing capability %x at offset %x\n",
2026
                        pci_root_bus_path(pdev), pci_bus_num(pdev->bus),
2027 2028 2029 2030 2031
                        PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
                        cap_id, offset, overlapping_cap, i);
                return -EINVAL;
            }
        }
2032 2033 2034
    }

    config = pdev->config + offset;
2035 2036 2037 2038
    config[PCI_CAP_LIST_ID] = cap_id;
    config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
    pdev->config[PCI_CAPABILITY_LIST] = offset;
    pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
2039
    memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
2040 2041
    /* Make capability read-only by default */
    memset(pdev->wmask + offset, 0, size);
2042 2043
    /* Check capability by default */
    memset(pdev->cmask + offset, 0xFF, size);
2044 2045 2046 2047 2048 2049 2050 2051 2052 2053
    return offset;
}

/* Unlink capability from the pci config space. */
void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
{
    uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
    if (!offset)
        return;
    pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
S
Stefan Weil 已提交
2054
    /* Make capability writable again */
2055
    memset(pdev->wmask + offset, 0xff, size);
2056
    memset(pdev->w1cmask + offset, 0, size);
2057 2058
    /* Clear cmask as device-specific registers can't be checked */
    memset(pdev->cmask + offset, 0, size);
2059
    memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
2060 2061 2062 2063 2064 2065 2066 2067 2068

    if (!pdev->config[PCI_CAPABILITY_LIST])
        pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
}

uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
{
    return pci_find_capability_list(pdev, cap_id, NULL);
}
2069 2070 2071 2072 2073 2074 2075 2076 2077

static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
{
    PCIDevice *d = (PCIDevice *)dev;
    const pci_class_desc *desc;
    char ctxt[64];
    PCIIORegion *r;
    int i, class;

2078
    class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089
    desc = pci_class_descriptions;
    while (desc->desc && class != desc->class)
        desc++;
    if (desc->desc) {
        snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
    } else {
        snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
    }

    monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
                   "pci id %04x:%04x (sub %04x:%04x)\n",
2090
                   indent, "", ctxt, pci_bus_num(d->bus),
2091
                   PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
2092 2093 2094 2095
                   pci_get_word(d->config + PCI_VENDOR_ID),
                   pci_get_word(d->config + PCI_DEVICE_ID),
                   pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
                   pci_get_word(d->config + PCI_SUBSYSTEM_ID));
2096 2097 2098 2099
    for (i = 0; i < PCI_NUM_REGIONS; i++) {
        r = &d->io_regions[i];
        if (!r->size)
            continue;
2100 2101 2102
        monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
                       " [0x%"FMT_PCIBUS"]\n",
                       indent, "",
2103
                       i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
2104 2105 2106
                       r->addr, r->addr + r->size - 1);
    }
}
G
Gerd Hoffmann 已提交
2107

2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146
static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
{
    PCIDevice *d = (PCIDevice *)dev;
    const char *name = NULL;
    const pci_class_desc *desc =  pci_class_descriptions;
    int class = pci_get_word(d->config + PCI_CLASS_DEVICE);

    while (desc->desc &&
          (class & ~desc->fw_ign_bits) !=
          (desc->class & ~desc->fw_ign_bits)) {
        desc++;
    }

    if (desc->desc) {
        name = desc->fw_name;
    }

    if (name) {
        pstrcpy(buf, len, name);
    } else {
        snprintf(buf, len, "pci%04x,%04x",
                 pci_get_word(d->config + PCI_VENDOR_ID),
                 pci_get_word(d->config + PCI_DEVICE_ID));
    }

    return buf;
}

static char *pcibus_get_fw_dev_path(DeviceState *dev)
{
    PCIDevice *d = (PCIDevice *)dev;
    char path[50], name[33];
    int off;

    off = snprintf(path, sizeof(path), "%s@%x",
                   pci_dev_fw_name(dev, name, sizeof name),
                   PCI_SLOT(d->devfn));
    if (PCI_FUNC(d->devfn))
        snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2147
    return g_strdup(path);
2148 2149
}

2150 2151
static char *pcibus_get_dev_path(DeviceState *dev)
{
2152 2153 2154 2155 2156 2157 2158 2159
    PCIDevice *d = container_of(dev, PCIDevice, qdev);
    PCIDevice *t;
    int slot_depth;
    /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
     * 00 is added here to make this format compatible with
     * domain:Bus:Slot.Func for systems without nested PCI bridges.
     * Slot.Function list specifies the slot and function numbers for all
     * devices on the path from root to the specific device. */
2160 2161
    const char *root_bus_path;
    int root_bus_len;
M
Michael S. Tsirkin 已提交
2162 2163
    char slot[] = ":SS.F";
    int slot_len = sizeof slot - 1 /* For '\0' */;
2164 2165
    int path_len;
    char *path, *p;
M
Michael S. Tsirkin 已提交
2166
    int s;
2167

2168 2169 2170
    root_bus_path = pci_root_bus_path(d);
    root_bus_len = strlen(root_bus_path);

2171 2172 2173 2174 2175 2176
    /* Calculate # of slots on path between device and root. */;
    slot_depth = 0;
    for (t = d; t; t = t->bus->parent_dev) {
        ++slot_depth;
    }

2177
    path_len = root_bus_len + slot_len * slot_depth;
2178 2179

    /* Allocate memory, fill in the terminating null byte. */
2180
    path = g_malloc(path_len + 1 /* For '\0' */);
2181 2182
    path[path_len] = '\0';

2183
    memcpy(path, root_bus_path, root_bus_len);
2184 2185 2186 2187 2188 2189

    /* Fill in slot numbers. We walk up from device to root, so need to print
     * them in the reverse order, last to first. */
    p = path + path_len;
    for (t = d; t; t = t->bus->parent_dev) {
        p -= slot_len;
M
Michael S. Tsirkin 已提交
2190
        s = snprintf(slot, sizeof slot, ":%02x.%x",
2191
                     PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
M
Michael S. Tsirkin 已提交
2192 2193
        assert(s == slot_len);
        memcpy(p, slot, slot_len);
2194 2195 2196
    }

    return path;
2197 2198
}

2199 2200 2201 2202 2203 2204 2205 2206 2207
static int pci_qdev_find_recursive(PCIBus *bus,
                                   const char *id, PCIDevice **pdev)
{
    DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
    if (!qdev) {
        return -ENODEV;
    }

    /* roughly check if given qdev is pci device */
A
Anthony Liguori 已提交
2208
    if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
2209
        *pdev = PCI_DEVICE(qdev);
2210 2211 2212 2213 2214 2215 2216
        return 0;
    }
    return -EINVAL;
}

int pci_qdev_find_device(const char *id, PCIDevice **pdev)
{
2217
    PCIHostState *host_bridge;
2218 2219
    int rc = -ENODEV;

2220 2221
    QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
        int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232
        if (!tmp) {
            rc = 0;
            break;
        }
        if (tmp != -ENODEV) {
            rc = tmp;
        }
    }

    return rc;
}
A
Avi Kivity 已提交
2233 2234 2235 2236 2237

MemoryRegion *pci_address_space(PCIDevice *dev)
{
    return dev->bus->address_space_mem;
}
2238 2239 2240 2241 2242

MemoryRegion *pci_address_space_io(PCIDevice *dev)
{
    return dev->bus->address_space_io;
}
2243

2244 2245 2246 2247 2248
static void pci_device_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *k = DEVICE_CLASS(klass);
    k->init = pci_qdev_init;
    k->exit = pci_unregister_device;
2249
    k->bus_type = TYPE_PCI_BUS;
2250
    k->props = pci_props;
2251 2252
}

2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269
AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
{
    PCIBus *bus = PCI_BUS(dev->bus);

    if (bus->iommu_fn) {
        return bus->iommu_fn(bus, bus->iommu_opaque, dev->devfn);
    }

    if (bus->parent_dev) {
        /** We are ignoring the bus master DMA bit of the bridge
         *  as it would complicate things such as VFIO for no good reason */
        return pci_device_iommu_address_space(bus->parent_dev);
    }

    return &address_space_memory;
}

2270
void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque)
2271
{
2272 2273
    bus->iommu_fn = fn;
    bus->iommu_opaque = opaque;
2274 2275
}

2276 2277 2278 2279 2280
static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
{
    Range *range = opaque;
    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
    uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
2281
    int i;
2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299

    if (!(cmd & PCI_COMMAND_MEMORY)) {
        return;
    }

    if (pc->is_bridge) {
        pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
        pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);

        base = MAX(base, 0x1ULL << 32);

        if (limit >= base) {
            Range pref_range;
            pref_range.begin = base;
            pref_range.end = limit + 1;
            range_extend(range, &pref_range);
        }
    }
2300 2301
    for (i = 0; i < PCI_NUM_REGIONS; ++i) {
        PCIIORegion *r = &dev->io_regions[i];
2302 2303
        Range region_range;

2304 2305 2306 2307 2308 2309 2310 2311 2312
        if (!r->size ||
            (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
            !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
            continue;
        }
        region_range.begin = pci_bar_address(dev, i, r->type, r->size);
        region_range.end = region_range.begin + r->size;

        if (region_range.begin == PCI_BAR_UNMAPPED) {
2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329
            continue;
        }

        region_range.begin = MAX(region_range.begin, 0x1ULL << 32);

        if (region_range.end - 1 >= region_range.begin) {
            range_extend(range, &region_range);
        }
    }
}

void pci_bus_get_w64_range(PCIBus *bus, Range *range)
{
    range->begin = range->end = 0;
    pci_for_each_device_under_bus(bus, pci_dev_get_w64, range);
}

2330
static const TypeInfo pci_device_type_info = {
2331 2332 2333 2334 2335
    .name = TYPE_PCI_DEVICE,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .abstract = true,
    .class_size = sizeof(PCIDeviceClass),
2336
    .class_init = pci_device_class_init,
2337 2338
};

A
Andreas Färber 已提交
2339
static void pci_register_types(void)
2340
{
2341
    type_register_static(&pci_bus_info);
2342
    type_register_static(&pcie_bus_info);
2343 2344 2345
    type_register_static(&pci_device_type_info);
}

A
Andreas Färber 已提交
2346
type_init(pci_register_types)