提交 d98f08f5 编写于 作者: M Marcel Apfelbaum 提交者: Michael S. Tsirkin

hw/pci: add pci wrappers for allocating and asserting irqs

Interrupt pin is selected and saved into PCI_INTERRUPT_PIN
register during device initialization. Devices should not call
directly qemu_set_irq and specify the INTx pin on each call.

Added pci_* wrappers to replace qemu_set_irq, qemu_irq_raise,
qemu_irq_lower and qemu_irq_pulse, setting the irq
based on PCI_INTERRUPT_PIN.

Added pci_allocate_irq wrapper to be used by devices that
still need PCIDevice infrastructure to assert irqs.

Renamed a static method which was named already pci_set_irq.
Signed-off-by: NMarcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
上级 a8a9d30b
master openEuler-20.03-LTS openEuler-20.09 openEuler-RISCV stable-1.7 stable-2.0 stable-2.1 stable-2.10 stable-2.11 stable-2.12 stable-2.2 stable-2.3 stable-2.4 stable-2.5 stable-2.6 stable-2.7 stable-2.8 stable-2.9 stable-3.0 stable-3.1 stable-4.0 stable-4.1 stable-4.2 v5.1.0-rc2 v5.1.0-rc1 v5.1.0-rc0 v5.0.0 v5.0.0-rc4 v5.0.0-rc3 v5.0.0-rc2 v5.0.0-rc1 v5.0.0-rc0 v4.2.1 v4.2.0 v4.2.0-rc5 v4.2.0-rc4 v4.2.0-rc3 v4.2.0-rc2 v4.2.0-rc1 v4.2.0-rc0 v4.1.1 v4.1.0 v4.1.0-rc5 v4.1.0-rc4 v4.1.0-rc3 v4.1.0-rc2 v4.1.0-rc1 v4.1.0-rc0 v4.0.1 v4.0.0 v4.0.0-rc4 v4.0.0-rc3 v4.0.0-rc2 v4.0.0-rc1 v4.0.0-rc0 v3.1.1.1 v3.1.1 v3.1.0 v3.1.0-rc5 v3.1.0-rc4 v3.1.0-rc3 v3.1.0-rc2 v3.1.0-rc1 v3.1.0-rc0 v3.0.1 v3.0.0 v3.0.0-rc4 v3.0.0-rc3 v3.0.0-rc2 v3.0.0-rc1 v3.0.0-rc0 v2.12.1 v2.12.0 v2.12.0-rc4 v2.12.0-rc3 v2.12.0-rc2 v2.12.0-rc1 v2.12.0-rc0 v2.11.2 v2.11.1 v2.11.0 v2.11.0-rc5 v2.11.0-rc4 v2.11.0-rc3 v2.11.0-rc2 v2.11.0-rc1 v2.11.0-rc0 v2.10.2 v2.10.1 v2.10.0 v2.10.0-rc4 v2.10.0-rc3 v2.10.0-rc2 v2.10.0-rc1 v2.10.0-rc0 v2.9.1 v2.9.0 v2.9.0-rc5 v2.9.0-rc4 v2.9.0-rc3 v2.9.0-rc2 v2.9.0-rc1 v2.9.0-rc0 v2.8.1.1 v2.8.1 v2.8.0 v2.8.0-rc4 v2.8.0-rc3 v2.8.0-rc2 v2.8.0-rc1 v2.8.0-rc0 v2.7.1 v2.7.0 v2.7.0-rc5 v2.7.0-rc4 v2.7.0-rc3 v2.7.0-rc2 v2.7.0-rc1 v2.7.0-rc0 v2.6.2 v2.6.1 v2.6.0 v2.6.0-rc5 v2.6.0-rc4 v2.6.0-rc3 v2.6.0-rc2 v2.6.0-rc1 v2.6.0-rc0 v2.5.1.1 v2.5.1 v2.5.0 v2.5.0-rc4 v2.5.0-rc3 v2.5.0-rc2 v2.5.0-rc1 v2.5.0-rc0 v2.4.1 v2.4.0.1 v2.4.0 v2.4.0-rc4 v2.4.0-rc3 v2.4.0-rc2 v2.4.0-rc1 v2.4.0-rc0 v2.3.1 v2.3.0 v2.3.0-rc4 v2.3.0-rc3 v2.3.0-rc2 v2.3.0-rc1 v2.3.0-rc0 v2.2.1 v2.2.0 v2.2.0-rc5 v2.2.0-rc4 v2.2.0-rc3 v2.2.0-rc2 v2.2.0-rc1 v2.2.0-rc0 v2.1.3 v2.1.2 v2.1.1 v2.1.0 v2.1.0-rc5 v2.1.0-rc4 v2.1.0-rc3 v2.1.0-rc2 v2.1.0-rc1 v2.1.0-rc0 v2.0.2 v2.0.1 v2.0.0 v2.0.0-rc3 v2.0.0-rc2 v2.0.0-rc1 v2.0.0-rc0 v1.7.2 v1.7.1 v1.7.0 v1.7.0-rc2 v1.7.0-rc1 v1.7.0-rc0
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......@@ -83,7 +83,7 @@ static const TypeInfo pcie_bus_info = {
static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
static void pci_update_mappings(PCIDevice *d);
static void pci_set_irq(void *opaque, int irq_num, int level);
static void pci_irq_handler(void *opaque, int irq_num, int level);
static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
static void pci_del_option_rom(PCIDevice *pdev);
......@@ -161,7 +161,7 @@ void pci_device_deassert_intx(PCIDevice *dev)
{
int i;
for (i = 0; i < PCI_NUM_PINS; ++i) {
qemu_set_irq(dev->irq[i], 0);
pci_irq_handler(dev, i, 0);
}
}
......@@ -889,7 +889,7 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
pci_dev->config_read = config_read;
pci_dev->config_write = config_write;
bus->devices[devfn] = pci_dev;
pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
pci_dev->irq = qemu_allocate_irqs(pci_irq_handler, pci_dev, PCI_NUM_PINS);
pci_dev->version_id = 2; /* Current pci device vmstate version */
return pci_dev;
}
......@@ -1201,7 +1201,7 @@ void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
/* generic PCI irq support */
/* 0 <= irq_num <= 3. level must be 0 or 1 */
static void pci_set_irq(void *opaque, int irq_num, int level)
static void pci_irq_handler(void *opaque, int irq_num, int level)
{
PCIDevice *pci_dev = opaque;
int change;
......@@ -1217,6 +1217,24 @@ static void pci_set_irq(void *opaque, int irq_num, int level)
pci_change_irq_level(pci_dev, irq_num, change);
}
static inline int pci_intx(PCIDevice *pci_dev)
{
return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
}
qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
{
int intx = pci_intx(pci_dev);
return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
}
void pci_set_irq(PCIDevice *pci_dev, int level)
{
int intx = pci_intx(pci_dev);
pci_irq_handler(pci_dev, intx, level);
}
/* Special hooks used by device assignment */
void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
{
......
......@@ -632,6 +632,29 @@ PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
void pci_set_irq(PCIDevice *pci_dev, int level);
static inline void pci_irq_assert(PCIDevice *pci_dev)
{
pci_set_irq(pci_dev, 1);
}
static inline void pci_irq_deassert(PCIDevice *pci_dev)
{
pci_set_irq(pci_dev, 0);
}
/*
* FIXME: PCI does not work this way.
* All the callers to this method should be fixed.
*/
static inline void pci_irq_pulse(PCIDevice *pci_dev)
{
pci_irq_assert(pci_dev);
pci_irq_deassert(pci_dev);
}
static inline int pci_is_express(const PCIDevice *d)
{
return d->cap_present & QEMU_PCI_CAP_EXPRESS;
......
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