提交 b1aeb926 编写于 作者: I Isaku Yamahata 提交者: Michael S. Tsirkin

pci: make command SERR bit writable

pcie aer needs SERR bit to be writable, and the PCI spec requires
this as well.  For compatibility, introduce compat global property
command_serr_enable and make this bit readonly for a pre 0.14 pc
machine.
Signed-off-by: NIsaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
上级 783e7706
master openEuler-20.03-LTS openEuler-20.09 openEuler-RISCV stable-0.14 stable-0.15 stable-1.0 stable-1.1 stable-1.2 stable-1.3 stable-1.4 stable-1.5 stable-1.6 stable-1.7 stable-2.0 stable-2.1 stable-2.10 stable-2.11 stable-2.12 stable-2.2 stable-2.3 stable-2.4 stable-2.5 stable-2.6 stable-2.7 stable-2.8 stable-2.9 stable-3.0 stable-3.1 stable-4.0 stable-4.1 stable-4.2 v5.1.0-rc2 v5.1.0-rc1 v5.1.0-rc0 v5.0.0 v5.0.0-rc4 v5.0.0-rc3 v5.0.0-rc2 v5.0.0-rc1 v5.0.0-rc0 v4.2.1 v4.2.0 v4.2.0-rc5 v4.2.0-rc4 v4.2.0-rc3 v4.2.0-rc2 v4.2.0-rc1 v4.2.0-rc0 v4.1.1 v4.1.0 v4.1.0-rc5 v4.1.0-rc4 v4.1.0-rc3 v4.1.0-rc2 v4.1.0-rc1 v4.1.0-rc0 v4.0.1 v4.0.0 v4.0.0-rc4 v4.0.0-rc3 v4.0.0-rc2 v4.0.0-rc1 v4.0.0-rc0 v3.1.1.1 v3.1.1 v3.1.0 v3.1.0-rc5 v3.1.0-rc4 v3.1.0-rc3 v3.1.0-rc2 v3.1.0-rc1 v3.1.0-rc0 v3.0.1 v3.0.0 v3.0.0-rc4 v3.0.0-rc3 v3.0.0-rc2 v3.0.0-rc1 v3.0.0-rc0 v2.12.1 v2.12.0 v2.12.0-rc4 v2.12.0-rc3 v2.12.0-rc2 v2.12.0-rc1 v2.12.0-rc0 v2.11.2 v2.11.1 v2.11.0 v2.11.0-rc5 v2.11.0-rc4 v2.11.0-rc3 v2.11.0-rc2 v2.11.0-rc1 v2.11.0-rc0 v2.10.2 v2.10.1 v2.10.0 v2.10.0-rc4 v2.10.0-rc3 v2.10.0-rc2 v2.10.0-rc1 v2.10.0-rc0 v2.9.1 v2.9.0 v2.9.0-rc5 v2.9.0-rc4 v2.9.0-rc3 v2.9.0-rc2 v2.9.0-rc1 v2.9.0-rc0 v2.8.1.1 v2.8.1 v2.8.0 v2.8.0-rc4 v2.8.0-rc3 v2.8.0-rc2 v2.8.0-rc1 v2.8.0-rc0 v2.7.1 v2.7.0 v2.7.0-rc5 v2.7.0-rc4 v2.7.0-rc3 v2.7.0-rc2 v2.7.0-rc1 v2.7.0-rc0 v2.6.2 v2.6.1 v2.6.0 v2.6.0-rc5 v2.6.0-rc4 v2.6.0-rc3 v2.6.0-rc2 v2.6.0-rc1 v2.6.0-rc0 v2.5.1.1 v2.5.1 v2.5.0 v2.5.0-rc4 v2.5.0-rc3 v2.5.0-rc2 v2.5.0-rc1 v2.5.0-rc0 v2.4.1 v2.4.0.1 v2.4.0 v2.4.0-rc4 v2.4.0-rc3 v2.4.0-rc2 v2.4.0-rc1 v2.4.0-rc0 v2.3.1 v2.3.0 v2.3.0-rc4 v2.3.0-rc3 v2.3.0-rc2 v2.3.0-rc1 v2.3.0-rc0 v2.2.1 v2.2.0 v2.2.0-rc5 v2.2.0-rc4 v2.2.0-rc3 v2.2.0-rc2 v2.2.0-rc1 v2.2.0-rc0 v2.1.3 v2.1.2 v2.1.1 v2.1.0 v2.1.0-rc5 v2.1.0-rc4 v2.1.0-rc3 v2.1.0-rc2 v2.1.0-rc1 v2.1.0-rc0 v2.0.2 v2.0.1 v2.0.0 v2.0.0-rc3 v2.0.0-rc2 v2.0.0-rc1 v2.0.0-rc0 v1.7.2 v1.7.1 v1.7.0 v1.7.0-rc2 v1.7.0-rc1 v1.7.0-rc0 v1.6.2 v1.6.1 v1.6.0 v1.6.0-rc3 v1.6.0-rc2 v1.6.0-rc1 v1.6.0-rc0 v1.5.3 v1.5.2 v1.5.1 v1.5.0 v1.5.0-rc3 v1.5.0-rc2 v1.5.0-rc1 v1.5.0-rc0 v1.4.2 v1.4.1 v1.4.0 v1.4.0-rc2 v1.4.0-rc1 v1.4.0-rc0 v1.3.1 v1.3.0 v1.3.0-rc2 v1.3.0-rc1 v1.3.0-rc0 v1.2.2 v1.2.1 v1.2.0 v1.2.0-rc3 v1.2.0-rc2 v1.2.0-rc1 v1.2.0-rc0 v1.1.2 v1.1.1 v1.1.0 v1.1.0-rc4 v1.1.0-rc3 v1.1.0-rc2 v1.1-rc2 v1.1-rc1 v1.1-rc0 v1.0.1 v1.0 v1.0-rc4 v1.0-rc3 v1.0-rc2 v1.0-rc1 v1.0-rc0 v0.15.1 v0.15.0 v0.15.0-rc2 v0.15.0-rc1 v0.15.0-rc0 v0.14.1 v0.14.0 v0.14.0-rc2 v0.14.0-rc1 v0.14.0-rc0
无相关合并请求
......@@ -217,6 +217,14 @@ static QEMUMachine pc_machine = {
.desc = "Standard PC",
.init = pc_init_pci,
.max_cpus = 255,
.compat_props = (GlobalProperty[]) {
{
.driver = "PCI",
.property = "command_serr_enable",
.value = "off",
},
{ /* end of list */ }
},
.is_default = 1,
};
......@@ -265,6 +273,10 @@ static QEMUMachine pc_machine_v0_12 = {
.driver = "vmware-svga",
.property = "rombar",
.value = stringify(0),
},{
.driver = "PCI",
.property = "command_serr_enable",
.value = "off",
},
{ /* end of list */ }
}
......@@ -300,6 +312,10 @@ static QEMUMachine pc_machine_v0_11 = {
.driver = "PCI",
.property = "rombar",
.value = stringify(0),
},{
.driver = "PCI",
.property = "command_serr_enable",
.value = "off",
},
{ /* end of list */ }
}
......@@ -347,6 +363,10 @@ static QEMUMachine pc_machine_v0_10 = {
.driver = "PCI",
.property = "rombar",
.value = stringify(0),
},{
.driver = "PCI",
.property = "command_serr_enable",
.value = "off",
},
{ /* end of list */ }
},
......
......@@ -57,6 +57,8 @@ struct BusInfo pci_bus_info = {
DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
QEMU_PCI_CAP_SERR_BITNR, true),
DEFINE_PROP_END_OF_LIST()
}
};
......@@ -568,6 +570,9 @@ static void pci_init_wmask(PCIDevice *dev)
pci_set_word(dev->wmask + PCI_COMMAND,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
PCI_COMMAND_INTX_DISABLE);
if (dev->cap_present & QEMU_PCI_CAP_SERR) {
pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
}
memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
config_size - PCI_CONFIG_HEADER_SIZE);
......
......@@ -118,6 +118,10 @@ enum {
/* multifunction capable device */
#define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
/* command register SERR bit enabled */
#define QEMU_PCI_CAP_SERR_BITNR 4
QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
};
struct PCIDevice {
......
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