Kconfig 43.8 KB
Newer Older
C
Catalin Marinas 已提交
1 2
config ARM64
	def_bool y
3
	select ACPI_CCA_REQUIRED if ACPI
4
	select ACPI_GENERIC_GSI if ACPI
F
Fu Wei 已提交
5
	select ACPI_GTDT if ACPI
6
	select ACPI_IORT if ACPI
7
	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8
	select ACPI_MCFG if ACPI
9
	select ACPI_SPCR_TABLE if ACPI
10
	select ACPI_PPTT if ACPI
11
	select ARCH_CLOCKSOURCE_DATA
12
	select ARCH_HAS_DEBUG_VIRTUAL
13
	select ARCH_HAS_DEVMEM_IS_ALLOWED
14
	select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
15
	select ARCH_HAS_ELF_RANDOMIZE
16
	select ARCH_HAS_FAST_MULTIPLIER
17
	select ARCH_HAS_FORTIFY_SOURCE
18
	select ARCH_HAS_GCOV_PROFILE_ALL
19
	select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
20
	select ARCH_HAS_KCOV
21
	select ARCH_HAS_MEMBARRIER_SYNC_CORE
22
	select ARCH_HAS_PTE_SPECIAL
23
	select ARCH_HAS_SET_MEMORY
24
	select ARCH_HAS_SG_CHAIN
25 26
	select ARCH_HAS_STRICT_KERNEL_RWX
	select ARCH_HAS_STRICT_MODULE_RWX
M
Mark Rutland 已提交
27
	select ARCH_HAS_SYSCALL_WRAPPER
28
	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
29
	select ARCH_HAVE_NMI_SAFE_CMPXCHG
30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
	select ARCH_INLINE_READ_LOCK if !PREEMPT
	select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
	select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
	select ARCH_INLINE_READ_UNLOCK if !PREEMPT
	select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
	select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
	select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
	select ARCH_INLINE_WRITE_LOCK if !PREEMPT
	select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
	select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
	select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
	select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
	select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
	select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
	select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
46 47 48 49 50 51 52 53 54 55
	select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
	select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
	select ARCH_INLINE_SPIN_LOCK if !PREEMPT
	select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
	select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
	select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
	select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
	select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
	select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
	select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
56
	select ARCH_USE_CMPXCHG_LOCKREF
57
	select ARCH_USE_QUEUED_RWLOCKS
58
	select ARCH_USE_QUEUED_SPINLOCKS
59
	select ARCH_SUPPORTS_MEMORY_FAILURE
60
	select ARCH_SUPPORTS_ATOMIC_RMW
61
	select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
62
	select ARCH_SUPPORTS_NUMA_BALANCING
63
	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
64
	select ARCH_WANT_FRAME_POINTERS
65
	select ARCH_HAS_UBSAN_SANITIZE_ALL
66
	select ARM_AMBA
67
	select ARM_ARCH_TIMER
68
	select ARM_GIC
A
AKASHI Takahiro 已提交
69
	select AUDIT_ARCH_COMPAT_GENERIC
70
	select ARM_GIC_V2M if PCI
71
	select ARM_GIC_V3
72
	select ARM_GIC_V3_ITS if PCI
73
	select ARM_PSCI_FW
74
	select BUILDTIME_EXTABLE_SORT
75
	select CLONE_BACKWARDS
76
	select COMMON_CLK
77
	select CPU_PM if (SUSPEND || CPU_IDLE)
78
	select CRC32
79
	select DCACHE_WORD_ACCESS
80
	select DMA_DIRECT_OPS
81
	select EDAC_SUPPORT
82
	select FRAME_POINTER
83
	select GENERIC_ALLOCATOR
84
	select GENERIC_ARCH_TOPOLOGY
C
Catalin Marinas 已提交
85
	select GENERIC_CLOCKEVENTS
86
	select GENERIC_CLOCKEVENTS_BROADCAST
87
	select GENERIC_CPU_AUTOPROBE
M
Mark Salter 已提交
88
	select GENERIC_EARLY_IOREMAP
L
Leo Yan 已提交
89
	select GENERIC_IDLE_POLL_SETUP
90
	select GENERIC_IRQ_MULTI_HANDLER
C
Catalin Marinas 已提交
91 92
	select GENERIC_IRQ_PROBE
	select GENERIC_IRQ_SHOW
93
	select GENERIC_IRQ_SHOW_LEVEL
A
Arnd Bergmann 已提交
94
	select GENERIC_PCI_IOMAP
95
	select GENERIC_SCHED_CLOCK
C
Catalin Marinas 已提交
96
	select GENERIC_SMP_IDLE_THREAD
97 98
	select GENERIC_STRNCPY_FROM_USER
	select GENERIC_STRNLEN_USER
C
Catalin Marinas 已提交
99
	select GENERIC_TIME_VSYSCALL
100
	select HANDLE_DOMAIN_IRQ
C
Catalin Marinas 已提交
101
	select HARDIRQS_SW_RESEND
102
	select HAVE_ACPI_APEI if (ACPI && EFI)
103
	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
A
AKASHI Takahiro 已提交
104
	select HAVE_ARCH_AUDITSYSCALL
105
	select HAVE_ARCH_BITREVERSE
106
	select HAVE_ARCH_HUGE_VMAP
107
	select HAVE_ARCH_JUMP_LABEL
108
	select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
V
Vijaya Kumar K 已提交
109
	select HAVE_ARCH_KGDB
110 111
	select HAVE_ARCH_MMAP_RND_BITS
	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
112
	select HAVE_ARCH_PREL32_RELOCATIONS
A
AKASHI Takahiro 已提交
113
	select HAVE_ARCH_SECCOMP_FILTER
114
	select HAVE_ARCH_STACKLEAK
115
	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
C
Catalin Marinas 已提交
116
	select HAVE_ARCH_TRACEHOOK
117
	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
118
	select HAVE_ARCH_VMAP_STACK
119
	select HAVE_ARM_SMCCC
120
	select HAVE_EBPF_JIT
121
	select HAVE_C_RECORDMCOUNT
122
	select HAVE_CMPXCHG_DOUBLE
123
	select HAVE_CMPXCHG_LOCAL
124
	select HAVE_CONTEXT_TRACKING
125
	select HAVE_DEBUG_BUGVERBOSE
126
	select HAVE_DEBUG_KMEMLEAK
L
Laura Abbott 已提交
127
	select HAVE_DMA_CONTIGUOUS
128
	select HAVE_DYNAMIC_FTRACE
129
	select HAVE_EFFICIENT_UNALIGNED_ACCESS
130
	select HAVE_FTRACE_MCOUNT_RECORD
A
AKASHI Takahiro 已提交
131 132
	select HAVE_FUNCTION_TRACER
	select HAVE_FUNCTION_GRAPH_TRACER
E
Emese Revfy 已提交
133
	select HAVE_GCC_PLUGINS
C
Catalin Marinas 已提交
134 135
	select HAVE_GENERIC_DMA_COHERENT
	select HAVE_HW_BREAKPOINT if PERF_EVENTS
136
	select HAVE_IRQ_TIME_ACCOUNTING
C
Catalin Marinas 已提交
137
	select HAVE_MEMBLOCK
138
	select HAVE_MEMBLOCK_NODE_MAP if NUMA
139
	select HAVE_NMI
140
	select HAVE_PATA_PLATFORM
C
Catalin Marinas 已提交
141
	select HAVE_PERF_EVENTS
142 143
	select HAVE_PERF_REGS
	select HAVE_PERF_USER_STACK_DUMP
144
	select HAVE_REGS_AND_STACK_ACCESS_API
145
	select HAVE_RCU_TABLE_FREE
146
	select HAVE_RCU_TABLE_INVALIDATE
147
	select HAVE_RSEQ
148
	select HAVE_STACKPROTECTOR
149
	select HAVE_SYSCALL_TRACEPOINTS
150
	select HAVE_KPROBES
151
	select HAVE_KRETPROBES
R
Robin Murphy 已提交
152
	select IOMMU_DMA if IOMMU_SUPPORT
C
Catalin Marinas 已提交
153
	select IRQ_DOMAIN
154
	select IRQ_FORCED_THREADING
155
	select MODULES_USE_ELF_RELA
156
	select MULTI_IRQ_HANDLER
157
	select NEED_DMA_MAP_STATE
158
	select NEED_SG_DMA_LENGTH
C
Catalin Marinas 已提交
159 160 161
	select NO_BOOTMEM
	select OF
	select OF_EARLY_FLATTREE
162
	select OF_RESERVED_MEM
163
	select PCI_ECAM if ACPI
164 165
	select POWER_RESET
	select POWER_SUPPLY
K
Kees Cook 已提交
166
	select REFCOUNT_FULL
C
Catalin Marinas 已提交
167
	select SPARSE_IRQ
168
	select SWIOTLB
169
	select SYSCTL_EXCEPTION_TRACE
170
	select THREAD_INFO_IN_TASK
171
	select HAVE_LIVEPATCH_WO_FTRACE
C
Catalin Marinas 已提交
172 173 174 175 176 177 178 179 180
	help
	  ARM 64-bit (AArch64) Linux support.

config 64BIT
	def_bool y

config MMU
	def_bool y

181 182 183 184 185 186 187 188 189 190 191 192
config ARM64_PAGE_SHIFT
	int
	default 16 if ARM64_64K_PAGES
	default 14 if ARM64_16K_PAGES
	default 12

config ARM64_CONT_SHIFT
	int
	default 5 if ARM64_64K_PAGES
	default 7 if ARM64_16K_PAGES
	default 4

193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219
config ARCH_MMAP_RND_BITS_MIN
       default 14 if ARM64_64K_PAGES
       default 16 if ARM64_16K_PAGES
       default 18

# max bits determined by the following formula:
#  VA_BITS - PAGE_SHIFT - 3
config ARCH_MMAP_RND_BITS_MAX
       default 19 if ARM64_VA_BITS=36
       default 24 if ARM64_VA_BITS=39
       default 27 if ARM64_VA_BITS=42
       default 30 if ARM64_VA_BITS=47
       default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
       default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
       default 33 if ARM64_VA_BITS=48
       default 14 if ARM64_64K_PAGES
       default 16 if ARM64_16K_PAGES
       default 18

config ARCH_MMAP_RND_COMPAT_BITS_MIN
       default 7 if ARM64_64K_PAGES
       default 9 if ARM64_16K_PAGES
       default 11

config ARCH_MMAP_RND_COMPAT_BITS_MAX
       default 16

220
config NO_IOPORT_MAP
221
	def_bool y if !PCI
C
Catalin Marinas 已提交
222 223 224 225

config STACKTRACE_SUPPORT
	def_bool y

226 227 228 229
config ILLEGAL_POINTER_VALUE
	hex
	default 0xdead000000000000

C
Catalin Marinas 已提交
230 231 232 233 234 235
config LOCKDEP_SUPPORT
	def_bool y

config TRACE_IRQFLAGS_SUPPORT
	def_bool y

236
config RWSEM_XCHGADD_ALGORITHM
C
Catalin Marinas 已提交
237 238
	def_bool y

239 240 241 242 243 244 245 246
config GENERIC_BUG
	def_bool y
	depends on BUG

config GENERIC_BUG_RELATIVE_POINTERS
	def_bool y
	depends on GENERIC_BUG

C
Catalin Marinas 已提交
247 248 249 250 251 252 253 254 255
config GENERIC_HWEIGHT
	def_bool y

config GENERIC_CSUM
        def_bool y

config GENERIC_CALIBRATE_DELAY
	def_bool y

256
config ZONE_DMA32
257 258
	bool "Support DMA32 zone" if EXPERT
	default y
C
Catalin Marinas 已提交
259

260
config HAVE_GENERIC_GUP
S
Steve Capper 已提交
261 262
	def_bool y

R
Robin Murphy 已提交
263 264 265
config ARCH_ENABLE_MEMORY_HOTPLUG
	def_bool y

266 267 268
config SMP
	def_bool y

269 270 271
config KERNEL_MODE_NEON
	def_bool y

272 273 274
config FIX_EARLYCON_MEM
	def_bool y

275 276
config PGTABLE_LEVELS
	int
S
Suzuki K. Poulose 已提交
277
	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
278 279 280
	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
	default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
281 282
	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
283

P
Pratyush Anand 已提交
284 285 286
config ARCH_SUPPORTS_UPROBES
	def_bool y

287 288 289
config ARCH_PROC_KCORE_TEXT
	def_bool y

O
Olof Johansson 已提交
290
source "arch/arm64/Kconfig.platforms"
C
Catalin Marinas 已提交
291

292 293
source "kernel/livepatch/Kconfig"

C
Catalin Marinas 已提交
294 295
menu "Bus support"

296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313
config PCI
	bool "PCI support"
	help
	  This feature enables support for PCI bus system. If you say Y
	  here, the kernel will include drivers and infrastructure code
	  to support PCI bus devices.

config PCI_DOMAINS
	def_bool PCI

config PCI_DOMAINS_GENERIC
	def_bool PCI

config PCI_SYSCALL
	def_bool PCI

source "drivers/pci/Kconfig"

C
Catalin Marinas 已提交
314 315 316 317
endmenu

menu "Kernel Features"

318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417
menu "ARM errata workarounds via the alternatives framework"

config ARM64_ERRATUM_826319
	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
	  AXI master interface and an L2 cache.

	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
	  and is unable to accept a certain write via this interface, it will
	  not progress on read data presented on the read data channel and the
	  system can deadlock.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_827319
	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
	  master interface and an L2 cache.

	  Under certain conditions this erratum can cause a clean line eviction
	  to occur at the same time as another transaction to the same address
	  on the AMBA 5 CHI interface, which can cause data corruption if the
	  interconnect reorders the two transactions.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_824069
	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
	  to a coherent interconnect.

	  If a Cortex-A53 processor is executing a store or prefetch for
	  write instruction at the same time as a processor in another
	  cluster is executing a cache maintenance operation to the same
	  address, then this erratum might cause a clean cache line to be
	  incorrectly marked as dirty.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this option does not necessarily enable the
	  workaround, as it depends on the alternative framework, which will
	  only patch the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_819472
	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
	  present when it is connected to a coherent interconnect.

	  If the processor is executing a load and store exclusive sequence at
	  the same time as a processor in another cluster is executing a cache
	  maintenance operation to the same address, then this erratum might
	  cause data corruption.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_832075
	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 832075 on Cortex-A57 parts up to r1p2.

	  Affected Cortex-A57 parts might deadlock when exclusive load/store
	  instructions to Write-Back memory are mixed with Device loads.

	  The workaround is to promote device loads to use Load-Acquire
	  semantics.
	  Please note that this does not necessarily enable the workaround,
418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_834220
	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
	depends on KVM
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 834220 on Cortex-A57 parts up to r1p2.

	  Affected Cortex-A57 parts might report a Stage 2 translation
	  fault as the result of a Stage 1 fault for load crossing a
	  page boundary when there is a permission or device memory
	  alignment fault at Stage 1 and a translation fault at Stage 2.

	  The workaround is to verify that the Stage 1 translation
	  doesn't generate a fault before handling the Stage 2 fault.
	  Please note that this does not necessarily enable the workaround,
439 440 441 442 443
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464
config ARM64_ERRATUM_845719
	bool "Cortex-A53: 845719: a load might read incorrect data"
	depends on COMPAT
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 845719 on Cortex-A53 parts up to r0p4.

	  When running a compat (AArch32) userspace on an affected Cortex-A53
	  part, a load at EL0 from a virtual address that matches the bottom 32
	  bits of the virtual address used by a recent load at (AArch64) EL1
	  might return incorrect data.

	  The workaround is to write the contextidr_el1 register on exception
	  return to a 32-bit task.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

465 466 467
config ARM64_ERRATUM_843419
	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
	default y
468
	select ARM64_MODULE_PLTS if MODULES
469
	help
470
	  This option links the kernel with '--fix-cortex-a53-843419' and
471 472 473
	  enables PLT support to replace certain ADRP instructions, which can
	  cause subsequent memory accesses to use an incorrect address on
	  Cortex-A53 parts up to r0p4.
474 475 476

	  If unsure, say Y.

477 478 479 480 481 482 483 484 485 486 487
config ARM64_ERRATUM_1024718
	bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
	default y
	help
	  This option adds work around for Arm Cortex-A55 Erratum 1024718.

	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
	  update of the hardware dirty bit when the DBM/AP bits are updated
	  without a break-before-make. The work around is to disable the usage
	  of hardware DBM locally on the affected cores. CPUs not affected by
	  erratum will continue to use the feature.
488 489 490

	  If unsure, say Y.

491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508
config ARM64_ERRATUM_1463225
	bool "Cortex-A76: Software Step might prevent interrupt recognition"
	default y
	help
	  This option adds a workaround for Arm Cortex-A76 erratum 1463225.

	  On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
	  of a system call instruction (SVC) can prevent recognition of
	  subsequent interrupts when software stepping is disabled in the
	  exception handler of the system call and either kernel debugging
	  is enabled or VHE is in use.

	  Work around the erratum by triggering a dummy step exception
	  when handling a system call from a task that is being stepped
	  in a VHE configuration of the kernel.

	  If unsure, say Y.

509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525
config CAVIUM_ERRATUM_22375
	bool "Cavium erratum 22375, 24313"
	default y
	help
	  Enable workaround for erratum 22375, 24313.

	  This implements two gicv3-its errata workarounds for ThunderX. Both
	  with small impact affecting only ITS table allocation.

	    erratum 22375: only alloc 8MB table size
	    erratum 24313: ignore memory access type

	  The fixes are in ITS initialization and basically ignore memory access
	  type and table size provided by the TYPER and BASER registers.

	  If unsure, say Y.

526 527 528 529 530 531 532 533 534
config CAVIUM_ERRATUM_23144
	bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
	depends on NUMA
	default y
	help
	  ITS SYNC command hang for cross node io and collections/cpu mapping.

	  If unsure, say Y.

535 536 537 538 539 540 541 542 543 544
config CAVIUM_ERRATUM_23154
	bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
	default y
	help
	  The gicv3 of ThunderX requires a modified version for
	  reading the IAR status to ensure data synchronization
	  (access to icc_iar1_el1 is not sync'ed before and after).

	  If unsure, say Y.

545 546 547 548 549 550 551 552 553 554 555
config CAVIUM_ERRATUM_27456
	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
	default y
	help
	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
	  instructions may cause the icache to become corrupted if it
	  contains data for a non-current ASID.  The fix is to
	  invalidate the icache when changing the mm context.

	  If unsure, say Y.

556 557 558 559 560 561 562 563 564 565 566
config CAVIUM_ERRATUM_30115
	bool "Cavium erratum 30115: Guest may disable interrupts in host"
	default y
	help
	  On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
	  1.2, and T83 Pass 1.0, KVM guest execution may disable
	  interrupts in host. Trapping both GICv3 group-0 and group-1
	  accesses sidesteps the issue.

	  If unsure, say Y.

567 568 569 570 571
config QCOM_FALKOR_ERRATUM_1003
	bool "Falkor E1003: Incorrect translation due to ASID change"
	default y
	help
	  On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
572 573 574 575 576
	  and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
	  in TTBR1_EL1, this situation only occurs in the entry trampoline and
	  then only for entries in the walk cache, since the leaf translation
	  is unchanged. Work around the erratum by invalidating the walk cache
	  entries for the trampoline before entering the kernel proper.
577

578 579 580 581 582 583 584 585 586 587
config QCOM_FALKOR_ERRATUM_1009
	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
	default y
	help
	  On Falkor v1, the CPU may prematurely complete a DSB following a
	  TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
	  one more time to fix the issue.

	  If unsure, say Y.

588 589 590 591 592 593 594 595 596 597
config QCOM_QDF2400_ERRATUM_0065
	bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
	default y
	help
	  On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
	  ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
	  been indicated as 16Bytes (0xf), not 8Bytes (0x7).

	  If unsure, say Y.

598 599 600 601 602 603 604
config SOCIONEXT_SYNQUACER_PREITS
	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
	default y
	help
	  Socionext Synquacer SoCs implement a separate h/w block to generate
	  MSI doorbell writes with non-zero values for the device ID.

605 606 607 608 609 610 611 612 613 614
	  If unsure, say Y.

config HISILICON_ERRATUM_161600802
	bool "Hip07 161600802: Erroneous redistributor VLPI base"
	default y
	help
	  The HiSilicon Hip07 SoC usees the wrong redistributor base
	  when issued ITS commands such as VMOVP and VMAPP, and requires
	  a 128kB offset to be applied to the target address in this commands.

615
	  If unsure, say Y.
616 617 618 619 620 621 622 623 624 625 626

config QCOM_FALKOR_ERRATUM_E1041
	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
	default y
	help
	  Falkor CPU may speculatively fetch instructions from an improper
	  memory location when MMU translation is changed from SCTLR_ELn[M]=1
	  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.

	  If unsure, say Y.

627 628 629
endmenu


630 631 632 633 634 635 636 637 638 639 640
choice
	prompt "Page size"
	default ARM64_4K_PAGES
	help
	  Page size (translation granule) configuration.

config ARM64_4K_PAGES
	bool "4KB"
	help
	  This feature enables 4KB pages support.

641 642 643 644 645 646 647
config ARM64_16K_PAGES
	bool "16KB"
	help
	  The system will use 16KB pages support. AArch32 emulation
	  requires applications compiled with 16K (or a multiple of 16K)
	  aligned segments.

C
Catalin Marinas 已提交
648
config ARM64_64K_PAGES
649
	bool "64KB"
C
Catalin Marinas 已提交
650 651 652
	help
	  This feature enables 64KB pages support (4KB by default)
	  allowing only two levels of page tables and faster TLB
653 654
	  look-up. AArch32 emulation requires applications compiled
	  with 64K aligned segments.
C
Catalin Marinas 已提交
655

656 657 658 659 660
endchoice

choice
	prompt "Virtual address space size"
	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
661
	default ARM64_VA_BITS_47 if ARM64_16K_PAGES
662 663 664 665 666 667
	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
	help
	  Allows choosing one of multiple possible virtual address
	  space sizes. The level of translation table is determined by
	  a combination of page size and virtual address space size.

S
Suzuki K. Poulose 已提交
668
config ARM64_VA_BITS_36
669
	bool "36-bit" if EXPERT
S
Suzuki K. Poulose 已提交
670 671
	depends on ARM64_16K_PAGES

672 673 674 675 676 677 678 679
config ARM64_VA_BITS_39
	bool "39-bit"
	depends on ARM64_4K_PAGES

config ARM64_VA_BITS_42
	bool "42-bit"
	depends on ARM64_64K_PAGES

680 681 682 683
config ARM64_VA_BITS_47
	bool "47-bit"
	depends on ARM64_16K_PAGES

684 685 686
config ARM64_VA_BITS_48
	bool "48-bit"

687 688 689 690
endchoice

config ARM64_VA_BITS
	int
S
Suzuki K. Poulose 已提交
691
	default 36 if ARM64_VA_BITS_36
692 693
	default 39 if ARM64_VA_BITS_39
	default 42 if ARM64_VA_BITS_42
694
	default 47 if ARM64_VA_BITS_47
695
	default 48 if ARM64_VA_BITS_48
696

697 698 699 700 701 702 703 704 705 706
choice
	prompt "Physical address space size"
	default ARM64_PA_BITS_48
	help
	  Choose the maximum physical address range that the kernel will
	  support.

config ARM64_PA_BITS_48
	bool "48-bit"

707 708 709 710 711 712 713 714 715 716 717 718
config ARM64_PA_BITS_52
	bool "52-bit (ARMv8.2)"
	depends on ARM64_64K_PAGES
	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
	help
	  Enable support for a 52-bit physical address space, introduced as
	  part of the ARMv8.2-LPA extension.

	  With this enabled, the kernel will also continue to work on CPUs that
	  do not support ARMv8.2-LPA, but with some added memory overhead (and
	  minor performance overhead).

719 720 721 722 723
endchoice

config ARM64_PA_BITS
	int
	default 48 if ARM64_PA_BITS_48
724
	default 52 if ARM64_PA_BITS_52
725

726 727 728 729 730
config CPU_BIG_ENDIAN
       bool "Build big-endian kernel"
       help
         Say Y if you plan on running a kernel in big-endian mode.

731 732 733 734 735 736 737 738 739 740 741 742 743 744
config SCHED_MC
	bool "Multi-core scheduler support"
	help
	  Multi-core scheduler support improves the CPU scheduler's decision
	  making when dealing with multi-core CPU chips at a cost of slightly
	  increased overhead in some places. If unsure say N here.

config SCHED_SMT
	bool "SMT scheduler support"
	help
	  Improves the CPU scheduler's decision making when dealing with
	  MultiThreading at a cost of slightly increased overhead in some
	  places. If unsure say N here.

C
Catalin Marinas 已提交
745
config NR_CPUS
746 747
	int "Maximum number of CPUs (2-4096)"
	range 2 4096
748
	# These have to remain sorted largest to smallest
749
	default "64"
C
Catalin Marinas 已提交
750

751 752
config HOTPLUG_CPU
	bool "Support for hot-pluggable CPUs"
753
	select GENERIC_IRQ_MIGRATION
754 755 756 757
	help
	  Say Y here to experiment with turning CPUs off and on.  CPUs
	  can be controlled through /sys/devices/system/cpu.

X
Xie XiuQi 已提交
758 759 760 761 762 763 764 765 766 767 768
config ARM64_ERR_RECOV
	bool "Support arm64 RAS error recovery"
	depends on ACPI_APEI_SEA && MEMORY_FAILURE
	help
	  With ARM v8.2 RAS Extension, SEA are usually triggered when memory errors
	  are consumed. In some cases, if the error address is in a clean page or a
	  read-only page, there is a chance to recover. Such as error occurs in a
	  instruction page, we can reread this page from disk instead of killing process.

	  Say Y if unsure.

769 770 771 772 773 774 775 776
config MPAM
	bool "Support Memory Partitioning and Monitoring"
	default n
	select RESCTRL
	help
	  Memory Partitioning and Monitoring. More exactly Memory system
	  performance resource Partitioning and Monitoring

777 778 779
# Common NUMA Features
config NUMA
	bool "Numa Memory Allocation and Scheduler Support"
780 781
	select ACPI_NUMA if ACPI
	select OF_NUMA
782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797
	help
	  Enable NUMA (Non Uniform Memory Access) support.

	  The kernel will try to allocate memory used by a CPU on the
	  local memory of the CPU and add some more
	  NUMA awareness to the kernel.

config NODES_SHIFT
	int "Maximum NUMA Nodes (as a power of 2)"
	range 1 10
	default "2"
	depends on NEED_MULTIPLE_NODES
	help
	  Specify the maximum number of NUMA Nodes available on the target
	  system.  Increases memory reserved to accommodate various tables.

W
Wei Li 已提交
798 799 800 801 802 803 804 805 806 807 808 809 810 811
config NUMA_AWARE_SPINLOCKS
	bool "Numa-aware spinlocks"
	depends on NUMA && QUEUED_SPINLOCKS
	default n
	help
	  Introduce NUMA (Non Uniform Memory Access) awareness into
	  the slow path of spinlocks.

	  The kernel will try to keep the lock on the same node,
	  thus reducing the number of remote cache misses, while
	  trading some of the short term fairness for better performance.

	  Say N if you want absolute first come first serve fairness.

812 813 814 815
config USE_PERCPU_NUMA_NODE_ID
	def_bool y
	depends on NUMA

816 817 818 819 820 821 822 823
config HAVE_SETUP_PER_CPU_AREA
	def_bool y
	depends on NUMA

config NEED_PER_CPU_EMBED_FIRST_CHUNK
	def_bool y
	depends on NUMA

824 825 826
config HOLES_IN_ZONE
	def_bool y

827
source kernel/Kconfig.hz
C
Catalin Marinas 已提交
828

829 830 831
config ARCH_SUPPORTS_DEBUG_PAGEALLOC
	def_bool y

C
Catalin Marinas 已提交
832 833 834 835 836 837 838 839 840 841 842 843 844
config ARCH_HAS_HOLES_MEMORYMODEL
	def_bool y if SPARSEMEM

config ARCH_SPARSEMEM_ENABLE
	def_bool y
	select SPARSEMEM_VMEMMAP_ENABLE

config ARCH_SPARSEMEM_DEFAULT
	def_bool ARCH_SPARSEMEM_ENABLE

config ARCH_SELECT_MEMORY_MODEL
	def_bool ARCH_SPARSEMEM_ENABLE

845
config ARCH_FLATMEM_ENABLE
846
	def_bool !NUMA
847

C
Catalin Marinas 已提交
848 849
config HAVE_ARCH_PFN_VALID
	def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
850
	select HAVE_MEMBLOCK_PFN_VALID
C
Catalin Marinas 已提交
851 852

config HW_PERF_EVENTS
853 854
	def_bool y
	depends on ARM_PMU
C
Catalin Marinas 已提交
855

S
Steve Capper 已提交
856 857 858 859
config SYS_SUPPORTS_HUGETLBFS
	def_bool y

config ARCH_WANT_HUGE_PMD_SHARE
S
Suzuki K. Poulose 已提交
860
	def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
S
Steve Capper 已提交
861

862 863 864
config ARCH_HAS_CACHE_LINE_SIZE
	def_bool y

A
AKASHI Takahiro 已提交
865 866 867 868 869 870 871 872 873 874 875 876 877
config SECCOMP
	bool "Enable seccomp to safely compute untrusted bytecode"
	---help---
	  This kernel feature is useful for number crunching applications
	  that may need to compute untrusted bytecode during their
	  execution. By using pipes or other transports made available to
	  the process as file descriptors supporting the read/write
	  syscalls, it's possible to isolate those applications in
	  their own address space using seccomp. Once seccomp is
	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
	  and the task is only allowed to execute a few safe syscalls
	  defined by each seccomp mode.

878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896
config PARAVIRT
	bool "Enable paravirtualization code"
	help
	  This changes the kernel so it can modify itself when it is run
	  under a hypervisor, potentially improving performance significantly
	  over full virtualization.

config PARAVIRT_TIME_ACCOUNTING
	bool "Paravirtual steal time accounting"
	select PARAVIRT
	default n
	help
	  Select this option to enable fine granularity task steal time
	  accounting. Time spent executing other tasks in parallel with
	  the current vCPU is discounted from the vCPU power. To account for
	  that, there can be a small performance impact.

	  If in doubt, say N here.

897 898 899 900 901 902 903 904 905 906
config KEXEC
	depends on PM_SLEEP_SMP
	select KEXEC_CORE
	bool "kexec system call"
	---help---
	  kexec is a system call that implements the ability to shutdown your
	  current kernel, and to start another kernel.  It is like a reboot
	  but it is independent of the system firmware.   And like a reboot
	  you can start any kernel with it, not just Linux.

907 908 909 910 911 912 913 914 915 916 917
config CRASH_DUMP
	bool "Build kdump crash kernel"
	help
	  Generate crash dump after being started by kexec. This should
	  be normally only set in special crash dump kernels which are
	  loaded in the main kernel with kexec-tools into a specially
	  reserved region and then later executed after a crash by
	  kdump/kexec.

	  For more details see Documentation/kdump/kdump.txt

918 919 920 921 922
config XEN_DOM0
	def_bool y
	depends on XEN

config XEN
923
	bool "Xen guest support on ARM64"
924
	depends on ARM64 && OF
925
	select SWIOTLB_XEN
926
	select PARAVIRT
927 928 929
	help
	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.

930 931 932
config FORCE_MAX_ZONEORDER
	int
	default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
933
	default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
934
	default "11"
935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951
	help
	  The kernel memory allocator divides physically contiguous memory
	  blocks into "zones", where each zone is a power of two number of
	  pages.  This option selects the largest power of two that the kernel
	  keeps in the memory allocator.  If you need to allocate very large
	  blocks of physically contiguous memory, then you may need to
	  increase this value.

	  This config option is actually maximum order plus one. For example,
	  a value of 11 means that the largest free memory block is 2^10 pages.

	  We make sure that we can allocate upto a HugePage size for each configuration.
	  Hence we have :
		MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2

	  However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
	  4M allocations matching the default size used by generic code.
952

953
config UNMAP_KERNEL_AT_EL0
954
	bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
955 956
	default y
	help
957 958 959 960 961
	  Speculation attacks against some high-performance processors can
	  be used to bypass MMU permission checks and leak kernel data to
	  userspace. This can be defended against by unmapping the kernel
	  when running in userspace, mapping it back in on exception entry
	  via a trampoline page in the vector table.
962 963 964

	  If unsure, say Y.

965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981
config HARDEN_BRANCH_PREDICTOR
	bool "Harden the branch predictor against aliasing attacks" if EXPERT
	default y
	help
	  Speculation attacks against some high-performance processors rely on
	  being able to manipulate the branch predictor for a victim context by
	  executing aliasing branches in the attacker context.  Such attacks
	  can be partially mitigated against by clearing internal branch
	  predictor state and limiting the prediction logic in some situations.

	  This config option will take CPU-specific actions to harden the
	  branch predictor against aliasing attacks and may rely on specific
	  instruction sequences or control bits being set by the system
	  firmware.

	  If unsure, say Y.

982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997
config HARDEN_EL2_VECTORS
	bool "Harden EL2 vector mapping against system register leak" if EXPERT
	default y
	help
	  Speculation attacks against some high-performance processors can
	  be used to leak privileged information such as the vector base
	  register, resulting in a potential defeat of the EL2 layout
	  randomization.

	  This config option will map the vectors to a fixed location,
	  independent of the EL2 code mapping, so that revealing VBAR_EL2
	  to an attacker does not give away any extra information. This
	  only gets enabled on affected CPUs.

	  If unsure, say Y.

998 999 1000 1001 1002 1003 1004 1005 1006
config ARM64_SSBD
	bool "Speculative Store Bypass Disable" if EXPERT
	default y
	help
	  This enables mitigation of the bypassing of previous stores
	  by speculative loads.

	  If unsure, say Y.

1007 1008 1009
menuconfig ARMV8_DEPRECATED
	bool "Emulate deprecated/obsolete ARMv8 instructions"
	depends on COMPAT
1010
	depends on SYSCTL
1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057
	help
	  Legacy software support may require certain instructions
	  that have been deprecated or obsoleted in the architecture.

	  Enable this config to enable selective emulation of these
	  features.

	  If unsure, say Y

if ARMV8_DEPRECATED

config SWP_EMULATION
	bool "Emulate SWP/SWPB instructions"
	help
	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
	  they are always undefined. Say Y here to enable software
	  emulation of these instructions for userspace using LDXR/STXR.

	  In some older versions of glibc [<=2.8] SWP is used during futex
	  trylock() operations with the assumption that the code will not
	  be preempted. This invalid assumption may be more likely to fail
	  with SWP emulation enabled, leading to deadlock of the user
	  application.

	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
	  on an external transaction monitoring block called a global
	  monitor to maintain update atomicity. If your system does not
	  implement a global monitor, this option can cause programs that
	  perform SWP operations to uncached memory to deadlock.

	  If unsure, say Y

config CP15_BARRIER_EMULATION
	bool "Emulate CP15 Barrier instructions"
	help
	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
	  strongly recommended to use the ISB, DSB, and DMB
	  instructions instead.

	  Say Y here to enable software emulation of these
	  instructions for AArch32 userspace code. When this option is
	  enabled, CP15 barrier usage is traced which can help
	  identify software that needs updating.

	  If unsure, say Y

1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072
config SETEND_EMULATION
	bool "Emulate SETEND instruction"
	help
	  The SETEND instruction alters the data-endianness of the
	  AArch32 EL0, and is deprecated in ARMv8.

	  Say Y here to enable software emulation of the instruction
	  for AArch32 userspace code.

	  Note: All the cpus on the system must have mixed endian support at EL0
	  for this feature to be enabled. If a new CPU - which doesn't support mixed
	  endian - is hotplugged in after this feature has been enabled, there could
	  be unexpected results in the applications.

	  If unsure, say Y
1073 1074
endif

1075 1076 1077 1078 1079 1080 1081 1082
config ARM64_SW_TTBR0_PAN
	bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
	help
	  Enabling this option prevents the kernel from accessing
	  user-space memory directly by pointing TTBR0_EL1 to a reserved
	  zeroed area and reserved ASID. The user access routines
	  restore the valid TTBR0_EL1 temporarily.

1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117
menu "ARMv8.1 architectural features"

config ARM64_HW_AFDBM
	bool "Support for hardware updates of the Access and Dirty page flags"
	default y
	help
	  The ARMv8.1 architecture extensions introduce support for
	  hardware updates of the access and dirty information in page
	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
	  capable processors, accesses to pages with PTE_AF cleared will
	  set this bit instead of raising an access flag fault.
	  Similarly, writes to read-only pages with the DBM bit set will
	  clear the read-only bit (AP[2]) instead of raising a
	  permission fault.

	  Kernels built with this configuration option enabled continue
	  to work on pre-ARMv8.1 hardware and the performance impact is
	  minimal. If unsure, say Y.

config ARM64_PAN
	bool "Enable support for Privileged Access Never (PAN)"
	default y
	help
	 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
	 prevents the kernel or hypervisor from accessing user-space (EL0)
	 memory directly.

	 Choosing this option will cause any unprotected (not using
	 copy_to_user et al) memory access to fail with a permission fault.

	 The feature is detected at runtime, and will remain as a 'nop'
	 instruction if the cpu does not implement the feature.

config ARM64_LSE_ATOMICS
	bool "Atomic instructions"
1118
	default y
1119 1120 1121 1122 1123 1124 1125 1126
	help
	  As part of the Large System Extensions, ARMv8.1 introduces new
	  atomic instructions that are designed specifically to scale in
	  very large systems.

	  Say Y here to make use of these instructions for the in-kernel
	  atomic routines. This incurs a small overhead on CPUs that do
	  not support these instructions and requires the kernel to be
1127 1128
	  built with binutils >= 2.25 in order for the new instructions
	  to be used.
1129

1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142
config ARM64_VHE
	bool "Enable support for Virtualization Host Extensions (VHE)"
	default y
	help
	  Virtualization Host Extensions (VHE) allow the kernel to run
	  directly at EL2 (instead of EL1) on processors that support
	  it. This leads to better performance for KVM, as they reduce
	  the cost of the world switch.

	  Selecting this option allows the VHE feature to be detected
	  at runtime, and does not affect processors that do not
	  implement this feature.

1143 1144
endmenu

1145 1146
menu "ARMv8.2 architectural features"

1147 1148 1149 1150 1151 1152
config ARM64_UAO
	bool "Enable support for User Access Override (UAO)"
	default y
	help
	  User Access Override (UAO; part of the ARMv8.2 Extensions)
	  causes the 'unprivileged' variant of the load/store instructions to
M
Masanari Iida 已提交
1153
	  be overridden to be privileged.
1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167

	  This option changes get_user() and friends to use the 'unprivileged'
	  variant of the load/store instructions. This ensures that user-space
	  really did have access to the supplied memory. When addr_limit is
	  set to kernel memory the UAO bit will be set, allowing privileged
	  access to kernel memory.

	  Choosing this option will cause copy_to_user() et al to use user-space
	  memory permissions.

	  The feature is detected at runtime, the kernel will use the
	  regular load/store instructions if the cpu does not implement the
	  feature.

R
Robin Murphy 已提交
1168 1169 1170
config ARM64_PMEM
	bool "Enable support for persistent memory"
	select ARCH_HAS_PMEM_API
1171
	select ARCH_HAS_UACCESS_FLUSHCACHE
R
Robin Murphy 已提交
1172 1173 1174 1175 1176 1177 1178 1179
	help
	  Say Y to enable support for the persistent memory API based on the
	  ARMv8.2 DCPoP feature.

	  The feature is detected at runtime, and the kernel will use DC CVAC
	  operations if DC CVAP is not supported (following the behaviour of
	  DC CVAP itself if the system does not define a point of persistence).

1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195
config ARM64_RAS_EXTN
	bool "Enable support for RAS CPU Extensions"
	default y
	help
	  CPUs that support the Reliability, Availability and Serviceability
	  (RAS) Extensions, part of ARMv8.2 are able to track faults and
	  errors, classify them and report them to software.

	  On CPUs with these extensions system software can use additional
	  barriers to determine if faults are pending and read the
	  classification from a new set of registers.

	  Selecting this feature will allow the kernel to use these barriers
	  and access the new registers if the system supports the extension.
	  Platform RAS features may additionally depend on firmware support.

1196 1197
endmenu

1198 1199 1200
config ARM64_SVE
	bool "ARM Scalable Vector Extension support"
	default y
1201
	depends on !KVM || ARM64_VHE
1202 1203 1204 1205 1206 1207 1208 1209
	help
	  The Scalable Vector Extension (SVE) is an extension to the AArch64
	  execution state which complements and extends the SIMD functionality
	  of the base architecture to support much larger vectors and to enable
	  additional vectorisation opportunities.

	  To enable use of this extension on CPUs that implement it, say Y.

1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225
	  Note that for architectural reasons, firmware _must_ implement SVE
	  support when running on SVE capable hardware.  The required support
	  is present in:

	    * version 1.5 and later of the ARM Trusted Firmware
	    * the AArch64 boot wrapper since commit 5e1261e08abf
	      ("bootwrapper: SVE: Enable SVE for EL2 and below").

	  For other firmware implementations, consult the firmware documentation
	  or vendor.

	  If you need the kernel to boot on SVE-capable hardware with broken
	  firmware, you may need to say N here until you get your firmware
	  fixed.  Otherwise, you may experience firmware panics or lockups when
	  booting the kernel.  If unsure and you are not observing these
	  symptoms, you should assume that it is safe to say Y.
1226

1227 1228 1229 1230 1231 1232
	  CPUs that support SVE are architecturally required to support the
	  Virtualization Host Extensions (VHE), so the kernel makes no
	  provision for supporting SVE alongside KVM without VHE enabled.
	  Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
	  KVM in the same kernel image.

1233 1234 1235 1236
config ARM64_MODULE_PLTS
	bool
	select HAVE_MOD_ARCH_SPECIFIC

1237 1238 1239
config ARM64_PSEUDO_NMI
	bool "Support for NMI-like interrupts"
	select CONFIG_ARM_GIC_V3
1240
	select HAVE_PERF_EVENTS_NMI
1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251
	help
	  Adds support for mimicking Non-Maskable Interrupts through the use of
	  GIC interrupt priority. This support requires version 3 or later of
	  Arm GIC.

	  This high priority configuration for interrupts needs to be
	  explicitly enabled by setting the kernel parameter
	  "irqchip.gicv3_pseudo_nmi" to 1.

	  If unsure, say N

1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262
config RELOCATABLE
	bool
	help
	  This builds the kernel as a Position Independent Executable (PIE),
	  which retains all relocation metadata required to relocate the
	  kernel binary at runtime to a different virtual address than the
	  address it was linked at.
	  Since AArch64 uses the RELA relocation format, this requires a
	  relocation pass at runtime even if the kernel is loaded at the
	  same address it was linked at.

1263 1264
config RANDOMIZE_BASE
	bool "Randomize the address of the kernel image"
1265
	select ARM64_MODULE_PLTS if MODULES
1266 1267 1268 1269 1270 1271 1272 1273 1274
	select RELOCATABLE
	help
	  Randomizes the virtual address at which the kernel image is
	  loaded, as a security feature that deters exploit attempts
	  relying on knowledge of the location of kernel internals.

	  It is the bootloader's job to provide entropy, by passing a
	  random u64 value in /chosen/kaslr-seed at kernel entry.

1275 1276 1277 1278 1279
	  When booting via the UEFI stub, it will invoke the firmware's
	  EFI_RNG_PROTOCOL implementation (if available) to supply entropy
	  to the kernel proper. In addition, it will randomise the physical
	  location of the kernel Image as well.

1280 1281 1282
	  If unsure, say N.

config RANDOMIZE_MODULE_REGION_FULL
1283
	bool "Randomize the module region over a 4 GB range"
1284
	depends on RANDOMIZE_BASE
1285 1286
	default y
	help
1287 1288
	  Randomizes the location of the module region inside a 4 GB window
	  covering the core kernel. This way, it is less likely for modules
1289 1290 1291 1292 1293 1294 1295 1296
	  to leak information about the location of core kernel data structures
	  but it does imply that function calls between modules and the core
	  kernel will need to be resolved via veneers in the module PLT.

	  When this option is not set, the module region will be randomized over
	  a limited range that contains the [_stext, _etext] interval of the
	  core kernel, so branch relocations are always in range.

C
Catalin Marinas 已提交
1297 1298 1299 1300
endmenu

menu "Boot options"

1301 1302 1303 1304 1305 1306 1307 1308 1309
config ARM64_ACPI_PARKING_PROTOCOL
	bool "Enable support for the ARM64 ACPI parking protocol"
	depends on ACPI
	help
	  Enable support for the ARM64 ACPI parking protocol. If disabled
	  the kernel will not allow booting through the ARM64 ACPI parking
	  protocol even if the corresponding data is present in the ACPI
	  MADT table.

C
Catalin Marinas 已提交
1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325
config CMDLINE
	string "Default kernel command string"
	default ""
	help
	  Provide a set of default command-line options at build time by
	  entering them here. As a minimum, you should specify the the
	  root device (e.g. root=/dev/nfs).

config CMDLINE_FORCE
	bool "Always use the default kernel command string"
	help
	  Always use the default kernel command string, even if the boot
	  loader passes other arguments to the kernel.
	  This is useful if you cannot or don't want to change the
	  command-line options your boot loader passes to the kernel.

1326 1327 1328
config EFI_STUB
	bool

M
Mark Salter 已提交
1329 1330 1331
config EFI
	bool "UEFI runtime support"
	depends on OF && !CPU_BIG_ENDIAN
1332
	depends on KERNEL_MODE_NEON
A
Arnd Bergmann 已提交
1333
	select ARCH_SUPPORTS_ACPI
M
Mark Salter 已提交
1334 1335 1336
	select LIBFDT
	select UCS2_STRING
	select EFI_PARAMS_FROM_FDT
1337
	select EFI_RUNTIME_WRAPPERS
1338 1339
	select EFI_STUB
	select EFI_ARMSTUB
M
Mark Salter 已提交
1340 1341 1342 1343
	default y
	help
	  This option provides support for runtime services provided
	  by UEFI firmware (such as non-volatile variables, realtime
M
Mark Salter 已提交
1344 1345 1346
          clock, and platform reset). A UEFI stub is also provided to
	  allow the kernel to be booted as an EFI application. This
	  is only useful on systems that have UEFI firmware.
M
Mark Salter 已提交
1347

Y
Yi Li 已提交
1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358
config DMI
	bool "Enable support for SMBIOS (DMI) tables"
	depends on EFI
	default y
	help
	  This enables SMBIOS/DMI feature for systems.

	  This option is only useful on systems that have UEFI firmware.
	  However, even with this option, the resultant kernel should
	  continue to boot on existing non-UEFI platforms.

C
Catalin Marinas 已提交
1359 1360 1361 1362
endmenu

config COMPAT
	bool "Kernel support for 32-bit EL0"
1363
	depends on ARM64_4K_PAGES || EXPERT
1364
	select COMPAT_BINFMT_ELF if BINFMT_ELF
1365
	select HAVE_UID16
1366
	select OLD_SIGSUSPEND3
1367
	select COMPAT_OLD_SIGACTION
C
Catalin Marinas 已提交
1368 1369 1370 1371 1372 1373
	help
	  This option enables support for a 32-bit EL0 running under a 64-bit
	  kernel at EL1. AArch32-specific components such as system calls,
	  the user helper functions, VFP support and the ptrace interface are
	  handled appropriately by the kernel.

1374 1375 1376
	  If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
	  that you will only be able to execute AArch32 binaries that were compiled
	  with page size aligned segments.
1377

C
Catalin Marinas 已提交
1378 1379 1380 1381 1382 1383
	  If you want to execute 32-bit userspace applications, say Y.

config SYSVIPC_COMPAT
	def_bool y
	depends on COMPAT && SYSVIPC

1384 1385 1386 1387
menu "Power management options"

source "kernel/power/Kconfig"

1388 1389 1390 1391 1392 1393 1394 1395
config ARCH_HIBERNATION_POSSIBLE
	def_bool y
	depends on CPU_PM

config ARCH_HIBERNATION_HEADER
	def_bool y
	depends on HIBERNATION

1396 1397 1398 1399 1400
config ARCH_SUSPEND_POSSIBLE
	def_bool y

endmenu

1401 1402 1403 1404
menu "CPU Power Management"

source "drivers/cpuidle/Kconfig"

1405 1406 1407 1408
source "drivers/cpufreq/Kconfig"

endmenu

M
Mark Salter 已提交
1409 1410
source "drivers/firmware/Kconfig"

1411 1412
source "drivers/acpi/Kconfig"

M
Marc Zyngier 已提交
1413 1414
source "arch/arm64/kvm/Kconfig"

1415 1416 1417
if CRYPTO
source "arch/arm64/crypto/Kconfig"
endif