Kconfig 21.6 KB
Newer Older
C
Catalin Marinas 已提交
1 2
config ARM64
	def_bool y
3
	select ACPI_CCA_REQUIRED if ACPI
4
	select ACPI_GENERIC_GSI if ACPI
5
	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
C
Catalin Marinas 已提交
6
	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7
	select ARCH_HAS_ELF_RANDOMIZE
8
	select ARCH_HAS_GCOV_PROFILE_ALL
9
	select ARCH_HAS_SG_CHAIN
10
	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11
	select ARCH_USE_CMPXCHG_LOCKREF
12
	select ARCH_SUPPORTS_ATOMIC_RMW
13
	select ARCH_WANT_OPTIONAL_GPIOLIB
14
	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15
	select ARCH_WANT_FRAME_POINTERS
16
	select ARM_AMBA
17
	select ARM_ARCH_TIMER
18
	select ARM_GIC
A
AKASHI Takahiro 已提交
19
	select AUDIT_ARCH_COMPAT_GENERIC
20
	select ARM_GIC_V2M if PCI_MSI
21
	select ARM_GIC_V3
22
	select ARM_GIC_V3_ITS if PCI_MSI
23
	select ARM_PSCI_FW
24
	select BUILDTIME_EXTABLE_SORT
25
	select CLONE_BACKWARDS
26
	select COMMON_CLK
27
	select CPU_PM if (SUSPEND || CPU_IDLE)
28
	select DCACHE_WORD_ACCESS
29
	select EDAC_SUPPORT
30
	select GENERIC_ALLOCATOR
C
Catalin Marinas 已提交
31
	select GENERIC_CLOCKEVENTS
32
	select GENERIC_CLOCKEVENTS_BROADCAST
33
	select GENERIC_CPU_AUTOPROBE
M
Mark Salter 已提交
34
	select GENERIC_EARLY_IOREMAP
L
Leo Yan 已提交
35
	select GENERIC_IDLE_POLL_SETUP
C
Catalin Marinas 已提交
36 37
	select GENERIC_IRQ_PROBE
	select GENERIC_IRQ_SHOW
38
	select GENERIC_IRQ_SHOW_LEVEL
A
Arnd Bergmann 已提交
39
	select GENERIC_PCI_IOMAP
40
	select GENERIC_SCHED_CLOCK
C
Catalin Marinas 已提交
41
	select GENERIC_SMP_IDLE_THREAD
42 43
	select GENERIC_STRNCPY_FROM_USER
	select GENERIC_STRNLEN_USER
C
Catalin Marinas 已提交
44
	select GENERIC_TIME_VSYSCALL
45
	select HANDLE_DOMAIN_IRQ
C
Catalin Marinas 已提交
46
	select HARDIRQS_SW_RESEND
47
	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
A
AKASHI Takahiro 已提交
48
	select HAVE_ARCH_AUDITSYSCALL
49
	select HAVE_ARCH_BITREVERSE
50
	select HAVE_ARCH_JUMP_LABEL
A
Andrey Ryabinin 已提交
51
	select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP
V
Vijaya Kumar K 已提交
52
	select HAVE_ARCH_KGDB
A
AKASHI Takahiro 已提交
53
	select HAVE_ARCH_SECCOMP_FILTER
C
Catalin Marinas 已提交
54
	select HAVE_ARCH_TRACEHOOK
Z
Zi Shen Lim 已提交
55
	select HAVE_BPF_JIT
56
	select HAVE_C_RECORDMCOUNT
57
	select HAVE_CC_STACKPROTECTOR
58
	select HAVE_CMPXCHG_DOUBLE
59
	select HAVE_CMPXCHG_LOCAL
60
	select HAVE_DEBUG_BUGVERBOSE
61
	select HAVE_DEBUG_KMEMLEAK
C
Catalin Marinas 已提交
62 63
	select HAVE_DMA_API_DEBUG
	select HAVE_DMA_ATTRS
L
Laura Abbott 已提交
64
	select HAVE_DMA_CONTIGUOUS
65
	select HAVE_DYNAMIC_FTRACE
66
	select HAVE_EFFICIENT_UNALIGNED_ACCESS
67
	select HAVE_FTRACE_MCOUNT_RECORD
A
AKASHI Takahiro 已提交
68 69
	select HAVE_FUNCTION_TRACER
	select HAVE_FUNCTION_GRAPH_TRACER
C
Catalin Marinas 已提交
70 71 72
	select HAVE_GENERIC_DMA_COHERENT
	select HAVE_HW_BREAKPOINT if PERF_EVENTS
	select HAVE_MEMBLOCK
73
	select HAVE_PATA_PLATFORM
C
Catalin Marinas 已提交
74
	select HAVE_PERF_EVENTS
75 76
	select HAVE_PERF_REGS
	select HAVE_PERF_USER_STACK_DUMP
77
	select HAVE_RCU_TABLE_FREE
78
	select HAVE_SYSCALL_TRACEPOINTS
C
Catalin Marinas 已提交
79
	select IRQ_DOMAIN
80
	select IRQ_FORCED_THREADING
81
	select MODULES_USE_ELF_RELA
C
Catalin Marinas 已提交
82 83 84
	select NO_BOOTMEM
	select OF
	select OF_EARLY_FLATTREE
85
	select OF_RESERVED_MEM
C
Catalin Marinas 已提交
86
	select PERF_USE_VMALLOC
87 88
	select POWER_RESET
	select POWER_SUPPLY
C
Catalin Marinas 已提交
89 90
	select RTC_LIB
	select SPARSE_IRQ
91
	select SYSCTL_EXCEPTION_TRACE
L
Larry Bassel 已提交
92
	select HAVE_CONTEXT_TRACKING
C
Catalin Marinas 已提交
93 94 95 96 97 98 99 100 101 102 103 104
	help
	  ARM 64-bit (AArch64) Linux support.

config 64BIT
	def_bool y

config ARCH_PHYS_ADDR_T_64BIT
	def_bool y

config MMU
	def_bool y

105
config NO_IOPORT_MAP
106
	def_bool y if !PCI
C
Catalin Marinas 已提交
107 108 109 110

config STACKTRACE_SUPPORT
	def_bool y

111 112 113 114
config ILLEGAL_POINTER_VALUE
	hex
	default 0xdead000000000000

C
Catalin Marinas 已提交
115 116 117 118 119 120
config LOCKDEP_SUPPORT
	def_bool y

config TRACE_IRQFLAGS_SUPPORT
	def_bool y

121
config RWSEM_XCHGADD_ALGORITHM
C
Catalin Marinas 已提交
122 123
	def_bool y

124 125 126 127 128 129 130 131
config GENERIC_BUG
	def_bool y
	depends on BUG

config GENERIC_BUG_RELATIVE_POINTERS
	def_bool y
	depends on GENERIC_BUG

C
Catalin Marinas 已提交
132 133 134 135 136 137 138 139 140
config GENERIC_HWEIGHT
	def_bool y

config GENERIC_CSUM
        def_bool y

config GENERIC_CALIBRATE_DELAY
	def_bool y

141
config ZONE_DMA
C
Catalin Marinas 已提交
142 143
	def_bool y

S
Steve Capper 已提交
144 145 146
config HAVE_GENERIC_RCU_GUP
	def_bool y

C
Catalin Marinas 已提交
147 148 149 150 151 152 153 154 155
config ARCH_DMA_ADDR_T_64BIT
	def_bool y

config NEED_DMA_MAP_STATE
	def_bool y

config NEED_SG_DMA_LENGTH
	def_bool y

156 157 158
config SMP
	def_bool y

C
Catalin Marinas 已提交
159 160 161 162 163 164
config SWIOTLB
	def_bool y

config IOMMU_HELPER
	def_bool SWIOTLB

165 166 167
config KERNEL_MODE_NEON
	def_bool y

168 169 170
config FIX_EARLYCON_MEM
	def_bool y

171 172
config PGTABLE_LEVELS
	int
S
Suzuki K. Poulose 已提交
173
	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
174 175 176
	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
	default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
177 178
	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
179

C
Catalin Marinas 已提交
180 181 182 183
source "init/Kconfig"

source "kernel/Kconfig.freezer"

O
Olof Johansson 已提交
184
source "arch/arm64/Kconfig.platforms"
C
Catalin Marinas 已提交
185 186 187

menu "Bus support"

188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207
config PCI
	bool "PCI support"
	help
	  This feature enables support for PCI bus system. If you say Y
	  here, the kernel will include drivers and infrastructure code
	  to support PCI bus devices.

config PCI_DOMAINS
	def_bool PCI

config PCI_DOMAINS_GENERIC
	def_bool PCI

config PCI_SYSCALL
	def_bool PCI

source "drivers/pci/Kconfig"
source "drivers/pci/pcie/Kconfig"
source "drivers/pci/hotplug/Kconfig"

C
Catalin Marinas 已提交
208 209 210 211
endmenu

menu "Kernel Features"

212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316
menu "ARM errata workarounds via the alternatives framework"

config ARM64_ERRATUM_826319
	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
	  AXI master interface and an L2 cache.

	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
	  and is unable to accept a certain write via this interface, it will
	  not progress on read data presented on the read data channel and the
	  system can deadlock.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_827319
	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
	  master interface and an L2 cache.

	  Under certain conditions this erratum can cause a clean line eviction
	  to occur at the same time as another transaction to the same address
	  on the AMBA 5 CHI interface, which can cause data corruption if the
	  interconnect reorders the two transactions.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_824069
	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
	  to a coherent interconnect.

	  If a Cortex-A53 processor is executing a store or prefetch for
	  write instruction at the same time as a processor in another
	  cluster is executing a cache maintenance operation to the same
	  address, then this erratum might cause a clean cache line to be
	  incorrectly marked as dirty.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this option does not necessarily enable the
	  workaround, as it depends on the alternative framework, which will
	  only patch the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_819472
	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
	  present when it is connected to a coherent interconnect.

	  If the processor is executing a load and store exclusive sequence at
	  the same time as a processor in another cluster is executing a cache
	  maintenance operation to the same address, then this erratum might
	  cause data corruption.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_832075
	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 832075 on Cortex-A57 parts up to r1p2.

	  Affected Cortex-A57 parts might deadlock when exclusive load/store
	  instructions to Write-Back memory are mixed with Device loads.

	  The workaround is to promote device loads to use Load-Acquire
	  semantics.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337
config ARM64_ERRATUM_845719
	bool "Cortex-A53: 845719: a load might read incorrect data"
	depends on COMPAT
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 845719 on Cortex-A53 parts up to r0p4.

	  When running a compat (AArch32) userspace on an affected Cortex-A53
	  part, a load at EL0 from a virtual address that matches the bottom 32
	  bits of the virtual address used by a recent load at (AArch64) EL1
	  might return incorrect data.

	  The workaround is to write the contextidr_el1 register on exception
	  return to a 32-bit task.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353
config ARM64_ERRATUM_843419
	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
	depends on MODULES
	default y
	help
	  This option builds kernel modules using the large memory model in
	  order to avoid the use of the ADRP instruction, which can cause
	  a subsequent memory access to use an incorrect address on Cortex-A53
	  parts up to r0p4.

	  Note that the kernel itself must be linked with a version of ld
	  which fixes potentially affected ADRP instructions through the
	  use of veneers.

	  If unsure, say Y.

354 355 356
endmenu


357 358 359 360 361 362 363 364 365 366 367
choice
	prompt "Page size"
	default ARM64_4K_PAGES
	help
	  Page size (translation granule) configuration.

config ARM64_4K_PAGES
	bool "4KB"
	help
	  This feature enables 4KB pages support.

368 369 370 371 372 373 374
config ARM64_16K_PAGES
	bool "16KB"
	help
	  The system will use 16KB pages support. AArch32 emulation
	  requires applications compiled with 16K (or a multiple of 16K)
	  aligned segments.

C
Catalin Marinas 已提交
375
config ARM64_64K_PAGES
376
	bool "64KB"
C
Catalin Marinas 已提交
377 378 379
	help
	  This feature enables 64KB pages support (4KB by default)
	  allowing only two levels of page tables and faster TLB
380 381
	  look-up. AArch32 emulation requires applications compiled
	  with 64K aligned segments.
C
Catalin Marinas 已提交
382

383 384 385 386 387
endchoice

choice
	prompt "Virtual address space size"
	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
388
	default ARM64_VA_BITS_47 if ARM64_16K_PAGES
389 390 391 392 393 394
	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
	help
	  Allows choosing one of multiple possible virtual address
	  space sizes. The level of translation table is determined by
	  a combination of page size and virtual address space size.

S
Suzuki K. Poulose 已提交
395 396 397 398
config ARM64_VA_BITS_36
	bool "36-bit"
	depends on ARM64_16K_PAGES

399 400 401 402 403 404 405 406
config ARM64_VA_BITS_39
	bool "39-bit"
	depends on ARM64_4K_PAGES

config ARM64_VA_BITS_42
	bool "42-bit"
	depends on ARM64_64K_PAGES

407 408 409 410
config ARM64_VA_BITS_47
	bool "47-bit"
	depends on ARM64_16K_PAGES

411 412 413
config ARM64_VA_BITS_48
	bool "48-bit"

414 415 416 417
endchoice

config ARM64_VA_BITS
	int
S
Suzuki K. Poulose 已提交
418
	default 36 if ARM64_VA_BITS_36
419 420
	default 39 if ARM64_VA_BITS_39
	default 42 if ARM64_VA_BITS_42
421
	default 47 if ARM64_VA_BITS_47
422
	default 48 if ARM64_VA_BITS_48
423

424 425 426 427 428
config CPU_BIG_ENDIAN
       bool "Build big-endian kernel"
       help
         Say Y if you plan on running a kernel in big-endian mode.

429 430 431 432 433 434 435 436 437 438 439 440 441 442
config SCHED_MC
	bool "Multi-core scheduler support"
	help
	  Multi-core scheduler support improves the CPU scheduler's decision
	  making when dealing with multi-core CPU chips at a cost of slightly
	  increased overhead in some places. If unsure say N here.

config SCHED_SMT
	bool "SMT scheduler support"
	help
	  Improves the CPU scheduler's decision making when dealing with
	  MultiThreading at a cost of slightly increased overhead in some
	  places. If unsure say N here.

C
Catalin Marinas 已提交
443
config NR_CPUS
444 445
	int "Maximum number of CPUs (2-4096)"
	range 2 4096
446
	# These have to remain sorted largest to smallest
447
	default "64"
C
Catalin Marinas 已提交
448

449 450
config HOTPLUG_CPU
	bool "Support for hot-pluggable CPUs"
451
	select GENERIC_IRQ_MIGRATION
452 453 454 455
	help
	  Say Y here to experiment with turning CPUs off and on.  CPUs
	  can be controlled through /sys/devices/system/cpu.

C
Catalin Marinas 已提交
456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478
source kernel/Kconfig.preempt

config HZ
	int
	default 100

config ARCH_HAS_HOLES_MEMORYMODEL
	def_bool y if SPARSEMEM

config ARCH_SPARSEMEM_ENABLE
	def_bool y
	select SPARSEMEM_VMEMMAP_ENABLE

config ARCH_SPARSEMEM_DEFAULT
	def_bool ARCH_SPARSEMEM_ENABLE

config ARCH_SELECT_MEMORY_MODEL
	def_bool ARCH_SPARSEMEM_ENABLE

config HAVE_ARCH_PFN_VALID
	def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM

config HW_PERF_EVENTS
479 480
	def_bool y
	depends on ARM_PMU
C
Catalin Marinas 已提交
481

S
Steve Capper 已提交
482 483 484 485 486 487 488
config SYS_SUPPORTS_HUGETLBFS
	def_bool y

config ARCH_WANT_GENERAL_HUGETLB
	def_bool y

config ARCH_WANT_HUGE_PMD_SHARE
S
Suzuki K. Poulose 已提交
489
	def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
S
Steve Capper 已提交
490

S
Steve Capper 已提交
491 492 493
config HAVE_ARCH_TRANSPARENT_HUGEPAGE
	def_bool y

494 495 496
config ARCH_HAS_CACHE_LINE_SIZE
	def_bool y

C
Catalin Marinas 已提交
497 498
source "mm/Kconfig"

A
AKASHI Takahiro 已提交
499 500 501 502 503 504 505 506 507 508 509 510 511
config SECCOMP
	bool "Enable seccomp to safely compute untrusted bytecode"
	---help---
	  This kernel feature is useful for number crunching applications
	  that may need to compute untrusted bytecode during their
	  execution. By using pipes or other transports made available to
	  the process as file descriptors supporting the read/write
	  syscalls, it's possible to isolate those applications in
	  their own address space using seccomp. Once seccomp is
	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
	  and the task is only allowed to execute a few safe syscalls
	  defined by each seccomp mode.

512 513 514 515 516
config XEN_DOM0
	def_bool y
	depends on XEN

config XEN
517
	bool "Xen guest support on ARM64"
518
	depends on ARM64 && OF
519
	select SWIOTLB_XEN
520 521 522
	help
	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.

523 524 525
config FORCE_MAX_ZONEORDER
	int
	default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
526
	default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
527
	default "11"
528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544
	help
	  The kernel memory allocator divides physically contiguous memory
	  blocks into "zones", where each zone is a power of two number of
	  pages.  This option selects the largest power of two that the kernel
	  keeps in the memory allocator.  If you need to allocate very large
	  blocks of physically contiguous memory, then you may need to
	  increase this value.

	  This config option is actually maximum order plus one. For example,
	  a value of 11 means that the largest free memory block is 2^10 pages.

	  We make sure that we can allocate upto a HugePage size for each configuration.
	  Hence we have :
		MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2

	  However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
	  4M allocations matching the default size used by generic code.
545

546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595
menuconfig ARMV8_DEPRECATED
	bool "Emulate deprecated/obsolete ARMv8 instructions"
	depends on COMPAT
	help
	  Legacy software support may require certain instructions
	  that have been deprecated or obsoleted in the architecture.

	  Enable this config to enable selective emulation of these
	  features.

	  If unsure, say Y

if ARMV8_DEPRECATED

config SWP_EMULATION
	bool "Emulate SWP/SWPB instructions"
	help
	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
	  they are always undefined. Say Y here to enable software
	  emulation of these instructions for userspace using LDXR/STXR.

	  In some older versions of glibc [<=2.8] SWP is used during futex
	  trylock() operations with the assumption that the code will not
	  be preempted. This invalid assumption may be more likely to fail
	  with SWP emulation enabled, leading to deadlock of the user
	  application.

	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
	  on an external transaction monitoring block called a global
	  monitor to maintain update atomicity. If your system does not
	  implement a global monitor, this option can cause programs that
	  perform SWP operations to uncached memory to deadlock.

	  If unsure, say Y

config CP15_BARRIER_EMULATION
	bool "Emulate CP15 Barrier instructions"
	help
	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
	  strongly recommended to use the ISB, DSB, and DMB
	  instructions instead.

	  Say Y here to enable software emulation of these
	  instructions for AArch32 userspace code. When this option is
	  enabled, CP15 barrier usage is traced which can help
	  identify software that needs updating.

	  If unsure, say Y

596 597 598 599 600 601 602 603 604 605 606 607 608 609 610
config SETEND_EMULATION
	bool "Emulate SETEND instruction"
	help
	  The SETEND instruction alters the data-endianness of the
	  AArch32 EL0, and is deprecated in ARMv8.

	  Say Y here to enable software emulation of the instruction
	  for AArch32 userspace code.

	  Note: All the cpus on the system must have mixed endian support at EL0
	  for this feature to be enabled. If a new CPU - which doesn't support mixed
	  endian - is hotplugged in after this feature has been enabled, there could
	  be unexpected results in the applications.

	  If unsure, say Y
611 612
endif

613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659
menu "ARMv8.1 architectural features"

config ARM64_HW_AFDBM
	bool "Support for hardware updates of the Access and Dirty page flags"
	default y
	help
	  The ARMv8.1 architecture extensions introduce support for
	  hardware updates of the access and dirty information in page
	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
	  capable processors, accesses to pages with PTE_AF cleared will
	  set this bit instead of raising an access flag fault.
	  Similarly, writes to read-only pages with the DBM bit set will
	  clear the read-only bit (AP[2]) instead of raising a
	  permission fault.

	  Kernels built with this configuration option enabled continue
	  to work on pre-ARMv8.1 hardware and the performance impact is
	  minimal. If unsure, say Y.

config ARM64_PAN
	bool "Enable support for Privileged Access Never (PAN)"
	default y
	help
	 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
	 prevents the kernel or hypervisor from accessing user-space (EL0)
	 memory directly.

	 Choosing this option will cause any unprotected (not using
	 copy_to_user et al) memory access to fail with a permission fault.

	 The feature is detected at runtime, and will remain as a 'nop'
	 instruction if the cpu does not implement the feature.

config ARM64_LSE_ATOMICS
	bool "Atomic instructions"
	help
	  As part of the Large System Extensions, ARMv8.1 introduces new
	  atomic instructions that are designed specifically to scale in
	  very large systems.

	  Say Y here to make use of these instructions for the in-kernel
	  atomic routines. This incurs a small overhead on CPUs that do
	  not support these instructions and requires the kernel to be
	  built with binutils >= 2.25.

endmenu

C
Catalin Marinas 已提交
660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679
endmenu

menu "Boot options"

config CMDLINE
	string "Default kernel command string"
	default ""
	help
	  Provide a set of default command-line options at build time by
	  entering them here. As a minimum, you should specify the the
	  root device (e.g. root=/dev/nfs).

config CMDLINE_FORCE
	bool "Always use the default kernel command string"
	help
	  Always use the default kernel command string, even if the boot
	  loader passes other arguments to the kernel.
	  This is useful if you cannot or don't want to change the
	  command-line options your boot loader passes to the kernel.

680 681 682
config EFI_STUB
	bool

M
Mark Salter 已提交
683 684 685 686 687 688
config EFI
	bool "UEFI runtime support"
	depends on OF && !CPU_BIG_ENDIAN
	select LIBFDT
	select UCS2_STRING
	select EFI_PARAMS_FROM_FDT
689
	select EFI_RUNTIME_WRAPPERS
690 691
	select EFI_STUB
	select EFI_ARMSTUB
M
Mark Salter 已提交
692 693 694 695
	default y
	help
	  This option provides support for runtime services provided
	  by UEFI firmware (such as non-volatile variables, realtime
M
Mark Salter 已提交
696 697 698
          clock, and platform reset). A UEFI stub is also provided to
	  allow the kernel to be booted as an EFI application. This
	  is only useful on systems that have UEFI firmware.
M
Mark Salter 已提交
699

Y
Yi Li 已提交
700 701 702 703 704 705 706 707 708 709 710
config DMI
	bool "Enable support for SMBIOS (DMI) tables"
	depends on EFI
	default y
	help
	  This enables SMBIOS/DMI feature for systems.

	  This option is only useful on systems that have UEFI firmware.
	  However, even with this option, the resultant kernel should
	  continue to boot on existing non-UEFI platforms.

C
Catalin Marinas 已提交
711 712 713 714 715 716 717 718
endmenu

menu "Userspace binary formats"

source "fs/Kconfig.binfmt"

config COMPAT
	bool "Kernel support for 32-bit EL0"
719
	depends on ARM64_4K_PAGES || EXPERT
C
Catalin Marinas 已提交
720
	select COMPAT_BINFMT_ELF
721
	select HAVE_UID16
722
	select OLD_SIGSUSPEND3
723
	select COMPAT_OLD_SIGACTION
C
Catalin Marinas 已提交
724 725 726 727 728 729
	help
	  This option enables support for a 32-bit EL0 running under a 64-bit
	  kernel at EL1. AArch32-specific components such as system calls,
	  the user helper functions, VFP support and the ptrace interface are
	  handled appropriately by the kernel.

730 731 732
	  If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
	  that you will only be able to execute AArch32 binaries that were compiled
	  with page size aligned segments.
733

C
Catalin Marinas 已提交
734 735 736 737 738 739 740 741
	  If you want to execute 32-bit userspace applications, say Y.

config SYSVIPC_COMPAT
	def_bool y
	depends on COMPAT && SYSVIPC

endmenu

742 743 744 745 746 747 748 749 750
menu "Power management options"

source "kernel/power/Kconfig"

config ARCH_SUSPEND_POSSIBLE
	def_bool y

endmenu

751 752 753 754
menu "CPU Power Management"

source "drivers/cpuidle/Kconfig"

755 756 757 758
source "drivers/cpufreq/Kconfig"

endmenu

C
Catalin Marinas 已提交
759 760 761 762
source "net/Kconfig"

source "drivers/Kconfig"

M
Mark Salter 已提交
763 764
source "drivers/firmware/Kconfig"

765 766
source "drivers/acpi/Kconfig"

C
Catalin Marinas 已提交
767 768
source "fs/Kconfig"

M
Marc Zyngier 已提交
769 770
source "arch/arm64/kvm/Kconfig"

C
Catalin Marinas 已提交
771 772 773 774 775
source "arch/arm64/Kconfig.debug"

source "security/Kconfig"

source "crypto/Kconfig"
776 777 778
if CRYPTO
source "arch/arm64/crypto/Kconfig"
endif
C
Catalin Marinas 已提交
779 780

source "lib/Kconfig"