imx6qdl.dtsi 34.9 KB
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// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2011 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
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#include <dt-bindings/clock/imx6qdl-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>

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/ {
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	#address-cells = <1>;
	#size-cells = <1>;
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	/*
	 * The decompressor and also some bootloaders rely on a
	 * pre-existing /chosen node to be available to insert the
	 * command line and merge other ATAGS info.
	 * Also for U-Boot there must be a pre-existing /memory node.
	 */
	chosen {};
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	memory { device_type = "memory"; };
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	aliases {
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		ethernet0 = &fec;
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		can0 = &can1;
		can1 = &can2;
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		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		gpio6 = &gpio7;
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		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
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		ipu0 = &ipu1;
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		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		mmc3 = &usdhc4;
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		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		spi0 = &ecspi1;
		spi1 = &ecspi2;
		spi2 = &ecspi3;
		spi3 = &ecspi4;
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		usbphy0 = &usbphy1;
		usbphy1 = &usbphy2;
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	};

	clocks {
		ckil {
			compatible = "fsl,imx-ckil", "fixed-clock";
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			#clock-cells = <0>;
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			clock-frequency = <32768>;
		};

		ckih1 {
			compatible = "fsl,imx-ckih1", "fixed-clock";
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			#clock-cells = <0>;
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			clock-frequency = <0>;
		};

		osc {
			compatible = "fsl,imx-osc", "fixed-clock";
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			#clock-cells = <0>;
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			clock-frequency = <24000000>;
		};
	};

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	tempmon: tempmon {
		compatible = "fsl,imx6q-tempmon";
		interrupt-parent = <&gpc>;
		interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
		fsl,tempmon = <&anatop>;
		fsl,tempmon-data = <&ocotp>;
		clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
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		#thermal-sensor-cells = <0>;
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	};

	ldb: ldb {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
		gpr = <&gpr>;
		status = "disabled";

		lvds-channel@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
			status = "disabled";

			port@0 {
				reg = <0>;

				lvds0_mux_0: endpoint {
					remote-endpoint = <&ipu1_di0_lvds0>;
				};
			};

			port@1 {
				reg = <1>;

				lvds0_mux_1: endpoint {
					remote-endpoint = <&ipu1_di1_lvds0>;
				};
			};
		};

		lvds-channel@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
			status = "disabled";

			port@0 {
				reg = <0>;

				lvds1_mux_0: endpoint {
					remote-endpoint = <&ipu1_di0_lvds1>;
				};
			};

			port@1 {
				reg = <1>;

				lvds1_mux_1: endpoint {
					remote-endpoint = <&ipu1_di1_lvds1>;
				};
			};
		};
	};

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	pmu: pmu {
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		compatible = "arm,cortex-a9-pmu";
		interrupt-parent = <&gpc>;
		interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
	};

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	usbphynop1: usbphynop1 {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};

	usbphynop2: usbphynop2 {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};

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	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
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		interrupt-parent = <&gpc>;
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		ranges;

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		dma_apbh: dma-apbh@110000 {
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			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
			reg = <0x00110000 0x2000>;
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			interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
				     <0 13 IRQ_TYPE_LEVEL_HIGH>,
				     <0 13 IRQ_TYPE_LEVEL_HIGH>,
				     <0 13 IRQ_TYPE_LEVEL_HIGH>;
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			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
			#dma-cells = <1>;
			dma-channels = <4>;
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			clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
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		};

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		gpmi: gpmi-nand@112000 {
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			compatible = "fsl,imx6q-gpmi-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
			reg-names = "gpmi-nand", "bch";
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			interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
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			interrupt-names = "bch";
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			clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
				 <&clks IMX6QDL_CLK_GPMI_APB>,
				 <&clks IMX6QDL_CLK_GPMI_BCH>,
				 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
				 <&clks IMX6QDL_CLK_PER1_BCH>;
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			clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
				      "gpmi_bch_apb", "per1_bch";
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			dmas = <&dma_apbh 0>;
			dma-names = "rx-tx";
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			status = "disabled";
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		};

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		hdmi: hdmi@120000 {
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			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x00120000 0x9000>;
			interrupts = <0 115 0x04>;
			gpr = <&gpr>;
			clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
				 <&clks IMX6QDL_CLK_HDMI_ISFR>;
			clock-names = "iahb", "isfr";
			status = "disabled";

			port@0 {
				reg = <0>;

				hdmi_mux_0: endpoint {
					remote-endpoint = <&ipu1_di0_hdmi>;
				};
			};

			port@1 {
				reg = <1>;

				hdmi_mux_1: endpoint {
					remote-endpoint = <&ipu1_di1_hdmi>;
				};
			};
		};

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		gpu_3d: gpu@130000 {
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			compatible = "vivante,gc";
			reg = <0x00130000 0x4000>;
			interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
				 <&clks IMX6QDL_CLK_GPU3D_CORE>,
				 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
			clock-names = "bus", "core", "shader";
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			power-domains = <&pd_pu>;
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			#cooling-cells = <2>;
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		};

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		gpu_2d: gpu@134000 {
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			compatible = "vivante,gc";
			reg = <0x00134000 0x4000>;
			interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
				 <&clks IMX6QDL_CLK_GPU2D_CORE>;
			clock-names = "bus", "core";
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			power-domains = <&pd_pu>;
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			#cooling-cells = <2>;
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		};

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		timer@a00600 {
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			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x00a00600 0x20>;
			interrupts = <1 13 0xf01>;
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			interrupt-parent = <&intc>;
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			clocks = <&clks IMX6QDL_CLK_TWD>;
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		};

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		intc: interrupt-controller@a01000 {
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			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x00a01000 0x1000>,
			      <0x00a00100 0x100>;
			interrupt-parent = <&intc>;
		};

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		L2: l2-cache@a02000 {
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			compatible = "arm,pl310-cache";
			reg = <0x00a02000 0x1000>;
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			interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
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			cache-unified;
			cache-level = <2>;
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			arm,tag-latency = <4 2 3>;
			arm,data-latency = <4 2 3>;
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			arm,shared-override;
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		};

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		pcie: pcie@1ffc000 {
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			compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
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			reg = <0x01ffc000 0x04000>,
			      <0x01f00000 0x80000>;
			reg-names = "dbi", "config";
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			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
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			bus-range = <0x00 0xff>;
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			ranges = <0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
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				  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
			num-lanes = <1>;
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			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
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			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
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			interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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					<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
				 <&clks IMX6QDL_CLK_LVDS1_GATE>,
				 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
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			clock-names = "pcie", "pcie_bus", "pcie_phy";
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			status = "disabled";
		};

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		aips-bus@2000000 { /* AIPS1 */
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			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02000000 0x100000>;
			ranges;

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			spba-bus@2000000 {
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				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x02000000 0x40000>;
				ranges;

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				spdif: spdif@2004000 {
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					compatible = "fsl,imx35-spdif";
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					reg = <0x02004000 0x4000>;
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					interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
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					dmas = <&sdma 14 18 0>,
					       <&sdma 15 18 0>;
					dma-names = "rx", "tx";
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					clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
						 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
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						 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
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						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
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					clock-names = "core",  "rxtx0",
						      "rxtx1", "rxtx2",
						      "rxtx3", "rxtx4",
						      "rxtx5", "rxtx6",
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						      "rxtx7", "spba";
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					status = "disabled";
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				};

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				ecspi1: spi@2008000 {
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					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
					reg = <0x02008000 0x4000>;
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					interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
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					clocks = <&clks IMX6QDL_CLK_ECSPI1>,
						 <&clks IMX6QDL_CLK_ECSPI1>;
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					clock-names = "ipg", "per";
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					dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
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					dma-names = "rx", "tx";
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					status = "disabled";
				};

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				ecspi2: spi@200c000 {
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					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
					reg = <0x0200c000 0x4000>;
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					interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
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					clocks = <&clks IMX6QDL_CLK_ECSPI2>,
						 <&clks IMX6QDL_CLK_ECSPI2>;
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					clock-names = "ipg", "per";
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					dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
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					dma-names = "rx", "tx";
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					status = "disabled";
				};

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				ecspi3: spi@2010000 {
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					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
					reg = <0x02010000 0x4000>;
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					interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
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					clocks = <&clks IMX6QDL_CLK_ECSPI3>,
						 <&clks IMX6QDL_CLK_ECSPI3>;
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					clock-names = "ipg", "per";
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					dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
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					dma-names = "rx", "tx";
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					status = "disabled";
				};

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				ecspi4: spi@2014000 {
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					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
					reg = <0x02014000 0x4000>;
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					interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
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					clocks = <&clks IMX6QDL_CLK_ECSPI4>,
						 <&clks IMX6QDL_CLK_ECSPI4>;
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					clock-names = "ipg", "per";
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					dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
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					dma-names = "rx", "tx";
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					status = "disabled";
				};

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				uart1: serial@2020000 {
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					compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
					reg = <0x02020000 0x4000>;
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					interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
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					clocks = <&clks IMX6QDL_CLK_UART_IPG>,
						 <&clks IMX6QDL_CLK_UART_SERIAL>;
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					clock-names = "ipg", "per";
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					dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
					dma-names = "rx", "tx";
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					status = "disabled";
				};

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				esai: esai@2024000 {
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					#sound-dai-cells = <0>;
					compatible = "fsl,imx35-esai";
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					reg = <0x02024000 0x4000>;
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					interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
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					clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
						 <&clks IMX6QDL_CLK_ESAI_MEM>,
						 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
						 <&clks IMX6QDL_CLK_ESAI_IPG>,
						 <&clks IMX6QDL_CLK_SPBA>;
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					clock-names = "core", "mem", "extal", "fsys", "spba";
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					dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
					dma-names = "rx", "tx";
					status = "disabled";
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				};

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				ssi1: ssi@2028000 {
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					#sound-dai-cells = <0>;
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					compatible = "fsl,imx6q-ssi",
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							"fsl,imx51-ssi";
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					reg = <0x02028000 0x4000>;
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					interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
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					clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
						 <&clks IMX6QDL_CLK_SSI1>;
					clock-names = "ipg", "baud";
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					dmas = <&sdma 37 1 0>,
					       <&sdma 38 1 0>;
					dma-names = "rx", "tx";
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					fsl,fifo-depth = <15>;
					status = "disabled";
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				};

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				ssi2: ssi@202c000 {
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					#sound-dai-cells = <0>;
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					compatible = "fsl,imx6q-ssi",
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							"fsl,imx51-ssi";
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					reg = <0x0202c000 0x4000>;
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					interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
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					clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
						 <&clks IMX6QDL_CLK_SSI2>;
					clock-names = "ipg", "baud";
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					dmas = <&sdma 41 1 0>,
					       <&sdma 42 1 0>;
					dma-names = "rx", "tx";
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					fsl,fifo-depth = <15>;
					status = "disabled";
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				};

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				ssi3: ssi@2030000 {
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					#sound-dai-cells = <0>;
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					compatible = "fsl,imx6q-ssi",
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							"fsl,imx51-ssi";
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					reg = <0x02030000 0x4000>;
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					interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
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					clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
						 <&clks IMX6QDL_CLK_SSI3>;
					clock-names = "ipg", "baud";
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					dmas = <&sdma 45 1 0>,
					       <&sdma 46 1 0>;
					dma-names = "rx", "tx";
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					fsl,fifo-depth = <15>;
					status = "disabled";
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				};

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				asrc: asrc@2034000 {
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					compatible = "fsl,imx53-asrc";
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					reg = <0x02034000 0x4000>;
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					interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
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					clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
						<&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
						<&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
						<&clks IMX6QDL_CLK_SPBA>;
					clock-names = "mem", "ipg", "asrck_0",
						"asrck_1", "asrck_2", "asrck_3", "asrck_4",
						"asrck_5", "asrck_6", "asrck_7", "asrck_8",
						"asrck_9", "asrck_a", "asrck_b", "asrck_c",
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						"asrck_d", "asrck_e", "asrck_f", "spba";
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					dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
						<&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
					dma-names = "rxa", "rxb", "rxc",
							"txa", "txb", "txc";
					fsl,asrc-rate  = <48000>;
					fsl,asrc-width = <16>;
					status = "okay";
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				};

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				spba@203c000 {
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					reg = <0x0203c000 0x4000>;
				};
			};

495
			vpu: vpu@2040000 {
496
				compatible = "cnm,coda960";
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				reg = <0x02040000 0x3c000>;
498 499
				interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
					     <0 3 IRQ_TYPE_LEVEL_HIGH>;
500 501
				interrupt-names = "bit", "jpeg";
				clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
502 503
					 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
				clock-names = "per", "ahb";
504
				power-domains = <&pd_pu>;
505 506
				resets = <&src 1>;
				iram = <&ocram>;
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507 508
			};

509
			aipstz@207c000 { /* AIPSTZ1 */
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510 511 512
				reg = <0x0207c000 0x4000>;
			};

513
			pwm1: pwm@2080000 {
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				#pwm-cells = <2>;
				compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
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516
				reg = <0x02080000 0x4000>;
517
				interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
518 519
				clocks = <&clks IMX6QDL_CLK_IPG>,
					 <&clks IMX6QDL_CLK_PWM1>;
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				clock-names = "ipg", "per";
521
				status = "disabled";
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522 523
			};

524
			pwm2: pwm@2084000 {
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525 526
				#pwm-cells = <2>;
				compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
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527
				reg = <0x02084000 0x4000>;
528
				interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
529 530
				clocks = <&clks IMX6QDL_CLK_IPG>,
					 <&clks IMX6QDL_CLK_PWM2>;
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				clock-names = "ipg", "per";
532
				status = "disabled";
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533 534
			};

535
			pwm3: pwm@2088000 {
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536 537
				#pwm-cells = <2>;
				compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
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538
				reg = <0x02088000 0x4000>;
539
				interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
540 541
				clocks = <&clks IMX6QDL_CLK_IPG>,
					 <&clks IMX6QDL_CLK_PWM3>;
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				clock-names = "ipg", "per";
543
				status = "disabled";
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544 545
			};

546
			pwm4: pwm@208c000 {
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				#pwm-cells = <2>;
				compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
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549
				reg = <0x0208c000 0x4000>;
550
				interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
551 552
				clocks = <&clks IMX6QDL_CLK_IPG>,
					 <&clks IMX6QDL_CLK_PWM4>;
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553
				clock-names = "ipg", "per";
554
				status = "disabled";
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555 556
			};

557
			can1: flexcan@2090000 {
558
				compatible = "fsl,imx6q-flexcan";
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				reg = <0x02090000 0x4000>;
560
				interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
561 562
				clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
					 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
563
				clock-names = "ipg", "per";
564
				status = "disabled";
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			};

567
			can2: flexcan@2094000 {
568
				compatible = "fsl,imx6q-flexcan";
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569
				reg = <0x02094000 0x4000>;
570
				interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
571 572
				clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
					 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
573
				clock-names = "ipg", "per";
574
				status = "disabled";
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			};

577
			gpt: gpt@2098000 {
578
				compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
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				reg = <0x02098000 0x4000>;
580
				interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
581
				clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
582 583 584
					 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
					 <&clks IMX6QDL_CLK_GPT_3M>;
				clock-names = "ipg", "per", "osc_per";
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			};

587
			gpio1: gpio@209c000 {
588
				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
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				reg = <0x0209c000 0x4000>;
590 591
				interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
					     <0 67 IRQ_TYPE_LEVEL_HIGH>;
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				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
595
				#interrupt-cells = <2>;
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596 597
			};

598
			gpio2: gpio@20a0000 {
599
				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
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				reg = <0x020a0000 0x4000>;
601 602
				interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
					     <0 69 IRQ_TYPE_LEVEL_HIGH>;
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603 604 605
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
606
				#interrupt-cells = <2>;
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607 608
			};

609
			gpio3: gpio@20a4000 {
610
				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
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611
				reg = <0x020a4000 0x4000>;
612 613
				interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
					     <0 71 IRQ_TYPE_LEVEL_HIGH>;
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614 615 616
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
617
				#interrupt-cells = <2>;
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618 619
			};

620
			gpio4: gpio@20a8000 {
621
				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
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622
				reg = <0x020a8000 0x4000>;
623 624
				interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
					     <0 73 IRQ_TYPE_LEVEL_HIGH>;
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625 626 627
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
628
				#interrupt-cells = <2>;
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629 630
			};

631
			gpio5: gpio@20ac000 {
632
				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
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633
				reg = <0x020ac000 0x4000>;
634 635
				interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
					     <0 75 IRQ_TYPE_LEVEL_HIGH>;
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636 637 638
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
639
				#interrupt-cells = <2>;
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640 641
			};

642
			gpio6: gpio@20b0000 {
643
				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
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644
				reg = <0x020b0000 0x4000>;
645 646
				interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
					     <0 77 IRQ_TYPE_LEVEL_HIGH>;
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647 648 649
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
650
				#interrupt-cells = <2>;
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651 652
			};

653
			gpio7: gpio@20b4000 {
654
				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
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655
				reg = <0x020b4000 0x4000>;
656 657
				interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
					     <0 79 IRQ_TYPE_LEVEL_HIGH>;
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658 659 660
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
661
				#interrupt-cells = <2>;
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662 663
			};

664
			kpp: kpp@20b8000 {
665
				compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
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666
				reg = <0x020b8000 0x4000>;
667
				interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
668
				clocks = <&clks IMX6QDL_CLK_IPG>;
669
				status = "disabled";
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670 671
			};

672
			wdog1: wdog@20bc000 {
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673 674
				compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
				reg = <0x020bc000 0x4000>;
675
				interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
676
				clocks = <&clks IMX6QDL_CLK_DUMMY>;
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677 678
			};

679
			wdog2: wdog@20c0000 {
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680 681
				compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
				reg = <0x020c0000 0x4000>;
682
				interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
683
				clocks = <&clks IMX6QDL_CLK_DUMMY>;
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684 685 686
				status = "disabled";
			};

687
			clks: ccm@20c4000 {
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688 689
				compatible = "fsl,imx6q-ccm";
				reg = <0x020c4000 0x4000>;
690 691
				interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
					     <0 88 IRQ_TYPE_LEVEL_HIGH>;
692
				#clock-cells = <1>;
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693 694
			};

695
			anatop: anatop@20c8000 {
696
				compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
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				reg = <0x020c8000 0x1000>;
698 699 700
				interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
					     <0 54 IRQ_TYPE_LEVEL_HIGH>,
					     <0 127 IRQ_TYPE_LEVEL_HIGH>;
701

702
				regulator-1p1 {
703 704
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd1p1";
705 706
					regulator-min-microvolt = <1000000>;
					regulator-max-microvolt = <1200000>;
707 708 709 710 711 712 713
					regulator-always-on;
					anatop-reg-offset = <0x110>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <4>;
					anatop-min-voltage = <800000>;
					anatop-max-voltage = <1375000>;
714
					anatop-enable-bit = <0>;
715 716
				};

717
				regulator-3p0 {
718 719 720 721 722 723 724 725 726 727 728
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd3p0";
					regulator-min-microvolt = <2800000>;
					regulator-max-microvolt = <3150000>;
					regulator-always-on;
					anatop-reg-offset = <0x120>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <0>;
					anatop-min-voltage = <2625000>;
					anatop-max-voltage = <3400000>;
729
					anatop-enable-bit = <0>;
730 731
				};

732
				regulator-2p5 {
733 734
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd2p5";
735
					regulator-min-microvolt = <2250000>;
736 737 738 739 740 741
					regulator-max-microvolt = <2750000>;
					regulator-always-on;
					anatop-reg-offset = <0x130>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <0>;
742 743
					anatop-min-voltage = <2100000>;
					anatop-max-voltage = <2875000>;
744
					anatop-enable-bit = <0>;
745 746
				};

747
				reg_arm: regulator-vddcore {
748
					compatible = "fsl,anatop-regulator";
749
					regulator-name = "vddarm";
750 751 752 753 754 755
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					regulator-always-on;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <0>;
					anatop-vol-bit-width = <5>;
756 757 758
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <24>;
					anatop-delay-bit-width = <2>;
759 760 761 762 763
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};

764
				reg_pu: regulator-vddpu {
765 766 767 768
					compatible = "fsl,anatop-regulator";
					regulator-name = "vddpu";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
769
					regulator-enable-ramp-delay = <150>;
770 771 772
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <9>;
					anatop-vol-bit-width = <5>;
773 774 775
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <26>;
					anatop-delay-bit-width = <2>;
776 777 778 779 780
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};

781
				reg_soc: regulator-vddsoc {
782 783 784 785 786 787 788 789
					compatible = "fsl,anatop-regulator";
					regulator-name = "vddsoc";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					regulator-always-on;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <18>;
					anatop-vol-bit-width = <5>;
790 791 792
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <28>;
					anatop-delay-bit-width = <2>;
793 794 795 796
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};
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			};

799
			usbphy1: usbphy@20c9000 {
800
				compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
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801
				reg = <0x020c9000 0x1000>;
802
				interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
803
				clocks = <&clks IMX6QDL_CLK_USBPHY1>;
804
				fsl,anatop = <&anatop>;
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			};

807
			usbphy2: usbphy@20ca000 {
808
				compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
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				reg = <0x020ca000 0x1000>;
810
				interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
811
				clocks = <&clks IMX6QDL_CLK_USBPHY2>;
812
				fsl,anatop = <&anatop>;
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			};

815
			snvs: snvs@20cc000 {
816 817
				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
				reg = <0x020cc000 0x4000>;
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819
				snvs_rtc: snvs-rtc-lp {
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820
					compatible = "fsl,sec-v4.0-mon-rtc-lp";
821 822
					regmap = <&snvs>;
					offset = <0x34>;
823 824
					interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
						     <0 20 IRQ_TYPE_LEVEL_HIGH>;
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				};
826

827 828 829 830
				snvs_poweroff: snvs-poweroff {
					compatible = "syscon-poweroff";
					regmap = <&snvs>;
					offset = <0x38>;
831
					value = <0x60>;
832
					mask = <0x60>;
833 834
					status = "disabled";
				};
835 836 837 838

				snvs_lpgpr: snvs-lpgpr {
					compatible = "fsl,imx6q-snvs-lpgpr";
				};
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839 840
			};

841
			epit1: epit@20d0000 { /* EPIT1 */
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842
				reg = <0x020d0000 0x4000>;
843
				interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
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844 845
			};

846
			epit2: epit@20d4000 { /* EPIT2 */
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847
				reg = <0x020d4000 0x4000>;
848
				interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
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849 850
			};

851
			src: src@20d8000 {
852
				compatible = "fsl,imx6q-src", "fsl,imx51-src";
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				reg = <0x020d8000 0x4000>;
854 855
				interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
					     <0 96 IRQ_TYPE_LEVEL_HIGH>;
856
				#reset-cells = <1>;
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857 858
			};

859
			gpc: gpc@20dc000 {
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860 861
				compatible = "fsl,imx6q-gpc";
				reg = <0x020dc000 0x4000>;
862 863
				interrupt-controller;
				#interrupt-cells = <3>;
864 865
				interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
					     <0 90 IRQ_TYPE_LEVEL_HIGH>;
866
				interrupt-parent = <&intc>;
867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889
				clocks = <&clks IMX6QDL_CLK_IPG>;
				clock-names = "ipg";

				pgc {
					#address-cells = <1>;
					#size-cells = <0>;

					power-domain@0 {
						reg = <0>;
						#power-domain-cells = <0>;
					};
					pd_pu: power-domain@1 {
						reg = <1>;
						#power-domain-cells = <0>;
						power-supply = <&reg_pu>;
						clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
						         <&clks IMX6QDL_CLK_GPU3D_SHADER>,
						         <&clks IMX6QDL_CLK_GPU2D_CORE>,
						         <&clks IMX6QDL_CLK_GPU2D_AXI>,
						         <&clks IMX6QDL_CLK_OPENVG_AXI>,
						         <&clks IMX6QDL_CLK_VPU_AXI>;
					};
				};
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890 891
			};

892
			gpr: iomuxc-gpr@20e0000 {
893
				compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
894
				reg = <0x20e0000 0x38>;
895 896 897 898 899

				mux: mux-controller {
					compatible = "mmio-mux";
					#mux-control-cells = <1>;
				};
900 901
			};

902
			iomuxc: iomuxc@20e0000 {
903
				compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
904
				reg = <0x20e0000 0x4000>;
905 906
			};

907
			dcic1: dcic@20e4000 {
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				reg = <0x020e4000 0x4000>;
909
				interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
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910 911
			};

912
			dcic2: dcic@20e8000 {
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				reg = <0x020e8000 0x4000>;
914
				interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
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915 916
			};

917
			sdma: sdma@20ec000 {
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918 919
				compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
				reg = <0x020ec000 0x4000>;
920
				interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
921 922
				clocks = <&clks IMX6QDL_CLK_SDMA>,
					 <&clks IMX6QDL_CLK_SDMA>;
923
				clock-names = "ipg", "ahb";
924
				#dma-cells = <3>;
925
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
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926 927 928
			};
		};

929
		aips-bus@2100000 { /* AIPS2 */
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930 931 932 933 934 935
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02100000 0x100000>;
			ranges;

936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958
			crypto: caam@2100000 {
				compatible = "fsl,sec-v4.0";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x2100000 0x10000>;
				ranges = <0 0x2100000 0x10000>;
				clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
					 <&clks IMX6QDL_CLK_CAAM_ACLK>,
					 <&clks IMX6QDL_CLK_CAAM_IPG>,
					 <&clks IMX6QDL_CLK_EIM_SLOW>;
				clock-names = "mem", "aclk", "ipg", "emi_slow";

				sec_jr0: jr0@1000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x1000 0x1000>;
					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
				};

				sec_jr1: jr1@2000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x2000 0x1000>;
					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
				};
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959 960
			};

961
			aipstz@217c000 { /* AIPSTZ2 */
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962 963 964
				reg = <0x0217c000 0x4000>;
			};

965
			usbotg: usb@2184000 {
966 967
				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
				reg = <0x02184000 0x200>;
968
				interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
969
				clocks = <&clks IMX6QDL_CLK_USBOH3>;
970
				fsl,usbphy = <&usbphy1>;
971
				fsl,usbmisc = <&usbmisc 0>;
972
				ahb-burst-config = <0x0>;
973 974
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
975 976 977
				status = "disabled";
			};

978
			usbh1: usb@2184200 {
979 980
				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
				reg = <0x02184200 0x200>;
981
				interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
982
				clocks = <&clks IMX6QDL_CLK_USBOH3>;
983
				fsl,usbphy = <&usbphy2>;
984
				fsl,usbmisc = <&usbmisc 1>;
985
				dr_mode = "host";
986
				ahb-burst-config = <0x0>;
987 988
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
989 990 991
				status = "disabled";
			};

992
			usbh2: usb@2184400 {
993 994
				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
				reg = <0x02184400 0x200>;
995
				interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
996
				clocks = <&clks IMX6QDL_CLK_USBOH3>;
997 998
				fsl,usbphy = <&usbphynop1>;
				phy_type = "hsic";
999
				fsl,usbmisc = <&usbmisc 2>;
1000
				dr_mode = "host";
1001
				ahb-burst-config = <0x0>;
1002 1003
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
1004 1005 1006
				status = "disabled";
			};

1007
			usbh3: usb@2184600 {
1008 1009
				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
				reg = <0x02184600 0x200>;
1010
				interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1011
				clocks = <&clks IMX6QDL_CLK_USBOH3>;
1012 1013
				fsl,usbphy = <&usbphynop2>;
				phy_type = "hsic";
1014
				fsl,usbmisc = <&usbmisc 3>;
1015
				dr_mode = "host";
1016
				ahb-burst-config = <0x0>;
1017 1018
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
1019 1020 1021
				status = "disabled";
			};

1022
			usbmisc: usbmisc@2184800 {
1023 1024 1025
				#index-cells = <1>;
				compatible = "fsl,imx6q-usbmisc";
				reg = <0x02184800 0x200>;
1026
				clocks = <&clks IMX6QDL_CLK_USBOH3>;
1027 1028
			};

1029
			fec: ethernet@2188000 {
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1030 1031
				compatible = "fsl,imx6q-fec";
				reg = <0x02188000 0x4000>;
1032
				interrupt-names = "int0", "pps";
1033 1034 1035
				interrupts-extended =
					<&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
					<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
1036 1037 1038
				clocks = <&clks IMX6QDL_CLK_ENET>,
					 <&clks IMX6QDL_CLK_ENET>,
					 <&clks IMX6QDL_CLK_ENET_REF>;
1039
				clock-names = "ipg", "ahb", "ptp";
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1040 1041 1042
				status = "disabled";
			};

1043
			mlb@218c000 {
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1044
				reg = <0x0218c000 0x4000>;
1045 1046 1047
				interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
					     <0 117 IRQ_TYPE_LEVEL_HIGH>,
					     <0 126 IRQ_TYPE_LEVEL_HIGH>;
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1048 1049
			};

1050
			usdhc1: usdhc@2190000 {
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1051 1052
				compatible = "fsl,imx6q-usdhc";
				reg = <0x02190000 0x4000>;
1053
				interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1054 1055 1056
				clocks = <&clks IMX6QDL_CLK_USDHC1>,
					 <&clks IMX6QDL_CLK_USDHC1>,
					 <&clks IMX6QDL_CLK_USDHC1>;
1057
				clock-names = "ipg", "ahb", "per";
1058
				bus-width = <4>;
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1059 1060 1061
				status = "disabled";
			};

1062
			usdhc2: usdhc@2194000 {
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1063 1064
				compatible = "fsl,imx6q-usdhc";
				reg = <0x02194000 0x4000>;
1065
				interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1066 1067 1068
				clocks = <&clks IMX6QDL_CLK_USDHC2>,
					 <&clks IMX6QDL_CLK_USDHC2>,
					 <&clks IMX6QDL_CLK_USDHC2>;
1069
				clock-names = "ipg", "ahb", "per";
1070
				bus-width = <4>;
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1071 1072 1073
				status = "disabled";
			};

1074
			usdhc3: usdhc@2198000 {
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1075 1076
				compatible = "fsl,imx6q-usdhc";
				reg = <0x02198000 0x4000>;
1077
				interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1078 1079 1080
				clocks = <&clks IMX6QDL_CLK_USDHC3>,
					 <&clks IMX6QDL_CLK_USDHC3>,
					 <&clks IMX6QDL_CLK_USDHC3>;
1081
				clock-names = "ipg", "ahb", "per";
1082
				bus-width = <4>;
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1083 1084 1085
				status = "disabled";
			};

1086
			usdhc4: usdhc@219c000 {
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1087 1088
				compatible = "fsl,imx6q-usdhc";
				reg = <0x0219c000 0x4000>;
1089
				interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1090 1091 1092
				clocks = <&clks IMX6QDL_CLK_USDHC4>,
					 <&clks IMX6QDL_CLK_USDHC4>,
					 <&clks IMX6QDL_CLK_USDHC4>;
1093
				clock-names = "ipg", "ahb", "per";
1094
				bus-width = <4>;
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1095 1096 1097
				status = "disabled";
			};

1098
			i2c1: i2c@21a0000 {
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1099 1100
				#address-cells = <1>;
				#size-cells = <0>;
1101
				compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
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1102
				reg = <0x021a0000 0x4000>;
1103
				interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1104
				clocks = <&clks IMX6QDL_CLK_I2C1>;
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1105 1106 1107
				status = "disabled";
			};

1108
			i2c2: i2c@21a4000 {
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1109 1110
				#address-cells = <1>;
				#size-cells = <0>;
1111
				compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
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1112
				reg = <0x021a4000 0x4000>;
1113
				interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1114
				clocks = <&clks IMX6QDL_CLK_I2C2>;
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1115 1116 1117
				status = "disabled";
			};

1118
			i2c3: i2c@21a8000 {
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1119 1120
				#address-cells = <1>;
				#size-cells = <0>;
1121
				compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
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1122
				reg = <0x021a8000 0x4000>;
1123
				interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1124
				clocks = <&clks IMX6QDL_CLK_I2C3>;
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1125 1126 1127
				status = "disabled";
			};

1128
			romcp@21ac000 {
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1129 1130 1131
				reg = <0x021ac000 0x4000>;
			};

1132
			mmdc0: mmdc@21b0000 { /* MMDC0 */
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1133 1134
				compatible = "fsl,imx6q-mmdc";
				reg = <0x021b0000 0x4000>;
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1135
				clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
S
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1136 1137
			};

1138
			mmdc1: mmdc@21b4000 { /* MMDC1 */
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1139 1140 1141
				reg = <0x021b4000 0x4000>;
			};

1142
			weim: weim@21b8000 {
1143 1144
				#address-cells = <2>;
				#size-cells = <1>;
1145
				compatible = "fsl,imx6q-weim";
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1146
				reg = <0x021b8000 0x4000>;
1147
				interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1148
				clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1149
				fsl,weim-cs-gpr = <&gpr>;
1150
				status = "disabled";
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1151 1152
			};

1153
			ocotp: ocotp@21bc000 {
1154
				compatible = "fsl,imx6q-ocotp", "syscon";
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1155
				reg = <0x021bc000 0x4000>;
1156
				clocks = <&clks IMX6QDL_CLK_IIM>;
S
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1157 1158
			};

1159
			tzasc@21d0000 { /* TZASC1 */
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1160
				reg = <0x021d0000 0x4000>;
1161
				interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
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1162 1163
			};

1164
			tzasc@21d4000 { /* TZASC2 */
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1165
				reg = <0x021d4000 0x4000>;
1166
				interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
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1167 1168
			};

1169
			audmux: audmux@21d8000 {
1170
				compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
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1171
				reg = <0x021d8000 0x4000>;
1172
				status = "disabled";
S
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1173 1174
			};

1175
			mipi_csi: mipi@21dc000 {
1176
				compatible = "fsl,imx6-mipi-csi2";
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1177
				reg = <0x021dc000 0x4000>;
1178 1179
				#address-cells = <1>;
				#size-cells = <0>;
1180 1181 1182 1183 1184 1185
				interrupts = <0 100 0x04>, <0 101 0x04>;
				clocks = <&clks IMX6QDL_CLK_HSI_TX>,
					 <&clks IMX6QDL_CLK_VIDEO_27M>,
					 <&clks IMX6QDL_CLK_EIM_PODF>;
				clock-names = "dphy", "ref", "pix";
				status = "disabled";
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1186 1187
			};

1188
			mipi_dsi: mipi@21e0000 {
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1189
				reg = <0x021e0000 0x4000>;
1190 1191
				status = "disabled";

1192 1193 1194 1195 1196 1197
				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
1198

1199 1200 1201
						mipi_mux_0: endpoint {
							remote-endpoint = <&ipu1_di0_mipi>;
						};
1202 1203
					};

1204 1205
					port@1 {
						reg = <1>;
1206

1207 1208 1209
						mipi_mux_1: endpoint {
							remote-endpoint = <&ipu1_di1_mipi>;
						};
1210 1211
					};
				};
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1212 1213
			};

1214
			vdoa@21e4000 {
1215
				compatible = "fsl,imx6q-vdoa";
S
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1216
				reg = <0x021e4000 0x4000>;
1217
				interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1218
				clocks = <&clks IMX6QDL_CLK_VDOA>;
S
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1219 1220
			};

1221
			uart2: serial@21e8000 {
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1222 1223
				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021e8000 0x4000>;
1224
				interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1225 1226
				clocks = <&clks IMX6QDL_CLK_UART_IPG>,
					 <&clks IMX6QDL_CLK_UART_SERIAL>;
1227
				clock-names = "ipg", "per";
1228 1229
				dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
				dma-names = "rx", "tx";
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1230 1231 1232
				status = "disabled";
			};

1233
			uart3: serial@21ec000 {
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1234 1235
				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021ec000 0x4000>;
1236
				interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1237 1238
				clocks = <&clks IMX6QDL_CLK_UART_IPG>,
					 <&clks IMX6QDL_CLK_UART_SERIAL>;
1239
				clock-names = "ipg", "per";
1240 1241
				dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
				dma-names = "rx", "tx";
S
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1242 1243 1244
				status = "disabled";
			};

1245
			uart4: serial@21f0000 {
S
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1246 1247
				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021f0000 0x4000>;
1248
				interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1249 1250
				clocks = <&clks IMX6QDL_CLK_UART_IPG>,
					 <&clks IMX6QDL_CLK_UART_SERIAL>;
1251
				clock-names = "ipg", "per";
1252 1253
				dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
				dma-names = "rx", "tx";
S
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1254 1255 1256
				status = "disabled";
			};

1257
			uart5: serial@21f4000 {
S
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1258 1259
				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021f4000 0x4000>;
1260
				interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1261 1262
				clocks = <&clks IMX6QDL_CLK_UART_IPG>,
					 <&clks IMX6QDL_CLK_UART_SERIAL>;
1263
				clock-names = "ipg", "per";
1264 1265
				dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
				dma-names = "rx", "tx";
S
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1266 1267 1268
				status = "disabled";
			};
		};
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1269

1270
		ipu1: ipu@2400000 {
1271 1272
			#address-cells = <1>;
			#size-cells = <0>;
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1273 1274
			compatible = "fsl,imx6q-ipu";
			reg = <0x02400000 0x400000>;
1275 1276
			interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
				     <0 5 IRQ_TYPE_LEVEL_HIGH>;
1277 1278 1279
			clocks = <&clks IMX6QDL_CLK_IPU1>,
				 <&clks IMX6QDL_CLK_IPU1_DI0>,
				 <&clks IMX6QDL_CLK_IPU1_DI1>;
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1280
			clock-names = "bus", "di0", "di1";
1281
			resets = <&src 2>;
1282

1283 1284
			ipu1_csi0: port@0 {
				reg = <0>;
1285 1286 1287 1288

				ipu1_csi0_from_ipu1_csi0_mux: endpoint {
					remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
				};
1289 1290 1291 1292 1293 1294
			};

			ipu1_csi1: port@1 {
				reg = <1>;
			};

1295 1296 1297 1298 1299
			ipu1_di0: port@2 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <2>;

1300 1301
				ipu1_di0_disp0: endpoint@0 {
					reg = <0>;
1302 1303
				};

1304 1305
				ipu1_di0_hdmi: endpoint@1 {
					reg = <1>;
1306 1307 1308
					remote-endpoint = <&hdmi_mux_0>;
				};

1309 1310
				ipu1_di0_mipi: endpoint@2 {
					reg = <2>;
1311 1312 1313
					remote-endpoint = <&mipi_mux_0>;
				};

1314 1315
				ipu1_di0_lvds0: endpoint@3 {
					reg = <3>;
1316 1317 1318
					remote-endpoint = <&lvds0_mux_0>;
				};

1319 1320
				ipu1_di0_lvds1: endpoint@4 {
					reg = <4>;
1321 1322 1323 1324 1325 1326 1327 1328 1329
					remote-endpoint = <&lvds1_mux_0>;
				};
			};

			ipu1_di1: port@3 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <3>;

1330 1331
				ipu1_di1_disp1: endpoint@0 {
					reg = <0>;
1332 1333
				};

1334 1335
				ipu1_di1_hdmi: endpoint@1 {
					reg = <1>;
1336 1337 1338
					remote-endpoint = <&hdmi_mux_1>;
				};

1339 1340
				ipu1_di1_mipi: endpoint@2 {
					reg = <2>;
1341 1342 1343
					remote-endpoint = <&mipi_mux_1>;
				};

1344 1345
				ipu1_di1_lvds0: endpoint@3 {
					reg = <3>;
1346 1347 1348
					remote-endpoint = <&lvds0_mux_1>;
				};

1349 1350
				ipu1_di1_lvds1: endpoint@4 {
					reg = <4>;
1351 1352 1353
					remote-endpoint = <&lvds1_mux_1>;
				};
			};
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1354
		};
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1355 1356
	};
};