提交 bd3d924d 编写于 作者: P Philipp Zabel 提交者: Shawn Guo

ARM i.MX5: Add System Reset Controller (SRC) support for i.MX51 and i.MX53

The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus
the IPU2 reset line and multi core CPU reset/enable bits.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Reviewed-by: NPavel Machek <pavel@ucw.cz>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
上级 8d84c374
......@@ -520,7 +520,7 @@
};
src: src@020d8000 {
compatible = "fsl,imx6q-src";
compatible = "fsl,imx6q-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <0 91 0x04 0 96 0x04>;
#reset-cells = <1>;
......
......@@ -149,6 +149,7 @@ config SOC_IMX5
config SOC_IMX51
bool
select HAVE_IMX_SRC
select PINCTRL
select PINCTRL_IMX51
select SOC_IMX5
......@@ -774,6 +775,7 @@ comment "Device tree only"
config SOC_IMX53
bool "i.MX53 support"
select HAVE_CAN_FLEXCAN if CAN
select HAVE_IMX_SRC
select IMX_HAVE_PLATFORM_IMX2_WDT
select PINCTRL
select PINCTRL_IMX53
......
......@@ -84,6 +84,7 @@ void __init imx51_init_early(void)
mxc_set_cpu_type(MXC_CPU_MX51);
mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
imx_src_init();
}
void __init imx53_init_early(void)
......@@ -91,6 +92,7 @@ void __init imx53_init_early(void)
mxc_set_cpu_type(MXC_CPU_MX53);
mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
imx_src_init();
}
void __init mx51_init_irq(void)
......
......@@ -61,7 +61,9 @@ void __init imx_src_init(void)
struct device_node *np;
u32 val;
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src");
np = of_find_compatible_node(NULL, NULL, "fsl,imx51-src");
if (!np)
return;
src_base = of_iomap(np, 0);
WARN_ON(!src_base);
......
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