r8169.c 191.2 KB
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/*
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 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
 *
 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
 * Copyright (c) a lot of people too. Please respect their work.
 *
 * See MAINTAINERS file for support contact information.
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 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/if_vlan.h>
#include <linux/crc32.h>
#include <linux/in.h>
#include <linux/ip.h>
#include <linux/tcp.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/pm_runtime.h>
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#include <linux/firmware.h>
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#include <linux/pci-aspm.h>
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#include <linux/prefetch.h>
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#include <linux/ipv6.h>
#include <net/ip6_checksum.h>
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#include <asm/io.h>
#include <asm/irq.h>

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#define RTL8169_VERSION "2.3LK-NAPI"
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#define MODULENAME "r8169"
#define PFX MODULENAME ": "

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#define FIRMWARE_8168D_1	"rtl_nic/rtl8168d-1.fw"
#define FIRMWARE_8168D_2	"rtl_nic/rtl8168d-2.fw"
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#define FIRMWARE_8168E_1	"rtl_nic/rtl8168e-1.fw"
#define FIRMWARE_8168E_2	"rtl_nic/rtl8168e-2.fw"
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#define FIRMWARE_8168E_3	"rtl_nic/rtl8168e-3.fw"
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#define FIRMWARE_8168F_1	"rtl_nic/rtl8168f-1.fw"
#define FIRMWARE_8168F_2	"rtl_nic/rtl8168f-2.fw"
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#define FIRMWARE_8105E_1	"rtl_nic/rtl8105e-1.fw"
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#define FIRMWARE_8402_1		"rtl_nic/rtl8402-1.fw"
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#define FIRMWARE_8411_1		"rtl_nic/rtl8411-1.fw"
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#define FIRMWARE_8411_2		"rtl_nic/rtl8411-2.fw"
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#define FIRMWARE_8106E_1	"rtl_nic/rtl8106e-1.fw"
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#define FIRMWARE_8106E_2	"rtl_nic/rtl8106e-2.fw"
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#define FIRMWARE_8168G_2	"rtl_nic/rtl8168g-2.fw"
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#define FIRMWARE_8168G_3	"rtl_nic/rtl8168g-3.fw"
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#define FIRMWARE_8168H_1	"rtl_nic/rtl8168h-1.fw"
#define FIRMWARE_8168H_2	"rtl_nic/rtl8168h-2.fw"
#define FIRMWARE_8107E_1	"rtl_nic/rtl8107e-1.fw"
#define FIRMWARE_8107E_2	"rtl_nic/rtl8107e-2.fw"
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#ifdef RTL8169_DEBUG
#define assert(expr) \
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	if (!(expr)) {					\
		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\
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		#expr,__FILE__,__func__,__LINE__);		\
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	}
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#define dprintk(fmt, args...) \
	do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
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#else
#define assert(expr) do {} while (0)
#define dprintk(fmt, args...)	do {} while (0)
#endif /* RTL8169_DEBUG */

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#define R8169_MSG_DEFAULT \
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	(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
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#define TX_SLOTS_AVAIL(tp) \
	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)

/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
#define TX_FRAGS_READY_FOR(tp,nr_frags) \
	(TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
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/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
   The RTL chips use a 64 element hash table based on the Ethernet CRC. */
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static const int multicast_filter_limit = 32;
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#define MAX_READ_REQUEST_SHIFT	12
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#define TX_DMA_BURST	7	/* Maximum PCI burst, '7' is unlimited */
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#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */

#define R8169_REGS_SIZE		256
#define R8169_NAPI_WEIGHT	64
#define NUM_TX_DESC	64	/* Number of Tx descriptor registers */
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#define NUM_RX_DESC	256U	/* Number of Rx descriptor registers */
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#define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))
#define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))

#define RTL8169_TX_TIMEOUT	(6*HZ)
#define RTL8169_PHY_TIMEOUT	(10*HZ)

/* write/read MMIO register */
#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))
#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))
#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))
#define RTL_R8(reg)		readb (ioaddr + (reg))
#define RTL_R16(reg)		readw (ioaddr + (reg))
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#define RTL_R32(reg)		readl (ioaddr + (reg))
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enum mac_version {
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	RTL_GIGA_MAC_VER_01 = 0,
	RTL_GIGA_MAC_VER_02,
	RTL_GIGA_MAC_VER_03,
	RTL_GIGA_MAC_VER_04,
	RTL_GIGA_MAC_VER_05,
	RTL_GIGA_MAC_VER_06,
	RTL_GIGA_MAC_VER_07,
	RTL_GIGA_MAC_VER_08,
	RTL_GIGA_MAC_VER_09,
	RTL_GIGA_MAC_VER_10,
	RTL_GIGA_MAC_VER_11,
	RTL_GIGA_MAC_VER_12,
	RTL_GIGA_MAC_VER_13,
	RTL_GIGA_MAC_VER_14,
	RTL_GIGA_MAC_VER_15,
	RTL_GIGA_MAC_VER_16,
	RTL_GIGA_MAC_VER_17,
	RTL_GIGA_MAC_VER_18,
	RTL_GIGA_MAC_VER_19,
	RTL_GIGA_MAC_VER_20,
	RTL_GIGA_MAC_VER_21,
	RTL_GIGA_MAC_VER_22,
	RTL_GIGA_MAC_VER_23,
	RTL_GIGA_MAC_VER_24,
	RTL_GIGA_MAC_VER_25,
	RTL_GIGA_MAC_VER_26,
	RTL_GIGA_MAC_VER_27,
	RTL_GIGA_MAC_VER_28,
	RTL_GIGA_MAC_VER_29,
	RTL_GIGA_MAC_VER_30,
	RTL_GIGA_MAC_VER_31,
	RTL_GIGA_MAC_VER_32,
	RTL_GIGA_MAC_VER_33,
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	RTL_GIGA_MAC_VER_34,
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	RTL_GIGA_MAC_VER_35,
	RTL_GIGA_MAC_VER_36,
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	RTL_GIGA_MAC_VER_37,
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	RTL_GIGA_MAC_VER_38,
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	RTL_GIGA_MAC_VER_39,
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	RTL_GIGA_MAC_VER_40,
	RTL_GIGA_MAC_VER_41,
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	RTL_GIGA_MAC_VER_42,
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	RTL_GIGA_MAC_VER_43,
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	RTL_GIGA_MAC_VER_44,
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	RTL_GIGA_MAC_VER_45,
	RTL_GIGA_MAC_VER_46,
	RTL_GIGA_MAC_VER_47,
	RTL_GIGA_MAC_VER_48,
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	RTL_GIGA_MAC_NONE   = 0xff,
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};

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enum rtl_tx_desc_version {
	RTL_TD_0	= 0,
	RTL_TD_1	= 1,
};

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#define JUMBO_1K	ETH_DATA_LEN
#define JUMBO_4K	(4*1024 - ETH_HLEN - 2)
#define JUMBO_6K	(6*1024 - ETH_HLEN - 2)
#define JUMBO_7K	(7*1024 - ETH_HLEN - 2)
#define JUMBO_9K	(9*1024 - ETH_HLEN - 2)

#define _R(NAME,TD,FW,SZ,B) {	\
	.name = NAME,		\
	.txd_version = TD,	\
	.fw_name = FW,		\
	.jumbo_max = SZ,	\
	.jumbo_tx_csum = B	\
}
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static const struct {
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	const char *name;
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	enum rtl_tx_desc_version txd_version;
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	const char *fw_name;
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	u16 jumbo_max;
	bool jumbo_tx_csum;
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} rtl_chip_infos[] = {
	/* PCI devices. */
	[RTL_GIGA_MAC_VER_01] =
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		_R("RTL8169",		RTL_TD_0, NULL, JUMBO_7K, true),
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	[RTL_GIGA_MAC_VER_02] =
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		_R("RTL8169s",		RTL_TD_0, NULL, JUMBO_7K, true),
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	[RTL_GIGA_MAC_VER_03] =
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		_R("RTL8110s",		RTL_TD_0, NULL, JUMBO_7K, true),
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	[RTL_GIGA_MAC_VER_04] =
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		_R("RTL8169sb/8110sb",	RTL_TD_0, NULL, JUMBO_7K, true),
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	[RTL_GIGA_MAC_VER_05] =
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		_R("RTL8169sc/8110sc",	RTL_TD_0, NULL, JUMBO_7K, true),
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	[RTL_GIGA_MAC_VER_06] =
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		_R("RTL8169sc/8110sc",	RTL_TD_0, NULL, JUMBO_7K, true),
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	/* PCI-E devices. */
	[RTL_GIGA_MAC_VER_07] =
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		_R("RTL8102e",		RTL_TD_1, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_08] =
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		_R("RTL8102e",		RTL_TD_1, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_09] =
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		_R("RTL8102e",		RTL_TD_1, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_10] =
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		_R("RTL8101e",		RTL_TD_0, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_11] =
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		_R("RTL8168b/8111b",	RTL_TD_0, NULL, JUMBO_4K, false),
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	[RTL_GIGA_MAC_VER_12] =
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		_R("RTL8168b/8111b",	RTL_TD_0, NULL, JUMBO_4K, false),
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	[RTL_GIGA_MAC_VER_13] =
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		_R("RTL8101e",		RTL_TD_0, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_14] =
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		_R("RTL8100e",		RTL_TD_0, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_15] =
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		_R("RTL8100e",		RTL_TD_0, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_16] =
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		_R("RTL8101e",		RTL_TD_0, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_17] =
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		_R("RTL8168b/8111b",	RTL_TD_0, NULL, JUMBO_4K, false),
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	[RTL_GIGA_MAC_VER_18] =
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		_R("RTL8168cp/8111cp",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_19] =
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		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_20] =
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		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_21] =
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		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_22] =
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		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_23] =
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		_R("RTL8168cp/8111cp",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_24] =
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		_R("RTL8168cp/8111cp",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_25] =
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		_R("RTL8168d/8111d",	RTL_TD_1, FIRMWARE_8168D_1,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_26] =
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		_R("RTL8168d/8111d",	RTL_TD_1, FIRMWARE_8168D_2,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_27] =
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		_R("RTL8168dp/8111dp",	RTL_TD_1, NULL, JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_28] =
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		_R("RTL8168dp/8111dp",	RTL_TD_1, NULL, JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_29] =
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		_R("RTL8105e",		RTL_TD_1, FIRMWARE_8105E_1,
							JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_30] =
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		_R("RTL8105e",		RTL_TD_1, FIRMWARE_8105E_1,
							JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_31] =
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		_R("RTL8168dp/8111dp",	RTL_TD_1, NULL, JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_32] =
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		_R("RTL8168e/8111e",	RTL_TD_1, FIRMWARE_8168E_1,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_33] =
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		_R("RTL8168e/8111e",	RTL_TD_1, FIRMWARE_8168E_2,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_34] =
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		_R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_35] =
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		_R("RTL8168f/8111f",	RTL_TD_1, FIRMWARE_8168F_1,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_36] =
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		_R("RTL8168f/8111f",	RTL_TD_1, FIRMWARE_8168F_2,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_37] =
		_R("RTL8402",		RTL_TD_1, FIRMWARE_8402_1,
							JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_38] =
		_R("RTL8411",		RTL_TD_1, FIRMWARE_8411_1,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_39] =
		_R("RTL8106e",		RTL_TD_1, FIRMWARE_8106E_1,
							JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_40] =
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		_R("RTL8168g/8111g",	RTL_TD_1, FIRMWARE_8168G_2,
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							JUMBO_9K, false),
	[RTL_GIGA_MAC_VER_41] =
		_R("RTL8168g/8111g",	RTL_TD_1, NULL, JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_42] =
		_R("RTL8168g/8111g",	RTL_TD_1, FIRMWARE_8168G_3,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_43] =
		_R("RTL8106e",		RTL_TD_1, FIRMWARE_8106E_2,
							JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_44] =
		_R("RTL8411",		RTL_TD_1, FIRMWARE_8411_2,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_45] =
		_R("RTL8168h/8111h",	RTL_TD_1, FIRMWARE_8168H_1,
							JUMBO_9K, false),
	[RTL_GIGA_MAC_VER_46] =
		_R("RTL8168h/8111h",	RTL_TD_1, FIRMWARE_8168H_2,
							JUMBO_9K, false),
	[RTL_GIGA_MAC_VER_47] =
		_R("RTL8107e",		RTL_TD_1, FIRMWARE_8107E_1,
							JUMBO_1K, false),
	[RTL_GIGA_MAC_VER_48] =
		_R("RTL8107e",		RTL_TD_1, FIRMWARE_8107E_2,
							JUMBO_1K, false),
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};
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#undef _R
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enum cfg_version {
	RTL_CFG_0 = 0x00,
	RTL_CFG_1,
	RTL_CFG_2
};

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static const struct pci_device_id rtl8169_pci_tbl[] = {
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_2 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_0 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_1 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },
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	{ PCI_VENDOR_ID_DLINK,			0x4300,
		PCI_VENDOR_ID_DLINK, 0x4b10,		 0, 0, RTL_CFG_1 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4302), 0, 0, RTL_CFG_0 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_AT,		0xc107), 0, 0, RTL_CFG_0 },
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	{ PCI_DEVICE(0x16ec,			0x0116), 0, 0, RTL_CFG_0 },
	{ PCI_VENDOR_ID_LINKSYS,		0x1032,
		PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
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	{ 0x0001,				0x8168,
		PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
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	{0,},
};

MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);

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static int rx_buf_sz = 16383;
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static int use_dac;
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static struct {
	u32 msg_enable;
} debug = { -1 };
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enum rtl_registers {
	MAC0		= 0,	/* Ethernet hardware address. */
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	MAC4		= 4,
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	MAR0		= 8,	/* Multicast filter. */
	CounterAddrLow		= 0x10,
	CounterAddrHigh		= 0x14,
	TxDescStartAddrLow	= 0x20,
	TxDescStartAddrHigh	= 0x24,
	TxHDescStartAddrLow	= 0x28,
	TxHDescStartAddrHigh	= 0x2c,
	FLASH		= 0x30,
	ERSR		= 0x36,
	ChipCmd		= 0x37,
	TxPoll		= 0x38,
	IntrMask	= 0x3c,
	IntrStatus	= 0x3e,
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	TxConfig	= 0x40,
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#define	TXCFG_AUTO_FIFO			(1 << 7)	/* 8111e-vl */
#define	TXCFG_EMPTY			(1 << 11)	/* 8111e-vl */
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	RxConfig	= 0x44,
#define	RX128_INT_EN			(1 << 15)	/* 8111c and later */
#define	RX_MULTI_EN			(1 << 14)	/* 8111c only */
#define	RXCFG_FIFO_SHIFT		13
					/* No threshold before first PCI xfer */
#define	RX_FIFO_THRESH			(7 << RXCFG_FIFO_SHIFT)
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#define	RX_EARLY_OFF			(1 << 11)
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#define	RXCFG_DMA_SHIFT			8
					/* Unlimited maximum PCI burst. */
#define	RX_DMA_BURST			(7 << RXCFG_DMA_SHIFT)
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	RxMissed	= 0x4c,
	Cfg9346		= 0x50,
	Config0		= 0x51,
	Config1		= 0x52,
	Config2		= 0x53,
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#define PME_SIGNAL			(1 << 5)	/* 8168c and later */

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	Config3		= 0x54,
	Config4		= 0x55,
	Config5		= 0x56,
	MultiIntr	= 0x5c,
	PHYAR		= 0x60,
	PHYstatus	= 0x6c,
	RxMaxSize	= 0xda,
	CPlusCmd	= 0xe0,
	IntrMitigate	= 0xe2,
	RxDescAddrLow	= 0xe4,
	RxDescAddrHigh	= 0xe8,
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	EarlyTxThres	= 0xec,	/* 8169. Unit of 32 bytes. */

#define NoEarlyTx	0x3f	/* Max value : no early transmit. */

	MaxTxPacketSize	= 0xec,	/* 8101/8168. Unit of 128 bytes. */

#define TxPacketMax	(8064 >> 7)
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#define EarlySize	0x27
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	FuncEvent	= 0xf0,
	FuncEventMask	= 0xf4,
	FuncPresetState	= 0xf8,
	FuncForceEvent	= 0xfc,
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};

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enum rtl8110_registers {
	TBICSR			= 0x64,
	TBI_ANAR		= 0x68,
	TBI_LPAR		= 0x6a,
};

enum rtl8168_8101_registers {
	CSIDR			= 0x64,
	CSIAR			= 0x68,
#define	CSIAR_FLAG			0x80000000
#define	CSIAR_WRITE_CMD			0x80000000
#define	CSIAR_BYTE_ENABLE		0x0f
#define	CSIAR_BYTE_ENABLE_SHIFT		12
#define	CSIAR_ADDR_MASK			0x0fff
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#define CSIAR_FUNC_CARD			0x00000000
#define CSIAR_FUNC_SDIO			0x00010000
#define CSIAR_FUNC_NIC			0x00020000
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#define CSIAR_FUNC_NIC2			0x00010000
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	PMCH			= 0x6f,
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	EPHYAR			= 0x80,
#define	EPHYAR_FLAG			0x80000000
#define	EPHYAR_WRITE_CMD		0x80000000
#define	EPHYAR_REG_MASK			0x1f
#define	EPHYAR_REG_SHIFT		16
#define	EPHYAR_DATA_MASK		0xffff
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	DLLPR			= 0xd0,
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#define	PFM_EN				(1 << 6)
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#define	TX_10M_PS_EN			(1 << 7)
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	DBG_REG			= 0xd1,
#define	FIX_NAK_1			(1 << 4)
#define	FIX_NAK_2			(1 << 3)
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	TWSI			= 0xd2,
	MCU			= 0xd3,
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#define	NOW_IS_OOB			(1 << 7)
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#define	TX_EMPTY			(1 << 5)
#define	RX_EMPTY			(1 << 4)
#define	RXTX_EMPTY			(TX_EMPTY | RX_EMPTY)
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#define	EN_NDP				(1 << 3)
#define	EN_OOB_RESET			(1 << 2)
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#define	LINK_LIST_RDY			(1 << 1)
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	EFUSEAR			= 0xdc,
#define	EFUSEAR_FLAG			0x80000000
#define	EFUSEAR_WRITE_CMD		0x80000000
#define	EFUSEAR_READ_CMD		0x00000000
#define	EFUSEAR_REG_MASK		0x03ff
#define	EFUSEAR_REG_SHIFT		8
#define	EFUSEAR_DATA_MASK		0xff
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	MISC_1			= 0xf2,
#define	PFM_D3COLD_EN			(1 << 6)
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};

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enum rtl8168_registers {
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	LED_FREQ		= 0x1a,
	EEE_LED			= 0x1b,
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	ERIDR			= 0x70,
	ERIAR			= 0x74,
#define ERIAR_FLAG			0x80000000
#define ERIAR_WRITE_CMD			0x80000000
#define ERIAR_READ_CMD			0x00000000
#define ERIAR_ADDR_BYTE_ALIGN		4
#define ERIAR_TYPE_SHIFT		16
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#define ERIAR_EXGMAC			(0x00 << ERIAR_TYPE_SHIFT)
#define ERIAR_MSIX			(0x01 << ERIAR_TYPE_SHIFT)
#define ERIAR_ASF			(0x02 << ERIAR_TYPE_SHIFT)
#define ERIAR_MASK_SHIFT		12
#define ERIAR_MASK_0001			(0x1 << ERIAR_MASK_SHIFT)
#define ERIAR_MASK_0011			(0x3 << ERIAR_MASK_SHIFT)
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#define ERIAR_MASK_0100			(0x4 << ERIAR_MASK_SHIFT)
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#define ERIAR_MASK_0101			(0x5 << ERIAR_MASK_SHIFT)
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#define ERIAR_MASK_1111			(0xf << ERIAR_MASK_SHIFT)
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	EPHY_RXER_NUM		= 0x7c,
	OCPDR			= 0xb0,	/* OCP GPHY access */
#define OCPDR_WRITE_CMD			0x80000000
#define OCPDR_READ_CMD			0x00000000
#define OCPDR_REG_MASK			0x7f
#define OCPDR_GPHY_REG_SHIFT		16
#define OCPDR_DATA_MASK			0xffff
	OCPAR			= 0xb4,
#define OCPAR_FLAG			0x80000000
#define OCPAR_GPHY_WRITE_CMD		0x8000f060
#define OCPAR_GPHY_READ_CMD		0x0000f060
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	GPHY_OCP		= 0xb8,
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	RDSAR1			= 0xd0,	/* 8168c only. Undocumented on 8168dp */
	MISC			= 0xf0,	/* 8168e only. */
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#define TXPLA_RST			(1 << 29)
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#define DISABLE_LAN_EN			(1 << 23) /* Enable GPIO pin */
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#define PWM_EN				(1 << 22)
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#define RXDV_GATED_EN			(1 << 19)
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#define EARLY_TALLY_EN			(1 << 16)
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};

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enum rtl_register_content {
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	/* InterruptStatusBits */
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	SYSErr		= 0x8000,
	PCSTimeout	= 0x4000,
	SWInt		= 0x0100,
	TxDescUnavail	= 0x0080,
	RxFIFOOver	= 0x0040,
	LinkChg		= 0x0020,
	RxOverflow	= 0x0010,
	TxErr		= 0x0008,
	TxOK		= 0x0004,
	RxErr		= 0x0002,
	RxOK		= 0x0001,
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	/* RxStatusDesc */
512
	RxBOVF	= (1 << 24),
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	RxFOVF	= (1 << 23),
	RxRWT	= (1 << 22),
	RxRES	= (1 << 21),
	RxRUNT	= (1 << 20),
	RxCRC	= (1 << 19),
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	/* ChipCmdBits */
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	StopReq		= 0x80,
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	CmdReset	= 0x10,
	CmdRxEnb	= 0x08,
	CmdTxEnb	= 0x04,
	RxBufEmpty	= 0x01,
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	/* TXPoll register p.5 */
	HPQ		= 0x80,		/* Poll cmd on the high prio queue */
	NPQ		= 0x40,		/* Poll cmd on the low prio queue */
	FSWInt		= 0x01,		/* Forced software interrupt */

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	/* Cfg9346Bits */
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	Cfg9346_Lock	= 0x00,
	Cfg9346_Unlock	= 0xc0,
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	/* rx_mode_bits */
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	AcceptErr	= 0x20,
	AcceptRunt	= 0x10,
	AcceptBroadcast	= 0x08,
	AcceptMulticast	= 0x04,
	AcceptMyPhys	= 0x02,
	AcceptAllPhys	= 0x01,
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#define RX_CONFIG_ACCEPT_MASK		0x3f
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	/* TxConfigBits */
	TxInterFrameGapShift = 24,
	TxDMAShift = 8,	/* DMA burst value (0-7) is shift this many bits */

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	/* Config1 register p.24 */
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	LEDS1		= (1 << 7),
	LEDS0		= (1 << 6),
	Speed_down	= (1 << 4),
	MEMMAP		= (1 << 3),
	IOMAP		= (1 << 2),
	VPD		= (1 << 1),
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	PMEnable	= (1 << 0),	/* Power Management Enable */

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	/* Config2 register p. 25 */
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	ClkReqEn	= (1 << 7),	/* Clock Request Enable */
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	MSIEnable	= (1 << 5),	/* 8169 only. Reserved in the 8168. */
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	PCI_Clock_66MHz = 0x01,
	PCI_Clock_33MHz = 0x00,

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	/* Config3 register p.25 */
	MagicPacket	= (1 << 5),	/* Wake up when receives a Magic Packet */
	LinkUp		= (1 << 4),	/* Wake up when the cable connection is re-established */
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	Jumbo_En0	= (1 << 2),	/* 8168 only. Reserved in the 8168b */
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	Rdy_to_L23	= (1 << 1),	/* L23 Enable */
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	Beacon_en	= (1 << 0),	/* 8168 only. Reserved in the 8168b */
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	/* Config4 register */
	Jumbo_En1	= (1 << 1),	/* 8168 only. Reserved in the 8168b */

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	/* Config5 register p.27 */
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	BWF		= (1 << 6),	/* Accept Broadcast wakeup frame */
	MWF		= (1 << 5),	/* Accept Multicast wakeup frame */
	UWF		= (1 << 4),	/* Accept Unicast wakeup frame */
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	Spi_en		= (1 << 3),
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	LanWake		= (1 << 1),	/* LanWake enable/disable */
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	PMEStatus	= (1 << 0),	/* PME status can be reset by PCI RST# */
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	ASPM_en		= (1 << 0),	/* ASPM enable */
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	/* TBICSR p.28 */
	TBIReset	= 0x80000000,
	TBILoopback	= 0x40000000,
	TBINwEnable	= 0x20000000,
	TBINwRestart	= 0x10000000,
	TBILinkOk	= 0x02000000,
	TBINwComplete	= 0x01000000,

	/* CPlusCmd p.31 */
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	EnableBist	= (1 << 15),	// 8168 8101
	Mac_dbgo_oe	= (1 << 14),	// 8168 8101
	Normal_mode	= (1 << 13),	// unused
	Force_half_dup	= (1 << 12),	// 8168 8101
	Force_rxflow_en	= (1 << 11),	// 8168 8101
	Force_txflow_en	= (1 << 10),	// 8168 8101
	Cxpl_dbg_sel	= (1 << 9),	// 8168 8101
	ASF		= (1 << 8),	// 8168 8101
	PktCntrDisable	= (1 << 7),	// 8168 8101
	Mac_dbgo_sel	= 0x001c,	// 8168
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	RxVlan		= (1 << 6),
	RxChkSum	= (1 << 5),
	PCIDAC		= (1 << 4),
	PCIMulRW	= (1 << 3),
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	INTT_0		= 0x0000,	// 8168
	INTT_1		= 0x0001,	// 8168
	INTT_2		= 0x0002,	// 8168
	INTT_3		= 0x0003,	// 8168
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	/* rtl8169_PHYstatus */
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	TBI_Enable	= 0x80,
	TxFlowCtrl	= 0x40,
	RxFlowCtrl	= 0x20,
	_1000bpsF	= 0x10,
	_100bps		= 0x08,
	_10bps		= 0x04,
	LinkStatus	= 0x02,
	FullDup		= 0x01,
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	/* _TBICSRBit */
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	TBILinkOK	= 0x02000000,
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	/* DumpCounterCommand */
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	CounterDump	= 0x8,
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	/* magic enable v2 */
	MagicPacket_v2	= (1 << 16),	/* Wake up when receives a Magic Packet */
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};

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enum rtl_desc_bit {
	/* First doubleword. */
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	DescOwn		= (1 << 31), /* Descriptor is owned by NIC */
	RingEnd		= (1 << 30), /* End of descriptor ring */
	FirstFrag	= (1 << 29), /* First segment of a packet */
	LastFrag	= (1 << 28), /* Final segment of a packet */
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};

/* Generic case. */
enum rtl_tx_desc_bit {
	/* First doubleword. */
	TD_LSO		= (1 << 27),		/* Large Send Offload */
#define TD_MSS_MAX			0x07ffu	/* MSS value */
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	/* Second doubleword. */
	TxVlanTag	= (1 << 17),		/* Add VLAN tag */
};

/* 8169, 8168b and 810x except 8102e. */
enum rtl_tx_desc_bit_0 {
	/* First doubleword. */
#define TD0_MSS_SHIFT			16	/* MSS position (11 bits) */
	TD0_TCP_CS	= (1 << 16),		/* Calculate TCP/IP checksum */
	TD0_UDP_CS	= (1 << 17),		/* Calculate UDP/IP checksum */
	TD0_IP_CS	= (1 << 18),		/* Calculate IP checksum */
};

/* 8102e, 8168c and beyond. */
enum rtl_tx_desc_bit_1 {
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	/* First doubleword. */
	TD1_GTSENV4	= (1 << 26),		/* Giant Send for IPv4 */
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	TD1_GTSENV6	= (1 << 25),		/* Giant Send for IPv6 */
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#define GTTCPHO_SHIFT			18
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#define GTTCPHO_MAX			0x7fU
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	/* Second doubleword. */
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#define TCPHO_SHIFT			18
#define TCPHO_MAX			0x3ffU
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#define TD1_MSS_SHIFT			18	/* MSS position (11 bits) */
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	TD1_IPv6_CS	= (1 << 28),		/* Calculate IPv6 checksum */
	TD1_IPv4_CS	= (1 << 29),		/* Calculate IPv4 checksum */
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	TD1_TCP_CS	= (1 << 30),		/* Calculate TCP/IP checksum */
	TD1_UDP_CS	= (1 << 31),		/* Calculate UDP/IP checksum */
};
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enum rtl_rx_desc_bit {
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	/* Rx private */
	PID1		= (1 << 18), /* Protocol ID bit 1/2 */
	PID0		= (1 << 17), /* Protocol ID bit 2/2 */

#define RxProtoUDP	(PID1)
#define RxProtoTCP	(PID0)
#define RxProtoIP	(PID1 | PID0)
#define RxProtoMask	RxProtoIP

	IPFail		= (1 << 16), /* IP checksum failed */
	UDPFail		= (1 << 15), /* UDP/IP checksum failed */
	TCPFail		= (1 << 14), /* TCP/IP checksum failed */
	RxVlanTag	= (1 << 16), /* VLAN tag available */
};

#define RsvdMask	0x3fffc000

struct TxDesc {
694 695 696
	__le32 opts1;
	__le32 opts2;
	__le64 addr;
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};

struct RxDesc {
700 701 702
	__le32 opts1;
	__le32 opts2;
	__le64 addr;
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};

struct ring_info {
	struct sk_buff	*skb;
	u32		len;
	u8		__pad[sizeof(void *) - sizeof(u32)];
};

711
enum features {
712 713 714
	RTL_FEATURE_WOL		= (1 << 0),
	RTL_FEATURE_MSI		= (1 << 1),
	RTL_FEATURE_GMII	= (1 << 2),
715 716
};

717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732
struct rtl8169_counters {
	__le64	tx_packets;
	__le64	rx_packets;
	__le64	tx_errors;
	__le32	rx_errors;
	__le16	rx_missed;
	__le16	align_errors;
	__le32	tx_one_collision;
	__le32	tx_multi_collision;
	__le64	rx_unicast;
	__le64	rx_broadcast;
	__le32	rx_multicast;
	__le16	tx_aborted;
	__le16	tx_underun;
};

733
enum rtl_flag {
734
	RTL_FLAG_TASK_ENABLED,
735 736 737 738 739 740
	RTL_FLAG_TASK_SLOW_PENDING,
	RTL_FLAG_TASK_RESET_PENDING,
	RTL_FLAG_TASK_PHY_PENDING,
	RTL_FLAG_MAX
};

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struct rtl8169_stats {
	u64			packets;
	u64			bytes;
	struct u64_stats_sync	syncp;
};

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struct rtl8169_private {
	void __iomem *mmio_addr;	/* memory map physical address */
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	struct pci_dev *pci_dev;
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	struct net_device *dev;
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	struct napi_struct napi;
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	u32 msg_enable;
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	u16 txd_version;
	u16 mac_version;
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	u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
	u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
	u32 dirty_tx;
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	struct rtl8169_stats rx_stats;
	struct rtl8169_stats tx_stats;
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	struct TxDesc *TxDescArray;	/* 256-aligned Tx descriptor ring */
	struct RxDesc *RxDescArray;	/* 256-aligned Rx descriptor ring */
	dma_addr_t TxPhyAddr;
	dma_addr_t RxPhyAddr;
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	void *Rx_databuff[NUM_RX_DESC];	/* Rx data buffers */
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	struct ring_info tx_skb[NUM_TX_DESC];	/* Tx data buffers */
	struct timer_list timer;
	u16 cp_cmd;
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	u16 event_slow;
770 771

	struct mdio_ops {
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		void (*write)(struct rtl8169_private *, int, int);
		int (*read)(struct rtl8169_private *, int);
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	} mdio_ops;

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	struct pll_power_ops {
		void (*down)(struct rtl8169_private *);
		void (*up)(struct rtl8169_private *);
	} pll_power_ops;

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	struct jumbo_ops {
		void (*enable)(struct rtl8169_private *);
		void (*disable)(struct rtl8169_private *);
	} jumbo_ops;

786
	struct csi_ops {
787 788
		void (*write)(struct rtl8169_private *, int, int);
		u32 (*read)(struct rtl8169_private *, int);
789 790
	} csi_ops;

791
	int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
792
	int (*get_settings)(struct net_device *, struct ethtool_cmd *);
793
	void (*phy_reset_enable)(struct rtl8169_private *tp);
794
	void (*hw_start)(struct net_device *);
795
	unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
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	unsigned int (*link_ok)(void __iomem *);
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	int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
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	bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
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	struct {
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		DECLARE_BITMAP(flags, RTL_FLAG_MAX);
		struct mutex mutex;
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		struct work_struct work;
	} wk;

806
	unsigned features;
807 808

	struct mii_if_info mii;
809
	struct rtl8169_counters counters;
810
	u32 saved_wolopts;
811
	u32 opts1_mask;
812

813 814
	struct rtl_fw {
		const struct firmware *fw;
815 816 817 818 819 820 821 822 823

#define RTL_VER_SIZE		32

		char version[RTL_VER_SIZE];

		struct rtl_fw_phy_action {
			__le32 *code;
			size_t size;
		} phy_action;
824
	} *rtl_fw;
825
#define RTL_FIRMWARE_UNKNOWN	ERR_PTR(-EAGAIN)
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	u32 ocp_base;
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};

830
MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
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MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
module_param(use_dac, int, 0);
833
MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
834 835
module_param_named(debug, debug.msg_enable, int, 0);
MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
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MODULE_LICENSE("GPL");
MODULE_VERSION(RTL8169_VERSION);
838 839
MODULE_FIRMWARE(FIRMWARE_8168D_1);
MODULE_FIRMWARE(FIRMWARE_8168D_2);
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MODULE_FIRMWARE(FIRMWARE_8168E_1);
MODULE_FIRMWARE(FIRMWARE_8168E_2);
842
MODULE_FIRMWARE(FIRMWARE_8168E_3);
843
MODULE_FIRMWARE(FIRMWARE_8105E_1);
844 845
MODULE_FIRMWARE(FIRMWARE_8168F_1);
MODULE_FIRMWARE(FIRMWARE_8168F_2);
846
MODULE_FIRMWARE(FIRMWARE_8402_1);
847
MODULE_FIRMWARE(FIRMWARE_8411_1);
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MODULE_FIRMWARE(FIRMWARE_8411_2);
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MODULE_FIRMWARE(FIRMWARE_8106E_1);
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MODULE_FIRMWARE(FIRMWARE_8106E_2);
851
MODULE_FIRMWARE(FIRMWARE_8168G_2);
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MODULE_FIRMWARE(FIRMWARE_8168G_3);
853 854
MODULE_FIRMWARE(FIRMWARE_8168H_1);
MODULE_FIRMWARE(FIRMWARE_8168H_2);
855 856
MODULE_FIRMWARE(FIRMWARE_8107E_1);
MODULE_FIRMWARE(FIRMWARE_8107E_2);
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858 859 860 861 862 863 864 865 866 867
static void rtl_lock_work(struct rtl8169_private *tp)
{
	mutex_lock(&tp->wk.mutex);
}

static void rtl_unlock_work(struct rtl8169_private *tp)
{
	mutex_unlock(&tp->wk.mutex);
}

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static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
{
870 871
	pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
					   PCI_EXP_DEVCTL_READRQ, force);
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}

874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894
struct rtl_cond {
	bool (*check)(struct rtl8169_private *);
	const char *msg;
};

static void rtl_udelay(unsigned int d)
{
	udelay(d);
}

static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
			  void (*delay)(unsigned int), unsigned int d, int n,
			  bool high)
{
	int i;

	for (i = 0; i < n; i++) {
		delay(d);
		if (c->check(tp) == high)
			return true;
	}
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	netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
		  c->msg, !high, n, d);
897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944
	return false;
}

static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
				      const struct rtl_cond *c,
				      unsigned int d, int n)
{
	return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
}

static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
				     const struct rtl_cond *c,
				     unsigned int d, int n)
{
	return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
}

static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
				      const struct rtl_cond *c,
				      unsigned int d, int n)
{
	return rtl_loop_wait(tp, c, msleep, d, n, true);
}

static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
				     const struct rtl_cond *c,
				     unsigned int d, int n)
{
	return rtl_loop_wait(tp, c, msleep, d, n, false);
}

#define DECLARE_RTL_COND(name)				\
static bool name ## _check(struct rtl8169_private *);	\
							\
static const struct rtl_cond name = {			\
	.check	= name ## _check,			\
	.msg	= #name					\
};							\
							\
static bool name ## _check(struct rtl8169_private *tp)

DECLARE_RTL_COND(rtl_ocpar_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R32(OCPAR) & OCPAR_FLAG;
}

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static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
950 951 952

	return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
		RTL_R32(OCPDR) : ~0;
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}

static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W32(OCPDR, data);
	RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
961 962 963 964 965 966 967 968 969

	rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
}

DECLARE_RTL_COND(rtl_eriar_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R32(ERIAR) & ERIAR_FLAG;
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}

972
static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
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{
974
	void __iomem *ioaddr = tp->mmio_addr;
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	RTL_W8(ERIDR, cmd);
	RTL_W32(ERIAR, 0x800010e8);
	msleep(2);
979 980 981

	if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
		return;
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983
	ocp_write(tp, 0x1, 0x30, 0x00000001);
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}

#define OOB_CMD_RESET		0x00
#define OOB_CMD_DRIVER_START	0x05
#define OOB_CMD_DRIVER_STOP	0x06

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static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
{
	return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
}

995
DECLARE_RTL_COND(rtl_ocp_read_cond)
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{
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	u16 reg;
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	reg = rtl8168_get_ocp_reg(tp);
1000

1001
	return ocp_read(tp, 0x0f, reg) & 0x00000800;
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}

1004
static void rtl8168_driver_start(struct rtl8169_private *tp)
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{
1006
	rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
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1008 1009
	rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
}
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1011 1012 1013
static void rtl8168_driver_stop(struct rtl8169_private *tp)
{
	rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1014

1015
	rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
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}

1018 1019
static int r8168dp_check_dash(struct rtl8169_private *tp)
{
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	u16 reg = rtl8168_get_ocp_reg(tp);
1021

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	return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1023
}
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static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
{
	if (reg & 0xffff0001) {
		netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
		return true;
	}
	return false;
}

DECLARE_RTL_COND(rtl_ocp_gphy_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
}

static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
{
	void __iomem *ioaddr = tp->mmio_addr;

	if (rtl_ocp_reg_failure(tp, reg))
		return;

	RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);

	rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
}

static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
{
	void __iomem *ioaddr = tp->mmio_addr;

	if (rtl_ocp_reg_failure(tp, reg))
		return 0;

	RTL_W32(GPHY_OCP, reg << 15);

	return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
		(RTL_R32(GPHY_OCP) & 0xffff) : ~0;
}

static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
{
	void __iomem *ioaddr = tp->mmio_addr;

	if (rtl_ocp_reg_failure(tp, reg))
		return;

	RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
}

static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
{
	void __iomem *ioaddr = tp->mmio_addr;

	if (rtl_ocp_reg_failure(tp, reg))
		return 0;

	RTL_W32(OCPDR, reg << 15);

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	return RTL_R32(OCPDR);
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}

#define OCP_STD_PHY_BASE	0xa400

static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
{
	if (reg == 0x1f) {
		tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
		return;
	}

	if (tp->ocp_base != OCP_STD_PHY_BASE)
		reg -= 0x10;

	r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
}

static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
{
	if (tp->ocp_base != OCP_STD_PHY_BASE)
		reg -= 0x10;

	return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
}

1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125
static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
{
	if (reg == 0x1f) {
		tp->ocp_base = value << 4;
		return;
	}

	r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
}

static int mac_mcu_read(struct rtl8169_private *tp, int reg)
{
	return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
}

1126 1127 1128 1129 1130 1131 1132
DECLARE_RTL_COND(rtl_phyar_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R32(PHYAR) & 0x80000000;
}

1133
static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
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{
1135
	void __iomem *ioaddr = tp->mmio_addr;
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1137
	RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
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1139
	rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1140
	/*
1141 1142
	 * According to hardware specs a 20us delay is required after write
	 * complete indication, but before sending next command.
1143
	 */
1144
	udelay(20);
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}

1147
static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
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{
1149
	void __iomem *ioaddr = tp->mmio_addr;
1150
	int value;
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1152
	RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
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1154 1155 1156
	value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
		RTL_R32(PHYAR) & 0xffff : ~0;

1157 1158 1159 1160 1161 1162
	/*
	 * According to hardware specs a 20us delay is required after read
	 * complete indication, but before sending next command.
	 */
	udelay(20);

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	return value;
}

1166
static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1167
{
1168
	void __iomem *ioaddr = tp->mmio_addr;
1169

1170
	RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1171 1172 1173
	RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
	RTL_W32(EPHY_RXER_NUM, 0);

1174
	rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1175 1176
}

1177
static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1178
{
1179 1180
	r8168dp_1_mdio_access(tp, reg,
			      OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1181 1182
}

1183
static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1184
{
1185
	void __iomem *ioaddr = tp->mmio_addr;
1186

1187
	r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1188 1189 1190 1191 1192

	mdelay(1);
	RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
	RTL_W32(EPHY_RXER_NUM, 0);

1193 1194
	return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
		RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1195 1196
}

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#define R8168DP_1_MDIO_ACCESS_BIT	0x00020000

static void r8168dp_2_mdio_start(void __iomem *ioaddr)
{
	RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
}

static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
{
	RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
}

1209
static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
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{
1211 1212
	void __iomem *ioaddr = tp->mmio_addr;

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	r8168dp_2_mdio_start(ioaddr);

1215
	r8169_mdio_write(tp, reg, value);
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	r8168dp_2_mdio_stop(ioaddr);
}

1220
static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
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{
1222
	void __iomem *ioaddr = tp->mmio_addr;
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	int value;

	r8168dp_2_mdio_start(ioaddr);

1227
	value = r8169_mdio_read(tp, reg);
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	r8168dp_2_mdio_stop(ioaddr);

	return value;
}

1234
static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1235
{
1236
	tp->mdio_ops.write(tp, location, val);
1237 1238
}

1239 1240
static int rtl_readphy(struct rtl8169_private *tp, int location)
{
1241
	return tp->mdio_ops.read(tp, location);
1242 1243 1244 1245 1246 1247 1248
}

static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
{
	rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
}

1249
static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1250 1251 1252
{
	int val;

1253
	val = rtl_readphy(tp, reg_addr);
1254
	rtl_writephy(tp, reg_addr, (val & ~m) | p);
1255 1256
}

1257 1258 1259 1260 1261
static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
			   int val)
{
	struct rtl8169_private *tp = netdev_priv(dev);

1262
	rtl_writephy(tp, location, val);
1263 1264 1265 1266 1267 1268
}

static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
{
	struct rtl8169_private *tp = netdev_priv(dev);

1269
	return rtl_readphy(tp, location);
1270 1271
}

1272 1273 1274 1275 1276 1277 1278
DECLARE_RTL_COND(rtl_ephyar_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R32(EPHYAR) & EPHYAR_FLAG;
}

1279
static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1280
{
1281
	void __iomem *ioaddr = tp->mmio_addr;
1282 1283 1284 1285

	RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
		(reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);

1286 1287 1288
	rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);

	udelay(10);
1289 1290
}

1291
static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1292
{
1293
	void __iomem *ioaddr = tp->mmio_addr;
1294 1295 1296

	RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);

1297 1298
	return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
		RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1299 1300
}

1301 1302
static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
			  u32 val, int type)
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{
1304
	void __iomem *ioaddr = tp->mmio_addr;
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	BUG_ON((addr & 3) || (mask == 0));
	RTL_W32(ERIDR, val);
	RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);

1310
	rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
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}

1313
static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
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{
1315
	void __iomem *ioaddr = tp->mmio_addr;
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	RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);

1319 1320
	return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
		RTL_R32(ERIDR) : ~0;
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}

1323 1324
static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
			 u32 m, int type)
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{
	u32 val;

1328 1329
	val = rtl_eri_read(tp, addr, type);
	rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
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}

1332 1333 1334 1335 1336 1337
struct exgmac_reg {
	u16 addr;
	u16 mask;
	u32 val;
};

1338
static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1339 1340 1341
				   const struct exgmac_reg *r, int len)
{
	while (len-- > 0) {
1342
		rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1343 1344 1345 1346
		r++;
	}
}

1347 1348 1349 1350 1351 1352 1353
DECLARE_RTL_COND(rtl_efusear_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
}

1354
static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1355
{
1356
	void __iomem *ioaddr = tp->mmio_addr;
1357 1358 1359

	RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);

1360 1361
	return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
		RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1362 1363
}

F
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1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386
static u16 rtl_get_events(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R16(IntrStatus);
}

static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W16(IntrStatus, bits);
	mmiowb();
}

static void rtl_irq_disable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W16(IntrMask, 0);
	mmiowb();
}

1387 1388 1389 1390 1391 1392 1393
static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W16(IntrMask, bits);
}

1394 1395 1396 1397 1398 1399 1400 1401 1402
#define RTL_EVENT_NAPI_RX	(RxOK | RxErr)
#define RTL_EVENT_NAPI_TX	(TxOK | TxErr)
#define RTL_EVENT_NAPI		(RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)

static void rtl_irq_enable_all(struct rtl8169_private *tp)
{
	rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
}

F
françois romieu 已提交
1403
static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
1404
{
F
françois romieu 已提交
1405
	void __iomem *ioaddr = tp->mmio_addr;
L
Linus Torvalds 已提交
1406

F
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1407
	rtl_irq_disable(tp);
1408
	rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
F
françois romieu 已提交
1409
	RTL_R8(ChipCmd);
L
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1410 1411
}

1412
static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
1413
{
1414 1415
	void __iomem *ioaddr = tp->mmio_addr;

L
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1416 1417 1418
	return RTL_R32(TBICSR) & TBIReset;
}

1419
static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
1420
{
1421
	return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
L
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1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433
}

static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
{
	return RTL_R32(TBICSR) & TBILinkOk;
}

static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
{
	return RTL_R8(PHYstatus) & LinkStatus;
}

1434
static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
1435
{
1436 1437
	void __iomem *ioaddr = tp->mmio_addr;

L
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1438 1439 1440
	RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
}

1441
static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
1442 1443 1444
{
	unsigned int val;

1445 1446
	val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
	rtl_writephy(tp, MII_BMCR, val & 0xffff);
L
Linus Torvalds 已提交
1447 1448
}

H
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1449 1450 1451 1452 1453 1454 1455 1456
static void rtl_link_chg_patch(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;
	struct net_device *dev = tp->dev;

	if (!netif_running(dev))
		return;

1457 1458
	if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_38) {
H
Hayes Wang 已提交
1459
		if (RTL_R8(PHYstatus) & _1000bpsF) {
1460 1461 1462 1463
			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
				      ERIAR_EXGMAC);
			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
				      ERIAR_EXGMAC);
H
Hayes Wang 已提交
1464
		} else if (RTL_R8(PHYstatus) & _100bps) {
1465 1466 1467 1468
			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
				      ERIAR_EXGMAC);
			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
				      ERIAR_EXGMAC);
H
Hayes Wang 已提交
1469
		} else {
1470 1471 1472 1473
			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
				      ERIAR_EXGMAC);
			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
				      ERIAR_EXGMAC);
H
Hayes Wang 已提交
1474 1475
		}
		/* Reset packet filter */
1476
		rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
H
Hayes Wang 已提交
1477
			     ERIAR_EXGMAC);
1478
		rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
H
Hayes Wang 已提交
1479
			     ERIAR_EXGMAC);
1480 1481 1482
	} else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_36) {
		if (RTL_R8(PHYstatus) & _1000bpsF) {
1483 1484 1485 1486
			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
				      ERIAR_EXGMAC);
			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
				      ERIAR_EXGMAC);
1487
		} else {
1488 1489 1490 1491
			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
				      ERIAR_EXGMAC);
			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
				      ERIAR_EXGMAC);
1492
		}
1493 1494
	} else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
		if (RTL_R8(PHYstatus) & _10bps) {
1495 1496 1497 1498
			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
				      ERIAR_EXGMAC);
			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
				      ERIAR_EXGMAC);
1499
		} else {
1500 1501
			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
				      ERIAR_EXGMAC);
1502
		}
H
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1503 1504 1505
	}
}

1506
static void __rtl8169_check_link_status(struct net_device *dev,
F
Francois Romieu 已提交
1507 1508
					struct rtl8169_private *tp,
					void __iomem *ioaddr, bool pm)
L
Linus Torvalds 已提交
1509 1510
{
	if (tp->link_ok(ioaddr)) {
H
Hayes Wang 已提交
1511
		rtl_link_chg_patch(tp);
1512
		/* This is to cancel a scheduled suspend if there's one. */
1513 1514
		if (pm)
			pm_request_resume(&tp->pci_dev->dev);
L
Linus Torvalds 已提交
1515
		netif_carrier_on(dev);
1516 1517
		if (net_ratelimit())
			netif_info(tp, ifup, dev, "link up\n");
1518
	} else {
L
Linus Torvalds 已提交
1519
		netif_carrier_off(dev);
1520
		netif_info(tp, ifdown, dev, "link down\n");
1521
		if (pm)
1522
			pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1523
	}
L
Linus Torvalds 已提交
1524 1525
}

1526 1527 1528 1529 1530 1531 1532
static void rtl8169_check_link_status(struct net_device *dev,
				      struct rtl8169_private *tp,
				      void __iomem *ioaddr)
{
	__rtl8169_check_link_status(dev, tp, ioaddr, false);
}

1533 1534 1535
#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)

static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
F
Francois Romieu 已提交
1536 1537 1538
{
	void __iomem *ioaddr = tp->mmio_addr;
	u8 options;
1539
	u32 wolopts = 0;
F
Francois Romieu 已提交
1540 1541 1542

	options = RTL_R8(Config1);
	if (!(options & PMEnable))
1543
		return 0;
F
Francois Romieu 已提交
1544 1545 1546

	options = RTL_R8(Config3);
	if (options & LinkUp)
1547
		wolopts |= WAKE_PHY;
1548
	switch (tp->mac_version) {
1549 1550 1551 1552 1553 1554 1555 1556 1557 1558
	case RTL_GIGA_MAC_VER_34:
	case RTL_GIGA_MAC_VER_35:
	case RTL_GIGA_MAC_VER_36:
	case RTL_GIGA_MAC_VER_37:
	case RTL_GIGA_MAC_VER_38:
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
	case RTL_GIGA_MAC_VER_42:
	case RTL_GIGA_MAC_VER_43:
	case RTL_GIGA_MAC_VER_44:
1559 1560
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
1561 1562
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
1563 1564 1565 1566 1567 1568 1569 1570
		if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
			wolopts |= WAKE_MAGIC;
		break;
	default:
		if (options & MagicPacket)
			wolopts |= WAKE_MAGIC;
		break;
	}
F
Francois Romieu 已提交
1571 1572 1573

	options = RTL_R8(Config5);
	if (options & UWF)
1574
		wolopts |= WAKE_UCAST;
F
Francois Romieu 已提交
1575
	if (options & BWF)
1576
		wolopts |= WAKE_BCAST;
F
Francois Romieu 已提交
1577
	if (options & MWF)
1578
		wolopts |= WAKE_MCAST;
F
Francois Romieu 已提交
1579

1580
	return wolopts;
F
Francois Romieu 已提交
1581 1582
}

1583
static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
F
Francois Romieu 已提交
1584 1585
{
	struct rtl8169_private *tp = netdev_priv(dev);
1586

1587
	rtl_lock_work(tp);
1588 1589 1590 1591

	wol->supported = WAKE_ANY;
	wol->wolopts = __rtl8169_get_wol(tp);

1592
	rtl_unlock_work(tp);
1593 1594 1595 1596
}

static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
{
F
Francois Romieu 已提交
1597
	void __iomem *ioaddr = tp->mmio_addr;
1598
	unsigned int i, tmp;
1599
	static const struct {
F
Francois Romieu 已提交
1600 1601 1602 1603 1604 1605 1606 1607
		u32 opt;
		u16 reg;
		u8  mask;
	} cfg[] = {
		{ WAKE_PHY,   Config3, LinkUp },
		{ WAKE_UCAST, Config5, UWF },
		{ WAKE_BCAST, Config5, BWF },
		{ WAKE_MCAST, Config5, MWF },
1608 1609
		{ WAKE_ANY,   Config5, LanWake },
		{ WAKE_MAGIC, Config3, MagicPacket }
F
Francois Romieu 已提交
1610
	};
1611
	u8 options;
F
Francois Romieu 已提交
1612 1613 1614

	RTL_W8(Cfg9346, Cfg9346_Unlock);

1615
	switch (tp->mac_version) {
1616 1617 1618 1619 1620 1621 1622 1623 1624 1625
	case RTL_GIGA_MAC_VER_34:
	case RTL_GIGA_MAC_VER_35:
	case RTL_GIGA_MAC_VER_36:
	case RTL_GIGA_MAC_VER_37:
	case RTL_GIGA_MAC_VER_38:
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
	case RTL_GIGA_MAC_VER_42:
	case RTL_GIGA_MAC_VER_43:
	case RTL_GIGA_MAC_VER_44:
1626 1627
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
1628 1629
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651
		tmp = ARRAY_SIZE(cfg) - 1;
		if (wolopts & WAKE_MAGIC)
			rtl_w1w0_eri(tp,
				     0x0dc,
				     ERIAR_MASK_0100,
				     MagicPacket_v2,
				     0x0000,
				     ERIAR_EXGMAC);
		else
			rtl_w1w0_eri(tp,
				     0x0dc,
				     ERIAR_MASK_0100,
				     0x0000,
				     MagicPacket_v2,
				     ERIAR_EXGMAC);
		break;
	default:
		tmp = ARRAY_SIZE(cfg);
		break;
	}

	for (i = 0; i < tmp; i++) {
1652
		options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1653
		if (wolopts & cfg[i].opt)
F
Francois Romieu 已提交
1654 1655 1656 1657
			options |= cfg[i].mask;
		RTL_W8(cfg[i].reg, options);
	}

1658 1659 1660 1661 1662 1663 1664 1665
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
		options = RTL_R8(Config1) & ~PMEnable;
		if (wolopts)
			options |= PMEnable;
		RTL_W8(Config1, options);
		break;
	default:
1666 1667 1668 1669
		options = RTL_R8(Config2) & ~PME_SIGNAL;
		if (wolopts)
			options |= PME_SIGNAL;
		RTL_W8(Config2, options);
1670 1671 1672
		break;
	}

F
Francois Romieu 已提交
1673
	RTL_W8(Cfg9346, Cfg9346_Lock);
1674 1675 1676 1677 1678 1679
}

static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
	struct rtl8169_private *tp = netdev_priv(dev);

1680
	rtl_lock_work(tp);
F
Francois Romieu 已提交
1681

1682 1683 1684 1685
	if (wol->wolopts)
		tp->features |= RTL_FEATURE_WOL;
	else
		tp->features &= ~RTL_FEATURE_WOL;
1686
	__rtl8169_set_wol(tp, wol->wolopts);
1687 1688

	rtl_unlock_work(tp);
F
Francois Romieu 已提交
1689

1690 1691
	device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);

F
Francois Romieu 已提交
1692 1693 1694
	return 0;
}

1695 1696
static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
{
1697
	return rtl_chip_infos[tp->mac_version].fw_name;
1698 1699
}

L
Linus Torvalds 已提交
1700 1701 1702 1703
static void rtl8169_get_drvinfo(struct net_device *dev,
				struct ethtool_drvinfo *info)
{
	struct rtl8169_private *tp = netdev_priv(dev);
1704
	struct rtl_fw *rtl_fw = tp->rtl_fw;
L
Linus Torvalds 已提交
1705

1706 1707 1708
	strlcpy(info->driver, MODULENAME, sizeof(info->driver));
	strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
	strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1709
	BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1710 1711 1712
	if (!IS_ERR_OR_NULL(rtl_fw))
		strlcpy(info->fw_version, rtl_fw->version,
			sizeof(info->fw_version));
L
Linus Torvalds 已提交
1713 1714 1715 1716 1717 1718 1719 1720
}

static int rtl8169_get_regs_len(struct net_device *dev)
{
	return R8169_REGS_SIZE;
}

static int rtl8169_set_speed_tbi(struct net_device *dev,
1721
				 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
L
Linus Torvalds 已提交
1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	int ret = 0;
	u32 reg;

	reg = RTL_R32(TBICSR);
	if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
	    (duplex == DUPLEX_FULL)) {
		RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
	} else if (autoneg == AUTONEG_ENABLE)
		RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
	else {
1735 1736
		netif_warn(tp, link, dev,
			   "incorrect speed setting refused in TBI mode\n");
L
Linus Torvalds 已提交
1737 1738 1739 1740 1741 1742 1743
		ret = -EOPNOTSUPP;
	}

	return ret;
}

static int rtl8169_set_speed_xmii(struct net_device *dev,
1744
				  u8 autoneg, u16 speed, u8 duplex, u32 adv)
L
Linus Torvalds 已提交
1745 1746
{
	struct rtl8169_private *tp = netdev_priv(dev);
1747
	int giga_ctrl, bmcr;
1748
	int rc = -EINVAL;
L
Linus Torvalds 已提交
1749

1750
	rtl_writephy(tp, 0x1f, 0x0000);
L
Linus Torvalds 已提交
1751 1752

	if (autoneg == AUTONEG_ENABLE) {
1753 1754
		int auto_nego;

1755
		auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767
		auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
				ADVERTISE_100HALF | ADVERTISE_100FULL);

		if (adv & ADVERTISED_10baseT_Half)
			auto_nego |= ADVERTISE_10HALF;
		if (adv & ADVERTISED_10baseT_Full)
			auto_nego |= ADVERTISE_10FULL;
		if (adv & ADVERTISED_100baseT_Half)
			auto_nego |= ADVERTISE_100HALF;
		if (adv & ADVERTISED_100baseT_Full)
			auto_nego |= ADVERTISE_100FULL;

1768
		auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
L
Linus Torvalds 已提交
1769

1770
		giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1771
		giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1772

1773
		/* The 8100e/8101e/8102e do Fast Ethernet only. */
1774
		if (tp->mii.supports_gmii) {
1775 1776 1777 1778 1779 1780
			if (adv & ADVERTISED_1000baseT_Half)
				giga_ctrl |= ADVERTISE_1000HALF;
			if (adv & ADVERTISED_1000baseT_Full)
				giga_ctrl |= ADVERTISE_1000FULL;
		} else if (adv & (ADVERTISED_1000baseT_Half |
				  ADVERTISED_1000baseT_Full)) {
1781 1782
			netif_info(tp, link, dev,
				   "PHY does not support 1000Mbps\n");
1783
			goto out;
1784
		}
L
Linus Torvalds 已提交
1785

1786 1787
		bmcr = BMCR_ANENABLE | BMCR_ANRESTART;

1788 1789
		rtl_writephy(tp, MII_ADVERTISE, auto_nego);
		rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1790 1791 1792 1793 1794 1795 1796 1797
	} else {
		giga_ctrl = 0;

		if (speed == SPEED_10)
			bmcr = 0;
		else if (speed == SPEED_100)
			bmcr = BMCR_SPEED100;
		else
1798
			goto out;
1799 1800 1801

		if (duplex == DUPLEX_FULL)
			bmcr |= BMCR_FULLDPLX;
R
Roger So 已提交
1802 1803
	}

1804
	rtl_writephy(tp, MII_BMCR, bmcr);
1805

F
Francois Romieu 已提交
1806 1807
	if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_03) {
1808
		if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1809 1810
			rtl_writephy(tp, 0x17, 0x2138);
			rtl_writephy(tp, 0x0e, 0x0260);
1811
		} else {
1812 1813
			rtl_writephy(tp, 0x17, 0x2108);
			rtl_writephy(tp, 0x0e, 0x0000);
1814 1815 1816
		}
	}

1817 1818 1819
	rc = 0;
out:
	return rc;
L
Linus Torvalds 已提交
1820 1821 1822
}

static int rtl8169_set_speed(struct net_device *dev,
1823
			     u8 autoneg, u16 speed, u8 duplex, u32 advertising)
L
Linus Torvalds 已提交
1824 1825 1826 1827
{
	struct rtl8169_private *tp = netdev_priv(dev);
	int ret;

1828
	ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1829 1830
	if (ret < 0)
		goto out;
L
Linus Torvalds 已提交
1831

1832 1833
	if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
	    (advertising & ADVERTISED_1000baseT_Full)) {
L
Linus Torvalds 已提交
1834
		mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1835 1836
	}
out:
L
Linus Torvalds 已提交
1837 1838 1839 1840 1841 1842 1843 1844
	return ret;
}

static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	int ret;

1845 1846
	del_timer_sync(&tp->timer);

1847
	rtl_lock_work(tp);
F
Francois Romieu 已提交
1848
	ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1849
				cmd->duplex, cmd->advertising);
1850
	rtl_unlock_work(tp);
1851

L
Linus Torvalds 已提交
1852 1853 1854
	return ret;
}

1855 1856
static netdev_features_t rtl8169_fix_features(struct net_device *dev,
	netdev_features_t features)
L
Linus Torvalds 已提交
1857
{
F
Francois Romieu 已提交
1858 1859
	struct rtl8169_private *tp = netdev_priv(dev);

F
Francois Romieu 已提交
1860
	if (dev->mtu > TD_MSS_MAX)
1861
		features &= ~NETIF_F_ALL_TSO;
L
Linus Torvalds 已提交
1862

F
Francois Romieu 已提交
1863 1864 1865 1866
	if (dev->mtu > JUMBO_1K &&
	    !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
		features &= ~NETIF_F_IP_CSUM;

1867
	return features;
L
Linus Torvalds 已提交
1868 1869
}

1870 1871
static void __rtl8169_set_features(struct net_device *dev,
				   netdev_features_t features)
L
Linus Torvalds 已提交
1872 1873
{
	struct rtl8169_private *tp = netdev_priv(dev);
1874
	void __iomem *ioaddr = tp->mmio_addr;
H
hayeswang 已提交
1875
	u32 rx_config;
L
Linus Torvalds 已提交
1876

H
hayeswang 已提交
1877 1878 1879 1880 1881
	rx_config = RTL_R32(RxConfig);
	if (features & NETIF_F_RXALL)
		rx_config |= (AcceptErr | AcceptRunt);
	else
		rx_config &= ~(AcceptErr | AcceptRunt);
L
Linus Torvalds 已提交
1882

H
hayeswang 已提交
1883
	RTL_W32(RxConfig, rx_config);
1884

H
hayeswang 已提交
1885 1886 1887 1888
	if (features & NETIF_F_RXCSUM)
		tp->cp_cmd |= RxChkSum;
	else
		tp->cp_cmd &= ~RxChkSum;
B
Ben Greear 已提交
1889

H
hayeswang 已提交
1890 1891 1892 1893 1894 1895 1896 1897 1898
	if (features & NETIF_F_HW_VLAN_CTAG_RX)
		tp->cp_cmd |= RxVlan;
	else
		tp->cp_cmd &= ~RxVlan;

	tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);

	RTL_W16(CPlusCmd, tp->cp_cmd);
	RTL_R16(CPlusCmd);
1899
}
L
Linus Torvalds 已提交
1900

1901 1902 1903 1904 1905
static int rtl8169_set_features(struct net_device *dev,
				netdev_features_t features)
{
	struct rtl8169_private *tp = netdev_priv(dev);

H
hayeswang 已提交
1906 1907
	features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;

1908
	rtl_lock_work(tp);
D
Dan Carpenter 已提交
1909
	if (features ^ dev->features)
H
hayeswang 已提交
1910
		__rtl8169_set_features(dev, features);
1911
	rtl_unlock_work(tp);
L
Linus Torvalds 已提交
1912 1913 1914 1915

	return 0;
}

1916

1917
static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
L
Linus Torvalds 已提交
1918
{
1919
	return (vlan_tx_tag_present(skb)) ?
L
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1920 1921 1922
		TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
}

1923
static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
L
Linus Torvalds 已提交
1924 1925 1926
{
	u32 opts2 = le32_to_cpu(desc->opts2);

1927
	if (opts2 & RxVlanTag)
1928
		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
L
Linus Torvalds 已提交
1929 1930
}

1931
static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
L
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1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	u32 status;

	cmd->supported =
		SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
	cmd->port = PORT_FIBRE;
	cmd->transceiver = XCVR_INTERNAL;

	status = RTL_R32(TBICSR);
	cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
	cmd->autoneg = !!(status & TBINwEnable);

1946
	ethtool_cmd_speed_set(cmd, SPEED_1000);
L
Linus Torvalds 已提交
1947
	cmd->duplex = DUPLEX_FULL; /* Always set */
1948 1949

	return 0;
L
Linus Torvalds 已提交
1950 1951
}

1952
static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
L
Linus Torvalds 已提交
1953 1954
{
	struct rtl8169_private *tp = netdev_priv(dev);
1955 1956

	return mii_ethtool_gset(&tp->mii, cmd);
L
Linus Torvalds 已提交
1957 1958 1959 1960 1961
}

static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
	struct rtl8169_private *tp = netdev_priv(dev);
1962
	int rc;
L
Linus Torvalds 已提交
1963

1964
	rtl_lock_work(tp);
1965
	rc = tp->get_settings(dev, cmd);
1966
	rtl_unlock_work(tp);
L
Linus Torvalds 已提交
1967

1968
	return rc;
L
Linus Torvalds 已提交
1969 1970 1971 1972 1973
}

static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
			     void *p)
{
1974
	struct rtl8169_private *tp = netdev_priv(dev);
P
Peter Wu 已提交
1975 1976 1977
	u32 __iomem *data = tp->mmio_addr;
	u32 *dw = p;
	int i;
L
Linus Torvalds 已提交
1978

1979
	rtl_lock_work(tp);
P
Peter Wu 已提交
1980 1981
	for (i = 0; i < R8169_REGS_SIZE; i += 4)
		memcpy_fromio(dw++, data++, 4);
1982
	rtl_unlock_work(tp);
L
Linus Torvalds 已提交
1983 1984
}

1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998
static u32 rtl8169_get_msglevel(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	return tp->msg_enable;
}

static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	tp->msg_enable = value;
}

1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014
static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
	"tx_packets",
	"rx_packets",
	"tx_errors",
	"rx_errors",
	"rx_missed",
	"align_errors",
	"tx_single_collisions",
	"tx_multi_collisions",
	"unicast",
	"broadcast",
	"multicast",
	"tx_aborted",
	"tx_underrun",
};

2015
static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2016
{
2017 2018 2019 2020 2021 2022
	switch (sset) {
	case ETH_SS_STATS:
		return ARRAY_SIZE(rtl8169_gstrings);
	default:
		return -EOPNOTSUPP;
	}
2023 2024
}

2025 2026 2027 2028 2029 2030 2031
DECLARE_RTL_COND(rtl_counters_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R32(CounterAddrLow) & CounterDump;
}

2032
static void rtl8169_update_counters(struct net_device *dev)
2033 2034 2035
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
F
Francois Romieu 已提交
2036
	struct device *d = &tp->pci_dev->dev;
2037 2038 2039 2040
	struct rtl8169_counters *counters;
	dma_addr_t paddr;
	u32 cmd;

2041 2042 2043 2044 2045 2046
	/*
	 * Some chips are unable to dump tally counters when the receiver
	 * is disabled.
	 */
	if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
		return;
2047

2048
	counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
2049 2050 2051 2052
	if (!counters)
		return;

	RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2053
	cmd = (u64)paddr & DMA_BIT_MASK(32);
2054 2055 2056
	RTL_W32(CounterAddrLow, cmd);
	RTL_W32(CounterAddrLow, cmd | CounterDump);

2057 2058
	if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
		memcpy(&tp->counters, counters, sizeof(*counters));
2059 2060 2061 2062

	RTL_W32(CounterAddrLow, 0);
	RTL_W32(CounterAddrHigh, 0);

2063
	dma_free_coherent(d, sizeof(*counters), counters, paddr);
2064 2065
}

2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089
static void rtl8169_get_ethtool_stats(struct net_device *dev,
				      struct ethtool_stats *stats, u64 *data)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	ASSERT_RTNL();

	rtl8169_update_counters(dev);

	data[0] = le64_to_cpu(tp->counters.tx_packets);
	data[1] = le64_to_cpu(tp->counters.rx_packets);
	data[2] = le64_to_cpu(tp->counters.tx_errors);
	data[3] = le32_to_cpu(tp->counters.rx_errors);
	data[4] = le16_to_cpu(tp->counters.rx_missed);
	data[5] = le16_to_cpu(tp->counters.align_errors);
	data[6] = le32_to_cpu(tp->counters.tx_one_collision);
	data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
	data[8] = le64_to_cpu(tp->counters.rx_unicast);
	data[9] = le64_to_cpu(tp->counters.rx_broadcast);
	data[10] = le32_to_cpu(tp->counters.rx_multicast);
	data[11] = le16_to_cpu(tp->counters.tx_aborted);
	data[12] = le16_to_cpu(tp->counters.tx_underun);
}

2090 2091 2092 2093 2094 2095 2096 2097 2098
static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
{
	switch(stringset) {
	case ETH_SS_STATS:
		memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
		break;
	}
}

2099
static const struct ethtool_ops rtl8169_ethtool_ops = {
L
Linus Torvalds 已提交
2100 2101 2102 2103 2104
	.get_drvinfo		= rtl8169_get_drvinfo,
	.get_regs_len		= rtl8169_get_regs_len,
	.get_link		= ethtool_op_get_link,
	.get_settings		= rtl8169_get_settings,
	.set_settings		= rtl8169_set_settings,
2105 2106
	.get_msglevel		= rtl8169_get_msglevel,
	.set_msglevel		= rtl8169_set_msglevel,
L
Linus Torvalds 已提交
2107
	.get_regs		= rtl8169_get_regs,
F
Francois Romieu 已提交
2108 2109
	.get_wol		= rtl8169_get_wol,
	.set_wol		= rtl8169_set_wol,
2110
	.get_strings		= rtl8169_get_strings,
2111
	.get_sset_count		= rtl8169_get_sset_count,
2112
	.get_ethtool_stats	= rtl8169_get_ethtool_stats,
2113
	.get_ts_info		= ethtool_op_get_ts_info,
L
Linus Torvalds 已提交
2114 2115
};

F
Francois Romieu 已提交
2116
static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2117
				    struct net_device *dev, u8 default_version)
L
Linus Torvalds 已提交
2118
{
2119
	void __iomem *ioaddr = tp->mmio_addr;
2120 2121 2122 2123 2124 2125
	/*
	 * The driver currently handles the 8168Bf and the 8168Be identically
	 * but they can be identified more specifically through the test below
	 * if needed:
	 *
	 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
F
Francois Romieu 已提交
2126 2127 2128 2129
	 *
	 * Same thing for the 8101Eb and the 8101Ec:
	 *
	 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2130
	 */
2131
	static const struct rtl_mac_info {
L
Linus Torvalds 已提交
2132
		u32 mask;
F
Francois Romieu 已提交
2133
		u32 val;
L
Linus Torvalds 已提交
2134 2135
		int mac_version;
	} mac_info[] = {
2136 2137 2138 2139
		/* 8168H family. */
		{ 0x7cf00000, 0x54100000,	RTL_GIGA_MAC_VER_46 },
		{ 0x7cf00000, 0x54000000,	RTL_GIGA_MAC_VER_45 },

H
Hayes Wang 已提交
2140
		/* 8168G family. */
H
hayeswang 已提交
2141
		{ 0x7cf00000, 0x5c800000,	RTL_GIGA_MAC_VER_44 },
H
hayeswang 已提交
2142
		{ 0x7cf00000, 0x50900000,	RTL_GIGA_MAC_VER_42 },
H
Hayes Wang 已提交
2143 2144 2145
		{ 0x7cf00000, 0x4c100000,	RTL_GIGA_MAC_VER_41 },
		{ 0x7cf00000, 0x4c000000,	RTL_GIGA_MAC_VER_40 },

2146
		/* 8168F family. */
2147
		{ 0x7c800000, 0x48800000,	RTL_GIGA_MAC_VER_38 },
2148 2149 2150
		{ 0x7cf00000, 0x48100000,	RTL_GIGA_MAC_VER_36 },
		{ 0x7cf00000, 0x48000000,	RTL_GIGA_MAC_VER_35 },

H
hayeswang 已提交
2151
		/* 8168E family. */
H
Hayes Wang 已提交
2152
		{ 0x7c800000, 0x2c800000,	RTL_GIGA_MAC_VER_34 },
H
hayeswang 已提交
2153 2154 2155 2156
		{ 0x7cf00000, 0x2c200000,	RTL_GIGA_MAC_VER_33 },
		{ 0x7cf00000, 0x2c100000,	RTL_GIGA_MAC_VER_32 },
		{ 0x7c800000, 0x2c000000,	RTL_GIGA_MAC_VER_33 },

F
Francois Romieu 已提交
2157
		/* 8168D family. */
2158 2159 2160
		{ 0x7cf00000, 0x28300000,	RTL_GIGA_MAC_VER_26 },
		{ 0x7cf00000, 0x28100000,	RTL_GIGA_MAC_VER_25 },
		{ 0x7c800000, 0x28000000,	RTL_GIGA_MAC_VER_26 },
F
Francois Romieu 已提交
2161

F
françois romieu 已提交
2162 2163 2164
		/* 8168DP family. */
		{ 0x7cf00000, 0x28800000,	RTL_GIGA_MAC_VER_27 },
		{ 0x7cf00000, 0x28a00000,	RTL_GIGA_MAC_VER_28 },
2165
		{ 0x7cf00000, 0x28b00000,	RTL_GIGA_MAC_VER_31 },
F
françois romieu 已提交
2166

2167
		/* 8168C family. */
2168
		{ 0x7cf00000, 0x3cb00000,	RTL_GIGA_MAC_VER_24 },
F
Francois Romieu 已提交
2169
		{ 0x7cf00000, 0x3c900000,	RTL_GIGA_MAC_VER_23 },
2170
		{ 0x7cf00000, 0x3c800000,	RTL_GIGA_MAC_VER_18 },
2171
		{ 0x7c800000, 0x3c800000,	RTL_GIGA_MAC_VER_24 },
F
Francois Romieu 已提交
2172 2173
		{ 0x7cf00000, 0x3c000000,	RTL_GIGA_MAC_VER_19 },
		{ 0x7cf00000, 0x3c200000,	RTL_GIGA_MAC_VER_20 },
F
Francois Romieu 已提交
2174
		{ 0x7cf00000, 0x3c300000,	RTL_GIGA_MAC_VER_21 },
2175
		{ 0x7cf00000, 0x3c400000,	RTL_GIGA_MAC_VER_22 },
2176
		{ 0x7c800000, 0x3c000000,	RTL_GIGA_MAC_VER_22 },
F
Francois Romieu 已提交
2177 2178 2179 2180 2181 2182 2183 2184

		/* 8168B family. */
		{ 0x7cf00000, 0x38000000,	RTL_GIGA_MAC_VER_12 },
		{ 0x7cf00000, 0x38500000,	RTL_GIGA_MAC_VER_17 },
		{ 0x7c800000, 0x38000000,	RTL_GIGA_MAC_VER_17 },
		{ 0x7c800000, 0x30000000,	RTL_GIGA_MAC_VER_11 },

		/* 8101 family. */
H
Hayes Wang 已提交
2185 2186
		{ 0x7cf00000, 0x44900000,	RTL_GIGA_MAC_VER_39 },
		{ 0x7c800000, 0x44800000,	RTL_GIGA_MAC_VER_39 },
2187
		{ 0x7c800000, 0x44000000,	RTL_GIGA_MAC_VER_37 },
2188
		{ 0x7cf00000, 0x40b00000,	RTL_GIGA_MAC_VER_30 },
2189 2190 2191
		{ 0x7cf00000, 0x40a00000,	RTL_GIGA_MAC_VER_30 },
		{ 0x7cf00000, 0x40900000,	RTL_GIGA_MAC_VER_29 },
		{ 0x7c800000, 0x40800000,	RTL_GIGA_MAC_VER_30 },
2192 2193 2194 2195 2196 2197
		{ 0x7cf00000, 0x34a00000,	RTL_GIGA_MAC_VER_09 },
		{ 0x7cf00000, 0x24a00000,	RTL_GIGA_MAC_VER_09 },
		{ 0x7cf00000, 0x34900000,	RTL_GIGA_MAC_VER_08 },
		{ 0x7cf00000, 0x24900000,	RTL_GIGA_MAC_VER_08 },
		{ 0x7cf00000, 0x34800000,	RTL_GIGA_MAC_VER_07 },
		{ 0x7cf00000, 0x24800000,	RTL_GIGA_MAC_VER_07 },
F
Francois Romieu 已提交
2198
		{ 0x7cf00000, 0x34000000,	RTL_GIGA_MAC_VER_13 },
2199
		{ 0x7cf00000, 0x34300000,	RTL_GIGA_MAC_VER_10 },
F
Francois Romieu 已提交
2200
		{ 0x7cf00000, 0x34200000,	RTL_GIGA_MAC_VER_16 },
2201 2202
		{ 0x7c800000, 0x34800000,	RTL_GIGA_MAC_VER_09 },
		{ 0x7c800000, 0x24800000,	RTL_GIGA_MAC_VER_09 },
F
Francois Romieu 已提交
2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215
		{ 0x7c800000, 0x34000000,	RTL_GIGA_MAC_VER_16 },
		/* FIXME: where did these entries come from ? -- FR */
		{ 0xfc800000, 0x38800000,	RTL_GIGA_MAC_VER_15 },
		{ 0xfc800000, 0x30800000,	RTL_GIGA_MAC_VER_14 },

		/* 8110 family. */
		{ 0xfc800000, 0x98000000,	RTL_GIGA_MAC_VER_06 },
		{ 0xfc800000, 0x18000000,	RTL_GIGA_MAC_VER_05 },
		{ 0xfc800000, 0x10000000,	RTL_GIGA_MAC_VER_04 },
		{ 0xfc800000, 0x04000000,	RTL_GIGA_MAC_VER_03 },
		{ 0xfc800000, 0x00800000,	RTL_GIGA_MAC_VER_02 },
		{ 0xfc800000, 0x00000000,	RTL_GIGA_MAC_VER_01 },

2216 2217
		/* Catch-all */
		{ 0x00000000, 0x00000000,	RTL_GIGA_MAC_NONE   }
2218 2219
	};
	const struct rtl_mac_info *p = mac_info;
L
Linus Torvalds 已提交
2220 2221
	u32 reg;

F
Francois Romieu 已提交
2222 2223
	reg = RTL_R32(TxConfig);
	while ((reg & p->mask) != p->val)
L
Linus Torvalds 已提交
2224 2225
		p++;
	tp->mac_version = p->mac_version;
2226 2227 2228 2229 2230

	if (tp->mac_version == RTL_GIGA_MAC_NONE) {
		netif_notice(tp, probe, dev,
			     "unknown MAC, using family default\n");
		tp->mac_version = default_version;
H
hayeswang 已提交
2231 2232 2233 2234
	} else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
		tp->mac_version = tp->mii.supports_gmii ?
				  RTL_GIGA_MAC_VER_42 :
				  RTL_GIGA_MAC_VER_43;
2235 2236 2237 2238 2239 2240 2241 2242
	} else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
		tp->mac_version = tp->mii.supports_gmii ?
				  RTL_GIGA_MAC_VER_45 :
				  RTL_GIGA_MAC_VER_47;
	} else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
		tp->mac_version = tp->mii.supports_gmii ?
				  RTL_GIGA_MAC_VER_46 :
				  RTL_GIGA_MAC_VER_48;
2243
	}
L
Linus Torvalds 已提交
2244 2245 2246 2247
}

static void rtl8169_print_mac_version(struct rtl8169_private *tp)
{
2248
	dprintk("mac_version = 0x%02x\n", tp->mac_version);
L
Linus Torvalds 已提交
2249 2250
}

F
Francois Romieu 已提交
2251 2252 2253 2254 2255
struct phy_reg {
	u16 reg;
	u16 val;
};

2256 2257
static void rtl_writephy_batch(struct rtl8169_private *tp,
			       const struct phy_reg *regs, int len)
F
Francois Romieu 已提交
2258 2259
{
	while (len-- > 0) {
2260
		rtl_writephy(tp, regs->reg, regs->val);
F
Francois Romieu 已提交
2261 2262 2263 2264
		regs++;
	}
}

2265 2266 2267 2268
#define PHY_READ		0x00000000
#define PHY_DATA_OR		0x10000000
#define PHY_DATA_AND		0x20000000
#define PHY_BJMPN		0x30000000
2269
#define PHY_MDIO_CHG		0x40000000
2270 2271 2272 2273 2274 2275 2276 2277 2278
#define PHY_CLEAR_READCOUNT	0x70000000
#define PHY_WRITE		0x80000000
#define PHY_READCOUNT_EQ_SKIP	0x90000000
#define PHY_COMP_EQ_SKIPN	0xa0000000
#define PHY_COMP_NEQ_SKIPN	0xb0000000
#define PHY_WRITE_PREVIOUS	0xc0000000
#define PHY_SKIPN		0xd0000000
#define PHY_DELAY_MS		0xe0000000

H
Hayes Wang 已提交
2279 2280 2281 2282 2283 2284 2285 2286
struct fw_info {
	u32	magic;
	char	version[RTL_VER_SIZE];
	__le32	fw_start;
	__le32	fw_len;
	u8	chksum;
} __packed;

2287 2288 2289
#define FW_OPCODE_SIZE	sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))

static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2290
{
2291
	const struct firmware *fw = rtl_fw->fw;
H
Hayes Wang 已提交
2292
	struct fw_info *fw_info = (struct fw_info *)fw->data;
2293 2294 2295 2296 2297 2298
	struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
	char *version = rtl_fw->version;
	bool rc = false;

	if (fw->size < FW_OPCODE_SIZE)
		goto out;
H
Hayes Wang 已提交
2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324

	if (!fw_info->magic) {
		size_t i, size, start;
		u8 checksum = 0;

		if (fw->size < sizeof(*fw_info))
			goto out;

		for (i = 0; i < fw->size; i++)
			checksum += fw->data[i];
		if (checksum != 0)
			goto out;

		start = le32_to_cpu(fw_info->fw_start);
		if (start > fw->size)
			goto out;

		size = le32_to_cpu(fw_info->fw_len);
		if (size > (fw->size - start) / FW_OPCODE_SIZE)
			goto out;

		memcpy(version, fw_info->version, RTL_VER_SIZE);

		pa->code = (__le32 *)(fw->data + start);
		pa->size = size;
	} else {
2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339
		if (fw->size % FW_OPCODE_SIZE)
			goto out;

		strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);

		pa->code = (__le32 *)fw->data;
		pa->size = fw->size / FW_OPCODE_SIZE;
	}
	version[RTL_VER_SIZE - 1] = 0;

	rc = true;
out:
	return rc;
}

2340 2341
static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
			   struct rtl_fw_phy_action *pa)
2342
{
2343
	bool rc = false;
2344
	size_t index;
2345

2346 2347
	for (index = 0; index < pa->size; index++) {
		u32 action = le32_to_cpu(pa->code[index]);
2348
		u32 regno = (action & 0x0fff0000) >> 16;
2349

2350 2351 2352 2353
		switch(action & 0xf0000000) {
		case PHY_READ:
		case PHY_DATA_OR:
		case PHY_DATA_AND:
2354
		case PHY_MDIO_CHG:
2355 2356 2357 2358 2359 2360 2361 2362
		case PHY_CLEAR_READCOUNT:
		case PHY_WRITE:
		case PHY_WRITE_PREVIOUS:
		case PHY_DELAY_MS:
			break;

		case PHY_BJMPN:
			if (regno > index) {
2363
				netif_err(tp, ifup, tp->dev,
F
Francois Romieu 已提交
2364
					  "Out of range of firmware\n");
2365
				goto out;
2366 2367 2368
			}
			break;
		case PHY_READCOUNT_EQ_SKIP:
2369
			if (index + 2 >= pa->size) {
2370
				netif_err(tp, ifup, tp->dev,
F
Francois Romieu 已提交
2371
					  "Out of range of firmware\n");
2372
				goto out;
2373 2374 2375 2376 2377
			}
			break;
		case PHY_COMP_EQ_SKIPN:
		case PHY_COMP_NEQ_SKIPN:
		case PHY_SKIPN:
2378
			if (index + 1 + regno >= pa->size) {
2379
				netif_err(tp, ifup, tp->dev,
F
Francois Romieu 已提交
2380
					  "Out of range of firmware\n");
2381
				goto out;
2382
			}
2383 2384
			break;

2385
		default:
2386
			netif_err(tp, ifup, tp->dev,
2387
				  "Invalid action 0x%08x\n", action);
2388
			goto out;
2389 2390
		}
	}
2391 2392 2393 2394
	rc = true;
out:
	return rc;
}
2395

2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414
static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
{
	struct net_device *dev = tp->dev;
	int rc = -EINVAL;

	if (!rtl_fw_format_ok(tp, rtl_fw)) {
		netif_err(tp, ifup, dev, "invalid firwmare\n");
		goto out;
	}

	if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
		rc = 0;
out:
	return rc;
}

static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
{
	struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2415
	struct mdio_ops org, *ops = &tp->mdio_ops;
2416 2417 2418 2419
	u32 predata, count;
	size_t index;

	predata = count = 0;
2420 2421
	org.write = ops->write;
	org.read = ops->read;
2422

2423 2424
	for (index = 0; index < pa->size; ) {
		u32 action = le32_to_cpu(pa->code[index]);
2425
		u32 data = action & 0x0000ffff;
2426 2427 2428 2429
		u32 regno = (action & 0x0fff0000) >> 16;

		if (!action)
			break;
2430 2431

		switch(action & 0xf0000000) {
2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447
		case PHY_READ:
			predata = rtl_readphy(tp, regno);
			count++;
			index++;
			break;
		case PHY_DATA_OR:
			predata |= data;
			index++;
			break;
		case PHY_DATA_AND:
			predata &= data;
			index++;
			break;
		case PHY_BJMPN:
			index -= regno;
			break;
2448 2449 2450 2451 2452 2453 2454 2455 2456
		case PHY_MDIO_CHG:
			if (data == 0) {
				ops->write = org.write;
				ops->read = org.read;
			} else if (data == 1) {
				ops->write = mac_mcu_write;
				ops->read = mac_mcu_read;
			}

2457 2458 2459 2460 2461 2462
			index++;
			break;
		case PHY_CLEAR_READCOUNT:
			count = 0;
			index++;
			break;
2463
		case PHY_WRITE:
2464 2465 2466 2467
			rtl_writephy(tp, regno, data);
			index++;
			break;
		case PHY_READCOUNT_EQ_SKIP:
F
Francois Romieu 已提交
2468
			index += (count == data) ? 2 : 1;
2469
			break;
2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491
		case PHY_COMP_EQ_SKIPN:
			if (predata == data)
				index += regno;
			index++;
			break;
		case PHY_COMP_NEQ_SKIPN:
			if (predata != data)
				index += regno;
			index++;
			break;
		case PHY_WRITE_PREVIOUS:
			rtl_writephy(tp, regno, predata);
			index++;
			break;
		case PHY_SKIPN:
			index += regno + 1;
			break;
		case PHY_DELAY_MS:
			mdelay(data);
			index++;
			break;

2492 2493 2494 2495
		default:
			BUG();
		}
	}
2496 2497 2498

	ops->write = org.write;
	ops->read = org.read;
2499 2500
}

2501 2502
static void rtl_release_firmware(struct rtl8169_private *tp)
{
2503 2504 2505 2506 2507
	if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
		release_firmware(tp->rtl_fw->fw);
		kfree(tp->rtl_fw);
	}
	tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2508 2509
}

2510
static void rtl_apply_firmware(struct rtl8169_private *tp)
2511
{
2512
	struct rtl_fw *rtl_fw = tp->rtl_fw;
2513 2514

	/* TODO: release firmware once rtl_phy_write_fw signals failures. */
2515
	if (!IS_ERR_OR_NULL(rtl_fw))
2516
		rtl_phy_write_fw(tp, rtl_fw);
2517 2518 2519 2520 2521 2522 2523 2524
}

static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
{
	if (rtl_readphy(tp, reg) != val)
		netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
	else
		rtl_apply_firmware(tp);
2525 2526
}

2527
static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
2528
{
2529
	static const struct phy_reg phy_reg_init[] = {
F
françois romieu 已提交
2530 2531 2532 2533 2534
		{ 0x1f, 0x0001 },
		{ 0x06, 0x006e },
		{ 0x08, 0x0708 },
		{ 0x15, 0x4000 },
		{ 0x18, 0x65c7 },
L
Linus Torvalds 已提交
2535

F
françois romieu 已提交
2536 2537 2538 2539 2540 2541 2542
		{ 0x1f, 0x0001 },
		{ 0x03, 0x00a1 },
		{ 0x02, 0x0008 },
		{ 0x01, 0x0120 },
		{ 0x00, 0x1000 },
		{ 0x04, 0x0800 },
		{ 0x04, 0x0000 },
L
Linus Torvalds 已提交
2543

F
françois romieu 已提交
2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589
		{ 0x03, 0xff41 },
		{ 0x02, 0xdf60 },
		{ 0x01, 0x0140 },
		{ 0x00, 0x0077 },
		{ 0x04, 0x7800 },
		{ 0x04, 0x7000 },

		{ 0x03, 0x802f },
		{ 0x02, 0x4f02 },
		{ 0x01, 0x0409 },
		{ 0x00, 0xf0f9 },
		{ 0x04, 0x9800 },
		{ 0x04, 0x9000 },

		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0xff95 },
		{ 0x00, 0xba00 },
		{ 0x04, 0xa800 },
		{ 0x04, 0xa000 },

		{ 0x03, 0xff41 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x0140 },
		{ 0x00, 0x00bb },
		{ 0x04, 0xb800 },
		{ 0x04, 0xb000 },

		{ 0x03, 0xdf41 },
		{ 0x02, 0xdc60 },
		{ 0x01, 0x6340 },
		{ 0x00, 0x007d },
		{ 0x04, 0xd800 },
		{ 0x04, 0xd000 },

		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x100a },
		{ 0x00, 0xa0ff },
		{ 0x04, 0xf800 },
		{ 0x04, 0xf000 },

		{ 0x1f, 0x0000 },
		{ 0x0b, 0x0000 },
		{ 0x00, 0x9200 }
	};
L
Linus Torvalds 已提交
2590

2591
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
L
Linus Torvalds 已提交
2592 2593
}

2594
static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2595
{
2596
	static const struct phy_reg phy_reg_init[] = {
F
Francois Romieu 已提交
2597 2598 2599 2600 2601
		{ 0x1f, 0x0002 },
		{ 0x01, 0x90d0 },
		{ 0x1f, 0x0000 }
	};

2602
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2603 2604
}

2605
static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2606 2607 2608
{
	struct pci_dev *pdev = tp->pci_dev;

2609 2610
	if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
	    (pdev->subsystem_device != 0xe000))
2611 2612
		return;

2613 2614 2615
	rtl_writephy(tp, 0x1f, 0x0001);
	rtl_writephy(tp, 0x10, 0xf01b);
	rtl_writephy(tp, 0x1f, 0x0000);
2616 2617
}

2618
static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2619
{
2620
	static const struct phy_reg phy_reg_init[] = {
2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659
		{ 0x1f, 0x0001 },
		{ 0x04, 0x0000 },
		{ 0x03, 0x00a1 },
		{ 0x02, 0x0008 },
		{ 0x01, 0x0120 },
		{ 0x00, 0x1000 },
		{ 0x04, 0x0800 },
		{ 0x04, 0x9000 },
		{ 0x03, 0x802f },
		{ 0x02, 0x4f02 },
		{ 0x01, 0x0409 },
		{ 0x00, 0xf099 },
		{ 0x04, 0x9800 },
		{ 0x04, 0xa000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0xff95 },
		{ 0x00, 0xba00 },
		{ 0x04, 0xa800 },
		{ 0x04, 0xf000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x101a },
		{ 0x00, 0xa0ff },
		{ 0x04, 0xf800 },
		{ 0x04, 0x0000 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x10, 0xf41b },
		{ 0x14, 0xfb54 },
		{ 0x18, 0xf5c7 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },
		{ 0x1f, 0x0000 }
	};

2660
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2661

2662
	rtl8169scd_hw_phy_config_quirk(tp);
2663 2664
}

2665
static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2666
{
2667
	static const struct phy_reg phy_reg_init[] = {
2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714
		{ 0x1f, 0x0001 },
		{ 0x04, 0x0000 },
		{ 0x03, 0x00a1 },
		{ 0x02, 0x0008 },
		{ 0x01, 0x0120 },
		{ 0x00, 0x1000 },
		{ 0x04, 0x0800 },
		{ 0x04, 0x9000 },
		{ 0x03, 0x802f },
		{ 0x02, 0x4f02 },
		{ 0x01, 0x0409 },
		{ 0x00, 0xf099 },
		{ 0x04, 0x9800 },
		{ 0x04, 0xa000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0xff95 },
		{ 0x00, 0xba00 },
		{ 0x04, 0xa800 },
		{ 0x04, 0xf000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x101a },
		{ 0x00, 0xa0ff },
		{ 0x04, 0xf800 },
		{ 0x04, 0x0000 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x0b, 0x8480 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x18, 0x67c7 },
		{ 0x04, 0x2000 },
		{ 0x03, 0x002f },
		{ 0x02, 0x4360 },
		{ 0x01, 0x0109 },
		{ 0x00, 0x3022 },
		{ 0x04, 0x2800 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },
		{ 0x1f, 0x0000 }
	};

2715
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2716 2717
}

2718
static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2719
{
2720
	static const struct phy_reg phy_reg_init[] = {
2721 2722 2723 2724
		{ 0x10, 0xf41b },
		{ 0x1f, 0x0000 }
	};

2725 2726
	rtl_writephy(tp, 0x1f, 0x0001);
	rtl_patchphy(tp, 0x16, 1 << 0);
2727

2728
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2729 2730
}

2731
static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2732
{
2733
	static const struct phy_reg phy_reg_init[] = {
2734 2735 2736 2737 2738
		{ 0x1f, 0x0001 },
		{ 0x10, 0xf41b },
		{ 0x1f, 0x0000 }
	};

2739
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2740 2741
}

2742
static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
F
Francois Romieu 已提交
2743
{
2744
	static const struct phy_reg phy_reg_init[] = {
F
Francois Romieu 已提交
2745 2746 2747 2748 2749 2750 2751
		{ 0x1f, 0x0000 },
		{ 0x1d, 0x0f00 },
		{ 0x1f, 0x0002 },
		{ 0x0c, 0x1ec8 },
		{ 0x1f, 0x0000 }
	};

2752
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
F
Francois Romieu 已提交
2753 2754
}

2755
static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
F
Francois Romieu 已提交
2756
{
2757
	static const struct phy_reg phy_reg_init[] = {
F
Francois Romieu 已提交
2758 2759 2760 2761 2762
		{ 0x1f, 0x0001 },
		{ 0x1d, 0x3d98 },
		{ 0x1f, 0x0000 }
	};

2763 2764 2765
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_patchphy(tp, 0x14, 1 << 5);
	rtl_patchphy(tp, 0x0d, 1 << 5);
F
Francois Romieu 已提交
2766

2767
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
F
Francois Romieu 已提交
2768 2769
}

2770
static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
F
Francois Romieu 已提交
2771
{
2772
	static const struct phy_reg phy_reg_init[] = {
2773 2774
		{ 0x1f, 0x0001 },
		{ 0x12, 0x2300 },
F
Francois Romieu 已提交
2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785
		{ 0x1f, 0x0002 },
		{ 0x00, 0x88d4 },
		{ 0x01, 0x82b1 },
		{ 0x03, 0x7002 },
		{ 0x08, 0x9e30 },
		{ 0x09, 0x01f0 },
		{ 0x0a, 0x5500 },
		{ 0x0c, 0x00c8 },
		{ 0x1f, 0x0003 },
		{ 0x12, 0xc096 },
		{ 0x16, 0x000a },
2786 2787 2788 2789
		{ 0x1f, 0x0000 },
		{ 0x1f, 0x0000 },
		{ 0x09, 0x2000 },
		{ 0x09, 0x0000 }
F
Francois Romieu 已提交
2790 2791
	};

2792
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2793

2794 2795 2796
	rtl_patchphy(tp, 0x14, 1 << 5);
	rtl_patchphy(tp, 0x0d, 1 << 5);
	rtl_writephy(tp, 0x1f, 0x0000);
F
Francois Romieu 已提交
2797 2798
}

2799
static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2800
{
2801
	static const struct phy_reg phy_reg_init[] = {
2802
		{ 0x1f, 0x0001 },
2803
		{ 0x12, 0x2300 },
2804 2805 2806 2807 2808 2809 2810
		{ 0x03, 0x802f },
		{ 0x02, 0x4f02 },
		{ 0x01, 0x0409 },
		{ 0x00, 0xf099 },
		{ 0x04, 0x9800 },
		{ 0x04, 0x9000 },
		{ 0x1d, 0x3d98 },
2811 2812
		{ 0x1f, 0x0002 },
		{ 0x0c, 0x7eb8 },
2813 2814 2815
		{ 0x06, 0x0761 },
		{ 0x1f, 0x0003 },
		{ 0x16, 0x0f0a },
2816 2817 2818
		{ 0x1f, 0x0000 }
	};

2819
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2820

2821 2822 2823 2824
	rtl_patchphy(tp, 0x16, 1 << 0);
	rtl_patchphy(tp, 0x14, 1 << 5);
	rtl_patchphy(tp, 0x0d, 1 << 5);
	rtl_writephy(tp, 0x1f, 0x0000);
2825 2826
}

2827
static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
F
Francois Romieu 已提交
2828
{
2829
	static const struct phy_reg phy_reg_init[] = {
F
Francois Romieu 已提交
2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840
		{ 0x1f, 0x0001 },
		{ 0x12, 0x2300 },
		{ 0x1d, 0x3d98 },
		{ 0x1f, 0x0002 },
		{ 0x0c, 0x7eb8 },
		{ 0x06, 0x5461 },
		{ 0x1f, 0x0003 },
		{ 0x16, 0x0f0a },
		{ 0x1f, 0x0000 }
	};

2841
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
F
Francois Romieu 已提交
2842

2843 2844 2845 2846
	rtl_patchphy(tp, 0x16, 1 << 0);
	rtl_patchphy(tp, 0x14, 1 << 5);
	rtl_patchphy(tp, 0x0d, 1 << 5);
	rtl_writephy(tp, 0x1f, 0x0000);
F
Francois Romieu 已提交
2847 2848
}

2849
static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2850
{
2851
	rtl8168c_3_hw_phy_config(tp);
2852 2853
}

2854
static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
F
Francois Romieu 已提交
2855
{
2856
	static const struct phy_reg phy_reg_init_0[] = {
2857
		/* Channel Estimation */
F
Francois Romieu 已提交
2858
		{ 0x1f, 0x0001 },
2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869
		{ 0x06, 0x4064 },
		{ 0x07, 0x2863 },
		{ 0x08, 0x059c },
		{ 0x09, 0x26b4 },
		{ 0x0a, 0x6a19 },
		{ 0x0b, 0xdcc8 },
		{ 0x10, 0xf06d },
		{ 0x14, 0x7f68 },
		{ 0x18, 0x7fd9 },
		{ 0x1c, 0xf0ff },
		{ 0x1d, 0x3d9c },
F
Francois Romieu 已提交
2870
		{ 0x1f, 0x0003 },
2871 2872 2873
		{ 0x12, 0xf49f },
		{ 0x13, 0x070b },
		{ 0x1a, 0x05ad },
2874 2875 2876 2877
		{ 0x14, 0x94c0 },

		/*
		 * Tx Error Issue
F
Francois Romieu 已提交
2878
		 * Enhance line driver power
2879
		 */
F
Francois Romieu 已提交
2880
		{ 0x1f, 0x0002 },
2881 2882 2883
		{ 0x06, 0x5561 },
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8332 },
2884 2885 2886 2887 2888 2889 2890 2891
		{ 0x06, 0x5561 },

		/*
		 * Can not link to 1Gbps with bad cable
		 * Decrease SNR threshold form 21.07dB to 19.04dB
		 */
		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },
2892

F
Francois Romieu 已提交
2893
		{ 0x1f, 0x0000 },
2894
		{ 0x0d, 0xf880 }
2895 2896
	};

2897
	rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2898

2899 2900 2901 2902
	/*
	 * Rx Error Issue
	 * Fine Tune Switching regulator parameter
	 */
2903
	rtl_writephy(tp, 0x1f, 0x0002);
2904 2905
	rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
	rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2906

2907
	if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2908
		static const struct phy_reg phy_reg_init[] = {
2909 2910 2911 2912 2913 2914 2915 2916 2917
			{ 0x1f, 0x0002 },
			{ 0x05, 0x669a },
			{ 0x1f, 0x0005 },
			{ 0x05, 0x8330 },
			{ 0x06, 0x669a },
			{ 0x1f, 0x0002 }
		};
		int val;

2918
		rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2919

2920
		val = rtl_readphy(tp, 0x0d);
2921 2922

		if ((val & 0x00ff) != 0x006c) {
2923
			static const u32 set[] = {
2924 2925 2926 2927 2928
				0x0065, 0x0066, 0x0067, 0x0068,
				0x0069, 0x006a, 0x006b, 0x006c
			};
			int i;

2929
			rtl_writephy(tp, 0x1f, 0x0002);
2930 2931 2932

			val &= 0xff00;
			for (i = 0; i < ARRAY_SIZE(set); i++)
2933
				rtl_writephy(tp, 0x0d, val | set[i]);
2934 2935
		}
	} else {
2936
		static const struct phy_reg phy_reg_init[] = {
2937 2938 2939 2940 2941 2942 2943
			{ 0x1f, 0x0002 },
			{ 0x05, 0x6662 },
			{ 0x1f, 0x0005 },
			{ 0x05, 0x8330 },
			{ 0x06, 0x6662 }
		};

2944
		rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2945 2946
	}

2947
	/* RSET couple improve */
2948 2949 2950
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_patchphy(tp, 0x0d, 0x0300);
	rtl_patchphy(tp, 0x0f, 0x0010);
2951

2952
	/* Fine tune PLL performance */
2953
	rtl_writephy(tp, 0x1f, 0x0002);
2954 2955
	rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
	rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2956

2957 2958
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x001b);
2959 2960

	rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2961

2962
	rtl_writephy(tp, 0x1f, 0x0000);
2963 2964
}

2965
static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2966
{
2967
	static const struct phy_reg phy_reg_init_0[] = {
2968
		/* Channel Estimation */
2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986
		{ 0x1f, 0x0001 },
		{ 0x06, 0x4064 },
		{ 0x07, 0x2863 },
		{ 0x08, 0x059c },
		{ 0x09, 0x26b4 },
		{ 0x0a, 0x6a19 },
		{ 0x0b, 0xdcc8 },
		{ 0x10, 0xf06d },
		{ 0x14, 0x7f68 },
		{ 0x18, 0x7fd9 },
		{ 0x1c, 0xf0ff },
		{ 0x1d, 0x3d9c },
		{ 0x1f, 0x0003 },
		{ 0x12, 0xf49f },
		{ 0x13, 0x070b },
		{ 0x1a, 0x05ad },
		{ 0x14, 0x94c0 },

2987 2988
		/*
		 * Tx Error Issue
F
Francois Romieu 已提交
2989
		 * Enhance line driver power
2990
		 */
2991 2992 2993 2994
		{ 0x1f, 0x0002 },
		{ 0x06, 0x5561 },
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8332 },
2995 2996 2997 2998 2999 3000 3001 3002
		{ 0x06, 0x5561 },

		/*
		 * Can not link to 1Gbps with bad cable
		 * Decrease SNR threshold form 21.07dB to 19.04dB
		 */
		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },
3003 3004

		{ 0x1f, 0x0000 },
3005
		{ 0x0d, 0xf880 }
F
Francois Romieu 已提交
3006 3007
	};

3008
	rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
F
Francois Romieu 已提交
3009

3010
	if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3011
		static const struct phy_reg phy_reg_init[] = {
3012 3013
			{ 0x1f, 0x0002 },
			{ 0x05, 0x669a },
F
Francois Romieu 已提交
3014
			{ 0x1f, 0x0005 },
3015 3016 3017 3018 3019 3020 3021
			{ 0x05, 0x8330 },
			{ 0x06, 0x669a },

			{ 0x1f, 0x0002 }
		};
		int val;

3022
		rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3023

3024
		val = rtl_readphy(tp, 0x0d);
3025
		if ((val & 0x00ff) != 0x006c) {
J
Joe Perches 已提交
3026
			static const u32 set[] = {
3027 3028 3029 3030 3031
				0x0065, 0x0066, 0x0067, 0x0068,
				0x0069, 0x006a, 0x006b, 0x006c
			};
			int i;

3032
			rtl_writephy(tp, 0x1f, 0x0002);
3033 3034 3035

			val &= 0xff00;
			for (i = 0; i < ARRAY_SIZE(set); i++)
3036
				rtl_writephy(tp, 0x0d, val | set[i]);
3037 3038
		}
	} else {
3039
		static const struct phy_reg phy_reg_init[] = {
3040 3041
			{ 0x1f, 0x0002 },
			{ 0x05, 0x2642 },
F
Francois Romieu 已提交
3042
			{ 0x1f, 0x0005 },
3043 3044
			{ 0x05, 0x8330 },
			{ 0x06, 0x2642 }
F
Francois Romieu 已提交
3045 3046
		};

3047
		rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
F
Francois Romieu 已提交
3048 3049
	}

3050
	/* Fine tune PLL performance */
3051
	rtl_writephy(tp, 0x1f, 0x0002);
3052 3053
	rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
	rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3054

3055
	/* Switching regulator Slew rate */
3056 3057
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_patchphy(tp, 0x0f, 0x0017);
3058

3059 3060
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x001b);
3061 3062

	rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3063

3064
	rtl_writephy(tp, 0x1f, 0x0000);
3065 3066
}

3067
static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3068
{
3069
	static const struct phy_reg phy_reg_init[] = {
3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124
		{ 0x1f, 0x0002 },
		{ 0x10, 0x0008 },
		{ 0x0d, 0x006c },

		{ 0x1f, 0x0000 },
		{ 0x0d, 0xf880 },

		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },

		{ 0x1f, 0x0001 },
		{ 0x0b, 0xa4d8 },
		{ 0x09, 0x281c },
		{ 0x07, 0x2883 },
		{ 0x0a, 0x6b35 },
		{ 0x1d, 0x3da4 },
		{ 0x1c, 0xeffd },
		{ 0x14, 0x7f52 },
		{ 0x18, 0x7fc6 },
		{ 0x08, 0x0601 },
		{ 0x06, 0x4063 },
		{ 0x10, 0xf074 },
		{ 0x1f, 0x0003 },
		{ 0x13, 0x0789 },
		{ 0x12, 0xf4bd },
		{ 0x1a, 0x04fd },
		{ 0x14, 0x84b0 },
		{ 0x1f, 0x0000 },
		{ 0x00, 0x9200 },

		{ 0x1f, 0x0005 },
		{ 0x01, 0x0340 },
		{ 0x1f, 0x0001 },
		{ 0x04, 0x4000 },
		{ 0x03, 0x1d21 },
		{ 0x02, 0x0c32 },
		{ 0x01, 0x0200 },
		{ 0x00, 0x5554 },
		{ 0x04, 0x4800 },
		{ 0x04, 0x4000 },
		{ 0x04, 0xf000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x101a },
		{ 0x00, 0xa0ff },
		{ 0x04, 0xf800 },
		{ 0x04, 0xf000 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0007 },
		{ 0x1e, 0x0023 },
		{ 0x16, 0x0000 },
		{ 0x1f, 0x0000 }
	};

3125
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
F
Francois Romieu 已提交
3126 3127
}

F
françois romieu 已提交
3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143
static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
{
	static const struct phy_reg phy_reg_init[] = {
		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },

		{ 0x1f, 0x0007 },
		{ 0x1e, 0x002d },
		{ 0x18, 0x0040 },
		{ 0x1f, 0x0000 }
	};

	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
	rtl_patchphy(tp, 0x0d, 1 << 5);
}

H
Hayes Wang 已提交
3144
static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
H
hayeswang 已提交
3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173
{
	static const struct phy_reg phy_reg_init[] = {
		/* Enable Delay cap */
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8b80 },
		{ 0x06, 0xc896 },
		{ 0x1f, 0x0000 },

		/* Channel estimation fine tune */
		{ 0x1f, 0x0001 },
		{ 0x0b, 0x6c20 },
		{ 0x07, 0x2872 },
		{ 0x1c, 0xefff },
		{ 0x1f, 0x0003 },
		{ 0x14, 0x6420 },
		{ 0x1f, 0x0000 },

		/* Update PFM & 10M TX idle timer */
		{ 0x1f, 0x0007 },
		{ 0x1e, 0x002f },
		{ 0x15, 0x1919 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0007 },
		{ 0x1e, 0x00ac },
		{ 0x18, 0x0006 },
		{ 0x1f, 0x0000 }
	};

F
Francois Romieu 已提交
3174 3175
	rtl_apply_firmware(tp);

H
hayeswang 已提交
3176 3177 3178 3179 3180
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));

	/* DCO enable for 10M IDLE Power */
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x0023);
3181
	rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
H
hayeswang 已提交
3182 3183 3184 3185
	rtl_writephy(tp, 0x1f, 0x0000);

	/* For impedance matching */
	rtl_writephy(tp, 0x1f, 0x0002);
3186
	rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
F
Francois Romieu 已提交
3187
	rtl_writephy(tp, 0x1f, 0x0000);
H
hayeswang 已提交
3188 3189 3190 3191

	/* PHY auto speed down */
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x002d);
3192
	rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
H
hayeswang 已提交
3193
	rtl_writephy(tp, 0x1f, 0x0000);
3194
	rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
H
hayeswang 已提交
3195 3196 3197

	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b86);
3198
	rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
H
hayeswang 已提交
3199 3200 3201 3202
	rtl_writephy(tp, 0x1f, 0x0000);

	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b85);
3203
	rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
H
hayeswang 已提交
3204 3205
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x0020);
3206
	rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
H
hayeswang 已提交
3207 3208 3209 3210 3211 3212 3213 3214 3215 3216
	rtl_writephy(tp, 0x1f, 0x0006);
	rtl_writephy(tp, 0x00, 0x5a00);
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, 0x0d, 0x0007);
	rtl_writephy(tp, 0x0e, 0x003c);
	rtl_writephy(tp, 0x0d, 0x4007);
	rtl_writephy(tp, 0x0e, 0x0000);
	rtl_writephy(tp, 0x0d, 0x0000);
}

3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233
static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
{
	const u16 w[] = {
		addr[0] | (addr[1] << 8),
		addr[2] | (addr[3] << 8),
		addr[4] | (addr[5] << 8)
	};
	const struct exgmac_reg e[] = {
		{ .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
		{ .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
		{ .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
		{ .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
	};

	rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
}

H
Hayes Wang 已提交
3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269
static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
{
	static const struct phy_reg phy_reg_init[] = {
		/* Enable Delay cap */
		{ 0x1f, 0x0004 },
		{ 0x1f, 0x0007 },
		{ 0x1e, 0x00ac },
		{ 0x18, 0x0006 },
		{ 0x1f, 0x0002 },
		{ 0x1f, 0x0000 },
		{ 0x1f, 0x0000 },

		/* Channel estimation fine tune */
		{ 0x1f, 0x0003 },
		{ 0x09, 0xa20f },
		{ 0x1f, 0x0000 },
		{ 0x1f, 0x0000 },

		/* Green Setting */
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8b5b },
		{ 0x06, 0x9222 },
		{ 0x05, 0x8b6d },
		{ 0x06, 0x8000 },
		{ 0x05, 0x8b76 },
		{ 0x06, 0x8000 },
		{ 0x1f, 0x0000 }
	};

	rtl_apply_firmware(tp);

	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));

	/* For 4-corner performance improve */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b80);
3270
	rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
H
Hayes Wang 已提交
3271 3272 3273 3274 3275 3276
	rtl_writephy(tp, 0x1f, 0x0000);

	/* PHY auto speed down */
	rtl_writephy(tp, 0x1f, 0x0004);
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x002d);
3277
	rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
H
Hayes Wang 已提交
3278 3279
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_writephy(tp, 0x1f, 0x0000);
3280
	rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
H
Hayes Wang 已提交
3281 3282 3283 3284

	/* improve 10M EEE waveform */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b86);
3285
	rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
H
Hayes Wang 已提交
3286 3287 3288 3289 3290
	rtl_writephy(tp, 0x1f, 0x0000);

	/* Improve 2-pair detection performance */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b85);
3291
	rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
H
Hayes Wang 已提交
3292 3293 3294
	rtl_writephy(tp, 0x1f, 0x0000);

	/* EEE setting */
3295
	rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
H
Hayes Wang 已提交
3296 3297
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b85);
3298
	rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
H
Hayes Wang 已提交
3299 3300 3301
	rtl_writephy(tp, 0x1f, 0x0004);
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x0020);
3302
	rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
H
Hayes Wang 已提交
3303 3304 3305 3306 3307 3308 3309 3310 3311 3312
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, 0x0d, 0x0007);
	rtl_writephy(tp, 0x0e, 0x003c);
	rtl_writephy(tp, 0x0d, 0x4007);
	rtl_writephy(tp, 0x0e, 0x0000);
	rtl_writephy(tp, 0x0d, 0x0000);

	/* Green feature */
	rtl_writephy(tp, 0x1f, 0x0003);
3313 3314
	rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
	rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
H
Hayes Wang 已提交
3315
	rtl_writephy(tp, 0x1f, 0x0000);
H
hayeswang 已提交
3316

3317 3318
	/* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
	rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
H
Hayes Wang 已提交
3319 3320
}

3321 3322 3323 3324 3325
static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
{
	/* For 4-corner performance improve */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b80);
3326
	rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3327 3328 3329 3330 3331
	rtl_writephy(tp, 0x1f, 0x0000);

	/* PHY auto speed down */
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x002d);
3332
	rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3333
	rtl_writephy(tp, 0x1f, 0x0000);
3334
	rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3335 3336 3337 3338

	/* Improve 10M EEE waveform */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b86);
3339
	rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3340 3341 3342
	rtl_writephy(tp, 0x1f, 0x0000);
}

3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383
static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
{
	static const struct phy_reg phy_reg_init[] = {
		/* Channel estimation fine tune */
		{ 0x1f, 0x0003 },
		{ 0x09, 0xa20f },
		{ 0x1f, 0x0000 },

		/* Modify green table for giga & fnet */
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8b55 },
		{ 0x06, 0x0000 },
		{ 0x05, 0x8b5e },
		{ 0x06, 0x0000 },
		{ 0x05, 0x8b67 },
		{ 0x06, 0x0000 },
		{ 0x05, 0x8b70 },
		{ 0x06, 0x0000 },
		{ 0x1f, 0x0000 },
		{ 0x1f, 0x0007 },
		{ 0x1e, 0x0078 },
		{ 0x17, 0x0000 },
		{ 0x19, 0x00fb },
		{ 0x1f, 0x0000 },

		/* Modify green table for 10M */
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8b79 },
		{ 0x06, 0xaa00 },
		{ 0x1f, 0x0000 },

		/* Disable hiimpedance detection (RTCT) */
		{ 0x1f, 0x0003 },
		{ 0x01, 0x328a },
		{ 0x1f, 0x0000 }
	};

	rtl_apply_firmware(tp);

	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));

3384
	rtl8168f_hw_phy_config(tp);
3385 3386 3387 3388

	/* Improve 2-pair detection performance */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b85);
3389
	rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3390 3391 3392 3393 3394 3395 3396
	rtl_writephy(tp, 0x1f, 0x0000);
}

static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
{
	rtl_apply_firmware(tp);

3397
	rtl8168f_hw_phy_config(tp);
3398 3399
}

3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444
static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
{
	static const struct phy_reg phy_reg_init[] = {
		/* Channel estimation fine tune */
		{ 0x1f, 0x0003 },
		{ 0x09, 0xa20f },
		{ 0x1f, 0x0000 },

		/* Modify green table for giga & fnet */
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8b55 },
		{ 0x06, 0x0000 },
		{ 0x05, 0x8b5e },
		{ 0x06, 0x0000 },
		{ 0x05, 0x8b67 },
		{ 0x06, 0x0000 },
		{ 0x05, 0x8b70 },
		{ 0x06, 0x0000 },
		{ 0x1f, 0x0000 },
		{ 0x1f, 0x0007 },
		{ 0x1e, 0x0078 },
		{ 0x17, 0x0000 },
		{ 0x19, 0x00aa },
		{ 0x1f, 0x0000 },

		/* Modify green table for 10M */
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8b79 },
		{ 0x06, 0xaa00 },
		{ 0x1f, 0x0000 },

		/* Disable hiimpedance detection (RTCT) */
		{ 0x1f, 0x0003 },
		{ 0x01, 0x328a },
		{ 0x1f, 0x0000 }
	};


	rtl_apply_firmware(tp);

	rtl8168f_hw_phy_config(tp);

	/* Improve 2-pair detection performance */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b85);
3445
	rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3446 3447 3448 3449 3450 3451 3452
	rtl_writephy(tp, 0x1f, 0x0000);

	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));

	/* Modify green table for giga */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b54);
3453
	rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3454
	rtl_writephy(tp, 0x05, 0x8b5d);
3455
	rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3456
	rtl_writephy(tp, 0x05, 0x8a7c);
3457
	rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3458
	rtl_writephy(tp, 0x05, 0x8a7f);
3459
	rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3460
	rtl_writephy(tp, 0x05, 0x8a82);
3461
	rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3462
	rtl_writephy(tp, 0x05, 0x8a85);
3463
	rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3464
	rtl_writephy(tp, 0x05, 0x8a88);
3465
	rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3466 3467 3468 3469 3470
	rtl_writephy(tp, 0x1f, 0x0000);

	/* uc same-seed solution */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b85);
3471
	rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3472 3473 3474
	rtl_writephy(tp, 0x1f, 0x0000);

	/* eee setting */
3475
	rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3476 3477
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b85);
3478
	rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3479 3480 3481
	rtl_writephy(tp, 0x1f, 0x0004);
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x0020);
3482
	rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3483 3484 3485 3486 3487 3488 3489 3490 3491
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, 0x0d, 0x0007);
	rtl_writephy(tp, 0x0e, 0x003c);
	rtl_writephy(tp, 0x0d, 0x4007);
	rtl_writephy(tp, 0x0e, 0x0000);
	rtl_writephy(tp, 0x0d, 0x0000);

	/* Green feature */
	rtl_writephy(tp, 0x1f, 0x0003);
3492 3493
	rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
	rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3494 3495 3496
	rtl_writephy(tp, 0x1f, 0x0000);
}

H
Hayes Wang 已提交
3497 3498 3499 3500
static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
{
	rtl_apply_firmware(tp);

3501 3502 3503
	rtl_writephy(tp, 0x1f, 0x0a46);
	if (rtl_readphy(tp, 0x10) & 0x0100) {
		rtl_writephy(tp, 0x1f, 0x0bcc);
3504
		rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3505 3506
	} else {
		rtl_writephy(tp, 0x1f, 0x0bcc);
3507
		rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3508
	}
H
Hayes Wang 已提交
3509

3510 3511 3512
	rtl_writephy(tp, 0x1f, 0x0a46);
	if (rtl_readphy(tp, 0x13) & 0x0100) {
		rtl_writephy(tp, 0x1f, 0x0c41);
3513
		rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3514
	} else {
3515
		rtl_writephy(tp, 0x1f, 0x0c41);
3516
		rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3517
	}
H
Hayes Wang 已提交
3518

3519 3520
	/* Enable PHY auto speed down */
	rtl_writephy(tp, 0x1f, 0x0a44);
3521
	rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
H
Hayes Wang 已提交
3522

3523
	rtl_writephy(tp, 0x1f, 0x0bcc);
3524
	rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3525
	rtl_writephy(tp, 0x1f, 0x0a44);
3526
	rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3527 3528
	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x8084);
3529 3530
	rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
	rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3531

3532 3533
	/* EEE auto-fallback function */
	rtl_writephy(tp, 0x1f, 0x0a4b);
3534
	rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
H
Hayes Wang 已提交
3535

3536 3537 3538
	/* Enable UC LPF tune function */
	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x8012);
3539
	rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3540 3541

	rtl_writephy(tp, 0x1f, 0x0c42);
3542
	rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3543

3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554
	/* Improve SWR Efficiency */
	rtl_writephy(tp, 0x1f, 0x0bcd);
	rtl_writephy(tp, 0x14, 0x5065);
	rtl_writephy(tp, 0x14, 0xd065);
	rtl_writephy(tp, 0x1f, 0x0bc8);
	rtl_writephy(tp, 0x11, 0x5655);
	rtl_writephy(tp, 0x1f, 0x0bcd);
	rtl_writephy(tp, 0x14, 0x1065);
	rtl_writephy(tp, 0x14, 0x9065);
	rtl_writephy(tp, 0x14, 0x1065);

3555 3556 3557
	/* Check ALDPS bit, disable it if enabled */
	rtl_writephy(tp, 0x1f, 0x0a43);
	if (rtl_readphy(tp, 0x10) & 0x0004)
3558
		rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3559

3560
	rtl_writephy(tp, 0x1f, 0x0000);
H
Hayes Wang 已提交
3561 3562
}

H
hayeswang 已提交
3563 3564 3565 3566 3567
static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
{
	rtl_apply_firmware(tp);
}

3568 3569 3570 3571 3572 3573 3574 3575 3576 3577
static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
{
	u16 dout_tapbin;
	u32 data;

	rtl_apply_firmware(tp);

	/* CHN EST parameters adjust - giga master */
	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x809b);
3578
	rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3579
	rtl_writephy(tp, 0x13, 0x80a2);
3580
	rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3581
	rtl_writephy(tp, 0x13, 0x80a4);
3582
	rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3583
	rtl_writephy(tp, 0x13, 0x809c);
3584
	rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3585 3586 3587 3588 3589
	rtl_writephy(tp, 0x1f, 0x0000);

	/* CHN EST parameters adjust - giga slave */
	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x80ad);
3590
	rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3591
	rtl_writephy(tp, 0x13, 0x80b4);
3592
	rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3593
	rtl_writephy(tp, 0x13, 0x80ac);
3594
	rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3595 3596 3597 3598 3599
	rtl_writephy(tp, 0x1f, 0x0000);

	/* CHN EST parameters adjust - fnet */
	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x808e);
3600
	rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3601
	rtl_writephy(tp, 0x13, 0x8090);
3602
	rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3603
	rtl_writephy(tp, 0x13, 0x8092);
3604
	rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622
	rtl_writephy(tp, 0x1f, 0x0000);

	/* enable R-tune & PGA-retune function */
	dout_tapbin = 0;
	rtl_writephy(tp, 0x1f, 0x0a46);
	data = rtl_readphy(tp, 0x13);
	data &= 3;
	data <<= 2;
	dout_tapbin |= data;
	data = rtl_readphy(tp, 0x12);
	data &= 0xc000;
	data >>= 14;
	dout_tapbin |= data;
	dout_tapbin = ~(dout_tapbin^0x08);
	dout_tapbin <<= 12;
	dout_tapbin &= 0xf000;
	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x827a);
3623
	rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3624
	rtl_writephy(tp, 0x13, 0x827b);
3625
	rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3626
	rtl_writephy(tp, 0x13, 0x827c);
3627
	rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3628
	rtl_writephy(tp, 0x13, 0x827d);
3629
	rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3630 3631 3632

	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x0811);
3633
	rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3634
	rtl_writephy(tp, 0x1f, 0x0a42);
3635
	rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3636 3637 3638 3639
	rtl_writephy(tp, 0x1f, 0x0000);

	/* enable GPHY 10M */
	rtl_writephy(tp, 0x1f, 0x0a44);
3640
	rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3641 3642 3643 3644
	rtl_writephy(tp, 0x1f, 0x0000);

	/* SAR ADC performance */
	rtl_writephy(tp, 0x1f, 0x0bca);
3645
	rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3646 3647 3648 3649
	rtl_writephy(tp, 0x1f, 0x0000);

	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x803f);
3650
	rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3651
	rtl_writephy(tp, 0x13, 0x8047);
3652
	rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3653
	rtl_writephy(tp, 0x13, 0x804f);
3654
	rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3655
	rtl_writephy(tp, 0x13, 0x8057);
3656
	rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3657
	rtl_writephy(tp, 0x13, 0x805f);
3658
	rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3659
	rtl_writephy(tp, 0x13, 0x8067);
3660
	rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3661
	rtl_writephy(tp, 0x13, 0x806f);
3662
	rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3663 3664 3665 3666
	rtl_writephy(tp, 0x1f, 0x0000);

	/* disable phy pfm mode */
	rtl_writephy(tp, 0x1f, 0x0a44);
3667
	rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3668 3669 3670 3671 3672
	rtl_writephy(tp, 0x1f, 0x0000);

	/* Check ALDPS bit, disable it if enabled */
	rtl_writephy(tp, 0x1f, 0x0a43);
	if (rtl_readphy(tp, 0x10) & 0x0004)
3673
		rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688

	rtl_writephy(tp, 0x1f, 0x0000);
}

static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
{
	u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
	u16 rlen;
	u32 data;

	rtl_apply_firmware(tp);

	/* CHIN EST parameter update */
	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x808a);
3689
	rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3690 3691 3692 3693 3694
	rtl_writephy(tp, 0x1f, 0x0000);

	/* enable R-tune & PGA-retune function */
	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x0811);
3695
	rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3696
	rtl_writephy(tp, 0x1f, 0x0a42);
3697
	rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3698 3699 3700 3701
	rtl_writephy(tp, 0x1f, 0x0000);

	/* enable GPHY 10M */
	rtl_writephy(tp, 0x1f, 0x0a44);
3702
	rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718
	rtl_writephy(tp, 0x1f, 0x0000);

	r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
	data = r8168_mac_ocp_read(tp, 0xdd02);
	ioffset_p3 = ((data & 0x80)>>7);
	ioffset_p3 <<= 3;

	data = r8168_mac_ocp_read(tp, 0xdd00);
	ioffset_p3 |= ((data & (0xe000))>>13);
	ioffset_p2 = ((data & (0x1e00))>>9);
	ioffset_p1 = ((data & (0x01e0))>>5);
	ioffset_p0 = ((data & 0x0010)>>4);
	ioffset_p0 <<= 3;
	ioffset_p0 |= (data & (0x07));
	data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);

3719 3720
	if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
	    (ioffset_p1 != 0x0f) || (ioffset_p0 == 0x0f)) {
3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739
		rtl_writephy(tp, 0x1f, 0x0bcf);
		rtl_writephy(tp, 0x16, data);
		rtl_writephy(tp, 0x1f, 0x0000);
	}

	/* Modify rlen (TX LPF corner frequency) level */
	rtl_writephy(tp, 0x1f, 0x0bcd);
	data = rtl_readphy(tp, 0x16);
	data &= 0x000f;
	rlen = 0;
	if (data > 3)
		rlen = data - 3;
	data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
	rtl_writephy(tp, 0x17, data);
	rtl_writephy(tp, 0x1f, 0x0bcd);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* disable phy pfm mode */
	rtl_writephy(tp, 0x1f, 0x0a44);
3740
	rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3741 3742 3743 3744 3745
	rtl_writephy(tp, 0x1f, 0x0000);

	/* Check ALDPS bit, disable it if enabled */
	rtl_writephy(tp, 0x1f, 0x0a43);
	if (rtl_readphy(tp, 0x10) & 0x0004)
3746
		rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3747 3748 3749 3750

	rtl_writephy(tp, 0x1f, 0x0000);
}

3751
static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3752
{
3753
	static const struct phy_reg phy_reg_init[] = {
3754 3755 3756 3757 3758 3759
		{ 0x1f, 0x0003 },
		{ 0x08, 0x441d },
		{ 0x01, 0x9100 },
		{ 0x1f, 0x0000 }
	};

3760 3761 3762 3763
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_patchphy(tp, 0x11, 1 << 12);
	rtl_patchphy(tp, 0x19, 1 << 13);
	rtl_patchphy(tp, 0x10, 1 << 15);
3764

3765
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3766 3767
}

3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784
static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
{
	static const struct phy_reg phy_reg_init[] = {
		{ 0x1f, 0x0005 },
		{ 0x1a, 0x0000 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0004 },
		{ 0x1c, 0x0000 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x15, 0x7701 },
		{ 0x1f, 0x0000 }
	};

	/* Disable ALDPS before ram code */
3785 3786 3787
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, 0x18, 0x0310);
	msleep(100);
3788

3789
	rtl_apply_firmware(tp);
3790 3791 3792 3793

	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
}

3794 3795 3796
static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
{
	/* Disable ALDPS before setting firmware */
3797 3798 3799
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, 0x18, 0x0310);
	msleep(20);
3800 3801 3802 3803

	rtl_apply_firmware(tp);

	/* EEE setting */
3804
	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3805 3806 3807 3808 3809 3810
	rtl_writephy(tp, 0x1f, 0x0004);
	rtl_writephy(tp, 0x10, 0x401f);
	rtl_writephy(tp, 0x19, 0x7030);
	rtl_writephy(tp, 0x1f, 0x0000);
}

H
Hayes Wang 已提交
3811 3812 3813 3814 3815 3816 3817 3818 3819 3820
static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
{
	static const struct phy_reg phy_reg_init[] = {
		{ 0x1f, 0x0004 },
		{ 0x10, 0xc07f },
		{ 0x19, 0x7030 },
		{ 0x1f, 0x0000 }
	};

	/* Disable ALDPS before ram code */
3821 3822 3823
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, 0x18, 0x0310);
	msleep(100);
H
Hayes Wang 已提交
3824 3825 3826

	rtl_apply_firmware(tp);

3827
	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
H
Hayes Wang 已提交
3828 3829
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));

3830
	rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
H
Hayes Wang 已提交
3831 3832
}

3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843
static void rtl_hw_phy_config(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl8169_print_mac_version(tp);

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_01:
		break;
	case RTL_GIGA_MAC_VER_02:
	case RTL_GIGA_MAC_VER_03:
3844
		rtl8169s_hw_phy_config(tp);
3845 3846
		break;
	case RTL_GIGA_MAC_VER_04:
3847
		rtl8169sb_hw_phy_config(tp);
3848
		break;
3849
	case RTL_GIGA_MAC_VER_05:
3850
		rtl8169scd_hw_phy_config(tp);
3851
		break;
3852
	case RTL_GIGA_MAC_VER_06:
3853
		rtl8169sce_hw_phy_config(tp);
3854
		break;
3855 3856 3857
	case RTL_GIGA_MAC_VER_07:
	case RTL_GIGA_MAC_VER_08:
	case RTL_GIGA_MAC_VER_09:
3858
		rtl8102e_hw_phy_config(tp);
3859
		break;
3860
	case RTL_GIGA_MAC_VER_11:
3861
		rtl8168bb_hw_phy_config(tp);
3862 3863
		break;
	case RTL_GIGA_MAC_VER_12:
3864
		rtl8168bef_hw_phy_config(tp);
3865 3866
		break;
	case RTL_GIGA_MAC_VER_17:
3867
		rtl8168bef_hw_phy_config(tp);
3868
		break;
F
Francois Romieu 已提交
3869
	case RTL_GIGA_MAC_VER_18:
3870
		rtl8168cp_1_hw_phy_config(tp);
F
Francois Romieu 已提交
3871 3872
		break;
	case RTL_GIGA_MAC_VER_19:
3873
		rtl8168c_1_hw_phy_config(tp);
F
Francois Romieu 已提交
3874
		break;
3875
	case RTL_GIGA_MAC_VER_20:
3876
		rtl8168c_2_hw_phy_config(tp);
3877
		break;
F
Francois Romieu 已提交
3878
	case RTL_GIGA_MAC_VER_21:
3879
		rtl8168c_3_hw_phy_config(tp);
F
Francois Romieu 已提交
3880
		break;
3881
	case RTL_GIGA_MAC_VER_22:
3882
		rtl8168c_4_hw_phy_config(tp);
3883
		break;
F
Francois Romieu 已提交
3884
	case RTL_GIGA_MAC_VER_23:
3885
	case RTL_GIGA_MAC_VER_24:
3886
		rtl8168cp_2_hw_phy_config(tp);
F
Francois Romieu 已提交
3887
		break;
F
Francois Romieu 已提交
3888
	case RTL_GIGA_MAC_VER_25:
3889
		rtl8168d_1_hw_phy_config(tp);
3890 3891
		break;
	case RTL_GIGA_MAC_VER_26:
3892
		rtl8168d_2_hw_phy_config(tp);
3893 3894
		break;
	case RTL_GIGA_MAC_VER_27:
3895
		rtl8168d_3_hw_phy_config(tp);
F
Francois Romieu 已提交
3896
		break;
F
françois romieu 已提交
3897 3898 3899
	case RTL_GIGA_MAC_VER_28:
		rtl8168d_4_hw_phy_config(tp);
		break;
3900 3901 3902 3903
	case RTL_GIGA_MAC_VER_29:
	case RTL_GIGA_MAC_VER_30:
		rtl8105e_hw_phy_config(tp);
		break;
F
Francois Romieu 已提交
3904 3905 3906
	case RTL_GIGA_MAC_VER_31:
		/* None. */
		break;
H
hayeswang 已提交
3907 3908
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
H
Hayes Wang 已提交
3909 3910 3911 3912
		rtl8168e_1_hw_phy_config(tp);
		break;
	case RTL_GIGA_MAC_VER_34:
		rtl8168e_2_hw_phy_config(tp);
H
hayeswang 已提交
3913
		break;
3914 3915 3916 3917 3918 3919
	case RTL_GIGA_MAC_VER_35:
		rtl8168f_1_hw_phy_config(tp);
		break;
	case RTL_GIGA_MAC_VER_36:
		rtl8168f_2_hw_phy_config(tp);
		break;
F
Francois Romieu 已提交
3920

3921 3922 3923 3924
	case RTL_GIGA_MAC_VER_37:
		rtl8402_hw_phy_config(tp);
		break;

3925 3926 3927 3928
	case RTL_GIGA_MAC_VER_38:
		rtl8411_hw_phy_config(tp);
		break;

H
Hayes Wang 已提交
3929 3930 3931 3932
	case RTL_GIGA_MAC_VER_39:
		rtl8106e_hw_phy_config(tp);
		break;

H
Hayes Wang 已提交
3933 3934 3935
	case RTL_GIGA_MAC_VER_40:
		rtl8168g_1_hw_phy_config(tp);
		break;
H
hayeswang 已提交
3936
	case RTL_GIGA_MAC_VER_42:
H
hayeswang 已提交
3937
	case RTL_GIGA_MAC_VER_43:
H
hayeswang 已提交
3938
	case RTL_GIGA_MAC_VER_44:
H
hayeswang 已提交
3939 3940
		rtl8168g_2_hw_phy_config(tp);
		break;
3941 3942 3943 3944 3945 3946 3947 3948
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_47:
		rtl8168h_1_hw_phy_config(tp);
		break;
	case RTL_GIGA_MAC_VER_46:
	case RTL_GIGA_MAC_VER_48:
		rtl8168h_2_hw_phy_config(tp);
		break;
H
Hayes Wang 已提交
3949 3950

	case RTL_GIGA_MAC_VER_41:
3951 3952 3953 3954 3955
	default:
		break;
	}
}

3956
static void rtl_phy_work(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
3957 3958 3959 3960 3961
{
	struct timer_list *timer = &tp->timer;
	void __iomem *ioaddr = tp->mmio_addr;
	unsigned long timeout = RTL8169_PHY_TIMEOUT;

3962
	assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
L
Linus Torvalds 已提交
3963

3964
	if (tp->phy_reset_pending(tp)) {
3965
		/*
L
Linus Torvalds 已提交
3966 3967 3968 3969 3970 3971 3972 3973
		 * A busy loop could burn quite a few cycles on nowadays CPU.
		 * Let's delay the execution of the timer for a few ticks.
		 */
		timeout = HZ/10;
		goto out_mod_timer;
	}

	if (tp->link_ok(ioaddr))
3974
		return;
L
Linus Torvalds 已提交
3975

3976
	netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
L
Linus Torvalds 已提交
3977

3978
	tp->phy_reset_enable(tp);
L
Linus Torvalds 已提交
3979 3980 3981

out_mod_timer:
	mod_timer(timer, jiffies + timeout);
3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994
}

static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
{
	if (!test_and_set_bit(flag, tp->wk.flags))
		schedule_work(&tp->wk.work);
}

static void rtl8169_phy_timer(unsigned long __opaque)
{
	struct net_device *dev = (struct net_device *)__opaque;
	struct rtl8169_private *tp = netdev_priv(dev);

3995
	rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
L
Linus Torvalds 已提交
3996 3997 3998 3999 4000 4001 4002
}

static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
				  void __iomem *ioaddr)
{
	iounmap(ioaddr);
	pci_release_regions(pdev);
4003
	pci_clear_mwi(pdev);
L
Linus Torvalds 已提交
4004 4005 4006 4007
	pci_disable_device(pdev);
	free_netdev(dev);
}

4008 4009 4010 4011 4012
DECLARE_RTL_COND(rtl_phy_reset_cond)
{
	return tp->phy_reset_pending(tp);
}

4013 4014 4015
static void rtl8169_phy_reset(struct net_device *dev,
			      struct rtl8169_private *tp)
{
4016
	tp->phy_reset_enable(tp);
4017
	rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4018 4019
}

4020 4021 4022 4023 4024 4025 4026 4027
static bool rtl_tbi_enabled(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
	    (RTL_R8(PHYstatus) & TBI_Enable);
}

4028 4029 4030 4031
static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

4032
	rtl_hw_phy_config(dev);
4033

4034 4035 4036 4037
	if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
		dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
		RTL_W8(0x82, 0x01);
	}
4038

4039 4040 4041 4042
	pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);

	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
		pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4043

4044
	if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4045 4046 4047
		dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
		RTL_W8(0x82, 0x01);
		dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4048
		rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4049 4050
	}

4051 4052
	rtl8169_phy_reset(dev, tp);

4053
	rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
F
Francois Romieu 已提交
4054 4055 4056 4057 4058
			  ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
			  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
			  (tp->mii.supports_gmii ?
			   ADVERTISED_1000baseT_Half |
			   ADVERTISED_1000baseT_Full : 0));
4059

4060
	if (rtl_tbi_enabled(tp))
4061
		netif_info(tp, link, dev, "TBI auto-negotiating\n");
4062 4063
}

4064 4065 4066 4067
static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
{
	void __iomem *ioaddr = tp->mmio_addr;

4068
	rtl_lock_work(tp);
4069 4070

	RTL_W8(Cfg9346, Cfg9346_Unlock);
4071

4072
	RTL_W32(MAC4, addr[4] | addr[5] << 8);
4073 4074
	RTL_R32(MAC4);

4075
	RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4076 4077
	RTL_R32(MAC0);

4078 4079
	if (tp->mac_version == RTL_GIGA_MAC_VER_34)
		rtl_rar_exgmac_set(tp, addr);
4080

4081 4082
	RTL_W8(Cfg9346, Cfg9346_Lock);

4083
	rtl_unlock_work(tp);
4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100
}

static int rtl_set_mac_address(struct net_device *dev, void *p)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct sockaddr *addr = p;

	if (!is_valid_ether_addr(addr->sa_data))
		return -EADDRNOTAVAIL;

	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);

	rtl_rar_set(tp, dev->dev_addr);

	return 0;
}

4101 4102 4103 4104 4105
static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct mii_ioctl_data *data = if_mii(ifr);

F
Francois Romieu 已提交
4106 4107
	return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
}
4108

F
Francois Romieu 已提交
4109 4110
static int rtl_xmii_ioctl(struct rtl8169_private *tp,
			  struct mii_ioctl_data *data, int cmd)
F
Francois Romieu 已提交
4111
{
4112 4113 4114 4115 4116 4117
	switch (cmd) {
	case SIOCGMIIPHY:
		data->phy_id = 32; /* Internal PHY */
		return 0;

	case SIOCGMIIREG:
4118
		data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4119 4120 4121
		return 0;

	case SIOCSMIIREG:
4122
		rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4123 4124 4125 4126 4127
		return 0;
	}
	return -EOPNOTSUPP;
}

F
Francois Romieu 已提交
4128 4129 4130 4131 4132
static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
{
	return -EOPNOTSUPP;
}

F
Francois Romieu 已提交
4133 4134 4135 4136 4137 4138 4139 4140
static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
{
	if (tp->features & RTL_FEATURE_MSI) {
		pci_disable_msi(pdev);
		tp->features &= ~RTL_FEATURE_MSI;
	}
}

B
Bill Pemberton 已提交
4141
static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4142 4143 4144 4145 4146 4147 4148 4149
{
	struct mdio_ops *ops = &tp->mdio_ops;

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_27:
		ops->write	= r8168dp_1_mdio_write;
		ops->read	= r8168dp_1_mdio_read;
		break;
F
françois romieu 已提交
4150
	case RTL_GIGA_MAC_VER_28:
4151
	case RTL_GIGA_MAC_VER_31:
F
françois romieu 已提交
4152 4153 4154
		ops->write	= r8168dp_2_mdio_write;
		ops->read	= r8168dp_2_mdio_read;
		break;
H
Hayes Wang 已提交
4155 4156
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
H
hayeswang 已提交
4157
	case RTL_GIGA_MAC_VER_42:
H
hayeswang 已提交
4158
	case RTL_GIGA_MAC_VER_43:
H
hayeswang 已提交
4159
	case RTL_GIGA_MAC_VER_44:
4160 4161 4162 4163
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
H
Hayes Wang 已提交
4164 4165 4166
		ops->write	= r8168g_mdio_write;
		ops->read	= r8168g_mdio_read;
		break;
4167 4168 4169 4170 4171 4172 4173
	default:
		ops->write	= r8169_mdio_write;
		ops->read	= r8169_mdio_read;
		break;
	}
}

H
hayeswang 已提交
4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197
static void rtl_speed_down(struct rtl8169_private *tp)
{
	u32 adv;
	int lpa;

	rtl_writephy(tp, 0x1f, 0x0000);
	lpa = rtl_readphy(tp, MII_LPA);

	if (lpa & (LPA_10HALF | LPA_10FULL))
		adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
	else if (lpa & (LPA_100HALF | LPA_100FULL))
		adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
		      ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
	else
		adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
		      ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
		      (tp->mii.supports_gmii ?
		       ADVERTISED_1000baseT_Half |
		       ADVERTISED_1000baseT_Full : 0);

	rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
			  adv);
}

4198 4199 4200 4201 4202
static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	switch (tp->mac_version) {
4203 4204
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
4205 4206 4207 4208 4209
	case RTL_GIGA_MAC_VER_29:
	case RTL_GIGA_MAC_VER_30:
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
	case RTL_GIGA_MAC_VER_34:
4210
	case RTL_GIGA_MAC_VER_37:
4211
	case RTL_GIGA_MAC_VER_38:
H
Hayes Wang 已提交
4212
	case RTL_GIGA_MAC_VER_39:
H
Hayes Wang 已提交
4213 4214
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
H
hayeswang 已提交
4215
	case RTL_GIGA_MAC_VER_42:
H
hayeswang 已提交
4216
	case RTL_GIGA_MAC_VER_43:
H
hayeswang 已提交
4217
	case RTL_GIGA_MAC_VER_44:
4218 4219 4220 4221
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234
		RTL_W32(RxConfig, RTL_R32(RxConfig) |
			AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
		break;
	default:
		break;
	}
}

static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
{
	if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
		return false;

H
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4235
	rtl_speed_down(tp);
4236 4237 4238 4239 4240
	rtl_wol_suspend_quirk(tp);

	return true;
}

F
françois romieu 已提交
4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254
static void r810x_phy_power_down(struct rtl8169_private *tp)
{
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
}

static void r810x_phy_power_up(struct rtl8169_private *tp)
{
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
}

static void r810x_pll_power_down(struct rtl8169_private *tp)
{
H
Hayes Wang 已提交
4255 4256
	void __iomem *ioaddr = tp->mmio_addr;

4257
	if (rtl_wol_pll_power_down(tp))
F
françois romieu 已提交
4258 4259 4260
		return;

	r810x_phy_power_down(tp);
H
Hayes Wang 已提交
4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_07:
	case RTL_GIGA_MAC_VER_08:
	case RTL_GIGA_MAC_VER_09:
	case RTL_GIGA_MAC_VER_10:
	case RTL_GIGA_MAC_VER_13:
	case RTL_GIGA_MAC_VER_16:
		break;
	default:
		RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
		break;
	}
F
françois romieu 已提交
4274 4275 4276 4277
}

static void r810x_pll_power_up(struct rtl8169_private *tp)
{
H
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4278 4279
	void __iomem *ioaddr = tp->mmio_addr;

F
françois romieu 已提交
4280
	r810x_phy_power_up(tp);
H
Hayes Wang 已提交
4281 4282 4283 4284 4285 4286 4287 4288 4289

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_07:
	case RTL_GIGA_MAC_VER_08:
	case RTL_GIGA_MAC_VER_09:
	case RTL_GIGA_MAC_VER_10:
	case RTL_GIGA_MAC_VER_13:
	case RTL_GIGA_MAC_VER_16:
		break;
4290 4291
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
4292
		RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4293
		break;
H
Hayes Wang 已提交
4294 4295 4296 4297
	default:
		RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
		break;
	}
F
françois romieu 已提交
4298 4299 4300 4301 4302
}

static void r8168_phy_power_up(struct rtl8169_private *tp)
{
	rtl_writephy(tp, 0x1f, 0x0000);
H
hayeswang 已提交
4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_11:
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
	case RTL_GIGA_MAC_VER_18:
	case RTL_GIGA_MAC_VER_19:
	case RTL_GIGA_MAC_VER_20:
	case RTL_GIGA_MAC_VER_21:
	case RTL_GIGA_MAC_VER_22:
	case RTL_GIGA_MAC_VER_23:
	case RTL_GIGA_MAC_VER_24:
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
	case RTL_GIGA_MAC_VER_27:
	case RTL_GIGA_MAC_VER_28:
	case RTL_GIGA_MAC_VER_31:
		rtl_writephy(tp, 0x0e, 0x0000);
		break;
	default:
		break;
	}
F
françois romieu 已提交
4324 4325 4326 4327 4328 4329
	rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
}

static void r8168_phy_power_down(struct rtl8169_private *tp)
{
	rtl_writephy(tp, 0x1f, 0x0000);
H
hayeswang 已提交
4330 4331 4332
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
4333 4334
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
H
hayeswang 已提交
4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357
		rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
		break;

	case RTL_GIGA_MAC_VER_11:
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
	case RTL_GIGA_MAC_VER_18:
	case RTL_GIGA_MAC_VER_19:
	case RTL_GIGA_MAC_VER_20:
	case RTL_GIGA_MAC_VER_21:
	case RTL_GIGA_MAC_VER_22:
	case RTL_GIGA_MAC_VER_23:
	case RTL_GIGA_MAC_VER_24:
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
	case RTL_GIGA_MAC_VER_27:
	case RTL_GIGA_MAC_VER_28:
	case RTL_GIGA_MAC_VER_31:
		rtl_writephy(tp, 0x0e, 0x0200);
	default:
		rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
		break;
	}
F
françois romieu 已提交
4358 4359 4360 4361 4362 4363
}

static void r8168_pll_power_down(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

F
Francois Romieu 已提交
4364 4365 4366
	if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
	     tp->mac_version == RTL_GIGA_MAC_VER_28 ||
	     tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4367
	    r8168dp_check_dash(tp)) {
F
françois romieu 已提交
4368
		return;
4369
	}
F
françois romieu 已提交
4370

F
Francois Romieu 已提交
4371 4372
	if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
	     tp->mac_version == RTL_GIGA_MAC_VER_24) &&
F
françois romieu 已提交
4373 4374 4375 4376
	    (RTL_R16(CPlusCmd) & ASF)) {
		return;
	}

H
hayeswang 已提交
4377 4378
	if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_33)
4379
		rtl_ephy_write(tp, 0x19, 0xff64);
H
hayeswang 已提交
4380

4381
	if (rtl_wol_pll_power_down(tp))
F
françois romieu 已提交
4382 4383 4384 4385 4386 4387 4388
		return;

	r8168_phy_power_down(tp);

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
4389 4390
	case RTL_GIGA_MAC_VER_27:
	case RTL_GIGA_MAC_VER_28:
4391
	case RTL_GIGA_MAC_VER_31:
H
hayeswang 已提交
4392 4393
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
4394
	case RTL_GIGA_MAC_VER_44:
4395 4396
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
F
françois romieu 已提交
4397 4398
		RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
		break;
4399 4400 4401 4402
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
		rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
			     0xfc000000, ERIAR_EXGMAC);
4403
		RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4404
		break;
F
françois romieu 已提交
4405 4406 4407 4408 4409 4410 4411 4412 4413 4414
	}
}

static void r8168_pll_power_up(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
4415 4416
	case RTL_GIGA_MAC_VER_27:
	case RTL_GIGA_MAC_VER_28:
4417
	case RTL_GIGA_MAC_VER_31:
H
hayeswang 已提交
4418 4419
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
F
françois romieu 已提交
4420 4421
		RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
		break;
4422
	case RTL_GIGA_MAC_VER_44:
4423 4424
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
4425
		RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4426
		break;
4427 4428
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
4429
		RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4430 4431 4432
		rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
			     0x00000000, ERIAR_EXGMAC);
		break;
F
françois romieu 已提交
4433 4434 4435 4436 4437
	}

	r8168_phy_power_up(tp);
}

F
Francois Romieu 已提交
4438 4439
static void rtl_generic_op(struct rtl8169_private *tp,
			   void (*op)(struct rtl8169_private *))
F
françois romieu 已提交
4440 4441 4442 4443 4444 4445 4446
{
	if (op)
		op(tp);
}

static void rtl_pll_power_down(struct rtl8169_private *tp)
{
F
Francois Romieu 已提交
4447
	rtl_generic_op(tp, tp->pll_power_ops.down);
F
françois romieu 已提交
4448 4449 4450 4451
}

static void rtl_pll_power_up(struct rtl8169_private *tp)
{
F
Francois Romieu 已提交
4452
	rtl_generic_op(tp, tp->pll_power_ops.up);
F
françois romieu 已提交
4453 4454
}

B
Bill Pemberton 已提交
4455
static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
F
françois romieu 已提交
4456 4457 4458 4459 4460 4461 4462 4463 4464
{
	struct pll_power_ops *ops = &tp->pll_power_ops;

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_07:
	case RTL_GIGA_MAC_VER_08:
	case RTL_GIGA_MAC_VER_09:
	case RTL_GIGA_MAC_VER_10:
	case RTL_GIGA_MAC_VER_16:
4465 4466
	case RTL_GIGA_MAC_VER_29:
	case RTL_GIGA_MAC_VER_30:
4467
	case RTL_GIGA_MAC_VER_37:
H
Hayes Wang 已提交
4468
	case RTL_GIGA_MAC_VER_39:
H
hayeswang 已提交
4469
	case RTL_GIGA_MAC_VER_43:
4470 4471
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
F
françois romieu 已提交
4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488
		ops->down	= r810x_pll_power_down;
		ops->up		= r810x_pll_power_up;
		break;

	case RTL_GIGA_MAC_VER_11:
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
	case RTL_GIGA_MAC_VER_18:
	case RTL_GIGA_MAC_VER_19:
	case RTL_GIGA_MAC_VER_20:
	case RTL_GIGA_MAC_VER_21:
	case RTL_GIGA_MAC_VER_22:
	case RTL_GIGA_MAC_VER_23:
	case RTL_GIGA_MAC_VER_24:
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
	case RTL_GIGA_MAC_VER_27:
F
françois romieu 已提交
4489
	case RTL_GIGA_MAC_VER_28:
4490
	case RTL_GIGA_MAC_VER_31:
H
hayeswang 已提交
4491 4492
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
H
Hayes Wang 已提交
4493
	case RTL_GIGA_MAC_VER_34:
4494 4495
	case RTL_GIGA_MAC_VER_35:
	case RTL_GIGA_MAC_VER_36:
4496
	case RTL_GIGA_MAC_VER_38:
H
Hayes Wang 已提交
4497 4498
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
H
hayeswang 已提交
4499
	case RTL_GIGA_MAC_VER_42:
H
hayeswang 已提交
4500
	case RTL_GIGA_MAC_VER_44:
4501 4502
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
F
françois romieu 已提交
4503 4504 4505 4506 4507 4508 4509 4510 4511 4512 4513
		ops->down	= r8168_pll_power_down;
		ops->up		= r8168_pll_power_up;
		break;

	default:
		ops->down	= NULL;
		ops->up		= NULL;
		break;
	}
}

4514 4515 4516 4517 4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538 4539 4540 4541
static void rtl_init_rxcfg(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_01:
	case RTL_GIGA_MAC_VER_02:
	case RTL_GIGA_MAC_VER_03:
	case RTL_GIGA_MAC_VER_04:
	case RTL_GIGA_MAC_VER_05:
	case RTL_GIGA_MAC_VER_06:
	case RTL_GIGA_MAC_VER_10:
	case RTL_GIGA_MAC_VER_11:
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_13:
	case RTL_GIGA_MAC_VER_14:
	case RTL_GIGA_MAC_VER_15:
	case RTL_GIGA_MAC_VER_16:
	case RTL_GIGA_MAC_VER_17:
		RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
		break;
	case RTL_GIGA_MAC_VER_18:
	case RTL_GIGA_MAC_VER_19:
	case RTL_GIGA_MAC_VER_20:
	case RTL_GIGA_MAC_VER_21:
	case RTL_GIGA_MAC_VER_22:
	case RTL_GIGA_MAC_VER_23:
	case RTL_GIGA_MAC_VER_24:
4542
	case RTL_GIGA_MAC_VER_34:
4543
	case RTL_GIGA_MAC_VER_35:
4544 4545
		RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
		break;
4546
	case RTL_GIGA_MAC_VER_40:
4547 4548
		RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
		break;
4549
	case RTL_GIGA_MAC_VER_41:
H
hayeswang 已提交
4550
	case RTL_GIGA_MAC_VER_42:
H
hayeswang 已提交
4551
	case RTL_GIGA_MAC_VER_43:
H
hayeswang 已提交
4552
	case RTL_GIGA_MAC_VER_44:
4553 4554 4555 4556
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
4557 4558
		RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
		break;
4559 4560 4561 4562 4563 4564
	default:
		RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
		break;
	}
}

4565 4566
static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
{
4567
	tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4568 4569
}

F
Francois Romieu 已提交
4570 4571
static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
{
4572 4573 4574
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Cfg9346, Cfg9346_Unlock);
F
Francois Romieu 已提交
4575
	rtl_generic_op(tp, tp->jumbo_ops.enable);
4576
	RTL_W8(Cfg9346, Cfg9346_Lock);
F
Francois Romieu 已提交
4577 4578 4579 4580
}

static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
{
4581 4582 4583
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Cfg9346, Cfg9346_Unlock);
F
Francois Romieu 已提交
4584
	rtl_generic_op(tp, tp->jumbo_ops.disable);
4585
	RTL_W8(Cfg9346, Cfg9346_Lock);
F
Francois Romieu 已提交
4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596 4597 4598 4599 4600 4601 4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626
}

static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
	RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
	rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
}

static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
	RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
	rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
}

static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
}

static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
}

static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(MaxTxPacketSize, 0x3f);
	RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
	RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4627
	rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
F
Francois Romieu 已提交
4628 4629 4630 4631 4632 4633 4634 4635 4636
}

static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(MaxTxPacketSize, 0x0c);
	RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
	RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4637
	rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
F
Francois Romieu 已提交
4638 4639 4640 4641 4642 4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 4668 4669
}

static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
{
	rtl_tx_performance_tweak(tp->pci_dev,
		(0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
}

static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
{
	rtl_tx_performance_tweak(tp->pci_dev,
		(0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
}

static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	r8168b_0_hw_jumbo_enable(tp);

	RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
}

static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	r8168b_0_hw_jumbo_disable(tp);

	RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
}

B
Bill Pemberton 已提交
4670
static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
F
Francois Romieu 已提交
4671 4672 4673 4674 4675 4676 4677 4678 4679 4680 4681 4682 4683 4684 4685 4686 4687 4688 4689 4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702 4703 4704 4705 4706 4707 4708 4709 4710 4711 4712
{
	struct jumbo_ops *ops = &tp->jumbo_ops;

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_11:
		ops->disable	= r8168b_0_hw_jumbo_disable;
		ops->enable	= r8168b_0_hw_jumbo_enable;
		break;
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
		ops->disable	= r8168b_1_hw_jumbo_disable;
		ops->enable	= r8168b_1_hw_jumbo_enable;
		break;
	case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
	case RTL_GIGA_MAC_VER_19:
	case RTL_GIGA_MAC_VER_20:
	case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
	case RTL_GIGA_MAC_VER_22:
	case RTL_GIGA_MAC_VER_23:
	case RTL_GIGA_MAC_VER_24:
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
		ops->disable	= r8168c_hw_jumbo_disable;
		ops->enable	= r8168c_hw_jumbo_enable;
		break;
	case RTL_GIGA_MAC_VER_27:
	case RTL_GIGA_MAC_VER_28:
		ops->disable	= r8168dp_hw_jumbo_disable;
		ops->enable	= r8168dp_hw_jumbo_enable;
		break;
	case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
	case RTL_GIGA_MAC_VER_34:
		ops->disable	= r8168e_hw_jumbo_disable;
		ops->enable	= r8168e_hw_jumbo_enable;
		break;

	/*
	 * No action needed for jumbo frames with 8169.
	 * No jumbo for 810x at all.
	 */
H
Hayes Wang 已提交
4713 4714
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
H
hayeswang 已提交
4715
	case RTL_GIGA_MAC_VER_42:
H
hayeswang 已提交
4716
	case RTL_GIGA_MAC_VER_43:
H
hayeswang 已提交
4717
	case RTL_GIGA_MAC_VER_44:
4718 4719 4720 4721
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
F
Francois Romieu 已提交
4722 4723 4724 4725 4726 4727 4728
	default:
		ops->disable	= NULL;
		ops->enable	= NULL;
		break;
	}
}

4729 4730 4731 4732 4733 4734 4735
DECLARE_RTL_COND(rtl_chipcmd_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R8(ChipCmd) & CmdReset;
}

4736 4737 4738 4739 4740 4741
static void rtl_hw_reset(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(ChipCmd, CmdReset);

4742
	rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4743 4744
}

4745
static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4746
{
4747 4748 4749
	struct rtl_fw *rtl_fw;
	const char *name;
	int rc = -ENOMEM;
4750

4751 4752 4753
	name = rtl_lookup_firmware_name(tp);
	if (!name)
		goto out_no_firmware;
4754

4755 4756 4757
	rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
	if (!rtl_fw)
		goto err_warn;
4758

4759 4760 4761 4762
	rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
	if (rc < 0)
		goto err_free;

4763 4764 4765 4766
	rc = rtl_check_firmware(tp, rtl_fw);
	if (rc < 0)
		goto err_release_firmware;

4767 4768 4769 4770
	tp->rtl_fw = rtl_fw;
out:
	return;

4771 4772
err_release_firmware:
	release_firmware(rtl_fw->fw);
4773 4774 4775 4776 4777 4778 4779 4780 4781 4782 4783 4784 4785 4786
err_free:
	kfree(rtl_fw);
err_warn:
	netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
		   name, rc);
out_no_firmware:
	tp->rtl_fw = NULL;
	goto out;
}

static void rtl_request_firmware(struct rtl8169_private *tp)
{
	if (IS_ERR(tp->rtl_fw))
		rtl_request_uncached_firmware(tp);
4787 4788
}

4789 4790 4791 4792
static void rtl_rx_close(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

4793
	RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4794 4795
}

4796 4797 4798 4799 4800 4801 4802 4803 4804 4805 4806 4807 4808 4809
DECLARE_RTL_COND(rtl_npq_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R8(TxPoll) & NPQ;
}

DECLARE_RTL_COND(rtl_txcfg_empty_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R32(TxConfig) & TXCFG_EMPTY;
}

F
françois romieu 已提交
4810
static void rtl8169_hw_reset(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
4811
{
F
françois romieu 已提交
4812 4813
	void __iomem *ioaddr = tp->mmio_addr;

L
Linus Torvalds 已提交
4814
	/* Disable interrupts */
F
françois romieu 已提交
4815
	rtl8169_irq_mask_and_ack(tp);
L
Linus Torvalds 已提交
4816

4817 4818
	rtl_rx_close(tp);

4819
	if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4820 4821
	    tp->mac_version == RTL_GIGA_MAC_VER_28 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_31) {
4822
		rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4823
	} else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4824 4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836
		   tp->mac_version == RTL_GIGA_MAC_VER_35 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_36 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_37 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_38 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_40 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_41 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_42 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_43 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_44 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_45 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_46 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_47 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_48) {
4837
		RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4838
		rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4839 4840 4841
	} else {
		RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
		udelay(100);
F
françois romieu 已提交
4842 4843
	}

4844
	rtl_hw_reset(tp);
L
Linus Torvalds 已提交
4845 4846
}

4847
static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4848 4849 4850 4851 4852 4853 4854 4855
{
	void __iomem *ioaddr = tp->mmio_addr;

	/* Set DMA burst size and Interframe Gap Time */
	RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
		(InterFrameGap << TxInterFrameGapShift));
}

4856
static void rtl_hw_start(struct net_device *dev)
L
Linus Torvalds 已提交
4857 4858 4859
{
	struct rtl8169_private *tp = netdev_priv(dev);

4860 4861
	tp->hw_start(dev);

4862
	rtl_irq_enable_all(tp);
4863 4864
}

4865 4866 4867 4868 4869 4870 4871 4872 4873
static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
					 void __iomem *ioaddr)
{
	/*
	 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
	 * register to be written before TxDescAddrLow to work.
	 * Switching from MMIO to I/O access fixes the issue as well.
	 */
	RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4874
	RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4875
	RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4876
	RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887
}

static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
{
	u16 cmd;

	cmd = RTL_R16(CPlusCmd);
	RTL_W16(CPlusCmd, cmd);
	return cmd;
}

4888
static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4889 4890
{
	/* Low hurts. Let's disable the filtering. */
4891
	RTL_W16(RxMaxSize, rx_buf_sz + 1);
4892 4893
}

4894 4895
static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
{
4896
	static const struct rtl_cfg2_info {
4897 4898 4899 4900 4901 4902 4903 4904
		u32 mac_version;
		u32 clk;
		u32 val;
	} cfg2_info [] = {
		{ RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
		{ RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
		{ RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
		{ RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4905 4906
	};
	const struct rtl_cfg2_info *p = cfg2_info;
4907 4908 4909 4910
	unsigned int i;
	u32 clk;

	clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4911
	for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4912 4913 4914 4915 4916 4917 4918
		if ((p->mac_version == mac_version) && (p->clk == clk)) {
			RTL_W32(0x7c, p->val);
			break;
		}
	}
}

4919 4920 4921 4922 4923 4924 4925 4926 4927 4928 4929 4930 4931 4932 4933 4934 4935 4936 4937 4938 4939 4940 4941 4942 4943 4944 4945 4946 4947 4948 4949 4950 4951 4952 4953 4954 4955 4956 4957 4958 4959 4960 4961 4962
static void rtl_set_rx_mode(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	u32 mc_filter[2];	/* Multicast hash filter */
	int rx_mode;
	u32 tmp = 0;

	if (dev->flags & IFF_PROMISC) {
		/* Unconditionally log net taps. */
		netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
		rx_mode =
		    AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
		    AcceptAllPhys;
		mc_filter[1] = mc_filter[0] = 0xffffffff;
	} else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
		   (dev->flags & IFF_ALLMULTI)) {
		/* Too many to filter perfectly -- accept all multicasts. */
		rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
		mc_filter[1] = mc_filter[0] = 0xffffffff;
	} else {
		struct netdev_hw_addr *ha;

		rx_mode = AcceptBroadcast | AcceptMyPhys;
		mc_filter[1] = mc_filter[0] = 0;
		netdev_for_each_mc_addr(ha, dev) {
			int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
			rx_mode |= AcceptMulticast;
		}
	}

	if (dev->features & NETIF_F_RXALL)
		rx_mode |= (AcceptErr | AcceptRunt);

	tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;

	if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
		u32 data = mc_filter[0];

		mc_filter[0] = swab32(mc_filter[1]);
		mc_filter[1] = swab32(data);
	}

4963 4964 4965
	if (tp->mac_version == RTL_GIGA_MAC_VER_35)
		mc_filter[1] = mc_filter[0] = 0xffffffff;

4966 4967 4968 4969 4970 4971
	RTL_W32(MAR0 + 4, mc_filter[1]);
	RTL_W32(MAR0 + 0, mc_filter[0]);

	RTL_W32(RxConfig, tmp);
}

4972 4973 4974 4975 4976 4977
static void rtl_hw_start_8169(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

4978 4979 4980 4981 4982
	if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
		RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
	}

L
Linus Torvalds 已提交
4983
	RTL_W8(Cfg9346, Cfg9346_Unlock);
F
Francois Romieu 已提交
4984 4985 4986 4987
	if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_02 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_03 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_04)
4988 4989
		RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);

4990 4991
	rtl_init_rxcfg(tp);

4992
	RTL_W8(EarlyTxThres, NoEarlyTx);
L
Linus Torvalds 已提交
4993

E
Eric Dumazet 已提交
4994
	rtl_set_rx_max_size(ioaddr, rx_buf_sz);
L
Linus Torvalds 已提交
4995

F
Francois Romieu 已提交
4996 4997 4998 4999
	if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_02 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_03 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_04)
5000
		rtl_set_rx_tx_config_registers(tp);
L
Linus Torvalds 已提交
5001

5002
	tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
L
Linus Torvalds 已提交
5003

F
Francois Romieu 已提交
5004 5005
	if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_03) {
5006
		dprintk("Set MAC Reg C+CR Offset 0xe0. "
L
Linus Torvalds 已提交
5007
			"Bit-3 and bit-14 MUST be 1\n");
5008
		tp->cp_cmd |= (1 << 14);
L
Linus Torvalds 已提交
5009 5010
	}

5011 5012
	RTL_W16(CPlusCmd, tp->cp_cmd);

5013 5014
	rtl8169_set_magic_reg(ioaddr, tp->mac_version);

L
Linus Torvalds 已提交
5015 5016 5017 5018 5019 5020
	/*
	 * Undocumented corner. Supposedly:
	 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
	 */
	RTL_W16(IntrMitigate, 0x0000);

5021
	rtl_set_rx_tx_desc_registers(tp, ioaddr);
5022

F
Francois Romieu 已提交
5023 5024 5025 5026
	if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
	    tp->mac_version != RTL_GIGA_MAC_VER_02 &&
	    tp->mac_version != RTL_GIGA_MAC_VER_03 &&
	    tp->mac_version != RTL_GIGA_MAC_VER_04) {
5027 5028 5029 5030
		RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
		rtl_set_rx_tx_config_registers(tp);
	}

L
Linus Torvalds 已提交
5031
	RTL_W8(Cfg9346, Cfg9346_Lock);
F
Francois Romieu 已提交
5032 5033 5034

	/* Initially a 10 us delay. Turned it into a PCI commit. - FR */
	RTL_R8(IntrMask);
L
Linus Torvalds 已提交
5035 5036 5037

	RTL_W32(RxMissed, 0);

5038
	rtl_set_rx_mode(dev);
L
Linus Torvalds 已提交
5039 5040

	/* no early-rx interrupts */
5041
	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5042
}
L
Linus Torvalds 已提交
5043

5044 5045 5046
static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
{
	if (tp->csi_ops.write)
5047
		tp->csi_ops.write(tp, addr, value);
5048 5049 5050 5051
}

static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
{
5052
	return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5053 5054 5055
}

static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5056 5057 5058
{
	u32 csi;

5059 5060 5061 5062 5063 5064 5065
	csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
	rtl_csi_write(tp, 0x070c, csi | bits);
}

static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
{
	rtl_csi_access_enable(tp, 0x17000000);
5066 5067
}

5068
static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
F
françois romieu 已提交
5069
{
5070
	rtl_csi_access_enable(tp, 0x27000000);
F
françois romieu 已提交
5071 5072
}

5073 5074 5075 5076 5077 5078 5079
DECLARE_RTL_COND(rtl_csiar_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R32(CSIAR) & CSIAR_FLAG;
}

5080
static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5081
{
5082
	void __iomem *ioaddr = tp->mmio_addr;
5083 5084 5085 5086 5087

	RTL_W32(CSIDR, value);
	RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);

5088
	rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5089 5090
}

5091
static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5092
{
5093
	void __iomem *ioaddr = tp->mmio_addr;
5094 5095 5096 5097

	RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);

5098 5099
	return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
		RTL_R32(CSIDR) : ~0;
5100 5101
}

5102
static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5103
{
5104
	void __iomem *ioaddr = tp->mmio_addr;
5105 5106 5107 5108 5109 5110

	RTL_W32(CSIDR, value);
	RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
		CSIAR_FUNC_NIC);

5111
	rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5112 5113
}

5114
static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5115
{
5116
	void __iomem *ioaddr = tp->mmio_addr;
5117 5118 5119 5120

	RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);

5121 5122
	return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
		RTL_R32(CSIDR) : ~0;
5123 5124
}

H
hayeswang 已提交
5125 5126 5127 5128 5129 5130 5131 5132 5133 5134 5135 5136 5137 5138 5139 5140 5141 5142 5143 5144 5145 5146 5147
static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W32(CSIDR, value);
	RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
		CSIAR_FUNC_NIC2);

	rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
}

static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);

	return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
		RTL_R32(CSIDR) : ~0;
}

B
Bill Pemberton 已提交
5148
static void rtl_init_csi_ops(struct rtl8169_private *tp)
5149 5150 5151 5152 5153 5154 5155 5156 5157 5158 5159 5160 5161 5162 5163 5164 5165 5166 5167 5168 5169 5170
{
	struct csi_ops *ops = &tp->csi_ops;

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_01:
	case RTL_GIGA_MAC_VER_02:
	case RTL_GIGA_MAC_VER_03:
	case RTL_GIGA_MAC_VER_04:
	case RTL_GIGA_MAC_VER_05:
	case RTL_GIGA_MAC_VER_06:
	case RTL_GIGA_MAC_VER_10:
	case RTL_GIGA_MAC_VER_11:
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_13:
	case RTL_GIGA_MAC_VER_14:
	case RTL_GIGA_MAC_VER_15:
	case RTL_GIGA_MAC_VER_16:
	case RTL_GIGA_MAC_VER_17:
		ops->write	= NULL;
		ops->read	= NULL;
		break;

5171
	case RTL_GIGA_MAC_VER_37:
5172
	case RTL_GIGA_MAC_VER_38:
5173 5174 5175 5176
		ops->write	= r8402_csi_write;
		ops->read	= r8402_csi_read;
		break;

H
hayeswang 已提交
5177 5178 5179 5180 5181
	case RTL_GIGA_MAC_VER_44:
		ops->write	= r8411_csi_write;
		ops->read	= r8411_csi_read;
		break;

5182 5183 5184 5185 5186
	default:
		ops->write	= r8169_csi_write;
		ops->read	= r8169_csi_read;
		break;
	}
5187 5188 5189 5190 5191 5192 5193 5194
}

struct ephy_info {
	unsigned int offset;
	u16 mask;
	u16 bits;
};

5195 5196
static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
			  int len)
5197 5198 5199 5200
{
	u16 w;

	while (len-- > 0) {
5201 5202
		w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
		rtl_ephy_write(tp, e->offset, w);
5203 5204 5205 5206
		e++;
	}
}

5207 5208
static void rtl_disable_clock_request(struct pci_dev *pdev)
{
5209 5210
	pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
				   PCI_EXP_LNKCTL_CLKREQ_EN);
5211 5212
}

F
françois romieu 已提交
5213 5214
static void rtl_enable_clock_request(struct pci_dev *pdev)
{
5215 5216
	pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
				 PCI_EXP_LNKCTL_CLKREQ_EN);
F
françois romieu 已提交
5217 5218
}

H
hayeswang 已提交
5219 5220 5221 5222 5223 5224 5225 5226 5227 5228 5229 5230 5231 5232 5233
static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
{
	void __iomem *ioaddr = tp->mmio_addr;
	u8 data;

	data = RTL_R8(Config3);

	if (enable)
		data |= Rdy_to_L23;
	else
		data &= ~Rdy_to_L23;

	RTL_W8(Config3, data);
}

5234 5235 5236 5237 5238 5239 5240 5241 5242 5243 5244
#define R8168_CPCMD_QUIRK_MASK (\
	EnableBist | \
	Mac_dbgo_oe | \
	Force_half_dup | \
	Force_rxflow_en | \
	Force_txflow_en | \
	Cxpl_dbg_sel | \
	ASF | \
	PktCntrDisable | \
	Mac_dbgo_sel)

5245
static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5246
{
5247 5248 5249
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

5250 5251 5252 5253
	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);

5254 5255 5256 5257
	if (tp->dev->mtu <= ETH_DATA_LEN) {
		rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
					 PCI_EXP_DEVCTL_NOSNOOP_EN);
	}
5258 5259
}

5260
static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5261
{
5262 5263 5264
	void __iomem *ioaddr = tp->mmio_addr;

	rtl_hw_start_8168bb(tp);
5265

5266
	RTL_W8(MaxTxPacketSize, TxPacketMax);
5267 5268

	RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5269 5270
}

5271
static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5272
{
5273 5274 5275
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

5276 5277 5278 5279
	RTL_W8(Config1, RTL_R8(Config1) | Speed_down);

	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

5280 5281
	if (tp->dev->mtu <= ETH_DATA_LEN)
		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5282 5283 5284 5285

	rtl_disable_clock_request(pdev);

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5286 5287
}

5288
static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5289
{
5290
	static const struct ephy_info e_info_8168cp[] = {
5291 5292 5293 5294 5295 5296 5297
		{ 0x01, 0,	0x0001 },
		{ 0x02, 0x0800,	0x1000 },
		{ 0x03, 0,	0x0042 },
		{ 0x06, 0x0080,	0x0000 },
		{ 0x07, 0,	0x2000 }
	};

5298
	rtl_csi_access_enable_2(tp);
5299

5300
	rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5301

5302
	__rtl_hw_start_8168cp(tp);
5303 5304
}

5305
static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
F
Francois Romieu 已提交
5306
{
5307 5308 5309 5310
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

	rtl_csi_access_enable_2(tp);
F
Francois Romieu 已提交
5311 5312 5313

	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

5314 5315
	if (tp->dev->mtu <= ETH_DATA_LEN)
		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
F
Francois Romieu 已提交
5316 5317 5318 5319

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
}

5320
static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5321
{
5322 5323 5324 5325
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

	rtl_csi_access_enable_2(tp);
5326 5327 5328 5329 5330 5331

	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

	/* Magic. */
	RTL_W8(DBG_REG, 0x20);

5332
	RTL_W8(MaxTxPacketSize, TxPacketMax);
5333

5334 5335
	if (tp->dev->mtu <= ETH_DATA_LEN)
		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5336 5337 5338 5339

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
}

5340
static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5341
{
5342
	void __iomem *ioaddr = tp->mmio_addr;
5343
	static const struct ephy_info e_info_8168c_1[] = {
5344 5345 5346 5347 5348
		{ 0x02, 0x0800,	0x1000 },
		{ 0x03, 0,	0x0002 },
		{ 0x06, 0x0080,	0x0000 }
	};

5349
	rtl_csi_access_enable_2(tp);
5350 5351 5352

	RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);

5353
	rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5354

5355
	__rtl_hw_start_8168cp(tp);
5356 5357
}

5358
static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5359
{
5360
	static const struct ephy_info e_info_8168c_2[] = {
5361 5362 5363 5364
		{ 0x01, 0,	0x0001 },
		{ 0x03, 0x0400,	0x0220 }
	};

5365
	rtl_csi_access_enable_2(tp);
5366

5367
	rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5368

5369
	__rtl_hw_start_8168cp(tp);
5370 5371
}

5372
static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
F
Francois Romieu 已提交
5373
{
5374
	rtl_hw_start_8168c_2(tp);
F
Francois Romieu 已提交
5375 5376
}

5377
static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5378
{
5379
	rtl_csi_access_enable_2(tp);
5380

5381
	__rtl_hw_start_8168cp(tp);
5382 5383
}

5384
static void rtl_hw_start_8168d(struct rtl8169_private *tp)
F
Francois Romieu 已提交
5385
{
5386 5387 5388 5389
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

	rtl_csi_access_enable_2(tp);
F
Francois Romieu 已提交
5390 5391 5392

	rtl_disable_clock_request(pdev);

5393
	RTL_W8(MaxTxPacketSize, TxPacketMax);
F
Francois Romieu 已提交
5394

5395 5396
	if (tp->dev->mtu <= ETH_DATA_LEN)
		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
F
Francois Romieu 已提交
5397 5398 5399 5400

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
}

5401
static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5402
{
5403 5404 5405 5406
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

	rtl_csi_access_enable_1(tp);
5407

5408 5409
	if (tp->dev->mtu <= ETH_DATA_LEN)
		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5410 5411 5412 5413 5414 5415

	RTL_W8(MaxTxPacketSize, TxPacketMax);

	rtl_disable_clock_request(pdev);
}

5416
static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
F
françois romieu 已提交
5417
{
5418 5419
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;
F
françois romieu 已提交
5420 5421 5422 5423 5424 5425 5426
	static const struct ephy_info e_info_8168d_4[] = {
		{ 0x0b, ~0,	0x48 },
		{ 0x19, 0x20,	0x50 },
		{ 0x0c, ~0,	0x20 }
	};
	int i;

5427
	rtl_csi_access_enable_1(tp);
F
françois romieu 已提交
5428 5429 5430 5431 5432 5433 5434 5435 5436

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	RTL_W8(MaxTxPacketSize, TxPacketMax);

	for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
		const struct ephy_info *e = e_info_8168d_4 + i;
		u16 w;

5437 5438
		w = rtl_ephy_read(tp, e->offset);
		rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
F
françois romieu 已提交
5439 5440 5441 5442 5443
	}

	rtl_enable_clock_request(pdev);
}

5444
static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
H
hayeswang 已提交
5445
{
5446 5447
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;
H
Hayes Wang 已提交
5448
	static const struct ephy_info e_info_8168e_1[] = {
H
hayeswang 已提交
5449 5450 5451 5452 5453 5454 5455 5456 5457 5458 5459 5460 5461 5462 5463
		{ 0x00, 0x0200,	0x0100 },
		{ 0x00, 0x0000,	0x0004 },
		{ 0x06, 0x0002,	0x0001 },
		{ 0x06, 0x0000,	0x0030 },
		{ 0x07, 0x0000,	0x2000 },
		{ 0x00, 0x0000,	0x0020 },
		{ 0x03, 0x5800,	0x2000 },
		{ 0x03, 0x0000,	0x0001 },
		{ 0x01, 0x0800,	0x1000 },
		{ 0x07, 0x0000,	0x4000 },
		{ 0x1e, 0x0000,	0x2000 },
		{ 0x19, 0xffff,	0xfe6c },
		{ 0x0a, 0x0000,	0x0040 }
	};

5464
	rtl_csi_access_enable_2(tp);
H
hayeswang 已提交
5465

5466
	rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
H
hayeswang 已提交
5467

5468 5469
	if (tp->dev->mtu <= ETH_DATA_LEN)
		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
H
hayeswang 已提交
5470 5471 5472 5473 5474 5475

	RTL_W8(MaxTxPacketSize, TxPacketMax);

	rtl_disable_clock_request(pdev);

	/* Reset tx FIFO pointer */
F
Francois Romieu 已提交
5476 5477
	RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
	RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
H
hayeswang 已提交
5478

F
Francois Romieu 已提交
5479
	RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
H
hayeswang 已提交
5480 5481
}

5482
static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
H
Hayes Wang 已提交
5483
{
5484 5485
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;
H
Hayes Wang 已提交
5486 5487 5488 5489 5490
	static const struct ephy_info e_info_8168e_2[] = {
		{ 0x09, 0x0000,	0x0080 },
		{ 0x19, 0x0000,	0x0224 }
	};

5491
	rtl_csi_access_enable_1(tp);
H
Hayes Wang 已提交
5492

5493
	rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
H
Hayes Wang 已提交
5494

5495 5496
	if (tp->dev->mtu <= ETH_DATA_LEN)
		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
H
Hayes Wang 已提交
5497

5498 5499 5500 5501 5502 5503 5504 5505
	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
H
Hayes Wang 已提交
5506

5507
	RTL_W8(MaxTxPacketSize, EarlySize);
H
Hayes Wang 已提交
5508

5509 5510
	rtl_disable_clock_request(pdev);

H
Hayes Wang 已提交
5511 5512 5513 5514 5515 5516 5517 5518
	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
	RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);

	/* Adjust EEE LED frequency */
	RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);

	RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
	RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5519
	RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
H
Hayes Wang 已提交
5520 5521
}

5522
static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5523
{
5524 5525
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;
5526

5527
	rtl_csi_access_enable_2(tp);
5528 5529 5530

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

5531 5532 5533 5534 5535 5536 5537 5538 5539 5540
	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5541 5542 5543

	RTL_W8(MaxTxPacketSize, EarlySize);

5544 5545
	rtl_disable_clock_request(pdev);

5546 5547 5548
	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
	RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
	RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5549 5550
	RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
	RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5551 5552
}

5553 5554 5555 5556 5557 5558 5559 5560 5561 5562 5563 5564
static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;
	static const struct ephy_info e_info_8168f_1[] = {
		{ 0x06, 0x00c0,	0x0020 },
		{ 0x08, 0x0001,	0x0002 },
		{ 0x09, 0x0000,	0x0080 },
		{ 0x19, 0x0000,	0x0224 }
	};

	rtl_hw_start_8168f(tp);

5565
	rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5566

5567
	rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5568 5569 5570 5571 5572

	/* Adjust EEE LED frequency */
	RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
}

5573 5574 5575 5576 5577 5578 5579 5580 5581 5582
static void rtl_hw_start_8411(struct rtl8169_private *tp)
{
	static const struct ephy_info e_info_8168f_1[] = {
		{ 0x06, 0x00c0,	0x0020 },
		{ 0x0f, 0xffff,	0x5200 },
		{ 0x1e, 0x0000,	0x4000 },
		{ 0x19, 0x0000,	0x0224 }
	};

	rtl_hw_start_8168f(tp);
H
hayeswang 已提交
5583
	rtl_pcie_state_l2l3_enable(tp, false);
5584

5585
	rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5586

5587
	rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5588 5589
}

H
Hayes Wang 已提交
5590 5591 5592 5593 5594
static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

5595 5596
	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);

H
Hayes Wang 已提交
5597 5598 5599 5600 5601 5602 5603 5604 5605 5606 5607
	rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);

	rtl_csi_access_enable_1(tp);

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5608
	rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
H
Hayes Wang 已提交
5609 5610

	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5611
	RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
H
Hayes Wang 已提交
5612 5613 5614 5615 5616 5617 5618 5619
	RTL_W8(MaxTxPacketSize, EarlySize);

	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	/* Adjust EEE LED frequency */
	RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);

5620 5621
	rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
H
hayeswang 已提交
5622 5623

	rtl_pcie_state_l2l3_enable(tp, false);
H
Hayes Wang 已提交
5624 5625
}

H
hayeswang 已提交
5626 5627 5628 5629 5630 5631 5632 5633 5634 5635 5636 5637 5638 5639 5640 5641 5642 5643
static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;
	static const struct ephy_info e_info_8168g_2[] = {
		{ 0x00, 0x0000,	0x0008 },
		{ 0x0c, 0x3df0,	0x0200 },
		{ 0x19, 0xffff,	0xfc00 },
		{ 0x1e, 0xffff,	0x20eb }
	};

	rtl_hw_start_8168g_1(tp);

	/* disable aspm and clock request before access ephy */
	RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
	RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
	rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
}

H
hayeswang 已提交
5644 5645 5646 5647 5648 5649 5650 5651 5652 5653 5654 5655 5656 5657 5658 5659 5660 5661 5662
static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;
	static const struct ephy_info e_info_8411_2[] = {
		{ 0x00, 0x0000,	0x0008 },
		{ 0x0c, 0x3df0,	0x0200 },
		{ 0x0f, 0xffff,	0x5200 },
		{ 0x19, 0x0020,	0x0000 },
		{ 0x1e, 0x0000,	0x2000 }
	};

	rtl_hw_start_8168g_1(tp);

	/* disable aspm and clock request before access ephy */
	RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
	RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
	rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
}

5663 5664 5665 5666 5667 5668 5669 5670 5671 5672 5673 5674 5675 5676 5677 5678 5679 5680 5681 5682 5683 5684 5685 5686 5687 5688 5689 5690 5691 5692 5693 5694 5695 5696 5697 5698 5699 5700 5701 5702 5703 5704 5705 5706 5707 5708 5709 5710 5711 5712 5713 5714 5715 5716 5717 5718 5719 5720 5721 5722 5723 5724 5725 5726 5727 5728 5729 5730 5731 5732 5733 5734 5735 5736 5737 5738 5739 5740 5741 5742 5743 5744 5745 5746 5747 5748 5749 5750 5751 5752 5753 5754 5755 5756 5757 5758 5759 5760 5761
static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;
	u16 rg_saw_cnt;
	u32 data;
	static const struct ephy_info e_info_8168h_1[] = {
		{ 0x1e, 0x0800,	0x0001 },
		{ 0x1d, 0x0000,	0x0800 },
		{ 0x05, 0xffff,	0x2089 },
		{ 0x06, 0xffff,	0x5881 },
		{ 0x04, 0xffff,	0x154a },
		{ 0x01, 0xffff,	0x068b }
	};

	/* disable aspm and clock request before access ephy */
	RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
	RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
	rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));

	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);

	rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);

	rtl_csi_access_enable_1(tp);

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);

	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);

	rtl_w1w0_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);

	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
	RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
	RTL_W8(MaxTxPacketSize, EarlySize);

	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	/* Adjust EEE LED frequency */
	RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);

	RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
	RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);

	RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);

	rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);

	rtl_pcie_state_l2l3_enable(tp, false);

	rtl_writephy(tp, 0x1f, 0x0c42);
	rg_saw_cnt = rtl_readphy(tp, 0x13);
	rtl_writephy(tp, 0x1f, 0x0000);
	if (rg_saw_cnt > 0) {
		u16 sw_cnt_1ms_ini;

		sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
		sw_cnt_1ms_ini &= 0x0fff;
		data = r8168_mac_ocp_read(tp, 0xd412);
		data &= 0x0fff;
		data |= sw_cnt_1ms_ini;
		r8168_mac_ocp_write(tp, 0xd412, data);
	}

	data = r8168_mac_ocp_read(tp, 0xe056);
	data &= 0xf0;
	data |= 0x07;
	r8168_mac_ocp_write(tp, 0xe056, data);

	data = r8168_mac_ocp_read(tp, 0xe052);
	data &= 0x8008;
	data |= 0x6000;
	r8168_mac_ocp_write(tp, 0xe052, data);

	data = r8168_mac_ocp_read(tp, 0xe0d6);
	data &= 0x01ff;
	data |= 0x017f;
	r8168_mac_ocp_write(tp, 0xe0d6, data);

	data = r8168_mac_ocp_read(tp, 0xd420);
	data &= 0x0fff;
	data |= 0x047f;
	r8168_mac_ocp_write(tp, 0xd420, data);

	r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
	r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
	r8168_mac_ocp_write(tp, 0xc094, 0x0000);
	r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
}

5762 5763
static void rtl_hw_start_8168(struct net_device *dev)
{
5764 5765 5766 5767 5768
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Cfg9346, Cfg9346_Unlock);

5769
	RTL_W8(MaxTxPacketSize, TxPacketMax);
5770

E
Eric Dumazet 已提交
5771
	rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5772

5773
	tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
5774 5775 5776

	RTL_W16(CPlusCmd, tp->cp_cmd);

5777
	RTL_W16(IntrMitigate, 0x5151);
5778

5779
	/* Work around for RxFIFO overflow. */
F
françois romieu 已提交
5780
	if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5781 5782
		tp->event_slow |= RxFIFOOver | PCSTimeout;
		tp->event_slow &= ~RxOverflow;
5783 5784 5785
	}

	rtl_set_rx_tx_desc_registers(tp, ioaddr);
5786

H
hayeswang 已提交
5787
	rtl_set_rx_tx_config_registers(tp);
5788 5789 5790

	RTL_R8(IntrMask);

5791 5792
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_11:
5793
		rtl_hw_start_8168bb(tp);
5794
		break;
5795 5796 5797

	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
5798
		rtl_hw_start_8168bef(tp);
5799
		break;
5800 5801

	case RTL_GIGA_MAC_VER_18:
5802
		rtl_hw_start_8168cp_1(tp);
5803
		break;
5804 5805

	case RTL_GIGA_MAC_VER_19:
5806
		rtl_hw_start_8168c_1(tp);
5807
		break;
5808 5809

	case RTL_GIGA_MAC_VER_20:
5810
		rtl_hw_start_8168c_2(tp);
5811
		break;
5812

F
Francois Romieu 已提交
5813
	case RTL_GIGA_MAC_VER_21:
5814
		rtl_hw_start_8168c_3(tp);
5815
		break;
F
Francois Romieu 已提交
5816

5817
	case RTL_GIGA_MAC_VER_22:
5818
		rtl_hw_start_8168c_4(tp);
5819
		break;
5820

F
Francois Romieu 已提交
5821
	case RTL_GIGA_MAC_VER_23:
5822
		rtl_hw_start_8168cp_2(tp);
5823
		break;
F
Francois Romieu 已提交
5824

5825
	case RTL_GIGA_MAC_VER_24:
5826
		rtl_hw_start_8168cp_3(tp);
5827
		break;
5828

F
Francois Romieu 已提交
5829
	case RTL_GIGA_MAC_VER_25:
5830 5831
	case RTL_GIGA_MAC_VER_26:
	case RTL_GIGA_MAC_VER_27:
5832
		rtl_hw_start_8168d(tp);
5833
		break;
F
Francois Romieu 已提交
5834

F
françois romieu 已提交
5835
	case RTL_GIGA_MAC_VER_28:
5836
		rtl_hw_start_8168d_4(tp);
5837
		break;
F
Francois Romieu 已提交
5838

5839
	case RTL_GIGA_MAC_VER_31:
5840
		rtl_hw_start_8168dp(tp);
5841 5842
		break;

H
hayeswang 已提交
5843 5844
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
5845
		rtl_hw_start_8168e_1(tp);
H
Hayes Wang 已提交
5846 5847
		break;
	case RTL_GIGA_MAC_VER_34:
5848
		rtl_hw_start_8168e_2(tp);
H
hayeswang 已提交
5849
		break;
F
françois romieu 已提交
5850

5851 5852
	case RTL_GIGA_MAC_VER_35:
	case RTL_GIGA_MAC_VER_36:
5853
		rtl_hw_start_8168f_1(tp);
5854 5855
		break;

5856 5857 5858 5859
	case RTL_GIGA_MAC_VER_38:
		rtl_hw_start_8411(tp);
		break;

H
Hayes Wang 已提交
5860 5861 5862 5863
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
		rtl_hw_start_8168g_1(tp);
		break;
H
hayeswang 已提交
5864 5865 5866
	case RTL_GIGA_MAC_VER_42:
		rtl_hw_start_8168g_2(tp);
		break;
H
Hayes Wang 已提交
5867

H
hayeswang 已提交
5868 5869 5870 5871
	case RTL_GIGA_MAC_VER_44:
		rtl_hw_start_8411_2(tp);
		break;

5872 5873 5874 5875 5876
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
		rtl_hw_start_8168h_1(tp);
		break;

5877 5878 5879
	default:
		printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
			dev->name, tp->mac_version);
5880
		break;
5881
	}
5882

H
hayeswang 已提交
5883 5884
	RTL_W8(Cfg9346, Cfg9346_Lock);

5885 5886
	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);

H
hayeswang 已提交
5887
	rtl_set_rx_mode(dev);
5888

5889
	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5890
}
L
Linus Torvalds 已提交
5891

5892 5893 5894 5895
#define R810X_CPCMD_QUIRK_MASK (\
	EnableBist | \
	Mac_dbgo_oe | \
	Force_half_dup | \
F
françois romieu 已提交
5896
	Force_rxflow_en | \
5897 5898 5899 5900
	Force_txflow_en | \
	Cxpl_dbg_sel | \
	ASF | \
	PktCntrDisable | \
5901
	Mac_dbgo_sel)
5902

5903
static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5904
{
5905 5906
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;
5907
	static const struct ephy_info e_info_8102e_1[] = {
5908 5909 5910 5911 5912 5913 5914 5915 5916 5917 5918
		{ 0x01,	0, 0x6e65 },
		{ 0x02,	0, 0x091f },
		{ 0x03,	0, 0xc2f9 },
		{ 0x06,	0, 0xafb5 },
		{ 0x07,	0, 0x0e00 },
		{ 0x19,	0, 0xec80 },
		{ 0x01,	0, 0x2e65 },
		{ 0x01,	0, 0x6e65 }
	};
	u8 cfg1;

5919
	rtl_csi_access_enable_2(tp);
5920 5921 5922 5923 5924 5925 5926 5927 5928 5929 5930 5931 5932

	RTL_W8(DBG_REG, FIX_NAK_1);

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	RTL_W8(Config1,
	       LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

	cfg1 = RTL_R8(Config1);
	if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
		RTL_W8(Config1, cfg1 & ~LEDS0);

5933
	rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5934 5935
}

5936
static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5937
{
5938 5939 5940 5941
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

	rtl_csi_access_enable_2(tp);
5942 5943 5944 5945 5946 5947 5948

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
}

5949
static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5950
{
5951
	rtl_hw_start_8102e_2(tp);
5952

5953
	rtl_ephy_write(tp, 0x03, 0xc2f9);
5954 5955
}

5956
static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5957
{
5958
	void __iomem *ioaddr = tp->mmio_addr;
5959 5960 5961 5962 5963 5964 5965 5966 5967 5968 5969
	static const struct ephy_info e_info_8105e_1[] = {
		{ 0x07,	0, 0x4000 },
		{ 0x19,	0, 0x0200 },
		{ 0x19,	0, 0x0020 },
		{ 0x1e,	0, 0x2000 },
		{ 0x03,	0, 0x0001 },
		{ 0x19,	0, 0x0100 },
		{ 0x19,	0, 0x0004 },
		{ 0x0a,	0, 0x0020 }
	};

F
Francois Romieu 已提交
5970
	/* Force LAN exit from ASPM if Rx/Tx are not idle */
5971 5972
	RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);

F
Francois Romieu 已提交
5973
	/* Disable Early Tally Counter */
5974 5975 5976
	RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);

	RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
H
Hayes Wang 已提交
5977
	RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5978

5979
	rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
H
hayeswang 已提交
5980 5981

	rtl_pcie_state_l2l3_enable(tp, false);
5982 5983
}

5984
static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5985
{
5986
	rtl_hw_start_8105e_1(tp);
5987
	rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5988 5989
}

5990 5991 5992 5993 5994 5995 5996 5997 5998 5999 6000 6001 6002 6003 6004 6005
static void rtl_hw_start_8402(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;
	static const struct ephy_info e_info_8402[] = {
		{ 0x19,	0xffff, 0xff64 },
		{ 0x1e,	0, 0x4000 }
	};

	rtl_csi_access_enable_2(tp);

	/* Force LAN exit from ASPM if Rx/Tx are not idle */
	RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);

	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
	RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);

6006
	rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6007 6008 6009

	rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);

6010 6011 6012 6013 6014 6015 6016
	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
H
hayeswang 已提交
6017 6018

	rtl_pcie_state_l2l3_enable(tp, false);
6019 6020
}

H
Hayes Wang 已提交
6021 6022 6023 6024 6025 6026 6027
static void rtl_hw_start_8106(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	/* Force LAN exit from ASPM if Rx/Tx are not idle */
	RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);

6028
	RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
H
Hayes Wang 已提交
6029 6030
	RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
	RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
H
hayeswang 已提交
6031 6032

	rtl_pcie_state_l2l3_enable(tp, false);
H
Hayes Wang 已提交
6033 6034
}

6035 6036
static void rtl_hw_start_8101(struct net_device *dev)
{
6037 6038 6039 6040
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

6041 6042
	if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
		tp->event_slow &= ~RxFIFOOver;
F
françois romieu 已提交
6043

F
Francois Romieu 已提交
6044
	if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6045
	    tp->mac_version == RTL_GIGA_MAC_VER_16)
6046 6047
		pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
					 PCI_EXP_DEVCTL_NOSNOOP_EN);
6048

6049 6050
	RTL_W8(Cfg9346, Cfg9346_Unlock);

H
hayeswang 已提交
6051 6052 6053 6054 6055 6056 6057 6058 6059 6060 6061
	RTL_W8(MaxTxPacketSize, TxPacketMax);

	rtl_set_rx_max_size(ioaddr, rx_buf_sz);

	tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
	RTL_W16(CPlusCmd, tp->cp_cmd);

	rtl_set_rx_tx_desc_registers(tp, ioaddr);

	rtl_set_rx_tx_config_registers(tp);

6062 6063
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_07:
6064
		rtl_hw_start_8102e_1(tp);
6065 6066 6067
		break;

	case RTL_GIGA_MAC_VER_08:
6068
		rtl_hw_start_8102e_3(tp);
6069 6070 6071
		break;

	case RTL_GIGA_MAC_VER_09:
6072
		rtl_hw_start_8102e_2(tp);
6073
		break;
6074 6075

	case RTL_GIGA_MAC_VER_29:
6076
		rtl_hw_start_8105e_1(tp);
6077 6078
		break;
	case RTL_GIGA_MAC_VER_30:
6079
		rtl_hw_start_8105e_2(tp);
6080
		break;
6081 6082 6083 6084

	case RTL_GIGA_MAC_VER_37:
		rtl_hw_start_8402(tp);
		break;
H
Hayes Wang 已提交
6085 6086 6087 6088

	case RTL_GIGA_MAC_VER_39:
		rtl_hw_start_8106(tp);
		break;
H
hayeswang 已提交
6089 6090 6091
	case RTL_GIGA_MAC_VER_43:
		rtl_hw_start_8168g_2(tp);
		break;
6092 6093 6094 6095
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
		rtl_hw_start_8168h_1(tp);
		break;
6096 6097
	}

6098
	RTL_W8(Cfg9346, Cfg9346_Lock);
6099 6100 6101 6102 6103 6104 6105

	RTL_W16(IntrMitigate, 0x0000);

	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);

	rtl_set_rx_mode(dev);

H
hayeswang 已提交
6106 6107
	RTL_R8(IntrMask);

6108
	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
L
Linus Torvalds 已提交
6109 6110 6111 6112
}

static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
{
F
Francois Romieu 已提交
6113 6114 6115 6116
	struct rtl8169_private *tp = netdev_priv(dev);

	if (new_mtu < ETH_ZLEN ||
	    new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
L
Linus Torvalds 已提交
6117 6118
		return -EINVAL;

F
Francois Romieu 已提交
6119 6120 6121 6122 6123
	if (new_mtu > ETH_DATA_LEN)
		rtl_hw_jumbo_enable(tp);
	else
		rtl_hw_jumbo_disable(tp);

L
Linus Torvalds 已提交
6124
	dev->mtu = new_mtu;
6125 6126
	netdev_update_features(dev);

S
Stanislaw Gruszka 已提交
6127
	return 0;
L
Linus Torvalds 已提交
6128 6129 6130 6131
}

static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
{
A
Al Viro 已提交
6132
	desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
L
Linus Torvalds 已提交
6133 6134 6135
	desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
}

E
Eric Dumazet 已提交
6136 6137
static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
				     void **data_buff, struct RxDesc *desc)
L
Linus Torvalds 已提交
6138
{
6139
	dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6140
			 DMA_FROM_DEVICE);
6141

E
Eric Dumazet 已提交
6142 6143
	kfree(*data_buff);
	*data_buff = NULL;
L
Linus Torvalds 已提交
6144 6145 6146 6147 6148 6149 6150 6151 6152 6153 6154 6155 6156 6157 6158 6159 6160 6161
	rtl8169_make_unusable_by_asic(desc);
}

static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
{
	u32 eor = le32_to_cpu(desc->opts1) & RingEnd;

	desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
}

static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
				       u32 rx_buf_sz)
{
	desc->addr = cpu_to_le64(mapping);
	wmb();
	rtl8169_mark_to_asic(desc, rx_buf_sz);
}

E
Eric Dumazet 已提交
6162 6163 6164 6165 6166
static inline void *rtl8169_align(void *data)
{
	return (void *)ALIGN((long)data, 16);
}

S
Stanislaw Gruszka 已提交
6167 6168
static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
					     struct RxDesc *desc)
L
Linus Torvalds 已提交
6169
{
E
Eric Dumazet 已提交
6170
	void *data;
L
Linus Torvalds 已提交
6171
	dma_addr_t mapping;
6172
	struct device *d = &tp->pci_dev->dev;
S
Stanislaw Gruszka 已提交
6173
	struct net_device *dev = tp->dev;
E
Eric Dumazet 已提交
6174
	int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
L
Linus Torvalds 已提交
6175

E
Eric Dumazet 已提交
6176 6177 6178
	data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
	if (!data)
		return NULL;
6179

E
Eric Dumazet 已提交
6180 6181 6182 6183 6184 6185
	if (rtl8169_align(data) != data) {
		kfree(data);
		data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
		if (!data)
			return NULL;
	}
6186

6187
	mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6188
				 DMA_FROM_DEVICE);
6189 6190 6191
	if (unlikely(dma_mapping_error(d, mapping))) {
		if (net_ratelimit())
			netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6192
		goto err_out;
6193
	}
L
Linus Torvalds 已提交
6194 6195

	rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
E
Eric Dumazet 已提交
6196
	return data;
6197 6198 6199 6200

err_out:
	kfree(data);
	return NULL;
L
Linus Torvalds 已提交
6201 6202 6203 6204
}

static void rtl8169_rx_clear(struct rtl8169_private *tp)
{
F
Francois Romieu 已提交
6205
	unsigned int i;
L
Linus Torvalds 已提交
6206 6207

	for (i = 0; i < NUM_RX_DESC; i++) {
E
Eric Dumazet 已提交
6208 6209
		if (tp->Rx_databuff[i]) {
			rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
L
Linus Torvalds 已提交
6210 6211 6212 6213 6214
					    tp->RxDescArray + i);
		}
	}
}

S
Stanislaw Gruszka 已提交
6215
static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
L
Linus Torvalds 已提交
6216
{
S
Stanislaw Gruszka 已提交
6217 6218
	desc->opts1 |= cpu_to_le32(RingEnd);
}
6219

S
Stanislaw Gruszka 已提交
6220 6221 6222
static int rtl8169_rx_fill(struct rtl8169_private *tp)
{
	unsigned int i;
L
Linus Torvalds 已提交
6223

S
Stanislaw Gruszka 已提交
6224 6225
	for (i = 0; i < NUM_RX_DESC; i++) {
		void *data;
6226

E
Eric Dumazet 已提交
6227
		if (tp->Rx_databuff[i])
L
Linus Torvalds 已提交
6228
			continue;
6229

S
Stanislaw Gruszka 已提交
6230
		data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
E
Eric Dumazet 已提交
6231 6232
		if (!data) {
			rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
S
Stanislaw Gruszka 已提交
6233
			goto err_out;
E
Eric Dumazet 已提交
6234 6235
		}
		tp->Rx_databuff[i] = data;
L
Linus Torvalds 已提交
6236 6237
	}

S
Stanislaw Gruszka 已提交
6238 6239 6240 6241 6242 6243
	rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
	return 0;

err_out:
	rtl8169_rx_clear(tp);
	return -ENOMEM;
L
Linus Torvalds 已提交
6244 6245 6246 6247 6248 6249 6250 6251 6252
}

static int rtl8169_init_ring(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl8169_init_ring_indexes(tp);

	memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
E
Eric Dumazet 已提交
6253
	memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
L
Linus Torvalds 已提交
6254

S
Stanislaw Gruszka 已提交
6255
	return rtl8169_rx_fill(tp);
L
Linus Torvalds 已提交
6256 6257
}

6258
static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
L
Linus Torvalds 已提交
6259 6260 6261 6262
				 struct TxDesc *desc)
{
	unsigned int len = tx_skb->len;

6263 6264
	dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);

L
Linus Torvalds 已提交
6265 6266 6267 6268 6269 6270
	desc->opts1 = 0x00;
	desc->opts2 = 0x00;
	desc->addr = 0x00;
	tx_skb->len = 0;
}

6271 6272
static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
				   unsigned int n)
L
Linus Torvalds 已提交
6273 6274 6275
{
	unsigned int i;

6276 6277
	for (i = 0; i < n; i++) {
		unsigned int entry = (start + i) % NUM_TX_DESC;
L
Linus Torvalds 已提交
6278 6279 6280 6281 6282 6283
		struct ring_info *tx_skb = tp->tx_skb + entry;
		unsigned int len = tx_skb->len;

		if (len) {
			struct sk_buff *skb = tx_skb->skb;

6284
			rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
L
Linus Torvalds 已提交
6285 6286
					     tp->TxDescArray + entry);
			if (skb) {
6287
				tp->dev->stats.tx_dropped++;
6288
				dev_kfree_skb_any(skb);
L
Linus Torvalds 已提交
6289 6290 6291 6292
				tx_skb->skb = NULL;
			}
		}
	}
6293 6294 6295 6296 6297
}

static void rtl8169_tx_clear(struct rtl8169_private *tp)
{
	rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
L
Linus Torvalds 已提交
6298 6299 6300
	tp->cur_tx = tp->dirty_tx = 0;
}

6301
static void rtl_reset_work(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
6302
{
D
David Howells 已提交
6303
	struct net_device *dev = tp->dev;
6304
	int i;
L
Linus Torvalds 已提交
6305

6306 6307 6308
	napi_disable(&tp->napi);
	netif_stop_queue(dev);
	synchronize_sched();
L
Linus Torvalds 已提交
6309

6310 6311
	rtl8169_hw_reset(tp);

6312 6313 6314
	for (i = 0; i < NUM_RX_DESC; i++)
		rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);

L
Linus Torvalds 已提交
6315
	rtl8169_tx_clear(tp);
6316
	rtl8169_init_ring_indexes(tp);
L
Linus Torvalds 已提交
6317

6318
	napi_enable(&tp->napi);
6319 6320 6321
	rtl_hw_start(dev);
	netif_wake_queue(dev);
	rtl8169_check_link_status(dev, tp, tp->mmio_addr);
L
Linus Torvalds 已提交
6322 6323 6324 6325
}

static void rtl8169_tx_timeout(struct net_device *dev)
{
6326 6327 6328
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
L
Linus Torvalds 已提交
6329 6330 6331
}

static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
F
Francois Romieu 已提交
6332
			      u32 *opts)
L
Linus Torvalds 已提交
6333 6334 6335
{
	struct skb_shared_info *info = skb_shinfo(skb);
	unsigned int cur_frag, entry;
6336
	struct TxDesc *uninitialized_var(txd);
6337
	struct device *d = &tp->pci_dev->dev;
L
Linus Torvalds 已提交
6338 6339 6340

	entry = tp->cur_tx;
	for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
E
Eric Dumazet 已提交
6341
		const skb_frag_t *frag = info->frags + cur_frag;
L
Linus Torvalds 已提交
6342 6343 6344 6345 6346 6347 6348
		dma_addr_t mapping;
		u32 status, len;
		void *addr;

		entry = (entry + 1) % NUM_TX_DESC;

		txd = tp->TxDescArray + entry;
E
Eric Dumazet 已提交
6349
		len = skb_frag_size(frag);
6350
		addr = skb_frag_address(frag);
6351
		mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6352 6353 6354 6355
		if (unlikely(dma_mapping_error(d, mapping))) {
			if (net_ratelimit())
				netif_err(tp, drv, tp->dev,
					  "Failed to map TX fragments DMA!\n");
6356
			goto err_out;
6357
		}
L
Linus Torvalds 已提交
6358

F
Francois Romieu 已提交
6359
		/* Anti gcc 2.95.3 bugware (sic) */
F
Francois Romieu 已提交
6360 6361
		status = opts[0] | len |
			(RingEnd * !((entry + 1) % NUM_TX_DESC));
L
Linus Torvalds 已提交
6362 6363

		txd->opts1 = cpu_to_le32(status);
F
Francois Romieu 已提交
6364
		txd->opts2 = cpu_to_le32(opts[1]);
L
Linus Torvalds 已提交
6365 6366 6367 6368 6369 6370 6371 6372 6373 6374 6375
		txd->addr = cpu_to_le64(mapping);

		tp->tx_skb[entry].len = len;
	}

	if (cur_frag) {
		tp->tx_skb[entry].skb = skb;
		txd->opts1 |= cpu_to_le32(LastFrag);
	}

	return cur_frag;
6376 6377 6378 6379

err_out:
	rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
	return -EIO;
L
Linus Torvalds 已提交
6380 6381
}

6382 6383 6384 6385 6386 6387 6388 6389 6390 6391 6392 6393 6394
static bool rtl_skb_pad(struct sk_buff *skb)
{
	if (skb_padto(skb, ETH_ZLEN))
		return false;
	skb_put(skb, ETH_ZLEN - skb->len);
	return true;
}

static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
{
	return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
}

H
hayeswang 已提交
6395 6396 6397 6398 6399 6400 6401 6402 6403 6404 6405 6406 6407 6408 6409 6410 6411 6412 6413 6414 6415 6416 6417 6418 6419 6420 6421 6422 6423 6424 6425 6426 6427 6428 6429 6430 6431 6432 6433 6434 6435 6436 6437 6438 6439 6440 6441 6442 6443 6444 6445 6446 6447 6448 6449 6450 6451 6452 6453 6454 6455 6456 6457 6458 6459 6460 6461 6462 6463 6464 6465 6466 6467 6468 6469 6470
static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
				      struct net_device *dev);
/* r8169_csum_workaround()
 * The hw limites the value the transport offset. When the offset is out of the
 * range, calculate the checksum by sw.
 */
static void r8169_csum_workaround(struct rtl8169_private *tp,
				  struct sk_buff *skb)
{
	if (skb_shinfo(skb)->gso_size) {
		netdev_features_t features = tp->dev->features;
		struct sk_buff *segs, *nskb;

		features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
		segs = skb_gso_segment(skb, features);
		if (IS_ERR(segs) || !segs)
			goto drop;

		do {
			nskb = segs;
			segs = segs->next;
			nskb->next = NULL;
			rtl8169_start_xmit(nskb, tp->dev);
		} while (segs);

		dev_kfree_skb(skb);
	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
		if (skb_checksum_help(skb) < 0)
			goto drop;

		rtl8169_start_xmit(skb, tp->dev);
	} else {
		struct net_device_stats *stats;

drop:
		stats = &tp->dev->stats;
		stats->tx_dropped++;
		dev_kfree_skb(skb);
	}
}

/* msdn_giant_send_check()
 * According to the document of microsoft, the TCP Pseudo Header excludes the
 * packet length for IPv6 TCP large packets.
 */
static int msdn_giant_send_check(struct sk_buff *skb)
{
	const struct ipv6hdr *ipv6h;
	struct tcphdr *th;
	int ret;

	ret = skb_cow_head(skb, 0);
	if (ret)
		return ret;

	ipv6h = ipv6_hdr(skb);
	th = tcp_hdr(skb);

	th->check = 0;
	th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);

	return ret;
}

static inline __be16 get_protocol(struct sk_buff *skb)
{
	__be16 protocol;

	if (skb->protocol == htons(ETH_P_8021Q))
		protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
	else
		protocol = skb->protocol;

	return protocol;
}

H
hayeswang 已提交
6471 6472
static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
				struct sk_buff *skb, u32 *opts)
L
Linus Torvalds 已提交
6473
{
6474 6475
	u32 mss = skb_shinfo(skb)->gso_size;

F
Francois Romieu 已提交
6476 6477
	if (mss) {
		opts[0] |= TD_LSO;
H
hayeswang 已提交
6478 6479 6480 6481 6482 6483 6484 6485 6486 6487 6488 6489 6490 6491 6492 6493 6494 6495
		opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
		const struct iphdr *ip = ip_hdr(skb);

		if (ip->protocol == IPPROTO_TCP)
			opts[0] |= TD0_IP_CS | TD0_TCP_CS;
		else if (ip->protocol == IPPROTO_UDP)
			opts[0] |= TD0_IP_CS | TD0_UDP_CS;
		else
			WARN_ON_ONCE(1);
	}

	return true;
}

static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
				struct sk_buff *skb, u32 *opts)
{
H
hayeswang 已提交
6496
	u32 transport_offset = (u32)skb_transport_offset(skb);
H
hayeswang 已提交
6497 6498 6499
	u32 mss = skb_shinfo(skb)->gso_size;

	if (mss) {
H
hayeswang 已提交
6500 6501 6502 6503 6504 6505 6506 6507 6508 6509 6510 6511 6512 6513 6514 6515 6516 6517 6518 6519 6520 6521 6522 6523
		if (transport_offset > GTTCPHO_MAX) {
			netif_warn(tp, tx_err, tp->dev,
				   "Invalid transport offset 0x%x for TSO\n",
				   transport_offset);
			return false;
		}

		switch (get_protocol(skb)) {
		case htons(ETH_P_IP):
			opts[0] |= TD1_GTSENV4;
			break;

		case htons(ETH_P_IPV6):
			if (msdn_giant_send_check(skb))
				return false;

			opts[0] |= TD1_GTSENV6;
			break;

		default:
			WARN_ON_ONCE(1);
			break;
		}

H
hayeswang 已提交
6524
		opts[0] |= transport_offset << GTTCPHO_SHIFT;
H
hayeswang 已提交
6525
		opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
F
Francois Romieu 已提交
6526
	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
H
hayeswang 已提交
6527
		u8 ip_protocol;
L
Linus Torvalds 已提交
6528

6529 6530 6531
		if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
			return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);

H
hayeswang 已提交
6532 6533 6534 6535 6536 6537 6538 6539 6540 6541 6542 6543 6544 6545 6546 6547 6548 6549 6550 6551 6552 6553 6554 6555 6556 6557 6558
		if (transport_offset > TCPHO_MAX) {
			netif_warn(tp, tx_err, tp->dev,
				   "Invalid transport offset 0x%x\n",
				   transport_offset);
			return false;
		}

		switch (get_protocol(skb)) {
		case htons(ETH_P_IP):
			opts[1] |= TD1_IPv4_CS;
			ip_protocol = ip_hdr(skb)->protocol;
			break;

		case htons(ETH_P_IPV6):
			opts[1] |= TD1_IPv6_CS;
			ip_protocol = ipv6_hdr(skb)->nexthdr;
			break;

		default:
			ip_protocol = IPPROTO_RAW;
			break;
		}

		if (ip_protocol == IPPROTO_TCP)
			opts[1] |= TD1_TCP_CS;
		else if (ip_protocol == IPPROTO_UDP)
			opts[1] |= TD1_UDP_CS;
F
Francois Romieu 已提交
6559 6560
		else
			WARN_ON_ONCE(1);
H
hayeswang 已提交
6561 6562

		opts[1] |= transport_offset << TCPHO_SHIFT;
6563 6564 6565
	} else {
		if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
			return rtl_skb_pad(skb);
L
Linus Torvalds 已提交
6566
	}
H
hayeswang 已提交
6567

6568
	return true;
L
Linus Torvalds 已提交
6569 6570
}

6571 6572
static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
				      struct net_device *dev)
L
Linus Torvalds 已提交
6573 6574
{
	struct rtl8169_private *tp = netdev_priv(dev);
6575
	unsigned int entry = tp->cur_tx % NUM_TX_DESC;
L
Linus Torvalds 已提交
6576 6577
	struct TxDesc *txd = tp->TxDescArray + entry;
	void __iomem *ioaddr = tp->mmio_addr;
6578
	struct device *d = &tp->pci_dev->dev;
L
Linus Torvalds 已提交
6579 6580
	dma_addr_t mapping;
	u32 status, len;
F
Francois Romieu 已提交
6581
	u32 opts[2];
6582
	int frags;
6583

6584
	if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6585
		netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6586
		goto err_stop_0;
L
Linus Torvalds 已提交
6587 6588 6589
	}

	if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6590 6591
		goto err_stop_0;

6592 6593 6594
	opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
	opts[0] = DescOwn;

H
hayeswang 已提交
6595 6596 6597 6598
	if (!tp->tso_csum(tp, skb, opts)) {
		r8169_csum_workaround(tp, skb);
		return NETDEV_TX_OK;
	}
6599

6600
	len = skb_headlen(skb);
6601
	mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6602 6603 6604
	if (unlikely(dma_mapping_error(d, mapping))) {
		if (net_ratelimit())
			netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6605
		goto err_dma_0;
6606
	}
6607 6608 6609

	tp->tx_skb[entry].len = len;
	txd->addr = cpu_to_le64(mapping);
L
Linus Torvalds 已提交
6610

F
Francois Romieu 已提交
6611
	frags = rtl8169_xmit_frags(tp, skb, opts);
6612 6613 6614
	if (frags < 0)
		goto err_dma_1;
	else if (frags)
F
Francois Romieu 已提交
6615
		opts[0] |= FirstFrag;
6616
	else {
F
Francois Romieu 已提交
6617
		opts[0] |= FirstFrag | LastFrag;
L
Linus Torvalds 已提交
6618 6619 6620
		tp->tx_skb[entry].skb = skb;
	}

F
Francois Romieu 已提交
6621 6622
	txd->opts2 = cpu_to_le32(opts[1]);

6623 6624
	skb_tx_timestamp(skb);

L
Linus Torvalds 已提交
6625 6626
	wmb();

F
Francois Romieu 已提交
6627
	/* Anti gcc 2.95.3 bugware (sic) */
F
Francois Romieu 已提交
6628
	status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
L
Linus Torvalds 已提交
6629 6630 6631 6632
	txd->opts1 = cpu_to_le32(status);

	tp->cur_tx += frags + 1;

6633
	wmb();
L
Linus Torvalds 已提交
6634

F
Francois Romieu 已提交
6635
	RTL_W8(TxPoll, NPQ);
L
Linus Torvalds 已提交
6636

6637 6638
	mmiowb();

6639
	if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6640 6641 6642 6643
		/* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
		 * not miss a ring update when it notices a stopped queue.
		 */
		smp_wmb();
L
Linus Torvalds 已提交
6644
		netif_stop_queue(dev);
6645 6646 6647 6648 6649 6650 6651
		/* Sync with rtl_tx:
		 * - publish queue status and cur_tx ring index (write barrier)
		 * - refresh dirty_tx ring index (read barrier).
		 * May the current thread have a pessimistic view of the ring
		 * status and forget to wake up queue, a racing rtl_tx thread
		 * can't.
		 */
F
Francois Romieu 已提交
6652
		smp_mb();
6653
		if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
L
Linus Torvalds 已提交
6654 6655 6656
			netif_wake_queue(dev);
	}

6657
	return NETDEV_TX_OK;
L
Linus Torvalds 已提交
6658

6659
err_dma_1:
6660
	rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6661
err_dma_0:
6662
	dev_kfree_skb_any(skb);
6663 6664 6665 6666
	dev->stats.tx_dropped++;
	return NETDEV_TX_OK;

err_stop_0:
L
Linus Torvalds 已提交
6667
	netif_stop_queue(dev);
6668
	dev->stats.tx_dropped++;
6669
	return NETDEV_TX_BUSY;
L
Linus Torvalds 已提交
6670 6671 6672 6673 6674 6675 6676 6677 6678 6679 6680
}

static void rtl8169_pcierr_interrupt(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct pci_dev *pdev = tp->pci_dev;
	u16 pci_status, pci_cmd;

	pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
	pci_read_config_word(pdev, PCI_STATUS, &pci_status);

6681 6682
	netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
		  pci_cmd, pci_status);
L
Linus Torvalds 已提交
6683 6684 6685 6686

	/*
	 * The recovery sequence below admits a very elaborated explanation:
	 * - it seems to work;
6687 6688
	 * - I did not see what else could be done;
	 * - it makes iop3xx happy.
L
Linus Torvalds 已提交
6689 6690 6691
	 *
	 * Feel free to adjust to your needs.
	 */
6692
	if (pdev->broken_parity_status)
6693 6694 6695 6696 6697
		pci_cmd &= ~PCI_COMMAND_PARITY;
	else
		pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;

	pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
L
Linus Torvalds 已提交
6698 6699 6700 6701 6702 6703 6704

	pci_write_config_word(pdev, PCI_STATUS,
		pci_status & (PCI_STATUS_DETECTED_PARITY |
		PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
		PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));

	/* The infamous DAC f*ckup only happens at boot time */
6705
	if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
F
françois romieu 已提交
6706 6707
		void __iomem *ioaddr = tp->mmio_addr;

6708
		netif_info(tp, intr, dev, "disabling PCI DAC\n");
L
Linus Torvalds 已提交
6709 6710 6711 6712 6713
		tp->cp_cmd &= ~PCIDAC;
		RTL_W16(CPlusCmd, tp->cp_cmd);
		dev->features &= ~NETIF_F_HIGHDMA;
	}

F
françois romieu 已提交
6714
	rtl8169_hw_reset(tp);
6715

6716
	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
L
Linus Torvalds 已提交
6717 6718
}

6719
static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
L
Linus Torvalds 已提交
6720 6721 6722 6723 6724 6725 6726 6727 6728 6729 6730 6731 6732 6733 6734 6735 6736
{
	unsigned int dirty_tx, tx_left;

	dirty_tx = tp->dirty_tx;
	smp_rmb();
	tx_left = tp->cur_tx - dirty_tx;

	while (tx_left > 0) {
		unsigned int entry = dirty_tx % NUM_TX_DESC;
		struct ring_info *tx_skb = tp->tx_skb + entry;
		u32 status;

		rmb();
		status = le32_to_cpu(tp->TxDescArray[entry].opts1);
		if (status & DescOwn)
			break;

6737 6738
		rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
				     tp->TxDescArray + entry);
L
Linus Torvalds 已提交
6739
		if (status & LastFrag) {
6740 6741 6742 6743
			u64_stats_update_begin(&tp->tx_stats.syncp);
			tp->tx_stats.packets++;
			tp->tx_stats.bytes += tx_skb->skb->len;
			u64_stats_update_end(&tp->tx_stats.syncp);
6744
			dev_kfree_skb_any(tx_skb->skb);
L
Linus Torvalds 已提交
6745 6746 6747 6748 6749 6750 6751 6752
			tx_skb->skb = NULL;
		}
		dirty_tx++;
		tx_left--;
	}

	if (tp->dirty_tx != dirty_tx) {
		tp->dirty_tx = dirty_tx;
6753 6754 6755 6756 6757 6758 6759
		/* Sync with rtl8169_start_xmit:
		 * - publish dirty_tx ring index (write barrier)
		 * - refresh cur_tx ring index and queue status (read barrier)
		 * May the current thread miss the stopped queue condition,
		 * a racing xmit thread can only have a right view of the
		 * ring status.
		 */
F
Francois Romieu 已提交
6760
		smp_mb();
L
Linus Torvalds 已提交
6761
		if (netif_queue_stopped(dev) &&
6762
		    TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
L
Linus Torvalds 已提交
6763 6764
			netif_wake_queue(dev);
		}
6765 6766 6767 6768 6769 6770
		/*
		 * 8168 hack: TxPoll requests are lost when the Tx packets are
		 * too close. Let's kick an extra TxPoll request when a burst
		 * of start_xmit activity is detected (if it is not detected,
		 * it is slow enough). -- FR
		 */
6771 6772 6773
		if (tp->cur_tx != dirty_tx) {
			void __iomem *ioaddr = tp->mmio_addr;

6774
			RTL_W8(TxPoll, NPQ);
6775
		}
L
Linus Torvalds 已提交
6776 6777 6778
	}
}

6779 6780 6781 6782 6783
static inline int rtl8169_fragmented_frame(u32 status)
{
	return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
}

E
Eric Dumazet 已提交
6784
static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
L
Linus Torvalds 已提交
6785 6786 6787 6788
{
	u32 status = opts1 & RxProtoMask;

	if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
S
Shan Wei 已提交
6789
	    ((status == RxProtoUDP) && !(opts1 & UDPFail)))
L
Linus Torvalds 已提交
6790 6791
		skb->ip_summed = CHECKSUM_UNNECESSARY;
	else
6792
		skb_checksum_none_assert(skb);
L
Linus Torvalds 已提交
6793 6794
}

E
Eric Dumazet 已提交
6795 6796 6797 6798
static struct sk_buff *rtl8169_try_rx_copy(void *data,
					   struct rtl8169_private *tp,
					   int pkt_size,
					   dma_addr_t addr)
L
Linus Torvalds 已提交
6799
{
S
Stephen Hemminger 已提交
6800
	struct sk_buff *skb;
6801
	struct device *d = &tp->pci_dev->dev;
S
Stephen Hemminger 已提交
6802

E
Eric Dumazet 已提交
6803
	data = rtl8169_align(data);
6804
	dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
E
Eric Dumazet 已提交
6805 6806 6807 6808
	prefetch(data);
	skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
	if (skb)
		memcpy(skb->data, data, pkt_size);
6809 6810
	dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);

E
Eric Dumazet 已提交
6811
	return skb;
L
Linus Torvalds 已提交
6812 6813
}

6814
static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
L
Linus Torvalds 已提交
6815 6816
{
	unsigned int cur_rx, rx_left;
E
Eric Dumazet 已提交
6817
	unsigned int count;
L
Linus Torvalds 已提交
6818 6819 6820

	cur_rx = tp->cur_rx;

6821
	for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
L
Linus Torvalds 已提交
6822
		unsigned int entry = cur_rx % NUM_RX_DESC;
6823
		struct RxDesc *desc = tp->RxDescArray + entry;
L
Linus Torvalds 已提交
6824 6825 6826
		u32 status;

		rmb();
6827
		status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
L
Linus Torvalds 已提交
6828 6829 6830

		if (status & DescOwn)
			break;
R
Richard Dawe 已提交
6831
		if (unlikely(status & RxRES)) {
6832 6833
			netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
				   status);
6834
			dev->stats.rx_errors++;
L
Linus Torvalds 已提交
6835
			if (status & (RxRWT | RxRUNT))
6836
				dev->stats.rx_length_errors++;
L
Linus Torvalds 已提交
6837
			if (status & RxCRC)
6838
				dev->stats.rx_crc_errors++;
6839
			if (status & RxFOVF) {
6840
				rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6841
				dev->stats.rx_fifo_errors++;
6842
			}
B
Ben Greear 已提交
6843 6844 6845 6846
			if ((status & (RxRUNT | RxCRC)) &&
			    !(status & (RxRWT | RxFOVF)) &&
			    (dev->features & NETIF_F_RXALL))
				goto process_pkt;
L
Linus Torvalds 已提交
6847
		} else {
E
Eric Dumazet 已提交
6848
			struct sk_buff *skb;
B
Ben Greear 已提交
6849 6850 6851 6852 6853
			dma_addr_t addr;
			int pkt_size;

process_pkt:
			addr = le64_to_cpu(desc->addr);
B
Ben Greear 已提交
6854 6855 6856 6857
			if (likely(!(dev->features & NETIF_F_RXFCS)))
				pkt_size = (status & 0x00003fff) - 4;
			else
				pkt_size = status & 0x00003fff;
L
Linus Torvalds 已提交
6858

6859 6860 6861 6862 6863 6864
			/*
			 * The driver does not support incoming fragmented
			 * frames. They are seen as a symptom of over-mtu
			 * sized frames.
			 */
			if (unlikely(rtl8169_fragmented_frame(status))) {
6865 6866
				dev->stats.rx_dropped++;
				dev->stats.rx_length_errors++;
6867
				goto release_descriptor;
6868 6869
			}

E
Eric Dumazet 已提交
6870 6871 6872 6873
			skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
						  tp, pkt_size, addr);
			if (!skb) {
				dev->stats.rx_dropped++;
6874
				goto release_descriptor;
L
Linus Torvalds 已提交
6875 6876
			}

E
Eric Dumazet 已提交
6877
			rtl8169_rx_csum(skb, status);
L
Linus Torvalds 已提交
6878 6879 6880
			skb_put(skb, pkt_size);
			skb->protocol = eth_type_trans(skb, dev);

6881 6882
			rtl8169_rx_vlan_tag(desc, skb);

6883
			napi_gro_receive(&tp->napi, skb);
L
Linus Torvalds 已提交
6884

J
Junchang Wang 已提交
6885 6886 6887 6888
			u64_stats_update_begin(&tp->rx_stats.syncp);
			tp->rx_stats.packets++;
			tp->rx_stats.bytes += pkt_size;
			u64_stats_update_end(&tp->rx_stats.syncp);
L
Linus Torvalds 已提交
6889
		}
6890 6891 6892 6893
release_descriptor:
		desc->opts2 = 0;
		wmb();
		rtl8169_mark_to_asic(desc, rx_buf_sz);
L
Linus Torvalds 已提交
6894 6895 6896 6897 6898 6899 6900 6901
	}

	count = cur_rx - tp->cur_rx;
	tp->cur_rx = cur_rx;

	return count;
}

F
Francois Romieu 已提交
6902
static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
L
Linus Torvalds 已提交
6903
{
F
Francois Romieu 已提交
6904
	struct net_device *dev = dev_instance;
L
Linus Torvalds 已提交
6905 6906
	struct rtl8169_private *tp = netdev_priv(dev);
	int handled = 0;
F
Francois Romieu 已提交
6907
	u16 status;
L
Linus Torvalds 已提交
6908

F
Francois Romieu 已提交
6909
	status = rtl_get_events(tp);
6910 6911 6912 6913
	if (status && status != 0xffff) {
		status &= RTL_EVENT_NAPI | tp->event_slow;
		if (status) {
			handled = 1;
L
Linus Torvalds 已提交
6914

6915 6916
			rtl_irq_disable(tp);
			napi_schedule(&tp->napi);
6917
		}
6918 6919 6920
	}
	return IRQ_RETVAL(handled);
}
L
Linus Torvalds 已提交
6921

6922 6923 6924 6925 6926 6927 6928 6929 6930 6931
/*
 * Workqueue context.
 */
static void rtl_slow_event_work(struct rtl8169_private *tp)
{
	struct net_device *dev = tp->dev;
	u16 status;

	status = rtl_get_events(tp) & tp->event_slow;
	rtl_ack_events(tp, status);
L
Linus Torvalds 已提交
6932

6933 6934 6935 6936 6937
	if (unlikely(status & RxFIFOOver)) {
		switch (tp->mac_version) {
		/* Work around for rx fifo overflow */
		case RTL_GIGA_MAC_VER_11:
			netif_stop_queue(dev);
6938 6939
			/* XXX - Hack alert. See rtl_task(). */
			set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6940
		default:
6941 6942
			break;
		}
6943
	}
L
Linus Torvalds 已提交
6944

6945 6946
	if (unlikely(status & SYSErr))
		rtl8169_pcierr_interrupt(dev);
6947

6948 6949
	if (status & LinkChg)
		__rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
L
Linus Torvalds 已提交
6950

6951
	rtl_irq_enable_all(tp);
L
Linus Torvalds 已提交
6952 6953
}

6954 6955
static void rtl_task(struct work_struct *work)
{
6956 6957 6958 6959
	static const struct {
		int bitnr;
		void (*action)(struct rtl8169_private *);
	} rtl_work[] = {
6960
		/* XXX - keep rtl_slow_event_work() as first element. */
6961 6962 6963 6964
		{ RTL_FLAG_TASK_SLOW_PENDING,	rtl_slow_event_work },
		{ RTL_FLAG_TASK_RESET_PENDING,	rtl_reset_work },
		{ RTL_FLAG_TASK_PHY_PENDING,	rtl_phy_work }
	};
6965 6966
	struct rtl8169_private *tp =
		container_of(work, struct rtl8169_private, wk.work);
6967 6968 6969 6970 6971
	struct net_device *dev = tp->dev;
	int i;

	rtl_lock_work(tp);

6972 6973
	if (!netif_running(dev) ||
	    !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6974 6975 6976 6977 6978 6979 6980 6981 6982
		goto out_unlock;

	for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
		bool pending;

		pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
		if (pending)
			rtl_work[i].action(tp);
	}
6983

6984 6985
out_unlock:
	rtl_unlock_work(tp);
6986 6987
}

6988
static int rtl8169_poll(struct napi_struct *napi, int budget)
L
Linus Torvalds 已提交
6989
{
6990 6991
	struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
	struct net_device *dev = tp->dev;
6992 6993 6994 6995 6996 6997 6998 6999 7000 7001 7002 7003
	u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
	int work_done= 0;
	u16 status;

	status = rtl_get_events(tp);
	rtl_ack_events(tp, status & ~tp->event_slow);

	if (status & RTL_EVENT_NAPI_RX)
		work_done = rtl_rx(dev, tp, (u32) budget);

	if (status & RTL_EVENT_NAPI_TX)
		rtl_tx(dev, tp);
L
Linus Torvalds 已提交
7004

7005 7006 7007 7008 7009
	if (status & tp->event_slow) {
		enable_mask &= ~tp->event_slow;

		rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
	}
L
Linus Torvalds 已提交
7010

7011
	if (work_done < budget) {
7012
		napi_complete(napi);
7013

7014 7015
		rtl_irq_enable(tp, enable_mask);
		mmiowb();
L
Linus Torvalds 已提交
7016 7017
	}

7018
	return work_done;
L
Linus Torvalds 已提交
7019 7020
}

7021 7022 7023 7024 7025 7026 7027 7028 7029 7030 7031
static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	if (tp->mac_version > RTL_GIGA_MAC_VER_06)
		return;

	dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
	RTL_W32(RxMissed, 0);
}

L
Linus Torvalds 已提交
7032 7033 7034 7035 7036
static void rtl8169_down(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;

7037
	del_timer_sync(&tp->timer);
L
Linus Torvalds 已提交
7038

7039
	napi_disable(&tp->napi);
7040
	netif_stop_queue(dev);
L
Linus Torvalds 已提交
7041

7042
	rtl8169_hw_reset(tp);
S
Stanislaw Gruszka 已提交
7043 7044
	/*
	 * At this point device interrupts can not be enabled in any function,
7045 7046
	 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
	 * and napi is disabled (rtl8169_poll).
S
Stanislaw Gruszka 已提交
7047
	 */
7048
	rtl8169_rx_missed(dev, ioaddr);
L
Linus Torvalds 已提交
7049 7050

	/* Give a racing hard_start_xmit a few cycles to complete. */
7051
	synchronize_sched();
L
Linus Torvalds 已提交
7052 7053 7054 7055

	rtl8169_tx_clear(tp);

	rtl8169_rx_clear(tp);
F
françois romieu 已提交
7056 7057

	rtl_pll_power_down(tp);
L
Linus Torvalds 已提交
7058 7059 7060 7061 7062 7063 7064
}

static int rtl8169_close(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct pci_dev *pdev = tp->pci_dev;

7065 7066
	pm_runtime_get_sync(&pdev->dev);

F
Francois Romieu 已提交
7067
	/* Update counters before going down */
7068 7069
	rtl8169_update_counters(dev);

7070
	rtl_lock_work(tp);
7071
	clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7072

L
Linus Torvalds 已提交
7073
	rtl8169_down(dev);
7074
	rtl_unlock_work(tp);
L
Linus Torvalds 已提交
7075

7076 7077
	cancel_work_sync(&tp->wk.work);

7078
	free_irq(pdev->irq, dev);
L
Linus Torvalds 已提交
7079

7080 7081 7082 7083
	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
			  tp->RxPhyAddr);
	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
			  tp->TxPhyAddr);
L
Linus Torvalds 已提交
7084 7085 7086
	tp->TxDescArray = NULL;
	tp->RxDescArray = NULL;

7087 7088
	pm_runtime_put_sync(&pdev->dev);

L
Linus Torvalds 已提交
7089 7090 7091
	return 0;
}

7092 7093 7094 7095 7096 7097 7098 7099 7100
#ifdef CONFIG_NET_POLL_CONTROLLER
static void rtl8169_netpoll(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl8169_interrupt(tp->pci_dev->irq, dev);
}
#endif

7101 7102 7103 7104 7105 7106 7107 7108 7109 7110
static int rtl_open(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;
	int retval = -ENOMEM;

	pm_runtime_get_sync(&pdev->dev);

	/*
7111
	 * Rx and Tx descriptors needs 256 bytes alignment.
7112 7113 7114 7115 7116 7117 7118 7119 7120 7121 7122 7123 7124 7125 7126 7127 7128 7129 7130 7131 7132 7133
	 * dma_alloc_coherent provides more.
	 */
	tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
					     &tp->TxPhyAddr, GFP_KERNEL);
	if (!tp->TxDescArray)
		goto err_pm_runtime_put;

	tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
					     &tp->RxPhyAddr, GFP_KERNEL);
	if (!tp->RxDescArray)
		goto err_free_tx_0;

	retval = rtl8169_init_ring(dev);
	if (retval < 0)
		goto err_free_rx_1;

	INIT_WORK(&tp->wk.work, rtl_task);

	smp_mb();

	rtl_request_firmware(tp);

7134
	retval = request_irq(pdev->irq, rtl8169_interrupt,
7135 7136 7137 7138 7139 7140 7141 7142 7143 7144 7145 7146 7147 7148 7149 7150 7151 7152 7153 7154 7155 7156 7157 7158 7159 7160 7161 7162 7163 7164 7165 7166 7167 7168 7169 7170 7171 7172 7173 7174 7175 7176 7177 7178 7179 7180
			     (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
			     dev->name, dev);
	if (retval < 0)
		goto err_release_fw_2;

	rtl_lock_work(tp);

	set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);

	napi_enable(&tp->napi);

	rtl8169_init_phy(dev, tp);

	__rtl8169_set_features(dev, dev->features);

	rtl_pll_power_up(tp);

	rtl_hw_start(dev);

	netif_start_queue(dev);

	rtl_unlock_work(tp);

	tp->saved_wolopts = 0;
	pm_runtime_put_noidle(&pdev->dev);

	rtl8169_check_link_status(dev, tp, ioaddr);
out:
	return retval;

err_release_fw_2:
	rtl_release_firmware(tp);
	rtl8169_rx_clear(tp);
err_free_rx_1:
	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
			  tp->RxPhyAddr);
	tp->RxDescArray = NULL;
err_free_tx_0:
	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
			  tp->TxPhyAddr);
	tp->TxDescArray = NULL;
err_pm_runtime_put:
	pm_runtime_put_noidle(&pdev->dev);
	goto out;
}

J
Junchang Wang 已提交
7181 7182
static struct rtnl_link_stats64 *
rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
L
Linus Torvalds 已提交
7183 7184 7185
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
J
Junchang Wang 已提交
7186
	unsigned int start;
L
Linus Torvalds 已提交
7187

7188
	if (netif_running(dev))
7189
		rtl8169_rx_missed(dev, ioaddr);
7190

J
Junchang Wang 已提交
7191
	do {
7192
		start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
J
Junchang Wang 已提交
7193 7194
		stats->rx_packets = tp->rx_stats.packets;
		stats->rx_bytes	= tp->rx_stats.bytes;
7195
	} while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
J
Junchang Wang 已提交
7196 7197 7198


	do {
7199
		start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
J
Junchang Wang 已提交
7200 7201
		stats->tx_packets = tp->tx_stats.packets;
		stats->tx_bytes	= tp->tx_stats.bytes;
7202
	} while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
J
Junchang Wang 已提交
7203 7204 7205 7206 7207 7208 7209 7210 7211 7212

	stats->rx_dropped	= dev->stats.rx_dropped;
	stats->tx_dropped	= dev->stats.tx_dropped;
	stats->rx_length_errors = dev->stats.rx_length_errors;
	stats->rx_errors	= dev->stats.rx_errors;
	stats->rx_crc_errors	= dev->stats.rx_crc_errors;
	stats->rx_fifo_errors	= dev->stats.rx_fifo_errors;
	stats->rx_missed_errors = dev->stats.rx_missed_errors;

	return stats;
L
Linus Torvalds 已提交
7213 7214
}

7215
static void rtl8169_net_suspend(struct net_device *dev)
7216
{
F
françois romieu 已提交
7217 7218
	struct rtl8169_private *tp = netdev_priv(dev);

7219
	if (!netif_running(dev))
7220
		return;
7221 7222 7223

	netif_device_detach(dev);
	netif_stop_queue(dev);
7224 7225 7226

	rtl_lock_work(tp);
	napi_disable(&tp->napi);
7227
	clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7228 7229 7230
	rtl_unlock_work(tp);

	rtl_pll_power_down(tp);
7231 7232 7233 7234 7235 7236 7237 7238
}

#ifdef CONFIG_PM

static int rtl8169_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct net_device *dev = pci_get_drvdata(pdev);
7239

7240
	rtl8169_net_suspend(dev);
7241

7242 7243 7244
	return 0;
}

7245 7246
static void __rtl8169_resume(struct net_device *dev)
{
F
françois romieu 已提交
7247 7248
	struct rtl8169_private *tp = netdev_priv(dev);

7249
	netif_device_attach(dev);
F
françois romieu 已提交
7250 7251 7252

	rtl_pll_power_up(tp);

A
Artem Savkov 已提交
7253 7254
	rtl_lock_work(tp);
	napi_enable(&tp->napi);
7255
	set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
A
Artem Savkov 已提交
7256
	rtl_unlock_work(tp);
7257

7258
	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7259 7260
}

7261
static int rtl8169_resume(struct device *device)
7262
{
7263
	struct pci_dev *pdev = to_pci_dev(device);
7264
	struct net_device *dev = pci_get_drvdata(pdev);
S
Stanislaw Gruszka 已提交
7265 7266 7267
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl8169_init_phy(dev, tp);
7268

7269 7270
	if (netif_running(dev))
		__rtl8169_resume(dev);
7271

7272 7273 7274 7275 7276 7277 7278 7279 7280 7281 7282 7283
	return 0;
}

static int rtl8169_runtime_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct net_device *dev = pci_get_drvdata(pdev);
	struct rtl8169_private *tp = netdev_priv(dev);

	if (!tp->TxDescArray)
		return 0;

7284
	rtl_lock_work(tp);
7285 7286
	tp->saved_wolopts = __rtl8169_get_wol(tp);
	__rtl8169_set_wol(tp, WAKE_ANY);
7287
	rtl_unlock_work(tp);
7288 7289 7290 7291 7292 7293 7294 7295 7296 7297 7298 7299 7300 7301 7302

	rtl8169_net_suspend(dev);

	return 0;
}

static int rtl8169_runtime_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct net_device *dev = pci_get_drvdata(pdev);
	struct rtl8169_private *tp = netdev_priv(dev);

	if (!tp->TxDescArray)
		return 0;

7303
	rtl_lock_work(tp);
7304 7305
	__rtl8169_set_wol(tp, tp->saved_wolopts);
	tp->saved_wolopts = 0;
7306
	rtl_unlock_work(tp);
7307

S
Stanislaw Gruszka 已提交
7308 7309
	rtl8169_init_phy(dev, tp);

7310
	__rtl8169_resume(dev);
7311 7312 7313 7314

	return 0;
}

7315 7316 7317 7318 7319 7320
static int rtl8169_runtime_idle(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct net_device *dev = pci_get_drvdata(pdev);
	struct rtl8169_private *tp = netdev_priv(dev);

7321
	return tp->TxDescArray ? -EBUSY : 0;
7322 7323
}

7324
static const struct dev_pm_ops rtl8169_pm_ops = {
F
Francois Romieu 已提交
7325 7326 7327 7328 7329 7330 7331 7332 7333
	.suspend		= rtl8169_suspend,
	.resume			= rtl8169_resume,
	.freeze			= rtl8169_suspend,
	.thaw			= rtl8169_resume,
	.poweroff		= rtl8169_suspend,
	.restore		= rtl8169_resume,
	.runtime_suspend	= rtl8169_runtime_suspend,
	.runtime_resume		= rtl8169_runtime_resume,
	.runtime_idle		= rtl8169_runtime_idle,
7334 7335 7336 7337 7338 7339 7340 7341 7342 7343
};

#define RTL8169_PM_OPS	(&rtl8169_pm_ops)

#else /* !CONFIG_PM */

#define RTL8169_PM_OPS	NULL

#endif /* !CONFIG_PM */

7344 7345 7346 7347 7348 7349 7350 7351 7352 7353 7354 7355 7356 7357 7358 7359 7360 7361 7362 7363
static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	/* WoL fails with 8168b when the receiver is disabled. */
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_11:
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
		pci_clear_master(tp->pci_dev);

		RTL_W8(ChipCmd, CmdRxEnb);
		/* PCI commit */
		RTL_R8(ChipCmd);
		break;
	default:
		break;
	}
}

F
Francois Romieu 已提交
7364 7365
static void rtl_shutdown(struct pci_dev *pdev)
{
7366
	struct net_device *dev = pci_get_drvdata(pdev);
7367
	struct rtl8169_private *tp = netdev_priv(dev);
7368 7369 7370
	struct device *d = &pdev->dev;

	pm_runtime_get_sync(d);
7371 7372

	rtl8169_net_suspend(dev);
F
Francois Romieu 已提交
7373

F
Francois Romieu 已提交
7374
	/* Restore original MAC address */
7375 7376
	rtl_rar_set(tp, dev->perm_addr);

7377
	rtl8169_hw_reset(tp);
7378

7379
	if (system_state == SYSTEM_POWER_OFF) {
7380 7381 7382
		if (__rtl8169_get_wol(tp) & WAKE_ANY) {
			rtl_wol_suspend_quirk(tp);
			rtl_wol_shutdown_quirk(tp);
7383 7384
		}

7385 7386 7387
		pci_wake_from_d3(pdev, true);
		pci_set_power_state(pdev, PCI_D3hot);
	}
7388 7389

	pm_runtime_put_noidle(d);
7390
}
7391

B
Bill Pemberton 已提交
7392
static void rtl_remove_one(struct pci_dev *pdev)
7393 7394 7395 7396 7397 7398 7399 7400 7401 7402
{
	struct net_device *dev = pci_get_drvdata(pdev);
	struct rtl8169_private *tp = netdev_priv(dev);

	if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_28 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_31) {
		rtl8168_driver_stop(tp);
	}

7403 7404
	netif_napi_del(&tp->napi);

7405 7406 7407 7408 7409 7410 7411 7412 7413 7414 7415 7416 7417 7418
	unregister_netdev(dev);

	rtl_release_firmware(tp);

	if (pci_dev_run_wake(pdev))
		pm_runtime_get_noresume(&pdev->dev);

	/* restore original MAC address */
	rtl_rar_set(tp, dev->perm_addr);

	rtl_disable_msi(pdev, tp);
	rtl8169_release_board(pdev, dev, tp->mmio_addr);
}

7419
static const struct net_device_ops rtl_netdev_ops = {
7420
	.ndo_open		= rtl_open,
7421 7422 7423 7424 7425 7426 7427 7428 7429 7430 7431 7432 7433 7434 7435 7436 7437
	.ndo_stop		= rtl8169_close,
	.ndo_get_stats64	= rtl8169_get_stats64,
	.ndo_start_xmit		= rtl8169_start_xmit,
	.ndo_tx_timeout		= rtl8169_tx_timeout,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_change_mtu		= rtl8169_change_mtu,
	.ndo_fix_features	= rtl8169_fix_features,
	.ndo_set_features	= rtl8169_set_features,
	.ndo_set_mac_address	= rtl_set_mac_address,
	.ndo_do_ioctl		= rtl8169_ioctl,
	.ndo_set_rx_mode	= rtl_set_rx_mode,
#ifdef CONFIG_NET_POLL_CONTROLLER
	.ndo_poll_controller	= rtl8169_netpoll,
#endif

};

7438 7439 7440 7441 7442 7443 7444 7445 7446 7447 7448 7449 7450 7451 7452 7453 7454 7455 7456 7457 7458 7459 7460 7461 7462 7463 7464 7465 7466 7467 7468 7469 7470 7471 7472 7473 7474 7475 7476 7477 7478 7479 7480 7481 7482 7483 7484 7485 7486 7487 7488 7489 7490 7491 7492 7493 7494
static const struct rtl_cfg_info {
	void (*hw_start)(struct net_device *);
	unsigned int region;
	unsigned int align;
	u16 event_slow;
	unsigned features;
	u8 default_ver;
} rtl_cfg_infos [] = {
	[RTL_CFG_0] = {
		.hw_start	= rtl_hw_start_8169,
		.region		= 1,
		.align		= 0,
		.event_slow	= SYSErr | LinkChg | RxOverflow | RxFIFOOver,
		.features	= RTL_FEATURE_GMII,
		.default_ver	= RTL_GIGA_MAC_VER_01,
	},
	[RTL_CFG_1] = {
		.hw_start	= rtl_hw_start_8168,
		.region		= 2,
		.align		= 8,
		.event_slow	= SYSErr | LinkChg | RxOverflow,
		.features	= RTL_FEATURE_GMII | RTL_FEATURE_MSI,
		.default_ver	= RTL_GIGA_MAC_VER_11,
	},
	[RTL_CFG_2] = {
		.hw_start	= rtl_hw_start_8101,
		.region		= 2,
		.align		= 8,
		.event_slow	= SYSErr | LinkChg | RxOverflow | RxFIFOOver |
				  PCSTimeout,
		.features	= RTL_FEATURE_MSI,
		.default_ver	= RTL_GIGA_MAC_VER_13,
	}
};

/* Cfg9346_Unlock assumed. */
static unsigned rtl_try_msi(struct rtl8169_private *tp,
			    const struct rtl_cfg_info *cfg)
{
	void __iomem *ioaddr = tp->mmio_addr;
	unsigned msi = 0;
	u8 cfg2;

	cfg2 = RTL_R8(Config2) & ~MSIEnable;
	if (cfg->features & RTL_FEATURE_MSI) {
		if (pci_enable_msi(tp->pci_dev)) {
			netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
		} else {
			cfg2 |= MSIEnable;
			msi = RTL_FEATURE_MSI;
		}
	}
	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
		RTL_W8(Config2, cfg2);
	return msi;
}

H
Hayes Wang 已提交
7495 7496 7497 7498 7499 7500 7501 7502 7503 7504 7505 7506 7507 7508
DECLARE_RTL_COND(rtl_link_list_ready_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R8(MCU) & LINK_LIST_RDY;
}

DECLARE_RTL_COND(rtl_rxtx_empty_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
}

B
Bill Pemberton 已提交
7509
static void rtl_hw_init_8168g(struct rtl8169_private *tp)
H
Hayes Wang 已提交
7510 7511 7512 7513 7514 7515 7516 7517 7518 7519 7520 7521 7522 7523 7524 7525 7526 7527
{
	void __iomem *ioaddr = tp->mmio_addr;
	u32 data;

	tp->ocp_base = OCP_STD_PHY_BASE;

	RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);

	if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
		return;

	if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
		return;

	RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
	msleep(1);
	RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);

7528
	data = r8168_mac_ocp_read(tp, 0xe8de);
H
Hayes Wang 已提交
7529 7530 7531 7532 7533 7534
	data &= ~(1 << 14);
	r8168_mac_ocp_write(tp, 0xe8de, data);

	if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
		return;

7535
	data = r8168_mac_ocp_read(tp, 0xe8de);
H
Hayes Wang 已提交
7536 7537 7538 7539 7540 7541 7542
	data |= (1 << 15);
	r8168_mac_ocp_write(tp, 0xe8de, data);

	if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
		return;
}

B
Bill Pemberton 已提交
7543
static void rtl_hw_initialize(struct rtl8169_private *tp)
H
Hayes Wang 已提交
7544 7545 7546 7547
{
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
H
hayeswang 已提交
7548
	case RTL_GIGA_MAC_VER_42:
H
hayeswang 已提交
7549
	case RTL_GIGA_MAC_VER_43:
H
hayeswang 已提交
7550
	case RTL_GIGA_MAC_VER_44:
7551 7552 7553 7554
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
H
Hayes Wang 已提交
7555 7556 7557 7558 7559 7560 7561 7562
		rtl_hw_init_8168g(tp);
		break;

	default:
		break;
	}
}

H
hayeswang 已提交
7563
static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7564 7565 7566 7567 7568 7569 7570 7571 7572 7573 7574 7575 7576 7577 7578 7579 7580 7581 7582 7583 7584 7585
{
	const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
	const unsigned int region = cfg->region;
	struct rtl8169_private *tp;
	struct mii_if_info *mii;
	struct net_device *dev;
	void __iomem *ioaddr;
	int chipset, i;
	int rc;

	if (netif_msg_drv(&debug)) {
		printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
		       MODULENAME, RTL8169_VERSION);
	}

	dev = alloc_etherdev(sizeof (*tp));
	if (!dev) {
		rc = -ENOMEM;
		goto out;
	}

	SET_NETDEV_DEV(dev, &pdev->dev);
7586
	dev->netdev_ops = &rtl_netdev_ops;
7587 7588 7589 7590 7591 7592 7593 7594 7595 7596 7597 7598 7599 7600 7601 7602 7603 7604 7605 7606 7607 7608 7609 7610 7611 7612 7613 7614 7615 7616 7617 7618 7619 7620 7621 7622 7623 7624 7625 7626 7627 7628 7629 7630 7631 7632 7633 7634 7635 7636 7637
	tp = netdev_priv(dev);
	tp->dev = dev;
	tp->pci_dev = pdev;
	tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);

	mii = &tp->mii;
	mii->dev = dev;
	mii->mdio_read = rtl_mdio_read;
	mii->mdio_write = rtl_mdio_write;
	mii->phy_id_mask = 0x1f;
	mii->reg_num_mask = 0x1f;
	mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);

	/* disable ASPM completely as that cause random device stop working
	 * problems as well as full system hangs for some PCIe devices users */
	pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
				     PCIE_LINK_STATE_CLKPM);

	/* enable device (incl. PCI PM wakeup and hotplug setup) */
	rc = pci_enable_device(pdev);
	if (rc < 0) {
		netif_err(tp, probe, dev, "enable failure\n");
		goto err_out_free_dev_1;
	}

	if (pci_set_mwi(pdev) < 0)
		netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");

	/* make sure PCI base addr 1 is MMIO */
	if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
		netif_err(tp, probe, dev,
			  "region #%d not an MMIO resource, aborting\n",
			  region);
		rc = -ENODEV;
		goto err_out_mwi_2;
	}

	/* check for weird/broken PCI region reporting */
	if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
		netif_err(tp, probe, dev,
			  "Invalid PCI region size(s), aborting\n");
		rc = -ENODEV;
		goto err_out_mwi_2;
	}

	rc = pci_request_regions(pdev, MODULENAME);
	if (rc < 0) {
		netif_err(tp, probe, dev, "could not request regions\n");
		goto err_out_mwi_2;
	}

H
hayeswang 已提交
7638
	tp->cp_cmd = 0;
7639 7640 7641 7642 7643 7644 7645 7646 7647 7648 7649 7650 7651 7652 7653 7654 7655 7656 7657 7658 7659 7660 7661 7662 7663 7664 7665 7666 7667 7668 7669 7670

	if ((sizeof(dma_addr_t) > 4) &&
	    !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
		tp->cp_cmd |= PCIDAC;
		dev->features |= NETIF_F_HIGHDMA;
	} else {
		rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
		if (rc < 0) {
			netif_err(tp, probe, dev, "DMA configuration failed\n");
			goto err_out_free_res_3;
		}
	}

	/* ioremap MMIO region */
	ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
	if (!ioaddr) {
		netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
		rc = -EIO;
		goto err_out_free_res_3;
	}
	tp->mmio_addr = ioaddr;

	if (!pci_is_pcie(pdev))
		netif_info(tp, probe, dev, "not PCI Express\n");

	/* Identify chip attached to board */
	rtl8169_get_mac_version(tp, dev, cfg->default_ver);

	rtl_init_rxcfg(tp);

	rtl_irq_disable(tp);

H
Hayes Wang 已提交
7671 7672
	rtl_hw_initialize(tp);

7673 7674 7675 7676 7677 7678 7679 7680 7681
	rtl_hw_reset(tp);

	rtl_ack_events(tp, 0xffff);

	pci_set_master(pdev);

	rtl_init_mdio_ops(tp);
	rtl_init_pll_power_ops(tp);
	rtl_init_jumbo_ops(tp);
7682
	rtl_init_csi_ops(tp);
7683 7684 7685 7686 7687 7688 7689 7690

	rtl8169_print_mac_version(tp);

	chipset = tp->mac_version;
	tp->txd_version = rtl_chip_infos[chipset].txd_version;

	RTL_W8(Cfg9346, Cfg9346_Unlock);
	RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
7691
	RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
7692
	switch (tp->mac_version) {
7693 7694 7695 7696 7697 7698 7699 7700 7701 7702
	case RTL_GIGA_MAC_VER_34:
	case RTL_GIGA_MAC_VER_35:
	case RTL_GIGA_MAC_VER_36:
	case RTL_GIGA_MAC_VER_37:
	case RTL_GIGA_MAC_VER_38:
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
	case RTL_GIGA_MAC_VER_42:
	case RTL_GIGA_MAC_VER_43:
	case RTL_GIGA_MAC_VER_44:
7703 7704
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
7705 7706
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
7707 7708 7709 7710 7711 7712 7713 7714 7715 7716
		if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
			tp->features |= RTL_FEATURE_WOL;
		if ((RTL_R8(Config3) & LinkUp) != 0)
			tp->features |= RTL_FEATURE_WOL;
		break;
	default:
		if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
			tp->features |= RTL_FEATURE_WOL;
		break;
	}
7717 7718 7719 7720 7721 7722 7723 7724 7725 7726 7727 7728 7729 7730 7731 7732 7733 7734 7735 7736 7737 7738
	if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
		tp->features |= RTL_FEATURE_WOL;
	tp->features |= rtl_try_msi(tp, cfg);
	RTL_W8(Cfg9346, Cfg9346_Lock);

	if (rtl_tbi_enabled(tp)) {
		tp->set_speed = rtl8169_set_speed_tbi;
		tp->get_settings = rtl8169_gset_tbi;
		tp->phy_reset_enable = rtl8169_tbi_reset_enable;
		tp->phy_reset_pending = rtl8169_tbi_reset_pending;
		tp->link_ok = rtl8169_tbi_link_ok;
		tp->do_ioctl = rtl_tbi_ioctl;
	} else {
		tp->set_speed = rtl8169_set_speed_xmii;
		tp->get_settings = rtl8169_gset_xmii;
		tp->phy_reset_enable = rtl8169_xmii_reset_enable;
		tp->phy_reset_pending = rtl8169_xmii_reset_pending;
		tp->link_ok = rtl8169_xmii_link_ok;
		tp->do_ioctl = rtl_xmii_ioctl;
	}

	mutex_init(&tp->wk.mutex);
7739 7740
	u64_stats_init(&tp->rx_stats.syncp);
	u64_stats_init(&tp->tx_stats.syncp);
7741 7742

	/* Get MAC address */
7743 7744 7745 7746 7747 7748 7749 7750 7751 7752
	if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_38 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_42 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_43 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_44 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_45 ||
7753 7754 7755 7756 7757
	    tp->mac_version == RTL_GIGA_MAC_VER_46 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_47 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_48) {
		u16 mac_addr[3];

7758 7759
		*(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
		*(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7760 7761 7762 7763

		if (is_valid_ether_addr((u8 *)mac_addr))
			rtl_rar_set(tp, (u8 *)mac_addr);
	}
7764 7765 7766
	for (i = 0; i < ETH_ALEN; i++)
		dev->dev_addr[i] = RTL_R8(MAC0 + i);

7767
	dev->ethtool_ops = &rtl8169_ethtool_ops;
7768 7769 7770 7771 7772 7773 7774
	dev->watchdog_timeo = RTL8169_TX_TIMEOUT;

	netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);

	/* don't enable SG, IP_CSUM and TSO by default - it might not work
	 * properly for all devices */
	dev->features |= NETIF_F_RXCSUM |
7775
		NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7776 7777

	dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7778 7779
		NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
		NETIF_F_HW_VLAN_CTAG_RX;
7780 7781 7782
	dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
		NETIF_F_HIGHDMA;

H
hayeswang 已提交
7783 7784 7785 7786 7787 7788
	tp->cp_cmd |= RxChkSum | RxVlan;

	/*
	 * Pretend we are using VLANs; This bypasses a nasty bug where
	 * Interrupts stop flowing on high load on 8110SCd controllers.
	 */
7789
	if (tp->mac_version == RTL_GIGA_MAC_VER_05)
H
hayeswang 已提交
7790
		/* Disallow toggling */
7791
		dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7792

H
hayeswang 已提交
7793 7794
	if (tp->txd_version == RTL_TD_0)
		tp->tso_csum = rtl8169_tso_csum_v1;
H
hayeswang 已提交
7795
	else if (tp->txd_version == RTL_TD_1) {
H
hayeswang 已提交
7796
		tp->tso_csum = rtl8169_tso_csum_v2;
H
hayeswang 已提交
7797 7798
		dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
	} else
H
hayeswang 已提交
7799 7800
		WARN_ON_ONCE(1);

7801 7802 7803 7804 7805 7806 7807 7808 7809 7810 7811 7812 7813 7814 7815 7816 7817 7818 7819 7820 7821
	dev->hw_features |= NETIF_F_RXALL;
	dev->hw_features |= NETIF_F_RXFCS;

	tp->hw_start = cfg->hw_start;
	tp->event_slow = cfg->event_slow;

	tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
		~(RxBOVF | RxFOVF) : ~0;

	init_timer(&tp->timer);
	tp->timer.data = (unsigned long) dev;
	tp->timer.function = rtl8169_phy_timer;

	tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;

	rc = register_netdev(dev);
	if (rc < 0)
		goto err_out_msi_4;

	pci_set_drvdata(pdev, dev);

7822 7823 7824
	netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
		   rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
		   (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
7825 7826 7827 7828 7829 7830 7831 7832 7833 7834 7835 7836 7837 7838 7839 7840 7841 7842 7843 7844 7845 7846 7847 7848
	if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
		netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
			   "tx checksumming: %s]\n",
			   rtl_chip_infos[chipset].jumbo_max,
			   rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
	}

	if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_28 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_31) {
		rtl8168_driver_start(tp);
	}

	device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);

	if (pci_dev_run_wake(pdev))
		pm_runtime_put_noidle(&pdev->dev);

	netif_carrier_off(dev);

out:
	return rc;

err_out_msi_4:
7849
	netif_napi_del(&tp->napi);
7850 7851 7852 7853 7854 7855 7856 7857 7858 7859 7860 7861
	rtl_disable_msi(pdev, tp);
	iounmap(ioaddr);
err_out_free_res_3:
	pci_release_regions(pdev);
err_out_mwi_2:
	pci_clear_mwi(pdev);
	pci_disable_device(pdev);
err_out_free_dev_1:
	free_netdev(dev);
	goto out;
}

L
Linus Torvalds 已提交
7862 7863 7864
static struct pci_driver rtl8169_pci_driver = {
	.name		= MODULENAME,
	.id_table	= rtl8169_pci_tbl,
7865
	.probe		= rtl_init_one,
B
Bill Pemberton 已提交
7866
	.remove		= rtl_remove_one,
F
Francois Romieu 已提交
7867
	.shutdown	= rtl_shutdown,
7868
	.driver.pm	= RTL8169_PM_OPS,
L
Linus Torvalds 已提交
7869 7870
};

7871
module_pci_driver(rtl8169_pci_driver);