r8169.c 150.4 KB
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/*
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 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
 *
 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
 * Copyright (c) a lot of people too. Please respect their work.
 *
 * See MAINTAINERS file for support contact information.
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 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/if_vlan.h>
#include <linux/crc32.h>
#include <linux/in.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/pm_runtime.h>
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#include <linux/firmware.h>
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#include <linux/pci-aspm.h>
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#include <linux/prefetch.h>
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#include <asm/system.h>
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#include <asm/io.h>
#include <asm/irq.h>

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#define RTL8169_VERSION "2.3LK-NAPI"
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#define MODULENAME "r8169"
#define PFX MODULENAME ": "

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#define FIRMWARE_8168D_1	"rtl_nic/rtl8168d-1.fw"
#define FIRMWARE_8168D_2	"rtl_nic/rtl8168d-2.fw"
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#define FIRMWARE_8168E_1	"rtl_nic/rtl8168e-1.fw"
#define FIRMWARE_8168E_2	"rtl_nic/rtl8168e-2.fw"
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#define FIRMWARE_8168E_3	"rtl_nic/rtl8168e-3.fw"
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#define FIRMWARE_8168F_1	"rtl_nic/rtl8168f-1.fw"
#define FIRMWARE_8168F_2	"rtl_nic/rtl8168f-2.fw"
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#define FIRMWARE_8105E_1	"rtl_nic/rtl8105e-1.fw"
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#ifdef RTL8169_DEBUG
#define assert(expr) \
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	if (!(expr)) {					\
		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\
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		#expr,__FILE__,__func__,__LINE__);		\
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	}
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#define dprintk(fmt, args...) \
	do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
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#else
#define assert(expr) do {} while (0)
#define dprintk(fmt, args...)	do {} while (0)
#endif /* RTL8169_DEBUG */

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#define R8169_MSG_DEFAULT \
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	(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
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#define TX_BUFFS_AVAIL(tp) \
	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
   The RTL chips use a 64 element hash table based on the Ethernet CRC. */
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static const int multicast_filter_limit = 32;
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#define MAX_READ_REQUEST_SHIFT	12
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#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */
#define SafeMtu		0x1c20	/* ... actually life sucks beyond ~7k */
#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */

#define R8169_REGS_SIZE		256
#define R8169_NAPI_WEIGHT	64
#define NUM_TX_DESC	64	/* Number of Tx descriptor registers */
#define NUM_RX_DESC	256	/* Number of Rx descriptor registers */
#define RX_BUF_SIZE	1536	/* Rx Buffer size */
#define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))
#define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))

#define RTL8169_TX_TIMEOUT	(6*HZ)
#define RTL8169_PHY_TIMEOUT	(10*HZ)

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#define RTL_EEPROM_SIG		cpu_to_le32(0x8129)
#define RTL_EEPROM_SIG_MASK	cpu_to_le32(0xffff)
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#define RTL_EEPROM_SIG_ADDR	0x0000

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/* write/read MMIO register */
#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))
#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))
#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))
#define RTL_R8(reg)		readb (ioaddr + (reg))
#define RTL_R16(reg)		readw (ioaddr + (reg))
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#define RTL_R32(reg)		readl (ioaddr + (reg))
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enum mac_version {
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	RTL_GIGA_MAC_VER_01 = 0,
	RTL_GIGA_MAC_VER_02,
	RTL_GIGA_MAC_VER_03,
	RTL_GIGA_MAC_VER_04,
	RTL_GIGA_MAC_VER_05,
	RTL_GIGA_MAC_VER_06,
	RTL_GIGA_MAC_VER_07,
	RTL_GIGA_MAC_VER_08,
	RTL_GIGA_MAC_VER_09,
	RTL_GIGA_MAC_VER_10,
	RTL_GIGA_MAC_VER_11,
	RTL_GIGA_MAC_VER_12,
	RTL_GIGA_MAC_VER_13,
	RTL_GIGA_MAC_VER_14,
	RTL_GIGA_MAC_VER_15,
	RTL_GIGA_MAC_VER_16,
	RTL_GIGA_MAC_VER_17,
	RTL_GIGA_MAC_VER_18,
	RTL_GIGA_MAC_VER_19,
	RTL_GIGA_MAC_VER_20,
	RTL_GIGA_MAC_VER_21,
	RTL_GIGA_MAC_VER_22,
	RTL_GIGA_MAC_VER_23,
	RTL_GIGA_MAC_VER_24,
	RTL_GIGA_MAC_VER_25,
	RTL_GIGA_MAC_VER_26,
	RTL_GIGA_MAC_VER_27,
	RTL_GIGA_MAC_VER_28,
	RTL_GIGA_MAC_VER_29,
	RTL_GIGA_MAC_VER_30,
	RTL_GIGA_MAC_VER_31,
	RTL_GIGA_MAC_VER_32,
	RTL_GIGA_MAC_VER_33,
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	RTL_GIGA_MAC_VER_34,
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	RTL_GIGA_MAC_VER_35,
	RTL_GIGA_MAC_VER_36,
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	RTL_GIGA_MAC_NONE   = 0xff,
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};

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enum rtl_tx_desc_version {
	RTL_TD_0	= 0,
	RTL_TD_1	= 1,
};

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#define JUMBO_1K	ETH_DATA_LEN
#define JUMBO_4K	(4*1024 - ETH_HLEN - 2)
#define JUMBO_6K	(6*1024 - ETH_HLEN - 2)
#define JUMBO_7K	(7*1024 - ETH_HLEN - 2)
#define JUMBO_9K	(9*1024 - ETH_HLEN - 2)

#define _R(NAME,TD,FW,SZ,B) {	\
	.name = NAME,		\
	.txd_version = TD,	\
	.fw_name = FW,		\
	.jumbo_max = SZ,	\
	.jumbo_tx_csum = B	\
}
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static const struct {
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	const char *name;
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	enum rtl_tx_desc_version txd_version;
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	const char *fw_name;
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	u16 jumbo_max;
	bool jumbo_tx_csum;
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} rtl_chip_infos[] = {
	/* PCI devices. */
	[RTL_GIGA_MAC_VER_01] =
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		_R("RTL8169",		RTL_TD_0, NULL, JUMBO_7K, true),
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	[RTL_GIGA_MAC_VER_02] =
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		_R("RTL8169s",		RTL_TD_0, NULL, JUMBO_7K, true),
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	[RTL_GIGA_MAC_VER_03] =
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		_R("RTL8110s",		RTL_TD_0, NULL, JUMBO_7K, true),
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	[RTL_GIGA_MAC_VER_04] =
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		_R("RTL8169sb/8110sb",	RTL_TD_0, NULL, JUMBO_7K, true),
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	[RTL_GIGA_MAC_VER_05] =
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		_R("RTL8169sc/8110sc",	RTL_TD_0, NULL, JUMBO_7K, true),
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	[RTL_GIGA_MAC_VER_06] =
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		_R("RTL8169sc/8110sc",	RTL_TD_0, NULL, JUMBO_7K, true),
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	/* PCI-E devices. */
	[RTL_GIGA_MAC_VER_07] =
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		_R("RTL8102e",		RTL_TD_1, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_08] =
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		_R("RTL8102e",		RTL_TD_1, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_09] =
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		_R("RTL8102e",		RTL_TD_1, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_10] =
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		_R("RTL8101e",		RTL_TD_0, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_11] =
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		_R("RTL8168b/8111b",	RTL_TD_0, NULL, JUMBO_4K, false),
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	[RTL_GIGA_MAC_VER_12] =
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		_R("RTL8168b/8111b",	RTL_TD_0, NULL, JUMBO_4K, false),
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	[RTL_GIGA_MAC_VER_13] =
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		_R("RTL8101e",		RTL_TD_0, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_14] =
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		_R("RTL8100e",		RTL_TD_0, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_15] =
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		_R("RTL8100e",		RTL_TD_0, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_16] =
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		_R("RTL8101e",		RTL_TD_0, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_17] =
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		_R("RTL8168b/8111b",	RTL_TD_1, NULL, JUMBO_4K, false),
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	[RTL_GIGA_MAC_VER_18] =
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		_R("RTL8168cp/8111cp",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_19] =
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		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_20] =
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		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_21] =
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		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_22] =
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		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_23] =
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		_R("RTL8168cp/8111cp",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_24] =
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		_R("RTL8168cp/8111cp",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_25] =
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		_R("RTL8168d/8111d",	RTL_TD_1, FIRMWARE_8168D_1,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_26] =
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		_R("RTL8168d/8111d",	RTL_TD_1, FIRMWARE_8168D_2,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_27] =
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		_R("RTL8168dp/8111dp",	RTL_TD_1, NULL, JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_28] =
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		_R("RTL8168dp/8111dp",	RTL_TD_1, NULL, JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_29] =
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		_R("RTL8105e",		RTL_TD_1, FIRMWARE_8105E_1,
							JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_30] =
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		_R("RTL8105e",		RTL_TD_1, FIRMWARE_8105E_1,
							JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_31] =
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		_R("RTL8168dp/8111dp",	RTL_TD_1, NULL, JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_32] =
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		_R("RTL8168e/8111e",	RTL_TD_1, FIRMWARE_8168E_1,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_33] =
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		_R("RTL8168e/8111e",	RTL_TD_1, FIRMWARE_8168E_2,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_34] =
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		_R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_35] =
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		_R("RTL8168f/8111f",	RTL_TD_1, FIRMWARE_8168F_1,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_36] =
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		_R("RTL8168f/8111f",	RTL_TD_1, FIRMWARE_8168F_2,
							JUMBO_9K, false),
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};
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#undef _R
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enum cfg_version {
	RTL_CFG_0 = 0x00,
	RTL_CFG_1,
	RTL_CFG_2
};

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static void rtl_hw_start_8169(struct net_device *);
static void rtl_hw_start_8168(struct net_device *);
static void rtl_hw_start_8101(struct net_device *);

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static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_2 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_0 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_1 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },
	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4302), 0, 0, RTL_CFG_0 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_AT,		0xc107), 0, 0, RTL_CFG_0 },
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	{ PCI_DEVICE(0x16ec,			0x0116), 0, 0, RTL_CFG_0 },
	{ PCI_VENDOR_ID_LINKSYS,		0x1032,
		PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
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	{ 0x0001,				0x8168,
		PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
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	{0,},
};

MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);

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static int rx_buf_sz = 16383;
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static int use_dac;
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static struct {
	u32 msg_enable;
} debug = { -1 };
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enum rtl_registers {
	MAC0		= 0,	/* Ethernet hardware address. */
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	MAC4		= 4,
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	MAR0		= 8,	/* Multicast filter. */
	CounterAddrLow		= 0x10,
	CounterAddrHigh		= 0x14,
	TxDescStartAddrLow	= 0x20,
	TxDescStartAddrHigh	= 0x24,
	TxHDescStartAddrLow	= 0x28,
	TxHDescStartAddrHigh	= 0x2c,
	FLASH		= 0x30,
	ERSR		= 0x36,
	ChipCmd		= 0x37,
	TxPoll		= 0x38,
	IntrMask	= 0x3c,
	IntrStatus	= 0x3e,
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	TxConfig	= 0x40,
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#define	TXCFG_AUTO_FIFO			(1 << 7)	/* 8111e-vl */
#define	TXCFG_EMPTY			(1 << 11)	/* 8111e-vl */
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	RxConfig	= 0x44,
#define	RX128_INT_EN			(1 << 15)	/* 8111c and later */
#define	RX_MULTI_EN			(1 << 14)	/* 8111c only */
#define	RXCFG_FIFO_SHIFT		13
					/* No threshold before first PCI xfer */
#define	RX_FIFO_THRESH			(7 << RXCFG_FIFO_SHIFT)
#define	RXCFG_DMA_SHIFT			8
					/* Unlimited maximum PCI burst. */
#define	RX_DMA_BURST			(7 << RXCFG_DMA_SHIFT)
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	RxMissed	= 0x4c,
	Cfg9346		= 0x50,
	Config0		= 0x51,
	Config1		= 0x52,
	Config2		= 0x53,
	Config3		= 0x54,
	Config4		= 0x55,
	Config5		= 0x56,
	MultiIntr	= 0x5c,
	PHYAR		= 0x60,
	PHYstatus	= 0x6c,
	RxMaxSize	= 0xda,
	CPlusCmd	= 0xe0,
	IntrMitigate	= 0xe2,
	RxDescAddrLow	= 0xe4,
	RxDescAddrHigh	= 0xe8,
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	EarlyTxThres	= 0xec,	/* 8169. Unit of 32 bytes. */

#define NoEarlyTx	0x3f	/* Max value : no early transmit. */

	MaxTxPacketSize	= 0xec,	/* 8101/8168. Unit of 128 bytes. */

#define TxPacketMax	(8064 >> 7)
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#define EarlySize	0x27
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	FuncEvent	= 0xf0,
	FuncEventMask	= 0xf4,
	FuncPresetState	= 0xf8,
	FuncForceEvent	= 0xfc,
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};

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enum rtl8110_registers {
	TBICSR			= 0x64,
	TBI_ANAR		= 0x68,
	TBI_LPAR		= 0x6a,
};

enum rtl8168_8101_registers {
	CSIDR			= 0x64,
	CSIAR			= 0x68,
#define	CSIAR_FLAG			0x80000000
#define	CSIAR_WRITE_CMD			0x80000000
#define	CSIAR_BYTE_ENABLE		0x0f
#define	CSIAR_BYTE_ENABLE_SHIFT		12
#define	CSIAR_ADDR_MASK			0x0fff
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	PMCH			= 0x6f,
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	EPHYAR			= 0x80,
#define	EPHYAR_FLAG			0x80000000
#define	EPHYAR_WRITE_CMD		0x80000000
#define	EPHYAR_REG_MASK			0x1f
#define	EPHYAR_REG_SHIFT		16
#define	EPHYAR_DATA_MASK		0xffff
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	DLLPR			= 0xd0,
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#define	PFM_EN				(1 << 6)
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	DBG_REG			= 0xd1,
#define	FIX_NAK_1			(1 << 4)
#define	FIX_NAK_2			(1 << 3)
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	TWSI			= 0xd2,
	MCU			= 0xd3,
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#define	NOW_IS_OOB			(1 << 7)
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#define	EN_NDP				(1 << 3)
#define	EN_OOB_RESET			(1 << 2)
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	EFUSEAR			= 0xdc,
#define	EFUSEAR_FLAG			0x80000000
#define	EFUSEAR_WRITE_CMD		0x80000000
#define	EFUSEAR_READ_CMD		0x00000000
#define	EFUSEAR_REG_MASK		0x03ff
#define	EFUSEAR_REG_SHIFT		8
#define	EFUSEAR_DATA_MASK		0xff
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};

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enum rtl8168_registers {
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	LED_FREQ		= 0x1a,
	EEE_LED			= 0x1b,
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	ERIDR			= 0x70,
	ERIAR			= 0x74,
#define ERIAR_FLAG			0x80000000
#define ERIAR_WRITE_CMD			0x80000000
#define ERIAR_READ_CMD			0x00000000
#define ERIAR_ADDR_BYTE_ALIGN		4
#define ERIAR_TYPE_SHIFT		16
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#define ERIAR_EXGMAC			(0x00 << ERIAR_TYPE_SHIFT)
#define ERIAR_MSIX			(0x01 << ERIAR_TYPE_SHIFT)
#define ERIAR_ASF			(0x02 << ERIAR_TYPE_SHIFT)
#define ERIAR_MASK_SHIFT		12
#define ERIAR_MASK_0001			(0x1 << ERIAR_MASK_SHIFT)
#define ERIAR_MASK_0011			(0x3 << ERIAR_MASK_SHIFT)
#define ERIAR_MASK_1111			(0xf << ERIAR_MASK_SHIFT)
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	EPHY_RXER_NUM		= 0x7c,
	OCPDR			= 0xb0,	/* OCP GPHY access */
#define OCPDR_WRITE_CMD			0x80000000
#define OCPDR_READ_CMD			0x00000000
#define OCPDR_REG_MASK			0x7f
#define OCPDR_GPHY_REG_SHIFT		16
#define OCPDR_DATA_MASK			0xffff
	OCPAR			= 0xb4,
#define OCPAR_FLAG			0x80000000
#define OCPAR_GPHY_WRITE_CMD		0x8000f060
#define OCPAR_GPHY_READ_CMD		0x0000f060
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	RDSAR1			= 0xd0,	/* 8168c only. Undocumented on 8168dp */
	MISC			= 0xf0,	/* 8168e only. */
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#define TXPLA_RST			(1 << 29)
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#define PWM_EN				(1 << 22)
421 422
};

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enum rtl_register_content {
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	/* InterruptStatusBits */
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	SYSErr		= 0x8000,
	PCSTimeout	= 0x4000,
	SWInt		= 0x0100,
	TxDescUnavail	= 0x0080,
	RxFIFOOver	= 0x0040,
	LinkChg		= 0x0020,
	RxOverflow	= 0x0010,
	TxErr		= 0x0008,
	TxOK		= 0x0004,
	RxErr		= 0x0002,
	RxOK		= 0x0001,
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	/* RxStatusDesc */
438
	RxBOVF	= (1 << 24),
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	RxFOVF	= (1 << 23),
	RxRWT	= (1 << 22),
	RxRES	= (1 << 21),
	RxRUNT	= (1 << 20),
	RxCRC	= (1 << 19),
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	/* ChipCmdBits */
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	StopReq		= 0x80,
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	CmdReset	= 0x10,
	CmdRxEnb	= 0x08,
	CmdTxEnb	= 0x04,
	RxBufEmpty	= 0x01,
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	/* TXPoll register p.5 */
	HPQ		= 0x80,		/* Poll cmd on the high prio queue */
	NPQ		= 0x40,		/* Poll cmd on the low prio queue */
	FSWInt		= 0x01,		/* Forced software interrupt */

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	/* Cfg9346Bits */
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	Cfg9346_Lock	= 0x00,
	Cfg9346_Unlock	= 0xc0,
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	/* rx_mode_bits */
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	AcceptErr	= 0x20,
	AcceptRunt	= 0x10,
	AcceptBroadcast	= 0x08,
	AcceptMulticast	= 0x04,
	AcceptMyPhys	= 0x02,
	AcceptAllPhys	= 0x01,
468
#define RX_CONFIG_ACCEPT_MASK		0x3f
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	/* TxConfigBits */
	TxInterFrameGapShift = 24,
	TxDMAShift = 8,	/* DMA burst value (0-7) is shift this many bits */

474
	/* Config1 register p.24 */
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	LEDS1		= (1 << 7),
	LEDS0		= (1 << 6),
	Speed_down	= (1 << 4),
	MEMMAP		= (1 << 3),
	IOMAP		= (1 << 2),
	VPD		= (1 << 1),
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	PMEnable	= (1 << 0),	/* Power Management Enable */

483
	/* Config2 register p. 25 */
484
	MSIEnable	= (1 << 5),	/* 8169 only. Reserved in the 8168. */
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	PCI_Clock_66MHz = 0x01,
	PCI_Clock_33MHz = 0x00,

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	/* Config3 register p.25 */
	MagicPacket	= (1 << 5),	/* Wake up when receives a Magic Packet */
	LinkUp		= (1 << 4),	/* Wake up when the cable connection is re-established */
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	Jumbo_En0	= (1 << 2),	/* 8168 only. Reserved in the 8168b */
492
	Beacon_en	= (1 << 0),	/* 8168 only. Reserved in the 8168b */
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	/* Config4 register */
	Jumbo_En1	= (1 << 1),	/* 8168 only. Reserved in the 8168b */

497
	/* Config5 register p.27 */
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	BWF		= (1 << 6),	/* Accept Broadcast wakeup frame */
	MWF		= (1 << 5),	/* Accept Multicast wakeup frame */
	UWF		= (1 << 4),	/* Accept Unicast wakeup frame */
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	Spi_en		= (1 << 3),
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	LanWake		= (1 << 1),	/* LanWake enable/disable */
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	PMEStatus	= (1 << 0),	/* PME status can be reset by PCI RST# */

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	/* TBICSR p.28 */
	TBIReset	= 0x80000000,
	TBILoopback	= 0x40000000,
	TBINwEnable	= 0x20000000,
	TBINwRestart	= 0x10000000,
	TBILinkOk	= 0x02000000,
	TBINwComplete	= 0x01000000,

	/* CPlusCmd p.31 */
514 515 516 517 518 519 520 521 522 523
	EnableBist	= (1 << 15),	// 8168 8101
	Mac_dbgo_oe	= (1 << 14),	// 8168 8101
	Normal_mode	= (1 << 13),	// unused
	Force_half_dup	= (1 << 12),	// 8168 8101
	Force_rxflow_en	= (1 << 11),	// 8168 8101
	Force_txflow_en	= (1 << 10),	// 8168 8101
	Cxpl_dbg_sel	= (1 << 9),	// 8168 8101
	ASF		= (1 << 8),	// 8168 8101
	PktCntrDisable	= (1 << 7),	// 8168 8101
	Mac_dbgo_sel	= 0x001c,	// 8168
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	RxVlan		= (1 << 6),
	RxChkSum	= (1 << 5),
	PCIDAC		= (1 << 4),
	PCIMulRW	= (1 << 3),
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	INTT_0		= 0x0000,	// 8168
	INTT_1		= 0x0001,	// 8168
	INTT_2		= 0x0002,	// 8168
	INTT_3		= 0x0003,	// 8168
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	/* rtl8169_PHYstatus */
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	TBI_Enable	= 0x80,
	TxFlowCtrl	= 0x40,
	RxFlowCtrl	= 0x20,
	_1000bpsF	= 0x10,
	_100bps		= 0x08,
	_10bps		= 0x04,
	LinkStatus	= 0x02,
	FullDup		= 0x01,
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	/* _TBICSRBit */
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	TBILinkOK	= 0x02000000,
545 546

	/* DumpCounterCommand */
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	CounterDump	= 0x8,
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};

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enum rtl_desc_bit {
	/* First doubleword. */
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	DescOwn		= (1 << 31), /* Descriptor is owned by NIC */
	RingEnd		= (1 << 30), /* End of descriptor ring */
	FirstFrag	= (1 << 29), /* First segment of a packet */
	LastFrag	= (1 << 28), /* Final segment of a packet */
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};

/* Generic case. */
enum rtl_tx_desc_bit {
	/* First doubleword. */
	TD_LSO		= (1 << 27),		/* Large Send Offload */
#define TD_MSS_MAX			0x07ffu	/* MSS value */
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	/* Second doubleword. */
	TxVlanTag	= (1 << 17),		/* Add VLAN tag */
};

/* 8169, 8168b and 810x except 8102e. */
enum rtl_tx_desc_bit_0 {
	/* First doubleword. */
#define TD0_MSS_SHIFT			16	/* MSS position (11 bits) */
	TD0_TCP_CS	= (1 << 16),		/* Calculate TCP/IP checksum */
	TD0_UDP_CS	= (1 << 17),		/* Calculate UDP/IP checksum */
	TD0_IP_CS	= (1 << 18),		/* Calculate IP checksum */
};

/* 8102e, 8168c and beyond. */
enum rtl_tx_desc_bit_1 {
	/* Second doubleword. */
#define TD1_MSS_SHIFT			18	/* MSS position (11 bits) */
	TD1_IP_CS	= (1 << 29),		/* Calculate IP checksum */
	TD1_TCP_CS	= (1 << 30),		/* Calculate TCP/IP checksum */
	TD1_UDP_CS	= (1 << 31),		/* Calculate UDP/IP checksum */
};
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static const struct rtl_tx_desc_info {
	struct {
		u32 udp;
		u32 tcp;
	} checksum;
	u16 mss_shift;
	u16 opts_offset;
} tx_desc_info [] = {
	[RTL_TD_0] = {
		.checksum = {
			.udp	= TD0_IP_CS | TD0_UDP_CS,
			.tcp	= TD0_IP_CS | TD0_TCP_CS
		},
		.mss_shift	= TD0_MSS_SHIFT,
		.opts_offset	= 0
	},
	[RTL_TD_1] = {
		.checksum = {
			.udp	= TD1_IP_CS | TD1_UDP_CS,
			.tcp	= TD1_IP_CS | TD1_TCP_CS
		},
		.mss_shift	= TD1_MSS_SHIFT,
		.opts_offset	= 1
	}
};

enum rtl_rx_desc_bit {
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	/* Rx private */
	PID1		= (1 << 18), /* Protocol ID bit 1/2 */
	PID0		= (1 << 17), /* Protocol ID bit 2/2 */

#define RxProtoUDP	(PID1)
#define RxProtoTCP	(PID0)
#define RxProtoIP	(PID1 | PID0)
#define RxProtoMask	RxProtoIP

	IPFail		= (1 << 16), /* IP checksum failed */
	UDPFail		= (1 << 15), /* UDP/IP checksum failed */
	TCPFail		= (1 << 14), /* TCP/IP checksum failed */
	RxVlanTag	= (1 << 16), /* VLAN tag available */
};

#define RsvdMask	0x3fffc000

struct TxDesc {
631 632 633
	__le32 opts1;
	__le32 opts2;
	__le64 addr;
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};

struct RxDesc {
637 638 639
	__le32 opts1;
	__le32 opts2;
	__le64 addr;
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};

struct ring_info {
	struct sk_buff	*skb;
	u32		len;
	u8		__pad[sizeof(void *) - sizeof(u32)];
};

648
enum features {
649 650 651
	RTL_FEATURE_WOL		= (1 << 0),
	RTL_FEATURE_MSI		= (1 << 1),
	RTL_FEATURE_GMII	= (1 << 2),
652 653
};

654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669
struct rtl8169_counters {
	__le64	tx_packets;
	__le64	rx_packets;
	__le64	tx_errors;
	__le32	rx_errors;
	__le16	rx_missed;
	__le16	align_errors;
	__le32	tx_one_collision;
	__le32	tx_multi_collision;
	__le64	rx_unicast;
	__le64	rx_broadcast;
	__le32	rx_multicast;
	__le16	tx_aborted;
	__le16	tx_underun;
};

670
enum rtl_flag {
671
	RTL_FLAG_TASK_ENABLED,
672 673 674 675 676 677
	RTL_FLAG_TASK_SLOW_PENDING,
	RTL_FLAG_TASK_RESET_PENDING,
	RTL_FLAG_TASK_PHY_PENDING,
	RTL_FLAG_MAX
};

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struct rtl8169_stats {
	u64			packets;
	u64			bytes;
	struct u64_stats_sync	syncp;
};

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struct rtl8169_private {
	void __iomem *mmio_addr;	/* memory map physical address */
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	struct pci_dev *pci_dev;
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	struct net_device *dev;
688
	struct napi_struct napi;
689
	u32 msg_enable;
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	u16 txd_version;
	u16 mac_version;
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	u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
	u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
	u32 dirty_rx;
	u32 dirty_tx;
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	struct rtl8169_stats rx_stats;
	struct rtl8169_stats tx_stats;
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	struct TxDesc *TxDescArray;	/* 256-aligned Tx descriptor ring */
	struct RxDesc *RxDescArray;	/* 256-aligned Rx descriptor ring */
	dma_addr_t TxPhyAddr;
	dma_addr_t RxPhyAddr;
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	void *Rx_databuff[NUM_RX_DESC];	/* Rx data buffers */
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	struct ring_info tx_skb[NUM_TX_DESC];	/* Tx data buffers */
	struct timer_list timer;
	u16 cp_cmd;
706 707

	u16 event_slow;
708 709 710 711 712 713

	struct mdio_ops {
		void (*write)(void __iomem *, int, int);
		int (*read)(void __iomem *, int);
	} mdio_ops;

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	struct pll_power_ops {
		void (*down)(struct rtl8169_private *);
		void (*up)(struct rtl8169_private *);
	} pll_power_ops;

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	struct jumbo_ops {
		void (*enable)(struct rtl8169_private *);
		void (*disable)(struct rtl8169_private *);
	} jumbo_ops;

724
	int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
725
	int (*get_settings)(struct net_device *, struct ethtool_cmd *);
726
	void (*phy_reset_enable)(struct rtl8169_private *tp);
727
	void (*hw_start)(struct net_device *);
728
	unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
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	unsigned int (*link_ok)(void __iomem *);
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	int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
731 732

	struct {
733 734
		DECLARE_BITMAP(flags, RTL_FLAG_MAX);
		struct mutex mutex;
735 736 737
		struct work_struct work;
	} wk;

738
	unsigned features;
739 740

	struct mii_if_info mii;
741
	struct rtl8169_counters counters;
742
	u32 saved_wolopts;
743
	u32 opts1_mask;
744

745 746
	struct rtl_fw {
		const struct firmware *fw;
747 748 749 750 751 752 753 754 755

#define RTL_VER_SIZE		32

		char version[RTL_VER_SIZE];

		struct rtl_fw_phy_action {
			__le32 *code;
			size_t size;
		} phy_action;
756
	} *rtl_fw;
757
#define RTL_FIRMWARE_UNKNOWN	ERR_PTR(-EAGAIN)
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};

760
MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
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MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
module_param(use_dac, int, 0);
763
MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
764 765
module_param_named(debug, debug.msg_enable, int, 0);
MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
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MODULE_LICENSE("GPL");
MODULE_VERSION(RTL8169_VERSION);
768 769
MODULE_FIRMWARE(FIRMWARE_8168D_1);
MODULE_FIRMWARE(FIRMWARE_8168D_2);
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MODULE_FIRMWARE(FIRMWARE_8168E_1);
MODULE_FIRMWARE(FIRMWARE_8168E_2);
772
MODULE_FIRMWARE(FIRMWARE_8168E_3);
773
MODULE_FIRMWARE(FIRMWARE_8105E_1);
774 775
MODULE_FIRMWARE(FIRMWARE_8168F_1);
MODULE_FIRMWARE(FIRMWARE_8168F_2);
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777
static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
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static int rtl8169_init_ring(struct net_device *dev);
779 780
static void rtl_hw_start(struct net_device *dev);
static void rtl_set_rx_mode(struct net_device *dev);
781
static void rtl8169_rx_clear(struct rtl8169_private *tp);
782
static int rtl8169_poll(struct napi_struct *napi, int budget);
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784 785 786 787 788 789 790 791 792 793
static void rtl_lock_work(struct rtl8169_private *tp)
{
	mutex_lock(&tp->wk.mutex);
}

static void rtl_unlock_work(struct rtl8169_private *tp)
{
	mutex_unlock(&tp->wk.mutex);
}

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static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
{
	int cap = pci_pcie_cap(pdev);

	if (cap) {
		u16 ctl;

		pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
		ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
		pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
	}
}

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static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
{
	void __iomem *ioaddr = tp->mmio_addr;
	int i;

	RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
	for (i = 0; i < 20; i++) {
		udelay(100);
		if (RTL_R32(OCPAR) & OCPAR_FLAG)
			break;
	}
	return RTL_R32(OCPDR);
}

static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
{
	void __iomem *ioaddr = tp->mmio_addr;
	int i;

	RTL_W32(OCPDR, data);
	RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
	for (i = 0; i < 20; i++) {
		udelay(100);
		if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
			break;
	}
}

835
static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
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{
837
	void __iomem *ioaddr = tp->mmio_addr;
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	int i;

	RTL_W8(ERIDR, cmd);
	RTL_W32(ERIAR, 0x800010e8);
	msleep(2);
	for (i = 0; i < 5; i++) {
		udelay(100);
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		if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
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			break;
	}

849
	ocp_write(tp, 0x1, 0x30, 0x00000001);
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}

#define OOB_CMD_RESET		0x00
#define OOB_CMD_DRIVER_START	0x05
#define OOB_CMD_DRIVER_STOP	0x06

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static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
{
	return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
}

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static void rtl8168_driver_start(struct rtl8169_private *tp)
{
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	u16 reg;
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	int i;

	rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);

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	reg = rtl8168_get_ocp_reg(tp);
869

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	for (i = 0; i < 10; i++) {
		msleep(10);
872
		if (ocp_read(tp, 0x0f, reg) & 0x00000800)
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			break;
	}
}

static void rtl8168_driver_stop(struct rtl8169_private *tp)
{
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	u16 reg;
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	int i;

	rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);

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	reg = rtl8168_get_ocp_reg(tp);
885

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	for (i = 0; i < 10; i++) {
		msleep(10);
888
		if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
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			break;
	}
}

893 894
static int r8168dp_check_dash(struct rtl8169_private *tp)
{
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	u16 reg = rtl8168_get_ocp_reg(tp);
896

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	return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
898
}
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900
static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
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{
	int i;

904
	RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
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906
	for (i = 20; i > 0; i--) {
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		/*
		 * Check if the RTL8169 has completed writing to the specified
		 * MII register.
		 */
911
		if (!(RTL_R32(PHYAR) & 0x80000000))
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			break;
913
		udelay(25);
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	}
915
	/*
916 917
	 * According to hardware specs a 20us delay is required after write
	 * complete indication, but before sending next command.
918
	 */
919
	udelay(20);
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}

922
static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
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{
	int i, value = -1;

926
	RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
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928
	for (i = 20; i > 0; i--) {
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		/*
		 * Check if the RTL8169 has completed retrieving data from
		 * the specified MII register.
		 */
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		if (RTL_R32(PHYAR) & 0x80000000) {
934
			value = RTL_R32(PHYAR) & 0xffff;
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			break;
		}
937
		udelay(25);
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	}
939 940 941 942 943 944
	/*
	 * According to hardware specs a 20us delay is required after read
	 * complete indication, but before sending next command.
	 */
	udelay(20);

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	return value;
}

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static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
{
	int i;

	RTL_W32(OCPDR, data |
		((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
	RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
	RTL_W32(EPHY_RXER_NUM, 0);

	for (i = 0; i < 100; i++) {
		mdelay(1);
		if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
			break;
	}
}

static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
{
	r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
		(value & OCPDR_DATA_MASK));
}

static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
{
	int i;

	r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);

	mdelay(1);
	RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
	RTL_W32(EPHY_RXER_NUM, 0);

	for (i = 0; i < 100; i++) {
		mdelay(1);
		if (RTL_R32(OCPAR) & OCPAR_FLAG)
			break;
	}

	return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
}

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#define R8168DP_1_MDIO_ACCESS_BIT	0x00020000

static void r8168dp_2_mdio_start(void __iomem *ioaddr)
{
	RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
}

static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
{
	RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
}

static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
{
	r8168dp_2_mdio_start(ioaddr);

	r8169_mdio_write(ioaddr, reg_addr, value);

	r8168dp_2_mdio_stop(ioaddr);
}

static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
{
	int value;

	r8168dp_2_mdio_start(ioaddr);

	value = r8169_mdio_read(ioaddr, reg_addr);

	r8168dp_2_mdio_stop(ioaddr);

	return value;
}

1023
static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1024
{
1025
	tp->mdio_ops.write(tp->mmio_addr, location, val);
1026 1027
}

1028 1029
static int rtl_readphy(struct rtl8169_private *tp, int location)
{
1030
	return tp->mdio_ops.read(tp->mmio_addr, location);
1031 1032 1033 1034 1035 1036 1037 1038
}

static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
{
	rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
}

static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1039 1040 1041
{
	int val;

1042 1043
	val = rtl_readphy(tp, reg_addr);
	rtl_writephy(tp, reg_addr, (val | p) & ~m);
1044 1045
}

1046 1047 1048 1049 1050
static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
			   int val)
{
	struct rtl8169_private *tp = netdev_priv(dev);

1051
	rtl_writephy(tp, location, val);
1052 1053 1054 1055 1056 1057
}

static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
{
	struct rtl8169_private *tp = netdev_priv(dev);

1058
	return rtl_readphy(tp, location);
1059 1060
}

1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126
static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
{
	unsigned int i;

	RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
		(reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);

	for (i = 0; i < 100; i++) {
		if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
			break;
		udelay(10);
	}
}

static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
{
	u16 value = 0xffff;
	unsigned int i;

	RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);

	for (i = 0; i < 100; i++) {
		if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
			value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
			break;
		}
		udelay(10);
	}

	return value;
}

static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
{
	unsigned int i;

	RTL_W32(CSIDR, value);
	RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);

	for (i = 0; i < 100; i++) {
		if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
			break;
		udelay(10);
	}
}

static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
{
	u32 value = ~0x00;
	unsigned int i;

	RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);

	for (i = 0; i < 100; i++) {
		if (RTL_R32(CSIAR) & CSIAR_FLAG) {
			value = RTL_R32(CSIDR);
			break;
		}
		udelay(10);
	}

	return value;
}

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static
void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
{
	unsigned int i;

	BUG_ON((addr & 3) || (mask == 0));
	RTL_W32(ERIDR, val);
	RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);

	for (i = 0; i < 100; i++) {
		if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
			break;
		udelay(100);
	}
}

static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
{
	u32 value = ~0x00;
	unsigned int i;

	RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);

	for (i = 0; i < 100; i++) {
		if (RTL_R32(ERIAR) & ERIAR_FLAG) {
			value = RTL_R32(ERIDR);
			break;
		}
		udelay(100);
	}

	return value;
}

static void
rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
{
	u32 val;

	val = rtl_eri_read(ioaddr, addr, type);
	rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
}

1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184
struct exgmac_reg {
	u16 addr;
	u16 mask;
	u32 val;
};

static void rtl_write_exgmac_batch(void __iomem *ioaddr,
				   const struct exgmac_reg *r, int len)
{
	while (len-- > 0) {
		rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
		r++;
	}
}

1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202
static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
{
	u8 value = 0xff;
	unsigned int i;

	RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);

	for (i = 0; i < 300; i++) {
		if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
			value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
			break;
		}
		udelay(100);
	}

	return value;
}

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static u16 rtl_get_events(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R16(IntrStatus);
}

static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W16(IntrStatus, bits);
	mmiowb();
}

static void rtl_irq_disable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W16(IntrMask, 0);
	mmiowb();
}

1226 1227 1228 1229 1230 1231 1232
static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W16(IntrMask, bits);
}

1233 1234 1235 1236 1237 1238 1239 1240 1241
#define RTL_EVENT_NAPI_RX	(RxOK | RxErr)
#define RTL_EVENT_NAPI_TX	(TxOK | TxErr)
#define RTL_EVENT_NAPI		(RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)

static void rtl_irq_enable_all(struct rtl8169_private *tp)
{
	rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
}

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static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
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{
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	void __iomem *ioaddr = tp->mmio_addr;
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	rtl_irq_disable(tp);
1247
	rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
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	RTL_R8(ChipCmd);
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}

1251
static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
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{
1253 1254
	void __iomem *ioaddr = tp->mmio_addr;

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	return RTL_R32(TBICSR) & TBIReset;
}

1258
static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
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{
1260
	return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
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}

static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
{
	return RTL_R32(TBICSR) & TBILinkOk;
}

static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
{
	return RTL_R8(PHYstatus) & LinkStatus;
}

1273
static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
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{
1275 1276
	void __iomem *ioaddr = tp->mmio_addr;

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	RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
}

1280
static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
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{
	unsigned int val;

1284 1285
	val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
	rtl_writephy(tp, MII_BMCR, val & 0xffff);
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}

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static void rtl_link_chg_patch(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;
	struct net_device *dev = tp->dev;

	if (!netif_running(dev))
		return;

	if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
		if (RTL_R8(PHYstatus) & _1000bpsF) {
			rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
				      0x00000011, ERIAR_EXGMAC);
			rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
				      0x00000005, ERIAR_EXGMAC);
		} else if (RTL_R8(PHYstatus) & _100bps) {
			rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
				      0x0000001f, ERIAR_EXGMAC);
			rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
				      0x00000005, ERIAR_EXGMAC);
		} else {
			rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
				      0x0000001f, ERIAR_EXGMAC);
			rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
				      0x0000003f, ERIAR_EXGMAC);
		}
		/* Reset packet filter */
		rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
			     ERIAR_EXGMAC);
		rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
			     ERIAR_EXGMAC);
1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330
	} else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_36) {
		if (RTL_R8(PHYstatus) & _1000bpsF) {
			rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
				      0x00000011, ERIAR_EXGMAC);
			rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
				      0x00000005, ERIAR_EXGMAC);
		} else {
			rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
				      0x0000001f, ERIAR_EXGMAC);
			rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
				      0x0000003f, ERIAR_EXGMAC);
		}
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	}
}

1334
static void __rtl8169_check_link_status(struct net_device *dev,
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					struct rtl8169_private *tp,
					void __iomem *ioaddr, bool pm)
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{
	if (tp->link_ok(ioaddr)) {
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		rtl_link_chg_patch(tp);
1340
		/* This is to cancel a scheduled suspend if there's one. */
1341 1342
		if (pm)
			pm_request_resume(&tp->pci_dev->dev);
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		netif_carrier_on(dev);
1344 1345
		if (net_ratelimit())
			netif_info(tp, ifup, dev, "link up\n");
1346
	} else {
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		netif_carrier_off(dev);
1348
		netif_info(tp, ifdown, dev, "link down\n");
1349
		if (pm)
1350
			pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1351
	}
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}

1354 1355 1356 1357 1358 1359 1360
static void rtl8169_check_link_status(struct net_device *dev,
				      struct rtl8169_private *tp,
				      void __iomem *ioaddr)
{
	__rtl8169_check_link_status(dev, tp, ioaddr, false);
}

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#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)

static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
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{
	void __iomem *ioaddr = tp->mmio_addr;
	u8 options;
1367
	u32 wolopts = 0;
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	options = RTL_R8(Config1);
	if (!(options & PMEnable))
1371
		return 0;
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	options = RTL_R8(Config3);
	if (options & LinkUp)
1375
		wolopts |= WAKE_PHY;
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	if (options & MagicPacket)
1377
		wolopts |= WAKE_MAGIC;
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	options = RTL_R8(Config5);
	if (options & UWF)
1381
		wolopts |= WAKE_UCAST;
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	if (options & BWF)
1383
		wolopts |= WAKE_BCAST;
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	if (options & MWF)
1385
		wolopts |= WAKE_MCAST;
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1387
	return wolopts;
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}

1390
static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
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{
	struct rtl8169_private *tp = netdev_priv(dev);
1393

1394
	rtl_lock_work(tp);
1395 1396 1397 1398

	wol->supported = WAKE_ANY;
	wol->wolopts = __rtl8169_get_wol(tp);

1399
	rtl_unlock_work(tp);
1400 1401 1402 1403
}

static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
{
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	void __iomem *ioaddr = tp->mmio_addr;
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	unsigned int i;
1406
	static const struct {
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		u32 opt;
		u16 reg;
		u8  mask;
	} cfg[] = {
		{ WAKE_ANY,   Config1, PMEnable },
		{ WAKE_PHY,   Config3, LinkUp },
		{ WAKE_MAGIC, Config3, MagicPacket },
		{ WAKE_UCAST, Config5, UWF },
		{ WAKE_BCAST, Config5, BWF },
		{ WAKE_MCAST, Config5, MWF },
		{ WAKE_ANY,   Config5, LanWake }
	};

	RTL_W8(Cfg9346, Cfg9346_Unlock);

	for (i = 0; i < ARRAY_SIZE(cfg); i++) {
		u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1424
		if (wolopts & cfg[i].opt)
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			options |= cfg[i].mask;
		RTL_W8(cfg[i].reg, options);
	}

	RTL_W8(Cfg9346, Cfg9346_Lock);
1430 1431 1432 1433 1434 1435
}

static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
	struct rtl8169_private *tp = netdev_priv(dev);

1436
	rtl_lock_work(tp);
F
Francois Romieu 已提交
1437

1438 1439 1440 1441
	if (wol->wolopts)
		tp->features |= RTL_FEATURE_WOL;
	else
		tp->features &= ~RTL_FEATURE_WOL;
1442
	__rtl8169_set_wol(tp, wol->wolopts);
1443 1444

	rtl_unlock_work(tp);
F
Francois Romieu 已提交
1445

1446 1447
	device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);

F
Francois Romieu 已提交
1448 1449 1450
	return 0;
}

1451 1452
static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
{
1453
	return rtl_chip_infos[tp->mac_version].fw_name;
1454 1455
}

L
Linus Torvalds 已提交
1456 1457 1458 1459
static void rtl8169_get_drvinfo(struct net_device *dev,
				struct ethtool_drvinfo *info)
{
	struct rtl8169_private *tp = netdev_priv(dev);
1460
	struct rtl_fw *rtl_fw = tp->rtl_fw;
L
Linus Torvalds 已提交
1461

1462 1463 1464
	strlcpy(info->driver, MODULENAME, sizeof(info->driver));
	strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
	strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1465
	BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1466 1467 1468
	if (!IS_ERR_OR_NULL(rtl_fw))
		strlcpy(info->fw_version, rtl_fw->version,
			sizeof(info->fw_version));
L
Linus Torvalds 已提交
1469 1470 1471 1472 1473 1474 1475 1476
}

static int rtl8169_get_regs_len(struct net_device *dev)
{
	return R8169_REGS_SIZE;
}

static int rtl8169_set_speed_tbi(struct net_device *dev,
1477
				 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
L
Linus Torvalds 已提交
1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	int ret = 0;
	u32 reg;

	reg = RTL_R32(TBICSR);
	if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
	    (duplex == DUPLEX_FULL)) {
		RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
	} else if (autoneg == AUTONEG_ENABLE)
		RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
	else {
1491 1492
		netif_warn(tp, link, dev,
			   "incorrect speed setting refused in TBI mode\n");
L
Linus Torvalds 已提交
1493 1494 1495 1496 1497 1498 1499
		ret = -EOPNOTSUPP;
	}

	return ret;
}

static int rtl8169_set_speed_xmii(struct net_device *dev,
1500
				  u8 autoneg, u16 speed, u8 duplex, u32 adv)
L
Linus Torvalds 已提交
1501 1502
{
	struct rtl8169_private *tp = netdev_priv(dev);
1503
	int giga_ctrl, bmcr;
1504
	int rc = -EINVAL;
L
Linus Torvalds 已提交
1505

1506
	rtl_writephy(tp, 0x1f, 0x0000);
L
Linus Torvalds 已提交
1507 1508

	if (autoneg == AUTONEG_ENABLE) {
1509 1510
		int auto_nego;

1511
		auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523
		auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
				ADVERTISE_100HALF | ADVERTISE_100FULL);

		if (adv & ADVERTISED_10baseT_Half)
			auto_nego |= ADVERTISE_10HALF;
		if (adv & ADVERTISED_10baseT_Full)
			auto_nego |= ADVERTISE_10FULL;
		if (adv & ADVERTISED_100baseT_Half)
			auto_nego |= ADVERTISE_100HALF;
		if (adv & ADVERTISED_100baseT_Full)
			auto_nego |= ADVERTISE_100FULL;

1524
		auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
L
Linus Torvalds 已提交
1525

1526
		giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1527
		giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1528

1529
		/* The 8100e/8101e/8102e do Fast Ethernet only. */
1530
		if (tp->mii.supports_gmii) {
1531 1532 1533 1534 1535 1536
			if (adv & ADVERTISED_1000baseT_Half)
				giga_ctrl |= ADVERTISE_1000HALF;
			if (adv & ADVERTISED_1000baseT_Full)
				giga_ctrl |= ADVERTISE_1000FULL;
		} else if (adv & (ADVERTISED_1000baseT_Half |
				  ADVERTISED_1000baseT_Full)) {
1537 1538
			netif_info(tp, link, dev,
				   "PHY does not support 1000Mbps\n");
1539
			goto out;
1540
		}
L
Linus Torvalds 已提交
1541

1542 1543
		bmcr = BMCR_ANENABLE | BMCR_ANRESTART;

1544 1545
		rtl_writephy(tp, MII_ADVERTISE, auto_nego);
		rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1546 1547 1548 1549 1550 1551 1552 1553
	} else {
		giga_ctrl = 0;

		if (speed == SPEED_10)
			bmcr = 0;
		else if (speed == SPEED_100)
			bmcr = BMCR_SPEED100;
		else
1554
			goto out;
1555 1556 1557

		if (duplex == DUPLEX_FULL)
			bmcr |= BMCR_FULLDPLX;
R
Roger So 已提交
1558 1559
	}

1560
	rtl_writephy(tp, MII_BMCR, bmcr);
1561

F
Francois Romieu 已提交
1562 1563
	if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_03) {
1564
		if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1565 1566
			rtl_writephy(tp, 0x17, 0x2138);
			rtl_writephy(tp, 0x0e, 0x0260);
1567
		} else {
1568 1569
			rtl_writephy(tp, 0x17, 0x2108);
			rtl_writephy(tp, 0x0e, 0x0000);
1570 1571 1572
		}
	}

1573 1574 1575
	rc = 0;
out:
	return rc;
L
Linus Torvalds 已提交
1576 1577 1578
}

static int rtl8169_set_speed(struct net_device *dev,
1579
			     u8 autoneg, u16 speed, u8 duplex, u32 advertising)
L
Linus Torvalds 已提交
1580 1581 1582 1583
{
	struct rtl8169_private *tp = netdev_priv(dev);
	int ret;

1584
	ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1585 1586
	if (ret < 0)
		goto out;
L
Linus Torvalds 已提交
1587

1588 1589
	if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
	    (advertising & ADVERTISED_1000baseT_Full)) {
L
Linus Torvalds 已提交
1590
		mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1591 1592
	}
out:
L
Linus Torvalds 已提交
1593 1594 1595 1596 1597 1598 1599 1600
	return ret;
}

static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	int ret;

1601 1602
	del_timer_sync(&tp->timer);

1603
	rtl_lock_work(tp);
F
Francois Romieu 已提交
1604
	ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1605
				cmd->duplex, cmd->advertising);
1606
	rtl_unlock_work(tp);
1607

L
Linus Torvalds 已提交
1608 1609 1610
	return ret;
}

1611 1612
static netdev_features_t rtl8169_fix_features(struct net_device *dev,
	netdev_features_t features)
L
Linus Torvalds 已提交
1613
{
F
Francois Romieu 已提交
1614 1615
	struct rtl8169_private *tp = netdev_priv(dev);

F
Francois Romieu 已提交
1616
	if (dev->mtu > TD_MSS_MAX)
1617
		features &= ~NETIF_F_ALL_TSO;
L
Linus Torvalds 已提交
1618

F
Francois Romieu 已提交
1619 1620 1621 1622
	if (dev->mtu > JUMBO_1K &&
	    !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
		features &= ~NETIF_F_IP_CSUM;

1623
	return features;
L
Linus Torvalds 已提交
1624 1625
}

1626 1627
static void __rtl8169_set_features(struct net_device *dev,
				   netdev_features_t features)
L
Linus Torvalds 已提交
1628 1629
{
	struct rtl8169_private *tp = netdev_priv(dev);
B
Ben Greear 已提交
1630
	netdev_features_t changed = features ^ dev->features;
1631
	void __iomem *ioaddr = tp->mmio_addr;
L
Linus Torvalds 已提交
1632

B
Ben Greear 已提交
1633 1634
	if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
		return;
L
Linus Torvalds 已提交
1635

B
Ben Greear 已提交
1636 1637 1638 1639 1640
	if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
		if (features & NETIF_F_RXCSUM)
			tp->cp_cmd |= RxChkSum;
		else
			tp->cp_cmd &= ~RxChkSum;
1641

B
Ben Greear 已提交
1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655
		if (dev->features & NETIF_F_HW_VLAN_RX)
			tp->cp_cmd |= RxVlan;
		else
			tp->cp_cmd &= ~RxVlan;

		RTL_W16(CPlusCmd, tp->cp_cmd);
		RTL_R16(CPlusCmd);
	}
	if (changed & NETIF_F_RXALL) {
		int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
		if (features & NETIF_F_RXALL)
			tmp |= (AcceptErr | AcceptRunt);
		RTL_W32(RxConfig, tmp);
	}
1656
}
L
Linus Torvalds 已提交
1657

1658 1659 1660 1661 1662 1663 1664 1665
static int rtl8169_set_features(struct net_device *dev,
				netdev_features_t features)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl_lock_work(tp);
	__rtl8169_set_features(dev, features);
	rtl_unlock_work(tp);
L
Linus Torvalds 已提交
1666 1667 1668 1669

	return 0;
}

1670

L
Linus Torvalds 已提交
1671 1672 1673
static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
				      struct sk_buff *skb)
{
1674
	return (vlan_tx_tag_present(skb)) ?
L
Linus Torvalds 已提交
1675 1676 1677
		TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
}

1678
static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
L
Linus Torvalds 已提交
1679 1680 1681
{
	u32 opts2 = le32_to_cpu(desc->opts2);

1682 1683
	if (opts2 & RxVlanTag)
		__vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
E
Eric Dumazet 已提交
1684

L
Linus Torvalds 已提交
1685 1686 1687
	desc->opts2 = 0;
}

1688
static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
L
Linus Torvalds 已提交
1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	u32 status;

	cmd->supported =
		SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
	cmd->port = PORT_FIBRE;
	cmd->transceiver = XCVR_INTERNAL;

	status = RTL_R32(TBICSR);
	cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
	cmd->autoneg = !!(status & TBINwEnable);

1703
	ethtool_cmd_speed_set(cmd, SPEED_1000);
L
Linus Torvalds 已提交
1704
	cmd->duplex = DUPLEX_FULL; /* Always set */
1705 1706

	return 0;
L
Linus Torvalds 已提交
1707 1708
}

1709
static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
L
Linus Torvalds 已提交
1710 1711
{
	struct rtl8169_private *tp = netdev_priv(dev);
1712 1713

	return mii_ethtool_gset(&tp->mii, cmd);
L
Linus Torvalds 已提交
1714 1715 1716 1717 1718
}

static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
	struct rtl8169_private *tp = netdev_priv(dev);
1719
	int rc;
L
Linus Torvalds 已提交
1720

1721
	rtl_lock_work(tp);
1722
	rc = tp->get_settings(dev, cmd);
1723
	rtl_unlock_work(tp);
L
Linus Torvalds 已提交
1724

1725
	return rc;
L
Linus Torvalds 已提交
1726 1727 1728 1729 1730
}

static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
			     void *p)
{
1731
	struct rtl8169_private *tp = netdev_priv(dev);
L
Linus Torvalds 已提交
1732

1733 1734
	if (regs->len > R8169_REGS_SIZE)
		regs->len = R8169_REGS_SIZE;
L
Linus Torvalds 已提交
1735

1736
	rtl_lock_work(tp);
1737
	memcpy_fromio(p, tp->mmio_addr, regs->len);
1738
	rtl_unlock_work(tp);
L
Linus Torvalds 已提交
1739 1740
}

1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754
static u32 rtl8169_get_msglevel(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	return tp->msg_enable;
}

static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	tp->msg_enable = value;
}

1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770
static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
	"tx_packets",
	"rx_packets",
	"tx_errors",
	"rx_errors",
	"rx_missed",
	"align_errors",
	"tx_single_collisions",
	"tx_multi_collisions",
	"unicast",
	"broadcast",
	"multicast",
	"tx_aborted",
	"tx_underrun",
};

1771
static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1772
{
1773 1774 1775 1776 1777 1778
	switch (sset) {
	case ETH_SS_STATS:
		return ARRAY_SIZE(rtl8169_gstrings);
	default:
		return -EOPNOTSUPP;
	}
1779 1780
}

1781
static void rtl8169_update_counters(struct net_device *dev)
1782 1783 1784
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
F
Francois Romieu 已提交
1785
	struct device *d = &tp->pci_dev->dev;
1786 1787 1788
	struct rtl8169_counters *counters;
	dma_addr_t paddr;
	u32 cmd;
1789
	int wait = 1000;
1790

1791 1792 1793 1794 1795 1796
	/*
	 * Some chips are unable to dump tally counters when the receiver
	 * is disabled.
	 */
	if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
		return;
1797

1798
	counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1799 1800 1801 1802
	if (!counters)
		return;

	RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1803
	cmd = (u64)paddr & DMA_BIT_MASK(32);
1804 1805 1806
	RTL_W32(CounterAddrLow, cmd);
	RTL_W32(CounterAddrLow, cmd | CounterDump);

1807 1808 1809
	while (wait--) {
		if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
			memcpy(&tp->counters, counters, sizeof(*counters));
1810
			break;
1811 1812
		}
		udelay(10);
1813 1814 1815 1816 1817
	}

	RTL_W32(CounterAddrLow, 0);
	RTL_W32(CounterAddrHigh, 0);

1818
	dma_free_coherent(d, sizeof(*counters), counters, paddr);
1819 1820
}

1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844
static void rtl8169_get_ethtool_stats(struct net_device *dev,
				      struct ethtool_stats *stats, u64 *data)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	ASSERT_RTNL();

	rtl8169_update_counters(dev);

	data[0] = le64_to_cpu(tp->counters.tx_packets);
	data[1] = le64_to_cpu(tp->counters.rx_packets);
	data[2] = le64_to_cpu(tp->counters.tx_errors);
	data[3] = le32_to_cpu(tp->counters.rx_errors);
	data[4] = le16_to_cpu(tp->counters.rx_missed);
	data[5] = le16_to_cpu(tp->counters.align_errors);
	data[6] = le32_to_cpu(tp->counters.tx_one_collision);
	data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
	data[8] = le64_to_cpu(tp->counters.rx_unicast);
	data[9] = le64_to_cpu(tp->counters.rx_broadcast);
	data[10] = le32_to_cpu(tp->counters.rx_multicast);
	data[11] = le16_to_cpu(tp->counters.tx_aborted);
	data[12] = le16_to_cpu(tp->counters.tx_underun);
}

1845 1846 1847 1848 1849 1850 1851 1852 1853
static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
{
	switch(stringset) {
	case ETH_SS_STATS:
		memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
		break;
	}
}

1854
static const struct ethtool_ops rtl8169_ethtool_ops = {
L
Linus Torvalds 已提交
1855 1856 1857 1858 1859
	.get_drvinfo		= rtl8169_get_drvinfo,
	.get_regs_len		= rtl8169_get_regs_len,
	.get_link		= ethtool_op_get_link,
	.get_settings		= rtl8169_get_settings,
	.set_settings		= rtl8169_set_settings,
1860 1861
	.get_msglevel		= rtl8169_get_msglevel,
	.set_msglevel		= rtl8169_set_msglevel,
L
Linus Torvalds 已提交
1862
	.get_regs		= rtl8169_get_regs,
F
Francois Romieu 已提交
1863 1864
	.get_wol		= rtl8169_get_wol,
	.set_wol		= rtl8169_set_wol,
1865
	.get_strings		= rtl8169_get_strings,
1866
	.get_sset_count		= rtl8169_get_sset_count,
1867
	.get_ethtool_stats	= rtl8169_get_ethtool_stats,
L
Linus Torvalds 已提交
1868 1869
};

F
Francois Romieu 已提交
1870
static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1871
				    struct net_device *dev, u8 default_version)
L
Linus Torvalds 已提交
1872
{
1873
	void __iomem *ioaddr = tp->mmio_addr;
1874 1875 1876 1877 1878 1879
	/*
	 * The driver currently handles the 8168Bf and the 8168Be identically
	 * but they can be identified more specifically through the test below
	 * if needed:
	 *
	 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
F
Francois Romieu 已提交
1880 1881 1882 1883
	 *
	 * Same thing for the 8101Eb and the 8101Ec:
	 *
	 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1884
	 */
1885
	static const struct rtl_mac_info {
L
Linus Torvalds 已提交
1886
		u32 mask;
F
Francois Romieu 已提交
1887
		u32 val;
L
Linus Torvalds 已提交
1888 1889
		int mac_version;
	} mac_info[] = {
1890 1891 1892 1893
		/* 8168F family. */
		{ 0x7cf00000, 0x48100000,	RTL_GIGA_MAC_VER_36 },
		{ 0x7cf00000, 0x48000000,	RTL_GIGA_MAC_VER_35 },

H
hayeswang 已提交
1894
		/* 8168E family. */
H
Hayes Wang 已提交
1895
		{ 0x7c800000, 0x2c800000,	RTL_GIGA_MAC_VER_34 },
H
hayeswang 已提交
1896 1897 1898 1899
		{ 0x7cf00000, 0x2c200000,	RTL_GIGA_MAC_VER_33 },
		{ 0x7cf00000, 0x2c100000,	RTL_GIGA_MAC_VER_32 },
		{ 0x7c800000, 0x2c000000,	RTL_GIGA_MAC_VER_33 },

F
Francois Romieu 已提交
1900
		/* 8168D family. */
1901 1902 1903
		{ 0x7cf00000, 0x28300000,	RTL_GIGA_MAC_VER_26 },
		{ 0x7cf00000, 0x28100000,	RTL_GIGA_MAC_VER_25 },
		{ 0x7c800000, 0x28000000,	RTL_GIGA_MAC_VER_26 },
F
Francois Romieu 已提交
1904

F
françois romieu 已提交
1905 1906 1907
		/* 8168DP family. */
		{ 0x7cf00000, 0x28800000,	RTL_GIGA_MAC_VER_27 },
		{ 0x7cf00000, 0x28a00000,	RTL_GIGA_MAC_VER_28 },
1908
		{ 0x7cf00000, 0x28b00000,	RTL_GIGA_MAC_VER_31 },
F
françois romieu 已提交
1909

1910
		/* 8168C family. */
1911
		{ 0x7cf00000, 0x3cb00000,	RTL_GIGA_MAC_VER_24 },
F
Francois Romieu 已提交
1912
		{ 0x7cf00000, 0x3c900000,	RTL_GIGA_MAC_VER_23 },
1913
		{ 0x7cf00000, 0x3c800000,	RTL_GIGA_MAC_VER_18 },
1914
		{ 0x7c800000, 0x3c800000,	RTL_GIGA_MAC_VER_24 },
F
Francois Romieu 已提交
1915 1916
		{ 0x7cf00000, 0x3c000000,	RTL_GIGA_MAC_VER_19 },
		{ 0x7cf00000, 0x3c200000,	RTL_GIGA_MAC_VER_20 },
F
Francois Romieu 已提交
1917
		{ 0x7cf00000, 0x3c300000,	RTL_GIGA_MAC_VER_21 },
1918
		{ 0x7cf00000, 0x3c400000,	RTL_GIGA_MAC_VER_22 },
1919
		{ 0x7c800000, 0x3c000000,	RTL_GIGA_MAC_VER_22 },
F
Francois Romieu 已提交
1920 1921 1922 1923 1924 1925 1926 1927

		/* 8168B family. */
		{ 0x7cf00000, 0x38000000,	RTL_GIGA_MAC_VER_12 },
		{ 0x7cf00000, 0x38500000,	RTL_GIGA_MAC_VER_17 },
		{ 0x7c800000, 0x38000000,	RTL_GIGA_MAC_VER_17 },
		{ 0x7c800000, 0x30000000,	RTL_GIGA_MAC_VER_11 },

		/* 8101 family. */
1928
		{ 0x7cf00000, 0x40b00000,	RTL_GIGA_MAC_VER_30 },
1929 1930 1931
		{ 0x7cf00000, 0x40a00000,	RTL_GIGA_MAC_VER_30 },
		{ 0x7cf00000, 0x40900000,	RTL_GIGA_MAC_VER_29 },
		{ 0x7c800000, 0x40800000,	RTL_GIGA_MAC_VER_30 },
1932 1933 1934 1935 1936 1937
		{ 0x7cf00000, 0x34a00000,	RTL_GIGA_MAC_VER_09 },
		{ 0x7cf00000, 0x24a00000,	RTL_GIGA_MAC_VER_09 },
		{ 0x7cf00000, 0x34900000,	RTL_GIGA_MAC_VER_08 },
		{ 0x7cf00000, 0x24900000,	RTL_GIGA_MAC_VER_08 },
		{ 0x7cf00000, 0x34800000,	RTL_GIGA_MAC_VER_07 },
		{ 0x7cf00000, 0x24800000,	RTL_GIGA_MAC_VER_07 },
F
Francois Romieu 已提交
1938
		{ 0x7cf00000, 0x34000000,	RTL_GIGA_MAC_VER_13 },
1939
		{ 0x7cf00000, 0x34300000,	RTL_GIGA_MAC_VER_10 },
F
Francois Romieu 已提交
1940
		{ 0x7cf00000, 0x34200000,	RTL_GIGA_MAC_VER_16 },
1941 1942
		{ 0x7c800000, 0x34800000,	RTL_GIGA_MAC_VER_09 },
		{ 0x7c800000, 0x24800000,	RTL_GIGA_MAC_VER_09 },
F
Francois Romieu 已提交
1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955
		{ 0x7c800000, 0x34000000,	RTL_GIGA_MAC_VER_16 },
		/* FIXME: where did these entries come from ? -- FR */
		{ 0xfc800000, 0x38800000,	RTL_GIGA_MAC_VER_15 },
		{ 0xfc800000, 0x30800000,	RTL_GIGA_MAC_VER_14 },

		/* 8110 family. */
		{ 0xfc800000, 0x98000000,	RTL_GIGA_MAC_VER_06 },
		{ 0xfc800000, 0x18000000,	RTL_GIGA_MAC_VER_05 },
		{ 0xfc800000, 0x10000000,	RTL_GIGA_MAC_VER_04 },
		{ 0xfc800000, 0x04000000,	RTL_GIGA_MAC_VER_03 },
		{ 0xfc800000, 0x00800000,	RTL_GIGA_MAC_VER_02 },
		{ 0xfc800000, 0x00000000,	RTL_GIGA_MAC_VER_01 },

1956 1957
		/* Catch-all */
		{ 0x00000000, 0x00000000,	RTL_GIGA_MAC_NONE   }
1958 1959
	};
	const struct rtl_mac_info *p = mac_info;
L
Linus Torvalds 已提交
1960 1961
	u32 reg;

F
Francois Romieu 已提交
1962 1963
	reg = RTL_R32(TxConfig);
	while ((reg & p->mask) != p->val)
L
Linus Torvalds 已提交
1964 1965
		p++;
	tp->mac_version = p->mac_version;
1966 1967 1968 1969 1970 1971

	if (tp->mac_version == RTL_GIGA_MAC_NONE) {
		netif_notice(tp, probe, dev,
			     "unknown MAC, using family default\n");
		tp->mac_version = default_version;
	}
L
Linus Torvalds 已提交
1972 1973 1974 1975
}

static void rtl8169_print_mac_version(struct rtl8169_private *tp)
{
1976
	dprintk("mac_version = 0x%02x\n", tp->mac_version);
L
Linus Torvalds 已提交
1977 1978
}

F
Francois Romieu 已提交
1979 1980 1981 1982 1983
struct phy_reg {
	u16 reg;
	u16 val;
};

1984 1985
static void rtl_writephy_batch(struct rtl8169_private *tp,
			       const struct phy_reg *regs, int len)
F
Francois Romieu 已提交
1986 1987
{
	while (len-- > 0) {
1988
		rtl_writephy(tp, regs->reg, regs->val);
F
Francois Romieu 已提交
1989 1990 1991 1992
		regs++;
	}
}

1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009
#define PHY_READ		0x00000000
#define PHY_DATA_OR		0x10000000
#define PHY_DATA_AND		0x20000000
#define PHY_BJMPN		0x30000000
#define PHY_READ_EFUSE		0x40000000
#define PHY_READ_MAC_BYTE	0x50000000
#define PHY_WRITE_MAC_BYTE	0x60000000
#define PHY_CLEAR_READCOUNT	0x70000000
#define PHY_WRITE		0x80000000
#define PHY_READCOUNT_EQ_SKIP	0x90000000
#define PHY_COMP_EQ_SKIPN	0xa0000000
#define PHY_COMP_NEQ_SKIPN	0xb0000000
#define PHY_WRITE_PREVIOUS	0xc0000000
#define PHY_SKIPN		0xd0000000
#define PHY_DELAY_MS		0xe0000000
#define PHY_WRITE_ERI_WORD	0xf0000000

H
Hayes Wang 已提交
2010 2011 2012 2013 2014 2015 2016 2017
struct fw_info {
	u32	magic;
	char	version[RTL_VER_SIZE];
	__le32	fw_start;
	__le32	fw_len;
	u8	chksum;
} __packed;

2018 2019 2020
#define FW_OPCODE_SIZE	sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))

static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2021
{
2022
	const struct firmware *fw = rtl_fw->fw;
H
Hayes Wang 已提交
2023
	struct fw_info *fw_info = (struct fw_info *)fw->data;
2024 2025 2026 2027 2028 2029
	struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
	char *version = rtl_fw->version;
	bool rc = false;

	if (fw->size < FW_OPCODE_SIZE)
		goto out;
H
Hayes Wang 已提交
2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055

	if (!fw_info->magic) {
		size_t i, size, start;
		u8 checksum = 0;

		if (fw->size < sizeof(*fw_info))
			goto out;

		for (i = 0; i < fw->size; i++)
			checksum += fw->data[i];
		if (checksum != 0)
			goto out;

		start = le32_to_cpu(fw_info->fw_start);
		if (start > fw->size)
			goto out;

		size = le32_to_cpu(fw_info->fw_len);
		if (size > (fw->size - start) / FW_OPCODE_SIZE)
			goto out;

		memcpy(version, fw_info->version, RTL_VER_SIZE);

		pa->code = (__le32 *)(fw->data + start);
		pa->size = size;
	} else {
2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070
		if (fw->size % FW_OPCODE_SIZE)
			goto out;

		strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);

		pa->code = (__le32 *)fw->data;
		pa->size = fw->size / FW_OPCODE_SIZE;
	}
	version[RTL_VER_SIZE - 1] = 0;

	rc = true;
out:
	return rc;
}

2071 2072
static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
			   struct rtl_fw_phy_action *pa)
2073
{
2074
	bool rc = false;
2075
	size_t index;
2076

2077 2078
	for (index = 0; index < pa->size; index++) {
		u32 action = le32_to_cpu(pa->code[index]);
2079
		u32 regno = (action & 0x0fff0000) >> 16;
2080

2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093
		switch(action & 0xf0000000) {
		case PHY_READ:
		case PHY_DATA_OR:
		case PHY_DATA_AND:
		case PHY_READ_EFUSE:
		case PHY_CLEAR_READCOUNT:
		case PHY_WRITE:
		case PHY_WRITE_PREVIOUS:
		case PHY_DELAY_MS:
			break;

		case PHY_BJMPN:
			if (regno > index) {
2094
				netif_err(tp, ifup, tp->dev,
F
Francois Romieu 已提交
2095
					  "Out of range of firmware\n");
2096
				goto out;
2097 2098 2099
			}
			break;
		case PHY_READCOUNT_EQ_SKIP:
2100
			if (index + 2 >= pa->size) {
2101
				netif_err(tp, ifup, tp->dev,
F
Francois Romieu 已提交
2102
					  "Out of range of firmware\n");
2103
				goto out;
2104 2105 2106 2107 2108
			}
			break;
		case PHY_COMP_EQ_SKIPN:
		case PHY_COMP_NEQ_SKIPN:
		case PHY_SKIPN:
2109
			if (index + 1 + regno >= pa->size) {
2110
				netif_err(tp, ifup, tp->dev,
F
Francois Romieu 已提交
2111
					  "Out of range of firmware\n");
2112
				goto out;
2113
			}
2114 2115
			break;

2116 2117 2118 2119
		case PHY_READ_MAC_BYTE:
		case PHY_WRITE_MAC_BYTE:
		case PHY_WRITE_ERI_WORD:
		default:
2120
			netif_err(tp, ifup, tp->dev,
2121
				  "Invalid action 0x%08x\n", action);
2122
			goto out;
2123 2124
		}
	}
2125 2126 2127 2128
	rc = true;
out:
	return rc;
}
2129

2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152
static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
{
	struct net_device *dev = tp->dev;
	int rc = -EINVAL;

	if (!rtl_fw_format_ok(tp, rtl_fw)) {
		netif_err(tp, ifup, dev, "invalid firwmare\n");
		goto out;
	}

	if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
		rc = 0;
out:
	return rc;
}

static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
{
	struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
	u32 predata, count;
	size_t index;

	predata = count = 0;
2153

2154 2155
	for (index = 0; index < pa->size; ) {
		u32 action = le32_to_cpu(pa->code[index]);
2156
		u32 data = action & 0x0000ffff;
2157 2158 2159 2160
		u32 regno = (action & 0x0fff0000) >> 16;

		if (!action)
			break;
2161 2162

		switch(action & 0xf0000000) {
2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186
		case PHY_READ:
			predata = rtl_readphy(tp, regno);
			count++;
			index++;
			break;
		case PHY_DATA_OR:
			predata |= data;
			index++;
			break;
		case PHY_DATA_AND:
			predata &= data;
			index++;
			break;
		case PHY_BJMPN:
			index -= regno;
			break;
		case PHY_READ_EFUSE:
			predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
			index++;
			break;
		case PHY_CLEAR_READCOUNT:
			count = 0;
			index++;
			break;
2187
		case PHY_WRITE:
2188 2189 2190 2191
			rtl_writephy(tp, regno, data);
			index++;
			break;
		case PHY_READCOUNT_EQ_SKIP:
F
Francois Romieu 已提交
2192
			index += (count == data) ? 2 : 1;
2193
			break;
2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218
		case PHY_COMP_EQ_SKIPN:
			if (predata == data)
				index += regno;
			index++;
			break;
		case PHY_COMP_NEQ_SKIPN:
			if (predata != data)
				index += regno;
			index++;
			break;
		case PHY_WRITE_PREVIOUS:
			rtl_writephy(tp, regno, predata);
			index++;
			break;
		case PHY_SKIPN:
			index += regno + 1;
			break;
		case PHY_DELAY_MS:
			mdelay(data);
			index++;
			break;

		case PHY_READ_MAC_BYTE:
		case PHY_WRITE_MAC_BYTE:
		case PHY_WRITE_ERI_WORD:
2219 2220 2221 2222 2223 2224
		default:
			BUG();
		}
	}
}

2225 2226
static void rtl_release_firmware(struct rtl8169_private *tp)
{
2227 2228 2229 2230 2231
	if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
		release_firmware(tp->rtl_fw->fw);
		kfree(tp->rtl_fw);
	}
	tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2232 2233
}

2234
static void rtl_apply_firmware(struct rtl8169_private *tp)
2235
{
2236
	struct rtl_fw *rtl_fw = tp->rtl_fw;
2237 2238

	/* TODO: release firmware once rtl_phy_write_fw signals failures. */
2239 2240
	if (!IS_ERR_OR_NULL(rtl_fw))
		rtl_phy_write_fw(tp, rtl_fw);
2241 2242 2243 2244 2245 2246 2247 2248
}

static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
{
	if (rtl_readphy(tp, reg) != val)
		netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
	else
		rtl_apply_firmware(tp);
2249 2250
}

2251
static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
2252
{
2253
	static const struct phy_reg phy_reg_init[] = {
F
françois romieu 已提交
2254 2255 2256 2257 2258
		{ 0x1f, 0x0001 },
		{ 0x06, 0x006e },
		{ 0x08, 0x0708 },
		{ 0x15, 0x4000 },
		{ 0x18, 0x65c7 },
L
Linus Torvalds 已提交
2259

F
françois romieu 已提交
2260 2261 2262 2263 2264 2265 2266
		{ 0x1f, 0x0001 },
		{ 0x03, 0x00a1 },
		{ 0x02, 0x0008 },
		{ 0x01, 0x0120 },
		{ 0x00, 0x1000 },
		{ 0x04, 0x0800 },
		{ 0x04, 0x0000 },
L
Linus Torvalds 已提交
2267

F
françois romieu 已提交
2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313
		{ 0x03, 0xff41 },
		{ 0x02, 0xdf60 },
		{ 0x01, 0x0140 },
		{ 0x00, 0x0077 },
		{ 0x04, 0x7800 },
		{ 0x04, 0x7000 },

		{ 0x03, 0x802f },
		{ 0x02, 0x4f02 },
		{ 0x01, 0x0409 },
		{ 0x00, 0xf0f9 },
		{ 0x04, 0x9800 },
		{ 0x04, 0x9000 },

		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0xff95 },
		{ 0x00, 0xba00 },
		{ 0x04, 0xa800 },
		{ 0x04, 0xa000 },

		{ 0x03, 0xff41 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x0140 },
		{ 0x00, 0x00bb },
		{ 0x04, 0xb800 },
		{ 0x04, 0xb000 },

		{ 0x03, 0xdf41 },
		{ 0x02, 0xdc60 },
		{ 0x01, 0x6340 },
		{ 0x00, 0x007d },
		{ 0x04, 0xd800 },
		{ 0x04, 0xd000 },

		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x100a },
		{ 0x00, 0xa0ff },
		{ 0x04, 0xf800 },
		{ 0x04, 0xf000 },

		{ 0x1f, 0x0000 },
		{ 0x0b, 0x0000 },
		{ 0x00, 0x9200 }
	};
L
Linus Torvalds 已提交
2314

2315
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
L
Linus Torvalds 已提交
2316 2317
}

2318
static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2319
{
2320
	static const struct phy_reg phy_reg_init[] = {
F
Francois Romieu 已提交
2321 2322 2323 2324 2325
		{ 0x1f, 0x0002 },
		{ 0x01, 0x90d0 },
		{ 0x1f, 0x0000 }
	};

2326
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2327 2328
}

2329
static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2330 2331 2332
{
	struct pci_dev *pdev = tp->pci_dev;

2333 2334
	if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
	    (pdev->subsystem_device != 0xe000))
2335 2336
		return;

2337 2338 2339
	rtl_writephy(tp, 0x1f, 0x0001);
	rtl_writephy(tp, 0x10, 0xf01b);
	rtl_writephy(tp, 0x1f, 0x0000);
2340 2341
}

2342
static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2343
{
2344
	static const struct phy_reg phy_reg_init[] = {
2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383
		{ 0x1f, 0x0001 },
		{ 0x04, 0x0000 },
		{ 0x03, 0x00a1 },
		{ 0x02, 0x0008 },
		{ 0x01, 0x0120 },
		{ 0x00, 0x1000 },
		{ 0x04, 0x0800 },
		{ 0x04, 0x9000 },
		{ 0x03, 0x802f },
		{ 0x02, 0x4f02 },
		{ 0x01, 0x0409 },
		{ 0x00, 0xf099 },
		{ 0x04, 0x9800 },
		{ 0x04, 0xa000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0xff95 },
		{ 0x00, 0xba00 },
		{ 0x04, 0xa800 },
		{ 0x04, 0xf000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x101a },
		{ 0x00, 0xa0ff },
		{ 0x04, 0xf800 },
		{ 0x04, 0x0000 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x10, 0xf41b },
		{ 0x14, 0xfb54 },
		{ 0x18, 0xf5c7 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },
		{ 0x1f, 0x0000 }
	};

2384
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2385

2386
	rtl8169scd_hw_phy_config_quirk(tp);
2387 2388
}

2389
static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2390
{
2391
	static const struct phy_reg phy_reg_init[] = {
2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438
		{ 0x1f, 0x0001 },
		{ 0x04, 0x0000 },
		{ 0x03, 0x00a1 },
		{ 0x02, 0x0008 },
		{ 0x01, 0x0120 },
		{ 0x00, 0x1000 },
		{ 0x04, 0x0800 },
		{ 0x04, 0x9000 },
		{ 0x03, 0x802f },
		{ 0x02, 0x4f02 },
		{ 0x01, 0x0409 },
		{ 0x00, 0xf099 },
		{ 0x04, 0x9800 },
		{ 0x04, 0xa000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0xff95 },
		{ 0x00, 0xba00 },
		{ 0x04, 0xa800 },
		{ 0x04, 0xf000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x101a },
		{ 0x00, 0xa0ff },
		{ 0x04, 0xf800 },
		{ 0x04, 0x0000 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x0b, 0x8480 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x18, 0x67c7 },
		{ 0x04, 0x2000 },
		{ 0x03, 0x002f },
		{ 0x02, 0x4360 },
		{ 0x01, 0x0109 },
		{ 0x00, 0x3022 },
		{ 0x04, 0x2800 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },
		{ 0x1f, 0x0000 }
	};

2439
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2440 2441
}

2442
static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2443
{
2444
	static const struct phy_reg phy_reg_init[] = {
2445 2446 2447 2448
		{ 0x10, 0xf41b },
		{ 0x1f, 0x0000 }
	};

2449 2450
	rtl_writephy(tp, 0x1f, 0x0001);
	rtl_patchphy(tp, 0x16, 1 << 0);
2451

2452
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2453 2454
}

2455
static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2456
{
2457
	static const struct phy_reg phy_reg_init[] = {
2458 2459 2460 2461 2462
		{ 0x1f, 0x0001 },
		{ 0x10, 0xf41b },
		{ 0x1f, 0x0000 }
	};

2463
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2464 2465
}

2466
static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
F
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2467
{
2468
	static const struct phy_reg phy_reg_init[] = {
F
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2469 2470 2471 2472 2473 2474 2475
		{ 0x1f, 0x0000 },
		{ 0x1d, 0x0f00 },
		{ 0x1f, 0x0002 },
		{ 0x0c, 0x1ec8 },
		{ 0x1f, 0x0000 }
	};

2476
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
F
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2477 2478
}

2479
static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
F
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2480
{
2481
	static const struct phy_reg phy_reg_init[] = {
F
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2482 2483 2484 2485 2486
		{ 0x1f, 0x0001 },
		{ 0x1d, 0x3d98 },
		{ 0x1f, 0x0000 }
	};

2487 2488 2489
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_patchphy(tp, 0x14, 1 << 5);
	rtl_patchphy(tp, 0x0d, 1 << 5);
F
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2490

2491
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
F
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2492 2493
}

2494
static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
F
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2495
{
2496
	static const struct phy_reg phy_reg_init[] = {
2497 2498
		{ 0x1f, 0x0001 },
		{ 0x12, 0x2300 },
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2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509
		{ 0x1f, 0x0002 },
		{ 0x00, 0x88d4 },
		{ 0x01, 0x82b1 },
		{ 0x03, 0x7002 },
		{ 0x08, 0x9e30 },
		{ 0x09, 0x01f0 },
		{ 0x0a, 0x5500 },
		{ 0x0c, 0x00c8 },
		{ 0x1f, 0x0003 },
		{ 0x12, 0xc096 },
		{ 0x16, 0x000a },
2510 2511 2512 2513
		{ 0x1f, 0x0000 },
		{ 0x1f, 0x0000 },
		{ 0x09, 0x2000 },
		{ 0x09, 0x0000 }
F
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2514 2515
	};

2516
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2517

2518 2519 2520
	rtl_patchphy(tp, 0x14, 1 << 5);
	rtl_patchphy(tp, 0x0d, 1 << 5);
	rtl_writephy(tp, 0x1f, 0x0000);
F
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2521 2522
}

2523
static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2524
{
2525
	static const struct phy_reg phy_reg_init[] = {
2526
		{ 0x1f, 0x0001 },
2527
		{ 0x12, 0x2300 },
2528 2529 2530 2531 2532 2533 2534
		{ 0x03, 0x802f },
		{ 0x02, 0x4f02 },
		{ 0x01, 0x0409 },
		{ 0x00, 0xf099 },
		{ 0x04, 0x9800 },
		{ 0x04, 0x9000 },
		{ 0x1d, 0x3d98 },
2535 2536
		{ 0x1f, 0x0002 },
		{ 0x0c, 0x7eb8 },
2537 2538 2539
		{ 0x06, 0x0761 },
		{ 0x1f, 0x0003 },
		{ 0x16, 0x0f0a },
2540 2541 2542
		{ 0x1f, 0x0000 }
	};

2543
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2544

2545 2546 2547 2548
	rtl_patchphy(tp, 0x16, 1 << 0);
	rtl_patchphy(tp, 0x14, 1 << 5);
	rtl_patchphy(tp, 0x0d, 1 << 5);
	rtl_writephy(tp, 0x1f, 0x0000);
2549 2550
}

2551
static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
F
Francois Romieu 已提交
2552
{
2553
	static const struct phy_reg phy_reg_init[] = {
F
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2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564
		{ 0x1f, 0x0001 },
		{ 0x12, 0x2300 },
		{ 0x1d, 0x3d98 },
		{ 0x1f, 0x0002 },
		{ 0x0c, 0x7eb8 },
		{ 0x06, 0x5461 },
		{ 0x1f, 0x0003 },
		{ 0x16, 0x0f0a },
		{ 0x1f, 0x0000 }
	};

2565
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
F
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2566

2567 2568 2569 2570
	rtl_patchphy(tp, 0x16, 1 << 0);
	rtl_patchphy(tp, 0x14, 1 << 5);
	rtl_patchphy(tp, 0x0d, 1 << 5);
	rtl_writephy(tp, 0x1f, 0x0000);
F
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2571 2572
}

2573
static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2574
{
2575
	rtl8168c_3_hw_phy_config(tp);
2576 2577
}

2578
static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
F
Francois Romieu 已提交
2579
{
2580
	static const struct phy_reg phy_reg_init_0[] = {
2581
		/* Channel Estimation */
F
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2582
		{ 0x1f, 0x0001 },
2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593
		{ 0x06, 0x4064 },
		{ 0x07, 0x2863 },
		{ 0x08, 0x059c },
		{ 0x09, 0x26b4 },
		{ 0x0a, 0x6a19 },
		{ 0x0b, 0xdcc8 },
		{ 0x10, 0xf06d },
		{ 0x14, 0x7f68 },
		{ 0x18, 0x7fd9 },
		{ 0x1c, 0xf0ff },
		{ 0x1d, 0x3d9c },
F
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2594
		{ 0x1f, 0x0003 },
2595 2596 2597
		{ 0x12, 0xf49f },
		{ 0x13, 0x070b },
		{ 0x1a, 0x05ad },
2598 2599 2600 2601
		{ 0x14, 0x94c0 },

		/*
		 * Tx Error Issue
F
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2602
		 * Enhance line driver power
2603
		 */
F
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2604
		{ 0x1f, 0x0002 },
2605 2606 2607
		{ 0x06, 0x5561 },
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8332 },
2608 2609 2610 2611 2612 2613 2614 2615
		{ 0x06, 0x5561 },

		/*
		 * Can not link to 1Gbps with bad cable
		 * Decrease SNR threshold form 21.07dB to 19.04dB
		 */
		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },
2616

F
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2617
		{ 0x1f, 0x0000 },
2618
		{ 0x0d, 0xf880 }
2619
	};
2620
	void __iomem *ioaddr = tp->mmio_addr;
2621

2622
	rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2623

2624 2625 2626 2627
	/*
	 * Rx Error Issue
	 * Fine Tune Switching regulator parameter
	 */
2628 2629 2630
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
	rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2631 2632

	if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2633
		static const struct phy_reg phy_reg_init[] = {
2634 2635 2636 2637 2638 2639 2640 2641 2642
			{ 0x1f, 0x0002 },
			{ 0x05, 0x669a },
			{ 0x1f, 0x0005 },
			{ 0x05, 0x8330 },
			{ 0x06, 0x669a },
			{ 0x1f, 0x0002 }
		};
		int val;

2643
		rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2644

2645
		val = rtl_readphy(tp, 0x0d);
2646 2647

		if ((val & 0x00ff) != 0x006c) {
2648
			static const u32 set[] = {
2649 2650 2651 2652 2653
				0x0065, 0x0066, 0x0067, 0x0068,
				0x0069, 0x006a, 0x006b, 0x006c
			};
			int i;

2654
			rtl_writephy(tp, 0x1f, 0x0002);
2655 2656 2657

			val &= 0xff00;
			for (i = 0; i < ARRAY_SIZE(set); i++)
2658
				rtl_writephy(tp, 0x0d, val | set[i]);
2659 2660
		}
	} else {
2661
		static const struct phy_reg phy_reg_init[] = {
2662 2663 2664 2665 2666 2667 2668
			{ 0x1f, 0x0002 },
			{ 0x05, 0x6662 },
			{ 0x1f, 0x0005 },
			{ 0x05, 0x8330 },
			{ 0x06, 0x6662 }
		};

2669
		rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2670 2671
	}

2672
	/* RSET couple improve */
2673 2674 2675
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_patchphy(tp, 0x0d, 0x0300);
	rtl_patchphy(tp, 0x0f, 0x0010);
2676

2677
	/* Fine tune PLL performance */
2678 2679 2680
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
	rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2681

2682 2683
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x001b);
2684 2685

	rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2686

2687
	rtl_writephy(tp, 0x1f, 0x0000);
2688 2689
}

2690
static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2691
{
2692
	static const struct phy_reg phy_reg_init_0[] = {
2693
		/* Channel Estimation */
2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711
		{ 0x1f, 0x0001 },
		{ 0x06, 0x4064 },
		{ 0x07, 0x2863 },
		{ 0x08, 0x059c },
		{ 0x09, 0x26b4 },
		{ 0x0a, 0x6a19 },
		{ 0x0b, 0xdcc8 },
		{ 0x10, 0xf06d },
		{ 0x14, 0x7f68 },
		{ 0x18, 0x7fd9 },
		{ 0x1c, 0xf0ff },
		{ 0x1d, 0x3d9c },
		{ 0x1f, 0x0003 },
		{ 0x12, 0xf49f },
		{ 0x13, 0x070b },
		{ 0x1a, 0x05ad },
		{ 0x14, 0x94c0 },

2712 2713
		/*
		 * Tx Error Issue
F
Francois Romieu 已提交
2714
		 * Enhance line driver power
2715
		 */
2716 2717 2718 2719
		{ 0x1f, 0x0002 },
		{ 0x06, 0x5561 },
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8332 },
2720 2721 2722 2723 2724 2725 2726 2727
		{ 0x06, 0x5561 },

		/*
		 * Can not link to 1Gbps with bad cable
		 * Decrease SNR threshold form 21.07dB to 19.04dB
		 */
		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },
2728 2729

		{ 0x1f, 0x0000 },
2730
		{ 0x0d, 0xf880 }
F
Francois Romieu 已提交
2731
	};
2732
	void __iomem *ioaddr = tp->mmio_addr;
F
Francois Romieu 已提交
2733

2734
	rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
F
Francois Romieu 已提交
2735

2736
	if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2737
		static const struct phy_reg phy_reg_init[] = {
2738 2739
			{ 0x1f, 0x0002 },
			{ 0x05, 0x669a },
F
Francois Romieu 已提交
2740
			{ 0x1f, 0x0005 },
2741 2742 2743 2744 2745 2746 2747
			{ 0x05, 0x8330 },
			{ 0x06, 0x669a },

			{ 0x1f, 0x0002 }
		};
		int val;

2748
		rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2749

2750
		val = rtl_readphy(tp, 0x0d);
2751
		if ((val & 0x00ff) != 0x006c) {
J
Joe Perches 已提交
2752
			static const u32 set[] = {
2753 2754 2755 2756 2757
				0x0065, 0x0066, 0x0067, 0x0068,
				0x0069, 0x006a, 0x006b, 0x006c
			};
			int i;

2758
			rtl_writephy(tp, 0x1f, 0x0002);
2759 2760 2761

			val &= 0xff00;
			for (i = 0; i < ARRAY_SIZE(set); i++)
2762
				rtl_writephy(tp, 0x0d, val | set[i]);
2763 2764
		}
	} else {
2765
		static const struct phy_reg phy_reg_init[] = {
2766 2767
			{ 0x1f, 0x0002 },
			{ 0x05, 0x2642 },
F
Francois Romieu 已提交
2768
			{ 0x1f, 0x0005 },
2769 2770
			{ 0x05, 0x8330 },
			{ 0x06, 0x2642 }
F
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2771 2772
		};

2773
		rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
F
Francois Romieu 已提交
2774 2775
	}

2776
	/* Fine tune PLL performance */
2777 2778 2779
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
	rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2780

2781
	/* Switching regulator Slew rate */
2782 2783
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_patchphy(tp, 0x0f, 0x0017);
2784

2785 2786
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x001b);
2787 2788

	rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2789

2790
	rtl_writephy(tp, 0x1f, 0x0000);
2791 2792
}

2793
static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2794
{
2795
	static const struct phy_reg phy_reg_init[] = {
2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850
		{ 0x1f, 0x0002 },
		{ 0x10, 0x0008 },
		{ 0x0d, 0x006c },

		{ 0x1f, 0x0000 },
		{ 0x0d, 0xf880 },

		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },

		{ 0x1f, 0x0001 },
		{ 0x0b, 0xa4d8 },
		{ 0x09, 0x281c },
		{ 0x07, 0x2883 },
		{ 0x0a, 0x6b35 },
		{ 0x1d, 0x3da4 },
		{ 0x1c, 0xeffd },
		{ 0x14, 0x7f52 },
		{ 0x18, 0x7fc6 },
		{ 0x08, 0x0601 },
		{ 0x06, 0x4063 },
		{ 0x10, 0xf074 },
		{ 0x1f, 0x0003 },
		{ 0x13, 0x0789 },
		{ 0x12, 0xf4bd },
		{ 0x1a, 0x04fd },
		{ 0x14, 0x84b0 },
		{ 0x1f, 0x0000 },
		{ 0x00, 0x9200 },

		{ 0x1f, 0x0005 },
		{ 0x01, 0x0340 },
		{ 0x1f, 0x0001 },
		{ 0x04, 0x4000 },
		{ 0x03, 0x1d21 },
		{ 0x02, 0x0c32 },
		{ 0x01, 0x0200 },
		{ 0x00, 0x5554 },
		{ 0x04, 0x4800 },
		{ 0x04, 0x4000 },
		{ 0x04, 0xf000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x101a },
		{ 0x00, 0xa0ff },
		{ 0x04, 0xf800 },
		{ 0x04, 0xf000 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0007 },
		{ 0x1e, 0x0023 },
		{ 0x16, 0x0000 },
		{ 0x1f, 0x0000 }
	};

2851
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
F
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2852 2853
}

F
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2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869
static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
{
	static const struct phy_reg phy_reg_init[] = {
		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },

		{ 0x1f, 0x0007 },
		{ 0x1e, 0x002d },
		{ 0x18, 0x0040 },
		{ 0x1f, 0x0000 }
	};

	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
	rtl_patchphy(tp, 0x0d, 1 << 5);
}

H
Hayes Wang 已提交
2870
static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
H
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2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899
{
	static const struct phy_reg phy_reg_init[] = {
		/* Enable Delay cap */
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8b80 },
		{ 0x06, 0xc896 },
		{ 0x1f, 0x0000 },

		/* Channel estimation fine tune */
		{ 0x1f, 0x0001 },
		{ 0x0b, 0x6c20 },
		{ 0x07, 0x2872 },
		{ 0x1c, 0xefff },
		{ 0x1f, 0x0003 },
		{ 0x14, 0x6420 },
		{ 0x1f, 0x0000 },

		/* Update PFM & 10M TX idle timer */
		{ 0x1f, 0x0007 },
		{ 0x1e, 0x002f },
		{ 0x15, 0x1919 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0007 },
		{ 0x1e, 0x00ac },
		{ 0x18, 0x0006 },
		{ 0x1f, 0x0000 }
	};

F
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2900 2901
	rtl_apply_firmware(tp);

H
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2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));

	/* DCO enable for 10M IDLE Power */
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x0023);
	rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* For impedance matching */
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
F
Francois Romieu 已提交
2913
	rtl_writephy(tp, 0x1f, 0x0000);
H
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2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942

	/* PHY auto speed down */
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x002d);
	rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);

	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b86);
	rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b85);
	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x0020);
	rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
	rtl_writephy(tp, 0x1f, 0x0006);
	rtl_writephy(tp, 0x00, 0x5a00);
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, 0x0d, 0x0007);
	rtl_writephy(tp, 0x0e, 0x003c);
	rtl_writephy(tp, 0x0d, 0x4007);
	rtl_writephy(tp, 0x0e, 0x0000);
	rtl_writephy(tp, 0x0d, 0x0000);
}

H
Hayes Wang 已提交
2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011
static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
{
	static const struct phy_reg phy_reg_init[] = {
		/* Enable Delay cap */
		{ 0x1f, 0x0004 },
		{ 0x1f, 0x0007 },
		{ 0x1e, 0x00ac },
		{ 0x18, 0x0006 },
		{ 0x1f, 0x0002 },
		{ 0x1f, 0x0000 },
		{ 0x1f, 0x0000 },

		/* Channel estimation fine tune */
		{ 0x1f, 0x0003 },
		{ 0x09, 0xa20f },
		{ 0x1f, 0x0000 },
		{ 0x1f, 0x0000 },

		/* Green Setting */
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8b5b },
		{ 0x06, 0x9222 },
		{ 0x05, 0x8b6d },
		{ 0x06, 0x8000 },
		{ 0x05, 0x8b76 },
		{ 0x06, 0x8000 },
		{ 0x1f, 0x0000 }
	};

	rtl_apply_firmware(tp);

	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));

	/* For 4-corner performance improve */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b80);
	rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* PHY auto speed down */
	rtl_writephy(tp, 0x1f, 0x0004);
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x002d);
	rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);

	/* improve 10M EEE waveform */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b86);
	rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* Improve 2-pair detection performance */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b85);
	rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* EEE setting */
	rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
		     ERIAR_EXGMAC);
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b85);
	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
	rtl_writephy(tp, 0x1f, 0x0004);
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x0020);
3012
	rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
H
Hayes Wang 已提交
3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, 0x0d, 0x0007);
	rtl_writephy(tp, 0x0e, 0x003c);
	rtl_writephy(tp, 0x0d, 0x4007);
	rtl_writephy(tp, 0x0e, 0x0000);
	rtl_writephy(tp, 0x0d, 0x0000);

	/* Green feature */
	rtl_writephy(tp, 0x1f, 0x0003);
	rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
	rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
	rtl_writephy(tp, 0x1f, 0x0000);
}

3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118
static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
{
	static const struct phy_reg phy_reg_init[] = {
		/* Channel estimation fine tune */
		{ 0x1f, 0x0003 },
		{ 0x09, 0xa20f },
		{ 0x1f, 0x0000 },

		/* Modify green table for giga & fnet */
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8b55 },
		{ 0x06, 0x0000 },
		{ 0x05, 0x8b5e },
		{ 0x06, 0x0000 },
		{ 0x05, 0x8b67 },
		{ 0x06, 0x0000 },
		{ 0x05, 0x8b70 },
		{ 0x06, 0x0000 },
		{ 0x1f, 0x0000 },
		{ 0x1f, 0x0007 },
		{ 0x1e, 0x0078 },
		{ 0x17, 0x0000 },
		{ 0x19, 0x00fb },
		{ 0x1f, 0x0000 },

		/* Modify green table for 10M */
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8b79 },
		{ 0x06, 0xaa00 },
		{ 0x1f, 0x0000 },

		/* Disable hiimpedance detection (RTCT) */
		{ 0x1f, 0x0003 },
		{ 0x01, 0x328a },
		{ 0x1f, 0x0000 }
	};

	rtl_apply_firmware(tp);

	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));

	/* For 4-corner performance improve */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b80);
	rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* PHY auto speed down */
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x002d);
	rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);

	/* Improve 10M EEE waveform */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b86);
	rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* Improve 2-pair detection performance */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b85);
	rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);
}

static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
{
	rtl_apply_firmware(tp);

	/* For 4-corner performance improve */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b80);
	rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* PHY auto speed down */
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x002d);
	rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);

	/* Improve 10M EEE waveform */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b86);
	rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);
}

3119
static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3120
{
3121
	static const struct phy_reg phy_reg_init[] = {
3122 3123 3124 3125 3126 3127
		{ 0x1f, 0x0003 },
		{ 0x08, 0x441d },
		{ 0x01, 0x9100 },
		{ 0x1f, 0x0000 }
	};

3128 3129 3130 3131
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_patchphy(tp, 0x11, 1 << 12);
	rtl_patchphy(tp, 0x19, 1 << 13);
	rtl_patchphy(tp, 0x10, 1 << 15);
3132

3133
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3134 3135
}

3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156
static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
{
	static const struct phy_reg phy_reg_init[] = {
		{ 0x1f, 0x0005 },
		{ 0x1a, 0x0000 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0004 },
		{ 0x1c, 0x0000 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x15, 0x7701 },
		{ 0x1f, 0x0000 }
	};

	/* Disable ALDPS before ram code */
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, 0x18, 0x0310);
	msleep(100);

3157
	rtl_apply_firmware(tp);
3158 3159 3160 3161

	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
}

3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172
static void rtl_hw_phy_config(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl8169_print_mac_version(tp);

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_01:
		break;
	case RTL_GIGA_MAC_VER_02:
	case RTL_GIGA_MAC_VER_03:
3173
		rtl8169s_hw_phy_config(tp);
3174 3175
		break;
	case RTL_GIGA_MAC_VER_04:
3176
		rtl8169sb_hw_phy_config(tp);
3177
		break;
3178
	case RTL_GIGA_MAC_VER_05:
3179
		rtl8169scd_hw_phy_config(tp);
3180
		break;
3181
	case RTL_GIGA_MAC_VER_06:
3182
		rtl8169sce_hw_phy_config(tp);
3183
		break;
3184 3185 3186
	case RTL_GIGA_MAC_VER_07:
	case RTL_GIGA_MAC_VER_08:
	case RTL_GIGA_MAC_VER_09:
3187
		rtl8102e_hw_phy_config(tp);
3188
		break;
3189
	case RTL_GIGA_MAC_VER_11:
3190
		rtl8168bb_hw_phy_config(tp);
3191 3192
		break;
	case RTL_GIGA_MAC_VER_12:
3193
		rtl8168bef_hw_phy_config(tp);
3194 3195
		break;
	case RTL_GIGA_MAC_VER_17:
3196
		rtl8168bef_hw_phy_config(tp);
3197
		break;
F
Francois Romieu 已提交
3198
	case RTL_GIGA_MAC_VER_18:
3199
		rtl8168cp_1_hw_phy_config(tp);
F
Francois Romieu 已提交
3200 3201
		break;
	case RTL_GIGA_MAC_VER_19:
3202
		rtl8168c_1_hw_phy_config(tp);
F
Francois Romieu 已提交
3203
		break;
3204
	case RTL_GIGA_MAC_VER_20:
3205
		rtl8168c_2_hw_phy_config(tp);
3206
		break;
F
Francois Romieu 已提交
3207
	case RTL_GIGA_MAC_VER_21:
3208
		rtl8168c_3_hw_phy_config(tp);
F
Francois Romieu 已提交
3209
		break;
3210
	case RTL_GIGA_MAC_VER_22:
3211
		rtl8168c_4_hw_phy_config(tp);
3212
		break;
F
Francois Romieu 已提交
3213
	case RTL_GIGA_MAC_VER_23:
3214
	case RTL_GIGA_MAC_VER_24:
3215
		rtl8168cp_2_hw_phy_config(tp);
F
Francois Romieu 已提交
3216
		break;
F
Francois Romieu 已提交
3217
	case RTL_GIGA_MAC_VER_25:
3218
		rtl8168d_1_hw_phy_config(tp);
3219 3220
		break;
	case RTL_GIGA_MAC_VER_26:
3221
		rtl8168d_2_hw_phy_config(tp);
3222 3223
		break;
	case RTL_GIGA_MAC_VER_27:
3224
		rtl8168d_3_hw_phy_config(tp);
F
Francois Romieu 已提交
3225
		break;
F
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3226 3227 3228
	case RTL_GIGA_MAC_VER_28:
		rtl8168d_4_hw_phy_config(tp);
		break;
3229 3230 3231 3232
	case RTL_GIGA_MAC_VER_29:
	case RTL_GIGA_MAC_VER_30:
		rtl8105e_hw_phy_config(tp);
		break;
F
Francois Romieu 已提交
3233 3234 3235
	case RTL_GIGA_MAC_VER_31:
		/* None. */
		break;
H
hayeswang 已提交
3236 3237
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
H
Hayes Wang 已提交
3238 3239 3240 3241
		rtl8168e_1_hw_phy_config(tp);
		break;
	case RTL_GIGA_MAC_VER_34:
		rtl8168e_2_hw_phy_config(tp);
H
hayeswang 已提交
3242
		break;
3243 3244 3245 3246 3247 3248
	case RTL_GIGA_MAC_VER_35:
		rtl8168f_1_hw_phy_config(tp);
		break;
	case RTL_GIGA_MAC_VER_36:
		rtl8168f_2_hw_phy_config(tp);
		break;
F
Francois Romieu 已提交
3249

3250 3251 3252 3253 3254
	default:
		break;
	}
}

3255
static void rtl_phy_work(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
3256 3257 3258 3259 3260
{
	struct timer_list *timer = &tp->timer;
	void __iomem *ioaddr = tp->mmio_addr;
	unsigned long timeout = RTL8169_PHY_TIMEOUT;

3261
	assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
L
Linus Torvalds 已提交
3262

3263
	if (tp->phy_reset_pending(tp)) {
3264
		/*
L
Linus Torvalds 已提交
3265 3266 3267 3268 3269 3270 3271 3272
		 * A busy loop could burn quite a few cycles on nowadays CPU.
		 * Let's delay the execution of the timer for a few ticks.
		 */
		timeout = HZ/10;
		goto out_mod_timer;
	}

	if (tp->link_ok(ioaddr))
3273
		return;
L
Linus Torvalds 已提交
3274

3275
	netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
L
Linus Torvalds 已提交
3276

3277
	tp->phy_reset_enable(tp);
L
Linus Torvalds 已提交
3278 3279 3280

out_mod_timer:
	mod_timer(timer, jiffies + timeout);
3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293
}

static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
{
	if (!test_and_set_bit(flag, tp->wk.flags))
		schedule_work(&tp->wk.work);
}

static void rtl8169_phy_timer(unsigned long __opaque)
{
	struct net_device *dev = (struct net_device *)__opaque;
	struct rtl8169_private *tp = netdev_priv(dev);

3294
	rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
L
Linus Torvalds 已提交
3295 3296 3297 3298 3299 3300 3301
}

#ifdef CONFIG_NET_POLL_CONTROLLER
static void rtl8169_netpoll(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);

3302
	rtl8169_interrupt(tp->pci_dev->irq, dev);
L
Linus Torvalds 已提交
3303 3304 3305 3306 3307 3308 3309 3310
}
#endif

static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
				  void __iomem *ioaddr)
{
	iounmap(ioaddr);
	pci_release_regions(pdev);
3311
	pci_clear_mwi(pdev);
L
Linus Torvalds 已提交
3312 3313 3314 3315
	pci_disable_device(pdev);
	free_netdev(dev);
}

3316 3317 3318
static void rtl8169_phy_reset(struct net_device *dev,
			      struct rtl8169_private *tp)
{
F
Francois Romieu 已提交
3319
	unsigned int i;
3320

3321
	tp->phy_reset_enable(tp);
3322
	for (i = 0; i < 100; i++) {
3323
		if (!tp->phy_reset_pending(tp))
3324 3325 3326
			return;
		msleep(1);
	}
3327
	netif_err(tp, link, dev, "PHY reset failed\n");
3328 3329
}

3330 3331 3332 3333 3334 3335 3336 3337
static bool rtl_tbi_enabled(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
	    (RTL_R8(PHYstatus) & TBI_Enable);
}

3338 3339 3340 3341
static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

3342
	rtl_hw_phy_config(dev);
3343

3344 3345 3346 3347
	if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
		dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
		RTL_W8(0x82, 0x01);
	}
3348

3349 3350 3351 3352
	pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);

	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
		pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3353

3354
	if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3355 3356 3357
		dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
		RTL_W8(0x82, 0x01);
		dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3358
		rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3359 3360
	}

3361 3362
	rtl8169_phy_reset(dev, tp);

3363
	rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
F
Francois Romieu 已提交
3364 3365 3366 3367 3368
			  ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
			  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
			  (tp->mii.supports_gmii ?
			   ADVERTISED_1000baseT_Half |
			   ADVERTISED_1000baseT_Full : 0));
3369

3370
	if (rtl_tbi_enabled(tp))
3371
		netif_info(tp, link, dev, "TBI auto-negotiating\n");
3372 3373
}

3374 3375 3376 3377 3378 3379 3380 3381 3382
static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
{
	void __iomem *ioaddr = tp->mmio_addr;
	u32 high;
	u32 low;

	low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
	high = addr[4] | (addr[5] << 8);

3383
	rtl_lock_work(tp);
3384 3385

	RTL_W8(Cfg9346, Cfg9346_Unlock);
3386

3387
	RTL_W32(MAC4, high);
3388 3389
	RTL_R32(MAC4);

3390
	RTL_W32(MAC0, low);
3391 3392
	RTL_R32(MAC0);

3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404
	if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
		const struct exgmac_reg e[] = {
			{ .addr = 0xe0, ERIAR_MASK_1111, .val = low },
			{ .addr = 0xe4, ERIAR_MASK_1111, .val = high },
			{ .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
			{ .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
								low  >> 16 },
		};

		rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
	}

3405 3406
	RTL_W8(Cfg9346, Cfg9346_Lock);

3407
	rtl_unlock_work(tp);
3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424
}

static int rtl_set_mac_address(struct net_device *dev, void *p)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct sockaddr *addr = p;

	if (!is_valid_ether_addr(addr->sa_data))
		return -EADDRNOTAVAIL;

	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);

	rtl_rar_set(tp, dev->dev_addr);

	return 0;
}

3425 3426 3427 3428 3429
static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct mii_ioctl_data *data = if_mii(ifr);

F
Francois Romieu 已提交
3430 3431
	return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
}
3432

F
Francois Romieu 已提交
3433 3434
static int rtl_xmii_ioctl(struct rtl8169_private *tp,
			  struct mii_ioctl_data *data, int cmd)
F
Francois Romieu 已提交
3435
{
3436 3437 3438 3439 3440 3441
	switch (cmd) {
	case SIOCGMIIPHY:
		data->phy_id = 32; /* Internal PHY */
		return 0;

	case SIOCGMIIREG:
3442
		data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3443 3444 3445
		return 0;

	case SIOCSMIIREG:
3446
		rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3447 3448 3449 3450 3451
		return 0;
	}
	return -EOPNOTSUPP;
}

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static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
{
	return -EOPNOTSUPP;
}

3457 3458 3459 3460
static const struct rtl_cfg_info {
	void (*hw_start)(struct net_device *);
	unsigned int region;
	unsigned int align;
3461
	u16 event_slow;
3462
	unsigned features;
3463
	u8 default_ver;
3464 3465 3466 3467
} rtl_cfg_infos [] = {
	[RTL_CFG_0] = {
		.hw_start	= rtl_hw_start_8169,
		.region		= 1,
3468
		.align		= 0,
3469
		.event_slow	= SYSErr | LinkChg | RxOverflow | RxFIFOOver,
3470 3471
		.features	= RTL_FEATURE_GMII,
		.default_ver	= RTL_GIGA_MAC_VER_01,
3472 3473 3474 3475 3476
	},
	[RTL_CFG_1] = {
		.hw_start	= rtl_hw_start_8168,
		.region		= 2,
		.align		= 8,
3477
		.event_slow	= SYSErr | LinkChg | RxOverflow,
3478 3479
		.features	= RTL_FEATURE_GMII | RTL_FEATURE_MSI,
		.default_ver	= RTL_GIGA_MAC_VER_11,
3480 3481 3482 3483 3484
	},
	[RTL_CFG_2] = {
		.hw_start	= rtl_hw_start_8101,
		.region		= 2,
		.align		= 8,
3485 3486
		.event_slow	= SYSErr | LinkChg | RxOverflow | RxFIFOOver |
				  PCSTimeout,
3487 3488
		.features	= RTL_FEATURE_MSI,
		.default_ver	= RTL_GIGA_MAC_VER_13,
3489 3490 3491
	}
};

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3492
/* Cfg9346_Unlock assumed. */
3493
static unsigned rtl_try_msi(struct rtl8169_private *tp,
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3494 3495
			    const struct rtl_cfg_info *cfg)
{
3496
	void __iomem *ioaddr = tp->mmio_addr;
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3497 3498 3499 3500
	unsigned msi = 0;
	u8 cfg2;

	cfg2 = RTL_R8(Config2) & ~MSIEnable;
3501
	if (cfg->features & RTL_FEATURE_MSI) {
3502 3503
		if (pci_enable_msi(tp->pci_dev)) {
			netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
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3504 3505 3506 3507 3508
		} else {
			cfg2 |= MSIEnable;
			msi = RTL_FEATURE_MSI;
		}
	}
3509 3510
	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
		RTL_W8(Config2, cfg2);
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3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521
	return msi;
}

static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
{
	if (tp->features & RTL_FEATURE_MSI) {
		pci_disable_msi(pdev);
		tp->features &= ~RTL_FEATURE_MSI;
	}
}

3522 3523 3524 3525 3526 3527 3528 3529 3530
static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
{
	struct mdio_ops *ops = &tp->mdio_ops;

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_27:
		ops->write	= r8168dp_1_mdio_write;
		ops->read	= r8168dp_1_mdio_read;
		break;
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3531
	case RTL_GIGA_MAC_VER_28:
3532
	case RTL_GIGA_MAC_VER_31:
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3533 3534 3535
		ops->write	= r8168dp_2_mdio_write;
		ops->read	= r8168dp_2_mdio_read;
		break;
3536 3537 3538 3539 3540 3541 3542
	default:
		ops->write	= r8169_mdio_write;
		ops->read	= r8169_mdio_read;
		break;
	}
}

3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573
static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_29:
	case RTL_GIGA_MAC_VER_30:
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
	case RTL_GIGA_MAC_VER_34:
		RTL_W32(RxConfig, RTL_R32(RxConfig) |
			AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
		break;
	default:
		break;
	}
}

static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
{
	if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
		return false;

	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, MII_BMCR, 0x0000);

	rtl_wol_suspend_quirk(tp);

	return true;
}

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3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587
static void r810x_phy_power_down(struct rtl8169_private *tp)
{
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
}

static void r810x_phy_power_up(struct rtl8169_private *tp)
{
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
}

static void r810x_pll_power_down(struct rtl8169_private *tp)
{
3588
	if (rtl_wol_pll_power_down(tp))
F
françois romieu 已提交
3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601
		return;

	r810x_phy_power_down(tp);
}

static void r810x_pll_power_up(struct rtl8169_private *tp)
{
	r810x_phy_power_up(tp);
}

static void r8168_phy_power_up(struct rtl8169_private *tp)
{
	rtl_writephy(tp, 0x1f, 0x0000);
H
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3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_11:
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
	case RTL_GIGA_MAC_VER_18:
	case RTL_GIGA_MAC_VER_19:
	case RTL_GIGA_MAC_VER_20:
	case RTL_GIGA_MAC_VER_21:
	case RTL_GIGA_MAC_VER_22:
	case RTL_GIGA_MAC_VER_23:
	case RTL_GIGA_MAC_VER_24:
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
	case RTL_GIGA_MAC_VER_27:
	case RTL_GIGA_MAC_VER_28:
	case RTL_GIGA_MAC_VER_31:
		rtl_writephy(tp, 0x0e, 0x0000);
		break;
	default:
		break;
	}
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3623 3624 3625 3626 3627 3628
	rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
}

static void r8168_phy_power_down(struct rtl8169_private *tp)
{
	rtl_writephy(tp, 0x1f, 0x0000);
H
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3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
		rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
		break;

	case RTL_GIGA_MAC_VER_11:
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
	case RTL_GIGA_MAC_VER_18:
	case RTL_GIGA_MAC_VER_19:
	case RTL_GIGA_MAC_VER_20:
	case RTL_GIGA_MAC_VER_21:
	case RTL_GIGA_MAC_VER_22:
	case RTL_GIGA_MAC_VER_23:
	case RTL_GIGA_MAC_VER_24:
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
	case RTL_GIGA_MAC_VER_27:
	case RTL_GIGA_MAC_VER_28:
	case RTL_GIGA_MAC_VER_31:
		rtl_writephy(tp, 0x0e, 0x0200);
	default:
		rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
		break;
	}
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3655 3656 3657 3658 3659 3660
}

static void r8168_pll_power_down(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

F
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	if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
	     tp->mac_version == RTL_GIGA_MAC_VER_28 ||
	     tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3664
	    r8168dp_check_dash(tp)) {
F
françois romieu 已提交
3665
		return;
3666
	}
F
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3667

F
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3668 3669
	if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
	     tp->mac_version == RTL_GIGA_MAC_VER_24) &&
F
françois romieu 已提交
3670 3671 3672 3673
	    (RTL_R16(CPlusCmd) & ASF)) {
		return;
	}

H
hayeswang 已提交
3674 3675 3676 3677
	if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_33)
		rtl_ephy_write(ioaddr, 0x19, 0xff64);

3678
	if (rtl_wol_pll_power_down(tp))
F
françois romieu 已提交
3679 3680 3681 3682 3683 3684 3685
		return;

	r8168_phy_power_down(tp);

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
3686 3687
	case RTL_GIGA_MAC_VER_27:
	case RTL_GIGA_MAC_VER_28:
3688
	case RTL_GIGA_MAC_VER_31:
H
hayeswang 已提交
3689 3690
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
F
françois romieu 已提交
3691 3692 3693 3694 3695 3696 3697 3698 3699
		RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
		break;
	}
}

static void r8168_pll_power_up(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

F
Francois Romieu 已提交
3700 3701 3702
	if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
	     tp->mac_version == RTL_GIGA_MAC_VER_28 ||
	     tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3703
	    r8168dp_check_dash(tp)) {
F
françois romieu 已提交
3704
		return;
3705
	}
F
françois romieu 已提交
3706 3707 3708 3709

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
3710 3711
	case RTL_GIGA_MAC_VER_27:
	case RTL_GIGA_MAC_VER_28:
3712
	case RTL_GIGA_MAC_VER_31:
H
hayeswang 已提交
3713 3714
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
F
françois romieu 已提交
3715 3716 3717 3718 3719 3720 3721
		RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
		break;
	}

	r8168_phy_power_up(tp);
}

F
Francois Romieu 已提交
3722 3723
static void rtl_generic_op(struct rtl8169_private *tp,
			   void (*op)(struct rtl8169_private *))
F
françois romieu 已提交
3724 3725 3726 3727 3728 3729 3730
{
	if (op)
		op(tp);
}

static void rtl_pll_power_down(struct rtl8169_private *tp)
{
F
Francois Romieu 已提交
3731
	rtl_generic_op(tp, tp->pll_power_ops.down);
F
françois romieu 已提交
3732 3733 3734 3735
}

static void rtl_pll_power_up(struct rtl8169_private *tp)
{
F
Francois Romieu 已提交
3736
	rtl_generic_op(tp, tp->pll_power_ops.up);
F
françois romieu 已提交
3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748
}

static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
{
	struct pll_power_ops *ops = &tp->pll_power_ops;

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_07:
	case RTL_GIGA_MAC_VER_08:
	case RTL_GIGA_MAC_VER_09:
	case RTL_GIGA_MAC_VER_10:
	case RTL_GIGA_MAC_VER_16:
3749 3750
	case RTL_GIGA_MAC_VER_29:
	case RTL_GIGA_MAC_VER_30:
F
françois romieu 已提交
3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767
		ops->down	= r810x_pll_power_down;
		ops->up		= r810x_pll_power_up;
		break;

	case RTL_GIGA_MAC_VER_11:
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
	case RTL_GIGA_MAC_VER_18:
	case RTL_GIGA_MAC_VER_19:
	case RTL_GIGA_MAC_VER_20:
	case RTL_GIGA_MAC_VER_21:
	case RTL_GIGA_MAC_VER_22:
	case RTL_GIGA_MAC_VER_23:
	case RTL_GIGA_MAC_VER_24:
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
	case RTL_GIGA_MAC_VER_27:
F
françois romieu 已提交
3768
	case RTL_GIGA_MAC_VER_28:
3769
	case RTL_GIGA_MAC_VER_31:
H
hayeswang 已提交
3770 3771
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
H
Hayes Wang 已提交
3772
	case RTL_GIGA_MAC_VER_34:
3773 3774
	case RTL_GIGA_MAC_VER_35:
	case RTL_GIGA_MAC_VER_36:
F
françois romieu 已提交
3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785
		ops->down	= r8168_pll_power_down;
		ops->up		= r8168_pll_power_up;
		break;

	default:
		ops->down	= NULL;
		ops->up		= NULL;
		break;
	}
}

3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821
static void rtl_init_rxcfg(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_01:
	case RTL_GIGA_MAC_VER_02:
	case RTL_GIGA_MAC_VER_03:
	case RTL_GIGA_MAC_VER_04:
	case RTL_GIGA_MAC_VER_05:
	case RTL_GIGA_MAC_VER_06:
	case RTL_GIGA_MAC_VER_10:
	case RTL_GIGA_MAC_VER_11:
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_13:
	case RTL_GIGA_MAC_VER_14:
	case RTL_GIGA_MAC_VER_15:
	case RTL_GIGA_MAC_VER_16:
	case RTL_GIGA_MAC_VER_17:
		RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
		break;
	case RTL_GIGA_MAC_VER_18:
	case RTL_GIGA_MAC_VER_19:
	case RTL_GIGA_MAC_VER_20:
	case RTL_GIGA_MAC_VER_21:
	case RTL_GIGA_MAC_VER_22:
	case RTL_GIGA_MAC_VER_23:
	case RTL_GIGA_MAC_VER_24:
		RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
		break;
	default:
		RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
		break;
	}
}

3822 3823 3824 3825 3826
static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
{
	tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
}

F
Francois Romieu 已提交
3827 3828
static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
{
3829 3830 3831
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Cfg9346, Cfg9346_Unlock);
F
Francois Romieu 已提交
3832
	rtl_generic_op(tp, tp->jumbo_ops.enable);
3833
	RTL_W8(Cfg9346, Cfg9346_Lock);
F
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3834 3835 3836 3837
}

static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
{
3838 3839 3840
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Cfg9346, Cfg9346_Unlock);
F
Francois Romieu 已提交
3841
	rtl_generic_op(tp, tp->jumbo_ops.disable);
3842
	RTL_W8(Cfg9346, Cfg9346_Lock);
F
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3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883
}

static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
	RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
	rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
}

static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
	RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
	rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
}

static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
}

static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
}

static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(MaxTxPacketSize, 0x3f);
	RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
	RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3884
	rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
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3885 3886 3887 3888 3889 3890 3891 3892 3893
}

static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(MaxTxPacketSize, 0x0c);
	RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
	RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3894
	rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
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Francois Romieu 已提交
3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976
}

static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
{
	rtl_tx_performance_tweak(tp->pci_dev,
		(0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
}

static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
{
	rtl_tx_performance_tweak(tp->pci_dev,
		(0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
}

static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	r8168b_0_hw_jumbo_enable(tp);

	RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
}

static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	r8168b_0_hw_jumbo_disable(tp);

	RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
}

static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
{
	struct jumbo_ops *ops = &tp->jumbo_ops;

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_11:
		ops->disable	= r8168b_0_hw_jumbo_disable;
		ops->enable	= r8168b_0_hw_jumbo_enable;
		break;
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
		ops->disable	= r8168b_1_hw_jumbo_disable;
		ops->enable	= r8168b_1_hw_jumbo_enable;
		break;
	case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
	case RTL_GIGA_MAC_VER_19:
	case RTL_GIGA_MAC_VER_20:
	case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
	case RTL_GIGA_MAC_VER_22:
	case RTL_GIGA_MAC_VER_23:
	case RTL_GIGA_MAC_VER_24:
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
		ops->disable	= r8168c_hw_jumbo_disable;
		ops->enable	= r8168c_hw_jumbo_enable;
		break;
	case RTL_GIGA_MAC_VER_27:
	case RTL_GIGA_MAC_VER_28:
		ops->disable	= r8168dp_hw_jumbo_disable;
		ops->enable	= r8168dp_hw_jumbo_enable;
		break;
	case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
	case RTL_GIGA_MAC_VER_34:
		ops->disable	= r8168e_hw_jumbo_disable;
		ops->enable	= r8168e_hw_jumbo_enable;
		break;

	/*
	 * No action needed for jumbo frames with 8169.
	 * No jumbo for 810x at all.
	 */
	default:
		ops->disable	= NULL;
		ops->enable	= NULL;
		break;
	}
}

3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988
static void rtl_hw_reset(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;
	int i;

	/* Soft reset the chip. */
	RTL_W8(ChipCmd, CmdReset);

	/* Check that the chip has finished the reset. */
	for (i = 0; i < 100; i++) {
		if ((RTL_R8(ChipCmd) & CmdReset) == 0)
			break;
3989
		udelay(100);
3990 3991 3992
	}
}

3993
static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3994
{
3995 3996 3997
	struct rtl_fw *rtl_fw;
	const char *name;
	int rc = -ENOMEM;
3998

3999 4000 4001
	name = rtl_lookup_firmware_name(tp);
	if (!name)
		goto out_no_firmware;
4002

4003 4004 4005
	rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
	if (!rtl_fw)
		goto err_warn;
4006

4007 4008 4009 4010
	rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
	if (rc < 0)
		goto err_free;

4011 4012 4013 4014
	rc = rtl_check_firmware(tp, rtl_fw);
	if (rc < 0)
		goto err_release_firmware;

4015 4016 4017 4018
	tp->rtl_fw = rtl_fw;
out:
	return;

4019 4020
err_release_firmware:
	release_firmware(rtl_fw->fw);
4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034
err_free:
	kfree(rtl_fw);
err_warn:
	netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
		   name, rc);
out_no_firmware:
	tp->rtl_fw = NULL;
	goto out;
}

static void rtl_request_firmware(struct rtl8169_private *tp)
{
	if (IS_ERR(tp->rtl_fw))
		rtl_request_uncached_firmware(tp);
4035 4036
}

4037 4038
static void rtl_task(struct work_struct *);

L
Linus Torvalds 已提交
4039 4040 4041
static int rtl8169_open(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
4042
	void __iomem *ioaddr = tp->mmio_addr;
L
Linus Torvalds 已提交
4043
	struct pci_dev *pdev = tp->pci_dev;
4044
	int retval = -ENOMEM;
L
Linus Torvalds 已提交
4045

4046
	pm_runtime_get_sync(&pdev->dev);
L
Linus Torvalds 已提交
4047 4048 4049

	/*
	 * Rx and Tx desscriptors needs 256 bytes alignment.
4050
	 * dma_alloc_coherent provides more.
L
Linus Torvalds 已提交
4051
	 */
4052 4053
	tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
					     &tp->TxPhyAddr, GFP_KERNEL);
L
Linus Torvalds 已提交
4054
	if (!tp->TxDescArray)
4055
		goto err_pm_runtime_put;
L
Linus Torvalds 已提交
4056

4057 4058
	tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
					     &tp->RxPhyAddr, GFP_KERNEL);
L
Linus Torvalds 已提交
4059
	if (!tp->RxDescArray)
4060
		goto err_free_tx_0;
L
Linus Torvalds 已提交
4061 4062 4063

	retval = rtl8169_init_ring(dev);
	if (retval < 0)
4064
		goto err_free_rx_1;
L
Linus Torvalds 已提交
4065

4066
	INIT_WORK(&tp->wk.work, rtl_task);
L
Linus Torvalds 已提交
4067

4068 4069
	smp_mb();

4070 4071
	rtl_request_firmware(tp);

F
Francois Romieu 已提交
4072 4073
	retval = request_irq(dev->irq, rtl8169_interrupt,
			     (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
4074 4075
			     dev->name, dev);
	if (retval < 0)
4076
		goto err_release_fw_2;
4077

4078 4079
	rtl_lock_work(tp);

4080
	set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4081

4082 4083
	napi_enable(&tp->napi);

4084 4085
	rtl8169_init_phy(dev, tp);

4086
	__rtl8169_set_features(dev, dev->features);
4087

F
françois romieu 已提交
4088 4089
	rtl_pll_power_up(tp);

4090
	rtl_hw_start(dev);
L
Linus Torvalds 已提交
4091

4092 4093 4094 4095
	netif_start_queue(dev);

	rtl_unlock_work(tp);

4096 4097 4098
	tp->saved_wolopts = 0;
	pm_runtime_put_noidle(&pdev->dev);

4099
	rtl8169_check_link_status(dev, tp, ioaddr);
L
Linus Torvalds 已提交
4100 4101 4102
out:
	return retval;

4103 4104
err_release_fw_2:
	rtl_release_firmware(tp);
4105 4106
	rtl8169_rx_clear(tp);
err_free_rx_1:
4107 4108
	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
			  tp->RxPhyAddr);
4109
	tp->RxDescArray = NULL;
4110
err_free_tx_0:
4111 4112
	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
			  tp->TxPhyAddr);
4113 4114 4115
	tp->TxDescArray = NULL;
err_pm_runtime_put:
	pm_runtime_put_noidle(&pdev->dev);
L
Linus Torvalds 已提交
4116 4117 4118
	goto out;
}

4119 4120 4121 4122
static void rtl_rx_close(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

4123
	RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4124 4125
}

F
françois romieu 已提交
4126
static void rtl8169_hw_reset(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
4127
{
F
françois romieu 已提交
4128 4129
	void __iomem *ioaddr = tp->mmio_addr;

L
Linus Torvalds 已提交
4130
	/* Disable interrupts */
F
françois romieu 已提交
4131
	rtl8169_irq_mask_and_ack(tp);
L
Linus Torvalds 已提交
4132

4133 4134
	rtl_rx_close(tp);

4135
	if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4136 4137
	    tp->mac_version == RTL_GIGA_MAC_VER_28 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_31) {
F
françois romieu 已提交
4138 4139
		while (RTL_R8(TxPoll) & NPQ)
			udelay(20);
4140 4141 4142
	} else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
	           tp->mac_version == RTL_GIGA_MAC_VER_35 ||
	           tp->mac_version == RTL_GIGA_MAC_VER_36) {
4143
		RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
H
Hayes Wang 已提交
4144 4145
		while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
			udelay(100);
4146 4147 4148
	} else {
		RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
		udelay(100);
F
françois romieu 已提交
4149 4150
	}

4151
	rtl_hw_reset(tp);
L
Linus Torvalds 已提交
4152 4153
}

4154
static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4155 4156 4157 4158 4159 4160 4161 4162
{
	void __iomem *ioaddr = tp->mmio_addr;

	/* Set DMA burst size and Interframe Gap Time */
	RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
		(InterFrameGap << TxInterFrameGapShift));
}

4163
static void rtl_hw_start(struct net_device *dev)
L
Linus Torvalds 已提交
4164 4165 4166
{
	struct rtl8169_private *tp = netdev_priv(dev);

4167 4168
	tp->hw_start(dev);

4169
	rtl_irq_enable_all(tp);
4170 4171
}

4172 4173 4174 4175 4176 4177 4178 4179 4180
static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
					 void __iomem *ioaddr)
{
	/*
	 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
	 * register to be written before TxDescAddrLow to work.
	 * Switching from MMIO to I/O access fixes the issue as well.
	 */
	RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4181
	RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4182
	RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4183
	RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194
}

static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
{
	u16 cmd;

	cmd = RTL_R16(CPlusCmd);
	RTL_W16(CPlusCmd, cmd);
	return cmd;
}

4195
static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4196 4197
{
	/* Low hurts. Let's disable the filtering. */
4198
	RTL_W16(RxMaxSize, rx_buf_sz + 1);
4199 4200
}

4201 4202
static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
{
4203
	static const struct rtl_cfg2_info {
4204 4205 4206 4207 4208 4209 4210 4211
		u32 mac_version;
		u32 clk;
		u32 val;
	} cfg2_info [] = {
		{ RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
		{ RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
		{ RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
		{ RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4212 4213
	};
	const struct rtl_cfg2_info *p = cfg2_info;
4214 4215 4216 4217
	unsigned int i;
	u32 clk;

	clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4218
	for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4219 4220 4221 4222 4223 4224 4225
		if ((p->mac_version == mac_version) && (p->clk == clk)) {
			RTL_W32(0x7c, p->val);
			break;
		}
	}
}

4226 4227 4228 4229 4230 4231
static void rtl_hw_start_8169(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

4232 4233 4234 4235 4236
	if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
		RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
	}

L
Linus Torvalds 已提交
4237
	RTL_W8(Cfg9346, Cfg9346_Unlock);
F
Francois Romieu 已提交
4238 4239 4240 4241
	if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_02 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_03 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_04)
4242 4243
		RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);

4244 4245
	rtl_init_rxcfg(tp);

4246
	RTL_W8(EarlyTxThres, NoEarlyTx);
L
Linus Torvalds 已提交
4247

E
Eric Dumazet 已提交
4248
	rtl_set_rx_max_size(ioaddr, rx_buf_sz);
L
Linus Torvalds 已提交
4249

F
Francois Romieu 已提交
4250 4251 4252 4253
	if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_02 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_03 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_04)
4254
		rtl_set_rx_tx_config_registers(tp);
L
Linus Torvalds 已提交
4255

4256
	tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
L
Linus Torvalds 已提交
4257

F
Francois Romieu 已提交
4258 4259
	if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_03) {
4260
		dprintk("Set MAC Reg C+CR Offset 0xE0. "
L
Linus Torvalds 已提交
4261
			"Bit-3 and bit-14 MUST be 1\n");
4262
		tp->cp_cmd |= (1 << 14);
L
Linus Torvalds 已提交
4263 4264
	}

4265 4266
	RTL_W16(CPlusCmd, tp->cp_cmd);

4267 4268
	rtl8169_set_magic_reg(ioaddr, tp->mac_version);

L
Linus Torvalds 已提交
4269 4270 4271 4272 4273 4274
	/*
	 * Undocumented corner. Supposedly:
	 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
	 */
	RTL_W16(IntrMitigate, 0x0000);

4275
	rtl_set_rx_tx_desc_registers(tp, ioaddr);
4276

F
Francois Romieu 已提交
4277 4278 4279 4280
	if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
	    tp->mac_version != RTL_GIGA_MAC_VER_02 &&
	    tp->mac_version != RTL_GIGA_MAC_VER_03 &&
	    tp->mac_version != RTL_GIGA_MAC_VER_04) {
4281 4282 4283 4284
		RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
		rtl_set_rx_tx_config_registers(tp);
	}

L
Linus Torvalds 已提交
4285
	RTL_W8(Cfg9346, Cfg9346_Lock);
F
Francois Romieu 已提交
4286 4287 4288

	/* Initially a 10 us delay. Turned it into a PCI commit. - FR */
	RTL_R8(IntrMask);
L
Linus Torvalds 已提交
4289 4290 4291

	RTL_W32(RxMissed, 0);

4292
	rtl_set_rx_mode(dev);
L
Linus Torvalds 已提交
4293 4294 4295

	/* no early-rx interrupts */
	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4296
}
L
Linus Torvalds 已提交
4297

4298
static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4299 4300 4301 4302
{
	u32 csi;

	csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4303 4304 4305
	rtl_csi_write(ioaddr, 0x070c, csi | bits);
}

F
françois romieu 已提交
4306 4307 4308 4309 4310
static void rtl_csi_access_enable_1(void __iomem *ioaddr)
{
	rtl_csi_access_enable(ioaddr, 0x17000000);
}

4311 4312 4313
static void rtl_csi_access_enable_2(void __iomem *ioaddr)
{
	rtl_csi_access_enable(ioaddr, 0x27000000);
4314 4315 4316 4317 4318 4319 4320 4321
}

struct ephy_info {
	unsigned int offset;
	u16 mask;
	u16 bits;
};

4322
static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4323 4324 4325 4326 4327 4328 4329 4330 4331 4332
{
	u16 w;

	while (len-- > 0) {
		w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
		rtl_ephy_write(ioaddr, e->offset, w);
		e++;
	}
}

4333 4334
static void rtl_disable_clock_request(struct pci_dev *pdev)
{
4335
	int cap = pci_pcie_cap(pdev);
4336 4337 4338 4339 4340 4341 4342 4343 4344 4345

	if (cap) {
		u16 ctl;

		pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
		ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
		pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
	}
}

F
françois romieu 已提交
4346 4347
static void rtl_enable_clock_request(struct pci_dev *pdev)
{
4348
	int cap = pci_pcie_cap(pdev);
F
françois romieu 已提交
4349 4350 4351 4352 4353 4354 4355 4356 4357 4358

	if (cap) {
		u16 ctl;

		pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
		ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
		pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
	}
}

4359 4360 4361 4362 4363 4364 4365 4366 4367 4368 4369
#define R8168_CPCMD_QUIRK_MASK (\
	EnableBist | \
	Mac_dbgo_oe | \
	Force_half_dup | \
	Force_rxflow_en | \
	Force_txflow_en | \
	Cxpl_dbg_sel | \
	ASF | \
	PktCntrDisable | \
	Mac_dbgo_sel)

4370 4371
static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
{
4372 4373 4374 4375
	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);

4376 4377
	rtl_tx_performance_tweak(pdev,
		(0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4378 4379 4380 4381 4382
}

static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
{
	rtl_hw_start_8168bb(ioaddr, pdev);
4383

4384
	RTL_W8(MaxTxPacketSize, TxPacketMax);
4385 4386

	RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4387 4388 4389 4390
}

static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
{
4391 4392 4393 4394
	RTL_W8(Config1, RTL_R8(Config1) | Speed_down);

	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

4395
	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4396 4397 4398 4399

	rtl_disable_clock_request(pdev);

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4400 4401
}

F
Francois Romieu 已提交
4402
static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4403
{
4404
	static const struct ephy_info e_info_8168cp[] = {
4405 4406 4407 4408 4409 4410 4411
		{ 0x01, 0,	0x0001 },
		{ 0x02, 0x0800,	0x1000 },
		{ 0x03, 0,	0x0042 },
		{ 0x06, 0x0080,	0x0000 },
		{ 0x07, 0,	0x2000 }
	};

4412
	rtl_csi_access_enable_2(ioaddr);
4413 4414 4415

	rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));

4416 4417 4418
	__rtl_hw_start_8168cp(ioaddr, pdev);
}

F
Francois Romieu 已提交
4419 4420
static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
{
4421
	rtl_csi_access_enable_2(ioaddr);
F
Francois Romieu 已提交
4422 4423 4424 4425 4426 4427 4428 4429

	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
}

4430 4431
static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
{
4432
	rtl_csi_access_enable_2(ioaddr);
4433 4434 4435 4436 4437 4438

	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

	/* Magic. */
	RTL_W8(DBG_REG, 0x20);

4439
	RTL_W8(MaxTxPacketSize, TxPacketMax);
4440 4441 4442 4443 4444 4445

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
}

4446 4447
static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
{
4448
	static const struct ephy_info e_info_8168c_1[] = {
4449 4450 4451 4452 4453
		{ 0x02, 0x0800,	0x1000 },
		{ 0x03, 0,	0x0002 },
		{ 0x06, 0x0080,	0x0000 }
	};

4454
	rtl_csi_access_enable_2(ioaddr);
4455 4456 4457 4458 4459

	RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);

	rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));

4460 4461 4462 4463 4464
	__rtl_hw_start_8168cp(ioaddr, pdev);
}

static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
{
4465
	static const struct ephy_info e_info_8168c_2[] = {
4466 4467 4468 4469
		{ 0x01, 0,	0x0001 },
		{ 0x03, 0x0400,	0x0220 }
	};

4470
	rtl_csi_access_enable_2(ioaddr);
4471 4472 4473

	rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));

4474 4475 4476
	__rtl_hw_start_8168cp(ioaddr, pdev);
}

F
Francois Romieu 已提交
4477 4478 4479 4480 4481
static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
{
	rtl_hw_start_8168c_2(ioaddr, pdev);
}

4482 4483
static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
{
4484
	rtl_csi_access_enable_2(ioaddr);
4485 4486 4487 4488

	__rtl_hw_start_8168cp(ioaddr, pdev);
}

F
Francois Romieu 已提交
4489 4490
static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
{
4491
	rtl_csi_access_enable_2(ioaddr);
F
Francois Romieu 已提交
4492 4493 4494

	rtl_disable_clock_request(pdev);

4495
	RTL_W8(MaxTxPacketSize, TxPacketMax);
F
Francois Romieu 已提交
4496 4497 4498 4499 4500 4501

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
}

4502 4503 4504 4505 4506 4507 4508 4509 4510 4511 4512
static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
{
	rtl_csi_access_enable_1(ioaddr);

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	RTL_W8(MaxTxPacketSize, TxPacketMax);

	rtl_disable_clock_request(pdev);
}

F
françois romieu 已提交
4513 4514 4515 4516 4517 4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538
static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
{
	static const struct ephy_info e_info_8168d_4[] = {
		{ 0x0b, ~0,	0x48 },
		{ 0x19, 0x20,	0x50 },
		{ 0x0c, ~0,	0x20 }
	};
	int i;

	rtl_csi_access_enable_1(ioaddr);

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	RTL_W8(MaxTxPacketSize, TxPacketMax);

	for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
		const struct ephy_info *e = e_info_8168d_4 + i;
		u16 w;

		w = rtl_ephy_read(ioaddr, e->offset);
		rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
	}

	rtl_enable_clock_request(pdev);
}

H
Hayes Wang 已提交
4539
static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
H
hayeswang 已提交
4540
{
H
Hayes Wang 已提交
4541
	static const struct ephy_info e_info_8168e_1[] = {
H
hayeswang 已提交
4542 4543 4544 4545 4546 4547 4548 4549 4550 4551 4552 4553 4554 4555 4556 4557 4558
		{ 0x00, 0x0200,	0x0100 },
		{ 0x00, 0x0000,	0x0004 },
		{ 0x06, 0x0002,	0x0001 },
		{ 0x06, 0x0000,	0x0030 },
		{ 0x07, 0x0000,	0x2000 },
		{ 0x00, 0x0000,	0x0020 },
		{ 0x03, 0x5800,	0x2000 },
		{ 0x03, 0x0000,	0x0001 },
		{ 0x01, 0x0800,	0x1000 },
		{ 0x07, 0x0000,	0x4000 },
		{ 0x1e, 0x0000,	0x2000 },
		{ 0x19, 0xffff,	0xfe6c },
		{ 0x0a, 0x0000,	0x0040 }
	};

	rtl_csi_access_enable_2(ioaddr);

H
Hayes Wang 已提交
4559
	rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
H
hayeswang 已提交
4560 4561 4562 4563 4564 4565 4566 4567

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	RTL_W8(MaxTxPacketSize, TxPacketMax);

	rtl_disable_clock_request(pdev);

	/* Reset tx FIFO pointer */
F
Francois Romieu 已提交
4568 4569
	RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
	RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
H
hayeswang 已提交
4570

F
Francois Romieu 已提交
4571
	RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
H
hayeswang 已提交
4572 4573
}

H
Hayes Wang 已提交
4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596
static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
{
	static const struct ephy_info e_info_8168e_2[] = {
		{ 0x09, 0x0000,	0x0080 },
		{ 0x19, 0x0000,	0x0224 }
	};

	rtl_csi_access_enable_1(ioaddr);

	rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
	rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
	rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
	rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
	rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
	rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
		     ERIAR_EXGMAC);

4597
	RTL_W8(MaxTxPacketSize, EarlySize);
H
Hayes Wang 已提交
4598 4599 4600 4601 4602 4603 4604 4605 4606 4607 4608 4609 4610 4611

	rtl_disable_clock_request(pdev);

	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
	RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);

	/* Adjust EEE LED frequency */
	RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);

	RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
	RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
	RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
}

4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654
static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
{
	static const struct ephy_info e_info_8168f_1[] = {
		{ 0x06, 0x00c0,	0x0020 },
		{ 0x08, 0x0001,	0x0002 },
		{ 0x09, 0x0000,	0x0080 },
		{ 0x19, 0x0000,	0x0224 }
	};

	rtl_csi_access_enable_1(ioaddr);

	rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
	rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
	rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
	rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
	rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
	rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
	rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
	rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
	rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
		     ERIAR_EXGMAC);

	RTL_W8(MaxTxPacketSize, EarlySize);

	rtl_disable_clock_request(pdev);

	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
	RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);

	/* Adjust EEE LED frequency */
	RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);

	RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
	RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
	RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
}

4655 4656
static void rtl_hw_start_8168(struct net_device *dev)
{
4657 4658
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
4659
	struct pci_dev *pdev = tp->pci_dev;
4660 4661 4662

	RTL_W8(Cfg9346, Cfg9346_Unlock);

4663
	RTL_W8(MaxTxPacketSize, TxPacketMax);
4664

E
Eric Dumazet 已提交
4665
	rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4666

4667
	tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4668 4669 4670

	RTL_W16(CPlusCmd, tp->cp_cmd);

4671
	RTL_W16(IntrMitigate, 0x5151);
4672

4673
	/* Work around for RxFIFO overflow. */
F
françois romieu 已提交
4674
	if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4675 4676
		tp->event_slow |= RxFIFOOver | PCSTimeout;
		tp->event_slow &= ~RxOverflow;
4677 4678 4679
	}

	rtl_set_rx_tx_desc_registers(tp, ioaddr);
4680

4681 4682 4683 4684
	rtl_set_rx_mode(dev);

	RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
		(InterFrameGap << TxInterFrameGapShift));
4685 4686 4687

	RTL_R8(IntrMask);

4688 4689 4690
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_11:
		rtl_hw_start_8168bb(ioaddr, pdev);
4691
		break;
4692 4693 4694 4695

	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
		rtl_hw_start_8168bef(ioaddr, pdev);
4696
		break;
4697 4698

	case RTL_GIGA_MAC_VER_18:
F
Francois Romieu 已提交
4699
		rtl_hw_start_8168cp_1(ioaddr, pdev);
4700
		break;
4701 4702 4703

	case RTL_GIGA_MAC_VER_19:
		rtl_hw_start_8168c_1(ioaddr, pdev);
4704
		break;
4705 4706 4707

	case RTL_GIGA_MAC_VER_20:
		rtl_hw_start_8168c_2(ioaddr, pdev);
4708
		break;
4709

F
Francois Romieu 已提交
4710 4711
	case RTL_GIGA_MAC_VER_21:
		rtl_hw_start_8168c_3(ioaddr, pdev);
4712
		break;
F
Francois Romieu 已提交
4713

4714 4715
	case RTL_GIGA_MAC_VER_22:
		rtl_hw_start_8168c_4(ioaddr, pdev);
4716
		break;
4717

F
Francois Romieu 已提交
4718 4719
	case RTL_GIGA_MAC_VER_23:
		rtl_hw_start_8168cp_2(ioaddr, pdev);
4720
		break;
F
Francois Romieu 已提交
4721

4722 4723
	case RTL_GIGA_MAC_VER_24:
		rtl_hw_start_8168cp_3(ioaddr, pdev);
4724
		break;
4725

F
Francois Romieu 已提交
4726
	case RTL_GIGA_MAC_VER_25:
4727 4728
	case RTL_GIGA_MAC_VER_26:
	case RTL_GIGA_MAC_VER_27:
F
Francois Romieu 已提交
4729
		rtl_hw_start_8168d(ioaddr, pdev);
4730
		break;
F
Francois Romieu 已提交
4731

F
françois romieu 已提交
4732 4733
	case RTL_GIGA_MAC_VER_28:
		rtl_hw_start_8168d_4(ioaddr, pdev);
4734
		break;
F
Francois Romieu 已提交
4735

4736 4737 4738 4739
	case RTL_GIGA_MAC_VER_31:
		rtl_hw_start_8168dp(ioaddr, pdev);
		break;

H
hayeswang 已提交
4740 4741
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
H
Hayes Wang 已提交
4742 4743 4744 4745
		rtl_hw_start_8168e_1(ioaddr, pdev);
		break;
	case RTL_GIGA_MAC_VER_34:
		rtl_hw_start_8168e_2(ioaddr, pdev);
H
hayeswang 已提交
4746
		break;
F
françois romieu 已提交
4747

4748 4749 4750 4751 4752
	case RTL_GIGA_MAC_VER_35:
	case RTL_GIGA_MAC_VER_36:
		rtl_hw_start_8168f_1(ioaddr, pdev);
		break;

4753 4754 4755
	default:
		printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
			dev->name, tp->mac_version);
4756
		break;
4757
	}
4758

4759 4760
	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);

4761 4762
	RTL_W8(Cfg9346, Cfg9346_Lock);

4763
	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4764
}
L
Linus Torvalds 已提交
4765

4766 4767 4768 4769
#define R810X_CPCMD_QUIRK_MASK (\
	EnableBist | \
	Mac_dbgo_oe | \
	Force_half_dup | \
F
françois romieu 已提交
4770
	Force_rxflow_en | \
4771 4772 4773 4774
	Force_txflow_en | \
	Cxpl_dbg_sel | \
	ASF | \
	PktCntrDisable | \
4775
	Mac_dbgo_sel)
4776 4777 4778

static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
{
4779
	static const struct ephy_info e_info_8102e_1[] = {
4780 4781 4782 4783 4784 4785 4786 4787 4788 4789 4790
		{ 0x01,	0, 0x6e65 },
		{ 0x02,	0, 0x091f },
		{ 0x03,	0, 0xc2f9 },
		{ 0x06,	0, 0xafb5 },
		{ 0x07,	0, 0x0e00 },
		{ 0x19,	0, 0xec80 },
		{ 0x01,	0, 0x2e65 },
		{ 0x01,	0, 0x6e65 }
	};
	u8 cfg1;

4791
	rtl_csi_access_enable_2(ioaddr);
4792 4793 4794 4795 4796 4797 4798 4799 4800 4801 4802 4803 4804 4805 4806 4807 4808 4809

	RTL_W8(DBG_REG, FIX_NAK_1);

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	RTL_W8(Config1,
	       LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

	cfg1 = RTL_R8(Config1);
	if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
		RTL_W8(Config1, cfg1 & ~LEDS0);

	rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
}

static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
{
4810
	rtl_csi_access_enable_2(ioaddr);
4811 4812 4813 4814 4815 4816 4817 4818 4819 4820 4821 4822 4823 4824

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
}

static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
{
	rtl_hw_start_8102e_2(ioaddr, pdev);

	rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
}

4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836 4837
static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
{
	static const struct ephy_info e_info_8105e_1[] = {
		{ 0x07,	0, 0x4000 },
		{ 0x19,	0, 0x0200 },
		{ 0x19,	0, 0x0020 },
		{ 0x1e,	0, 0x2000 },
		{ 0x03,	0, 0x0001 },
		{ 0x19,	0, 0x0100 },
		{ 0x19,	0, 0x0004 },
		{ 0x0a,	0, 0x0020 }
	};

F
Francois Romieu 已提交
4838
	/* Force LAN exit from ASPM if Rx/Tx are not idle */
4839 4840
	RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);

F
Francois Romieu 已提交
4841
	/* Disable Early Tally Counter */
4842 4843 4844
	RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);

	RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
H
Hayes Wang 已提交
4845
	RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4846 4847 4848 4849 4850 4851 4852 4853 4854 4855

	rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
}

static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
{
	rtl_hw_start_8105e_1(ioaddr, pdev);
	rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
}

4856 4857
static void rtl_hw_start_8101(struct net_device *dev)
{
4858 4859 4860 4861
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

4862 4863
	if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
		tp->event_slow &= ~RxFIFOOver;
F
françois romieu 已提交
4864

F
Francois Romieu 已提交
4865 4866
	if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_16) {
4867
		int cap = pci_pcie_cap(pdev);
4868 4869 4870 4871 4872

		if (cap) {
			pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
					      PCI_EXP_DEVCTL_NOSNOOP_EN);
		}
4873 4874
	}

4875 4876
	RTL_W8(Cfg9346, Cfg9346_Unlock);

4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_07:
		rtl_hw_start_8102e_1(ioaddr, pdev);
		break;

	case RTL_GIGA_MAC_VER_08:
		rtl_hw_start_8102e_3(ioaddr, pdev);
		break;

	case RTL_GIGA_MAC_VER_09:
		rtl_hw_start_8102e_2(ioaddr, pdev);
		break;
4889 4890 4891 4892 4893 4894 4895

	case RTL_GIGA_MAC_VER_29:
		rtl_hw_start_8105e_1(ioaddr, pdev);
		break;
	case RTL_GIGA_MAC_VER_30:
		rtl_hw_start_8105e_2(ioaddr, pdev);
		break;
4896 4897
	}

4898
	RTL_W8(Cfg9346, Cfg9346_Lock);
4899

4900
	RTL_W8(MaxTxPacketSize, TxPacketMax);
4901

E
Eric Dumazet 已提交
4902
	rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4903

4904
	tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918
	RTL_W16(CPlusCmd, tp->cp_cmd);

	RTL_W16(IntrMitigate, 0x0000);

	rtl_set_rx_tx_desc_registers(tp, ioaddr);

	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
	rtl_set_rx_tx_config_registers(tp);

	RTL_R8(IntrMask);

	rtl_set_rx_mode(dev);

	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
L
Linus Torvalds 已提交
4919 4920 4921 4922
}

static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
{
F
Francois Romieu 已提交
4923 4924 4925 4926
	struct rtl8169_private *tp = netdev_priv(dev);

	if (new_mtu < ETH_ZLEN ||
	    new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
L
Linus Torvalds 已提交
4927 4928
		return -EINVAL;

F
Francois Romieu 已提交
4929 4930 4931 4932 4933
	if (new_mtu > ETH_DATA_LEN)
		rtl_hw_jumbo_enable(tp);
	else
		rtl_hw_jumbo_disable(tp);

L
Linus Torvalds 已提交
4934
	dev->mtu = new_mtu;
4935 4936
	netdev_update_features(dev);

S
Stanislaw Gruszka 已提交
4937
	return 0;
L
Linus Torvalds 已提交
4938 4939 4940 4941
}

static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
{
A
Al Viro 已提交
4942
	desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
L
Linus Torvalds 已提交
4943 4944 4945
	desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
}

E
Eric Dumazet 已提交
4946 4947
static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
				     void **data_buff, struct RxDesc *desc)
L
Linus Torvalds 已提交
4948
{
4949
	dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4950
			 DMA_FROM_DEVICE);
4951

E
Eric Dumazet 已提交
4952 4953
	kfree(*data_buff);
	*data_buff = NULL;
L
Linus Torvalds 已提交
4954 4955 4956 4957 4958 4959 4960 4961 4962 4963 4964 4965 4966 4967 4968 4969 4970 4971
	rtl8169_make_unusable_by_asic(desc);
}

static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
{
	u32 eor = le32_to_cpu(desc->opts1) & RingEnd;

	desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
}

static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
				       u32 rx_buf_sz)
{
	desc->addr = cpu_to_le64(mapping);
	wmb();
	rtl8169_mark_to_asic(desc, rx_buf_sz);
}

E
Eric Dumazet 已提交
4972 4973 4974 4975 4976
static inline void *rtl8169_align(void *data)
{
	return (void *)ALIGN((long)data, 16);
}

S
Stanislaw Gruszka 已提交
4977 4978
static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
					     struct RxDesc *desc)
L
Linus Torvalds 已提交
4979
{
E
Eric Dumazet 已提交
4980
	void *data;
L
Linus Torvalds 已提交
4981
	dma_addr_t mapping;
4982
	struct device *d = &tp->pci_dev->dev;
S
Stanislaw Gruszka 已提交
4983
	struct net_device *dev = tp->dev;
E
Eric Dumazet 已提交
4984
	int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
L
Linus Torvalds 已提交
4985

E
Eric Dumazet 已提交
4986 4987 4988
	data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
	if (!data)
		return NULL;
4989

E
Eric Dumazet 已提交
4990 4991 4992 4993 4994 4995
	if (rtl8169_align(data) != data) {
		kfree(data);
		data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
		if (!data)
			return NULL;
	}
4996

4997
	mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4998
				 DMA_FROM_DEVICE);
4999 5000 5001
	if (unlikely(dma_mapping_error(d, mapping))) {
		if (net_ratelimit())
			netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5002
		goto err_out;
5003
	}
L
Linus Torvalds 已提交
5004 5005

	rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
E
Eric Dumazet 已提交
5006
	return data;
5007 5008 5009 5010

err_out:
	kfree(data);
	return NULL;
L
Linus Torvalds 已提交
5011 5012 5013 5014
}

static void rtl8169_rx_clear(struct rtl8169_private *tp)
{
F
Francois Romieu 已提交
5015
	unsigned int i;
L
Linus Torvalds 已提交
5016 5017

	for (i = 0; i < NUM_RX_DESC; i++) {
E
Eric Dumazet 已提交
5018 5019
		if (tp->Rx_databuff[i]) {
			rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
L
Linus Torvalds 已提交
5020 5021 5022 5023 5024
					    tp->RxDescArray + i);
		}
	}
}

S
Stanislaw Gruszka 已提交
5025
static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
L
Linus Torvalds 已提交
5026
{
S
Stanislaw Gruszka 已提交
5027 5028
	desc->opts1 |= cpu_to_le32(RingEnd);
}
5029

S
Stanislaw Gruszka 已提交
5030 5031 5032
static int rtl8169_rx_fill(struct rtl8169_private *tp)
{
	unsigned int i;
L
Linus Torvalds 已提交
5033

S
Stanislaw Gruszka 已提交
5034 5035
	for (i = 0; i < NUM_RX_DESC; i++) {
		void *data;
5036

E
Eric Dumazet 已提交
5037
		if (tp->Rx_databuff[i])
L
Linus Torvalds 已提交
5038
			continue;
5039

S
Stanislaw Gruszka 已提交
5040
		data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
E
Eric Dumazet 已提交
5041 5042
		if (!data) {
			rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
S
Stanislaw Gruszka 已提交
5043
			goto err_out;
E
Eric Dumazet 已提交
5044 5045
		}
		tp->Rx_databuff[i] = data;
L
Linus Torvalds 已提交
5046 5047
	}

S
Stanislaw Gruszka 已提交
5048 5049 5050 5051 5052 5053
	rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
	return 0;

err_out:
	rtl8169_rx_clear(tp);
	return -ENOMEM;
L
Linus Torvalds 已提交
5054 5055 5056 5057 5058 5059 5060 5061 5062
}

static int rtl8169_init_ring(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl8169_init_ring_indexes(tp);

	memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
E
Eric Dumazet 已提交
5063
	memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
L
Linus Torvalds 已提交
5064

S
Stanislaw Gruszka 已提交
5065
	return rtl8169_rx_fill(tp);
L
Linus Torvalds 已提交
5066 5067
}

5068
static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
L
Linus Torvalds 已提交
5069 5070 5071 5072
				 struct TxDesc *desc)
{
	unsigned int len = tx_skb->len;

5073 5074
	dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);

L
Linus Torvalds 已提交
5075 5076 5077 5078 5079 5080
	desc->opts1 = 0x00;
	desc->opts2 = 0x00;
	desc->addr = 0x00;
	tx_skb->len = 0;
}

5081 5082
static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
				   unsigned int n)
L
Linus Torvalds 已提交
5083 5084 5085
{
	unsigned int i;

5086 5087
	for (i = 0; i < n; i++) {
		unsigned int entry = (start + i) % NUM_TX_DESC;
L
Linus Torvalds 已提交
5088 5089 5090 5091 5092 5093
		struct ring_info *tx_skb = tp->tx_skb + entry;
		unsigned int len = tx_skb->len;

		if (len) {
			struct sk_buff *skb = tx_skb->skb;

5094
			rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
L
Linus Torvalds 已提交
5095 5096
					     tp->TxDescArray + entry);
			if (skb) {
5097
				tp->dev->stats.tx_dropped++;
L
Linus Torvalds 已提交
5098 5099 5100 5101 5102
				dev_kfree_skb(skb);
				tx_skb->skb = NULL;
			}
		}
	}
5103 5104 5105 5106 5107
}

static void rtl8169_tx_clear(struct rtl8169_private *tp)
{
	rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
L
Linus Torvalds 已提交
5108
	tp->cur_tx = tp->dirty_tx = 0;
5109
	netdev_reset_queue(tp->dev);
L
Linus Torvalds 已提交
5110 5111
}

5112
static void rtl_reset_work(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
5113
{
D
David Howells 已提交
5114
	struct net_device *dev = tp->dev;
5115
	int i;
L
Linus Torvalds 已提交
5116

5117 5118 5119
	napi_disable(&tp->napi);
	netif_stop_queue(dev);
	synchronize_sched();
L
Linus Torvalds 已提交
5120

5121 5122
	rtl8169_hw_reset(tp);

5123 5124 5125
	for (i = 0; i < NUM_RX_DESC; i++)
		rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);

L
Linus Torvalds 已提交
5126
	rtl8169_tx_clear(tp);
5127
	rtl8169_init_ring_indexes(tp);
L
Linus Torvalds 已提交
5128

5129
	napi_enable(&tp->napi);
5130 5131 5132
	rtl_hw_start(dev);
	netif_wake_queue(dev);
	rtl8169_check_link_status(dev, tp, tp->mmio_addr);
L
Linus Torvalds 已提交
5133 5134 5135 5136
}

static void rtl8169_tx_timeout(struct net_device *dev)
{
5137 5138 5139
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
L
Linus Torvalds 已提交
5140 5141 5142
}

static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
F
Francois Romieu 已提交
5143
			      u32 *opts)
L
Linus Torvalds 已提交
5144 5145 5146
{
	struct skb_shared_info *info = skb_shinfo(skb);
	unsigned int cur_frag, entry;
5147
	struct TxDesc * uninitialized_var(txd);
5148
	struct device *d = &tp->pci_dev->dev;
L
Linus Torvalds 已提交
5149 5150 5151

	entry = tp->cur_tx;
	for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
E
Eric Dumazet 已提交
5152
		const skb_frag_t *frag = info->frags + cur_frag;
L
Linus Torvalds 已提交
5153 5154 5155 5156 5157 5158 5159
		dma_addr_t mapping;
		u32 status, len;
		void *addr;

		entry = (entry + 1) % NUM_TX_DESC;

		txd = tp->TxDescArray + entry;
E
Eric Dumazet 已提交
5160
		len = skb_frag_size(frag);
5161
		addr = skb_frag_address(frag);
5162
		mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5163 5164 5165 5166
		if (unlikely(dma_mapping_error(d, mapping))) {
			if (net_ratelimit())
				netif_err(tp, drv, tp->dev,
					  "Failed to map TX fragments DMA!\n");
5167
			goto err_out;
5168
		}
L
Linus Torvalds 已提交
5169

F
Francois Romieu 已提交
5170
		/* Anti gcc 2.95.3 bugware (sic) */
F
Francois Romieu 已提交
5171 5172
		status = opts[0] | len |
			(RingEnd * !((entry + 1) % NUM_TX_DESC));
L
Linus Torvalds 已提交
5173 5174

		txd->opts1 = cpu_to_le32(status);
F
Francois Romieu 已提交
5175
		txd->opts2 = cpu_to_le32(opts[1]);
L
Linus Torvalds 已提交
5176 5177 5178 5179 5180 5181 5182 5183 5184 5185 5186
		txd->addr = cpu_to_le64(mapping);

		tp->tx_skb[entry].len = len;
	}

	if (cur_frag) {
		tp->tx_skb[entry].skb = skb;
		txd->opts1 |= cpu_to_le32(LastFrag);
	}

	return cur_frag;
5187 5188 5189 5190

err_out:
	rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
	return -EIO;
L
Linus Torvalds 已提交
5191 5192
}

F
Francois Romieu 已提交
5193 5194
static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
				    struct sk_buff *skb, u32 *opts)
L
Linus Torvalds 已提交
5195
{
F
Francois Romieu 已提交
5196
	const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5197
	u32 mss = skb_shinfo(skb)->gso_size;
F
Francois Romieu 已提交
5198
	int offset = info->opts_offset;
5199

F
Francois Romieu 已提交
5200 5201 5202 5203
	if (mss) {
		opts[0] |= TD_LSO;
		opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5204
		const struct iphdr *ip = ip_hdr(skb);
L
Linus Torvalds 已提交
5205 5206

		if (ip->protocol == IPPROTO_TCP)
F
Francois Romieu 已提交
5207
			opts[offset] |= info->checksum.tcp;
L
Linus Torvalds 已提交
5208
		else if (ip->protocol == IPPROTO_UDP)
F
Francois Romieu 已提交
5209 5210 5211
			opts[offset] |= info->checksum.udp;
		else
			WARN_ON_ONCE(1);
L
Linus Torvalds 已提交
5212 5213 5214
	}
}

5215 5216
static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
				      struct net_device *dev)
L
Linus Torvalds 已提交
5217 5218
{
	struct rtl8169_private *tp = netdev_priv(dev);
5219
	unsigned int entry = tp->cur_tx % NUM_TX_DESC;
L
Linus Torvalds 已提交
5220 5221
	struct TxDesc *txd = tp->TxDescArray + entry;
	void __iomem *ioaddr = tp->mmio_addr;
5222
	struct device *d = &tp->pci_dev->dev;
L
Linus Torvalds 已提交
5223 5224
	dma_addr_t mapping;
	u32 status, len;
F
Francois Romieu 已提交
5225
	u32 opts[2];
5226
	int frags;
5227

L
Linus Torvalds 已提交
5228
	if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
5229
		netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5230
		goto err_stop_0;
L
Linus Torvalds 已提交
5231 5232 5233
	}

	if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5234 5235 5236
		goto err_stop_0;

	len = skb_headlen(skb);
5237
	mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5238 5239 5240
	if (unlikely(dma_mapping_error(d, mapping))) {
		if (net_ratelimit())
			netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5241
		goto err_dma_0;
5242
	}
5243 5244 5245

	tp->tx_skb[entry].len = len;
	txd->addr = cpu_to_le64(mapping);
L
Linus Torvalds 已提交
5246

F
Francois Romieu 已提交
5247 5248
	opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
	opts[0] = DescOwn;
L
Linus Torvalds 已提交
5249

F
Francois Romieu 已提交
5250 5251 5252
	rtl8169_tso_csum(tp, skb, opts);

	frags = rtl8169_xmit_frags(tp, skb, opts);
5253 5254 5255
	if (frags < 0)
		goto err_dma_1;
	else if (frags)
F
Francois Romieu 已提交
5256
		opts[0] |= FirstFrag;
5257
	else {
F
Francois Romieu 已提交
5258
		opts[0] |= FirstFrag | LastFrag;
L
Linus Torvalds 已提交
5259 5260 5261
		tp->tx_skb[entry].skb = skb;
	}

F
Francois Romieu 已提交
5262 5263
	txd->opts2 = cpu_to_le32(opts[1]);

5264 5265
	netdev_sent_queue(dev, skb->len);

L
Linus Torvalds 已提交
5266 5267
	wmb();

F
Francois Romieu 已提交
5268
	/* Anti gcc 2.95.3 bugware (sic) */
F
Francois Romieu 已提交
5269
	status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
L
Linus Torvalds 已提交
5270 5271 5272 5273
	txd->opts1 = cpu_to_le32(status);

	tp->cur_tx += frags + 1;

5274
	wmb();
L
Linus Torvalds 已提交
5275

F
Francois Romieu 已提交
5276
	RTL_W8(TxPoll, NPQ);
L
Linus Torvalds 已提交
5277

5278 5279
	mmiowb();

L
Linus Torvalds 已提交
5280
	if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5281 5282 5283 5284
		/* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
		 * not miss a ring update when it notices a stopped queue.
		 */
		smp_wmb();
L
Linus Torvalds 已提交
5285
		netif_stop_queue(dev);
5286 5287 5288 5289 5290 5291 5292
		/* Sync with rtl_tx:
		 * - publish queue status and cur_tx ring index (write barrier)
		 * - refresh dirty_tx ring index (read barrier).
		 * May the current thread have a pessimistic view of the ring
		 * status and forget to wake up queue, a racing rtl_tx thread
		 * can't.
		 */
F
Francois Romieu 已提交
5293
		smp_mb();
L
Linus Torvalds 已提交
5294 5295 5296 5297
		if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
			netif_wake_queue(dev);
	}

5298
	return NETDEV_TX_OK;
L
Linus Torvalds 已提交
5299

5300
err_dma_1:
5301
	rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5302 5303 5304 5305 5306 5307
err_dma_0:
	dev_kfree_skb(skb);
	dev->stats.tx_dropped++;
	return NETDEV_TX_OK;

err_stop_0:
L
Linus Torvalds 已提交
5308
	netif_stop_queue(dev);
5309
	dev->stats.tx_dropped++;
5310
	return NETDEV_TX_BUSY;
L
Linus Torvalds 已提交
5311 5312 5313 5314 5315 5316 5317 5318 5319 5320 5321
}

static void rtl8169_pcierr_interrupt(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct pci_dev *pdev = tp->pci_dev;
	u16 pci_status, pci_cmd;

	pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
	pci_read_config_word(pdev, PCI_STATUS, &pci_status);

5322 5323
	netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
		  pci_cmd, pci_status);
L
Linus Torvalds 已提交
5324 5325 5326 5327

	/*
	 * The recovery sequence below admits a very elaborated explanation:
	 * - it seems to work;
5328 5329
	 * - I did not see what else could be done;
	 * - it makes iop3xx happy.
L
Linus Torvalds 已提交
5330 5331 5332
	 *
	 * Feel free to adjust to your needs.
	 */
5333
	if (pdev->broken_parity_status)
5334 5335 5336 5337 5338
		pci_cmd &= ~PCI_COMMAND_PARITY;
	else
		pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;

	pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
L
Linus Torvalds 已提交
5339 5340 5341 5342 5343 5344 5345 5346

	pci_write_config_word(pdev, PCI_STATUS,
		pci_status & (PCI_STATUS_DETECTED_PARITY |
		PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
		PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));

	/* The infamous DAC f*ckup only happens at boot time */
	if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
F
françois romieu 已提交
5347 5348
		void __iomem *ioaddr = tp->mmio_addr;

5349
		netif_info(tp, intr, dev, "disabling PCI DAC\n");
L
Linus Torvalds 已提交
5350 5351 5352 5353 5354
		tp->cp_cmd &= ~PCIDAC;
		RTL_W16(CPlusCmd, tp->cp_cmd);
		dev->features &= ~NETIF_F_HIGHDMA;
	}

F
françois romieu 已提交
5355
	rtl8169_hw_reset(tp);
5356

5357
	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
L
Linus Torvalds 已提交
5358 5359
}

5360 5361 5362 5363 5364
struct rtl_txc {
	int packets;
	int bytes;
};

5365
static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
L
Linus Torvalds 已提交
5366
{
5367
	struct rtl8169_stats *tx_stats = &tp->tx_stats;
L
Linus Torvalds 已提交
5368
	unsigned int dirty_tx, tx_left;
5369
	struct rtl_txc txc = { 0, 0 };
L
Linus Torvalds 已提交
5370 5371 5372 5373 5374 5375 5376 5377 5378 5379 5380 5381 5382 5383 5384

	dirty_tx = tp->dirty_tx;
	smp_rmb();
	tx_left = tp->cur_tx - dirty_tx;

	while (tx_left > 0) {
		unsigned int entry = dirty_tx % NUM_TX_DESC;
		struct ring_info *tx_skb = tp->tx_skb + entry;
		u32 status;

		rmb();
		status = le32_to_cpu(tp->TxDescArray[entry].opts1);
		if (status & DescOwn)
			break;

5385 5386
		rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
				     tp->TxDescArray + entry);
L
Linus Torvalds 已提交
5387
		if (status & LastFrag) {
5388 5389 5390 5391 5392
			struct sk_buff *skb = tx_skb->skb;

			txc.packets++;
			txc.bytes += skb->len;
			dev_kfree_skb(skb);
L
Linus Torvalds 已提交
5393 5394 5395 5396 5397 5398
			tx_skb->skb = NULL;
		}
		dirty_tx++;
		tx_left--;
	}

5399 5400 5401 5402 5403 5404 5405
	u64_stats_update_begin(&tx_stats->syncp);
	tx_stats->packets += txc.packets;
	tx_stats->bytes += txc.bytes;
	u64_stats_update_end(&tx_stats->syncp);

	netdev_completed_queue(dev, txc.packets, txc.bytes);

L
Linus Torvalds 已提交
5406 5407
	if (tp->dirty_tx != dirty_tx) {
		tp->dirty_tx = dirty_tx;
5408 5409 5410 5411 5412 5413 5414
		/* Sync with rtl8169_start_xmit:
		 * - publish dirty_tx ring index (write barrier)
		 * - refresh cur_tx ring index and queue status (read barrier)
		 * May the current thread miss the stopped queue condition,
		 * a racing xmit thread can only have a right view of the
		 * ring status.
		 */
F
Francois Romieu 已提交
5415
		smp_mb();
L
Linus Torvalds 已提交
5416 5417 5418 5419
		if (netif_queue_stopped(dev) &&
		    (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
			netif_wake_queue(dev);
		}
5420 5421 5422 5423 5424 5425
		/*
		 * 8168 hack: TxPoll requests are lost when the Tx packets are
		 * too close. Let's kick an extra TxPoll request when a burst
		 * of start_xmit activity is detected (if it is not detected,
		 * it is slow enough). -- FR
		 */
5426 5427 5428
		if (tp->cur_tx != dirty_tx) {
			void __iomem *ioaddr = tp->mmio_addr;

5429
			RTL_W8(TxPoll, NPQ);
5430
		}
L
Linus Torvalds 已提交
5431 5432 5433
	}
}

5434 5435 5436 5437 5438
static inline int rtl8169_fragmented_frame(u32 status)
{
	return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
}

E
Eric Dumazet 已提交
5439
static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
L
Linus Torvalds 已提交
5440 5441 5442 5443
{
	u32 status = opts1 & RxProtoMask;

	if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
S
Shan Wei 已提交
5444
	    ((status == RxProtoUDP) && !(opts1 & UDPFail)))
L
Linus Torvalds 已提交
5445 5446
		skb->ip_summed = CHECKSUM_UNNECESSARY;
	else
5447
		skb_checksum_none_assert(skb);
L
Linus Torvalds 已提交
5448 5449
}

E
Eric Dumazet 已提交
5450 5451 5452 5453
static struct sk_buff *rtl8169_try_rx_copy(void *data,
					   struct rtl8169_private *tp,
					   int pkt_size,
					   dma_addr_t addr)
L
Linus Torvalds 已提交
5454
{
S
Stephen Hemminger 已提交
5455
	struct sk_buff *skb;
5456
	struct device *d = &tp->pci_dev->dev;
S
Stephen Hemminger 已提交
5457

E
Eric Dumazet 已提交
5458
	data = rtl8169_align(data);
5459
	dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
E
Eric Dumazet 已提交
5460 5461 5462 5463
	prefetch(data);
	skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
	if (skb)
		memcpy(skb->data, data, pkt_size);
5464 5465
	dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);

E
Eric Dumazet 已提交
5466
	return skb;
L
Linus Torvalds 已提交
5467 5468
}

5469
static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
L
Linus Torvalds 已提交
5470 5471
{
	unsigned int cur_rx, rx_left;
E
Eric Dumazet 已提交
5472
	unsigned int count;
L
Linus Torvalds 已提交
5473 5474 5475

	cur_rx = tp->cur_rx;
	rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
F
Francois Romieu 已提交
5476
	rx_left = min(rx_left, budget);
L
Linus Torvalds 已提交
5477

R
Richard Dawe 已提交
5478
	for (; rx_left > 0; rx_left--, cur_rx++) {
L
Linus Torvalds 已提交
5479
		unsigned int entry = cur_rx % NUM_RX_DESC;
5480
		struct RxDesc *desc = tp->RxDescArray + entry;
L
Linus Torvalds 已提交
5481 5482 5483
		u32 status;

		rmb();
5484
		status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
L
Linus Torvalds 已提交
5485 5486 5487

		if (status & DescOwn)
			break;
R
Richard Dawe 已提交
5488
		if (unlikely(status & RxRES)) {
5489 5490
			netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
				   status);
5491
			dev->stats.rx_errors++;
L
Linus Torvalds 已提交
5492
			if (status & (RxRWT | RxRUNT))
5493
				dev->stats.rx_length_errors++;
L
Linus Torvalds 已提交
5494
			if (status & RxCRC)
5495
				dev->stats.rx_crc_errors++;
5496
			if (status & RxFOVF) {
5497
				rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5498
				dev->stats.rx_fifo_errors++;
5499
			}
B
Ben Greear 已提交
5500 5501 5502 5503 5504
			if ((status & (RxRUNT | RxCRC)) &&
			    !(status & (RxRWT | RxFOVF)) &&
			    (dev->features & NETIF_F_RXALL))
				goto process_pkt;

E
Eric Dumazet 已提交
5505
			rtl8169_mark_to_asic(desc, rx_buf_sz);
L
Linus Torvalds 已提交
5506
		} else {
E
Eric Dumazet 已提交
5507
			struct sk_buff *skb;
B
Ben Greear 已提交
5508 5509 5510 5511 5512
			dma_addr_t addr;
			int pkt_size;

process_pkt:
			addr = le64_to_cpu(desc->addr);
B
Ben Greear 已提交
5513 5514 5515 5516
			if (likely(!(dev->features & NETIF_F_RXFCS)))
				pkt_size = (status & 0x00003fff) - 4;
			else
				pkt_size = status & 0x00003fff;
L
Linus Torvalds 已提交
5517

5518 5519 5520 5521 5522 5523
			/*
			 * The driver does not support incoming fragmented
			 * frames. They are seen as a symptom of over-mtu
			 * sized frames.
			 */
			if (unlikely(rtl8169_fragmented_frame(status))) {
5524 5525
				dev->stats.rx_dropped++;
				dev->stats.rx_length_errors++;
E
Eric Dumazet 已提交
5526
				rtl8169_mark_to_asic(desc, rx_buf_sz);
R
Richard Dawe 已提交
5527
				continue;
5528 5529
			}

E
Eric Dumazet 已提交
5530 5531 5532 5533 5534 5535
			skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
						  tp, pkt_size, addr);
			rtl8169_mark_to_asic(desc, rx_buf_sz);
			if (!skb) {
				dev->stats.rx_dropped++;
				continue;
L
Linus Torvalds 已提交
5536 5537
			}

E
Eric Dumazet 已提交
5538
			rtl8169_rx_csum(skb, status);
L
Linus Torvalds 已提交
5539 5540 5541
			skb_put(skb, pkt_size);
			skb->protocol = eth_type_trans(skb, dev);

5542 5543
			rtl8169_rx_vlan_tag(desc, skb);

5544
			napi_gro_receive(&tp->napi, skb);
L
Linus Torvalds 已提交
5545

J
Junchang Wang 已提交
5546 5547 5548 5549
			u64_stats_update_begin(&tp->rx_stats.syncp);
			tp->rx_stats.packets++;
			tp->rx_stats.bytes += pkt_size;
			u64_stats_update_end(&tp->rx_stats.syncp);
L
Linus Torvalds 已提交
5550
		}
5551 5552

		/* Work around for AMD plateform. */
A
Al Viro 已提交
5553
		if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5554 5555 5556 5557
		    (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
			desc->opts2 = 0;
			cur_rx++;
		}
L
Linus Torvalds 已提交
5558 5559 5560 5561 5562
	}

	count = cur_rx - tp->cur_rx;
	tp->cur_rx = cur_rx;

E
Eric Dumazet 已提交
5563
	tp->dirty_rx += count;
L
Linus Torvalds 已提交
5564 5565 5566 5567

	return count;
}

F
Francois Romieu 已提交
5568
static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
L
Linus Torvalds 已提交
5569
{
F
Francois Romieu 已提交
5570
	struct net_device *dev = dev_instance;
L
Linus Torvalds 已提交
5571 5572
	struct rtl8169_private *tp = netdev_priv(dev);
	int handled = 0;
F
Francois Romieu 已提交
5573
	u16 status;
L
Linus Torvalds 已提交
5574

F
Francois Romieu 已提交
5575
	status = rtl_get_events(tp);
5576 5577 5578 5579
	if (status && status != 0xffff) {
		status &= RTL_EVENT_NAPI | tp->event_slow;
		if (status) {
			handled = 1;
L
Linus Torvalds 已提交
5580

5581 5582
			rtl_irq_disable(tp);
			napi_schedule(&tp->napi);
5583
		}
5584 5585 5586
	}
	return IRQ_RETVAL(handled);
}
L
Linus Torvalds 已提交
5587

5588 5589 5590 5591 5592 5593 5594 5595 5596 5597
/*
 * Workqueue context.
 */
static void rtl_slow_event_work(struct rtl8169_private *tp)
{
	struct net_device *dev = tp->dev;
	u16 status;

	status = rtl_get_events(tp) & tp->event_slow;
	rtl_ack_events(tp, status);
L
Linus Torvalds 已提交
5598

5599 5600 5601 5602 5603
	if (unlikely(status & RxFIFOOver)) {
		switch (tp->mac_version) {
		/* Work around for rx fifo overflow */
		case RTL_GIGA_MAC_VER_11:
			netif_stop_queue(dev);
5604 5605
			/* XXX - Hack alert. See rtl_task(). */
			set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5606
		default:
5607 5608
			break;
		}
5609
	}
L
Linus Torvalds 已提交
5610

5611 5612
	if (unlikely(status & SYSErr))
		rtl8169_pcierr_interrupt(dev);
5613

5614 5615
	if (status & LinkChg)
		__rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
L
Linus Torvalds 已提交
5616

5617 5618 5619 5620 5621
	napi_disable(&tp->napi);
	rtl_irq_disable(tp);

	napi_enable(&tp->napi);
	napi_schedule(&tp->napi);
L
Linus Torvalds 已提交
5622 5623
}

5624 5625
static void rtl_task(struct work_struct *work)
{
5626 5627 5628 5629
	static const struct {
		int bitnr;
		void (*action)(struct rtl8169_private *);
	} rtl_work[] = {
5630
		/* XXX - keep rtl_slow_event_work() as first element. */
5631 5632 5633 5634
		{ RTL_FLAG_TASK_SLOW_PENDING,	rtl_slow_event_work },
		{ RTL_FLAG_TASK_RESET_PENDING,	rtl_reset_work },
		{ RTL_FLAG_TASK_PHY_PENDING,	rtl_phy_work }
	};
5635 5636
	struct rtl8169_private *tp =
		container_of(work, struct rtl8169_private, wk.work);
5637 5638 5639 5640 5641
	struct net_device *dev = tp->dev;
	int i;

	rtl_lock_work(tp);

5642 5643
	if (!netif_running(dev) ||
	    !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5644 5645 5646 5647 5648 5649 5650 5651 5652
		goto out_unlock;

	for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
		bool pending;

		pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
		if (pending)
			rtl_work[i].action(tp);
	}
5653

5654 5655
out_unlock:
	rtl_unlock_work(tp);
5656 5657
}

5658
static int rtl8169_poll(struct napi_struct *napi, int budget)
L
Linus Torvalds 已提交
5659
{
5660 5661
	struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
	struct net_device *dev = tp->dev;
5662 5663 5664 5665 5666 5667 5668 5669 5670 5671 5672 5673
	u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
	int work_done= 0;
	u16 status;

	status = rtl_get_events(tp);
	rtl_ack_events(tp, status & ~tp->event_slow);

	if (status & RTL_EVENT_NAPI_RX)
		work_done = rtl_rx(dev, tp, (u32) budget);

	if (status & RTL_EVENT_NAPI_TX)
		rtl_tx(dev, tp);
L
Linus Torvalds 已提交
5674

5675 5676 5677 5678 5679
	if (status & tp->event_slow) {
		enable_mask &= ~tp->event_slow;

		rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
	}
L
Linus Torvalds 已提交
5680

5681
	if (work_done < budget) {
5682
		napi_complete(napi);
5683

5684 5685
		rtl_irq_enable(tp, enable_mask);
		mmiowb();
L
Linus Torvalds 已提交
5686 5687
	}

5688
	return work_done;
L
Linus Torvalds 已提交
5689 5690
}

5691 5692 5693 5694 5695 5696 5697 5698 5699 5700 5701
static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	if (tp->mac_version > RTL_GIGA_MAC_VER_06)
		return;

	dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
	RTL_W32(RxMissed, 0);
}

L
Linus Torvalds 已提交
5702 5703 5704 5705 5706
static void rtl8169_down(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;

5707
	del_timer_sync(&tp->timer);
L
Linus Torvalds 已提交
5708

5709
	napi_disable(&tp->napi);
5710
	netif_stop_queue(dev);
L
Linus Torvalds 已提交
5711

5712
	rtl8169_hw_reset(tp);
S
Stanislaw Gruszka 已提交
5713 5714
	/*
	 * At this point device interrupts can not be enabled in any function,
5715 5716
	 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
	 * and napi is disabled (rtl8169_poll).
S
Stanislaw Gruszka 已提交
5717
	 */
5718
	rtl8169_rx_missed(dev, ioaddr);
L
Linus Torvalds 已提交
5719 5720

	/* Give a racing hard_start_xmit a few cycles to complete. */
5721
	synchronize_sched();
L
Linus Torvalds 已提交
5722 5723 5724 5725

	rtl8169_tx_clear(tp);

	rtl8169_rx_clear(tp);
F
françois romieu 已提交
5726 5727

	rtl_pll_power_down(tp);
L
Linus Torvalds 已提交
5728 5729 5730 5731 5732 5733 5734
}

static int rtl8169_close(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct pci_dev *pdev = tp->pci_dev;

5735 5736
	pm_runtime_get_sync(&pdev->dev);

F
Francois Romieu 已提交
5737
	/* Update counters before going down */
5738 5739
	rtl8169_update_counters(dev);

5740
	rtl_lock_work(tp);
5741
	clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5742

L
Linus Torvalds 已提交
5743
	rtl8169_down(dev);
5744
	rtl_unlock_work(tp);
L
Linus Torvalds 已提交
5745 5746 5747

	free_irq(dev->irq, dev);

5748 5749 5750 5751
	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
			  tp->RxPhyAddr);
	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
			  tp->TxPhyAddr);
L
Linus Torvalds 已提交
5752 5753 5754
	tp->TxDescArray = NULL;
	tp->RxDescArray = NULL;

5755 5756
	pm_runtime_put_sync(&pdev->dev);

L
Linus Torvalds 已提交
5757 5758 5759
	return 0;
}

5760
static void rtl_set_rx_mode(struct net_device *dev)
L
Linus Torvalds 已提交
5761 5762 5763 5764
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	u32 mc_filter[2];	/* Multicast hash filter */
F
Francois Romieu 已提交
5765
	int rx_mode;
L
Linus Torvalds 已提交
5766 5767 5768 5769
	u32 tmp = 0;

	if (dev->flags & IFF_PROMISC) {
		/* Unconditionally log net taps. */
5770
		netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
L
Linus Torvalds 已提交
5771 5772 5773 5774
		rx_mode =
		    AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
		    AcceptAllPhys;
		mc_filter[1] = mc_filter[0] = 0xffffffff;
5775
	} else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5776
		   (dev->flags & IFF_ALLMULTI)) {
L
Linus Torvalds 已提交
5777 5778 5779 5780
		/* Too many to filter perfectly -- accept all multicasts. */
		rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
		mc_filter[1] = mc_filter[0] = 0xffffffff;
	} else {
5781
		struct netdev_hw_addr *ha;
F
Francois Romieu 已提交
5782

L
Linus Torvalds 已提交
5783 5784
		rx_mode = AcceptBroadcast | AcceptMyPhys;
		mc_filter[1] = mc_filter[0] = 0;
5785 5786
		netdev_for_each_mc_addr(ha, dev) {
			int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
L
Linus Torvalds 已提交
5787 5788 5789 5790 5791
			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
			rx_mode |= AcceptMulticast;
		}
	}

B
Ben Greear 已提交
5792 5793 5794
	if (dev->features & NETIF_F_RXALL)
		rx_mode |= (AcceptErr | AcceptRunt);

5795
	tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
L
Linus Torvalds 已提交
5796

5797
	if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5798 5799 5800 5801
		u32 data = mc_filter[0];

		mc_filter[0] = swab32(mc_filter[1]);
		mc_filter[1] = swab32(data);
5802 5803
	}

L
Linus Torvalds 已提交
5804
	RTL_W32(MAR0 + 4, mc_filter[1]);
5805
	RTL_W32(MAR0 + 0, mc_filter[0]);
L
Linus Torvalds 已提交
5806

5807
	RTL_W32(RxConfig, tmp);
L
Linus Torvalds 已提交
5808 5809
}

J
Junchang Wang 已提交
5810 5811
static struct rtnl_link_stats64 *
rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
L
Linus Torvalds 已提交
5812 5813 5814
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
J
Junchang Wang 已提交
5815
	unsigned int start;
L
Linus Torvalds 已提交
5816

5817
	if (netif_running(dev))
5818
		rtl8169_rx_missed(dev, ioaddr);
5819

J
Junchang Wang 已提交
5820 5821 5822 5823 5824 5825 5826 5827 5828 5829 5830 5831 5832 5833 5834 5835 5836 5837 5838 5839 5840 5841
	do {
		start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
		stats->rx_packets = tp->rx_stats.packets;
		stats->rx_bytes	= tp->rx_stats.bytes;
	} while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));


	do {
		start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
		stats->tx_packets = tp->tx_stats.packets;
		stats->tx_bytes	= tp->tx_stats.bytes;
	} while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));

	stats->rx_dropped	= dev->stats.rx_dropped;
	stats->tx_dropped	= dev->stats.tx_dropped;
	stats->rx_length_errors = dev->stats.rx_length_errors;
	stats->rx_errors	= dev->stats.rx_errors;
	stats->rx_crc_errors	= dev->stats.rx_crc_errors;
	stats->rx_fifo_errors	= dev->stats.rx_fifo_errors;
	stats->rx_missed_errors = dev->stats.rx_missed_errors;

	return stats;
L
Linus Torvalds 已提交
5842 5843
}

5844
static void rtl8169_net_suspend(struct net_device *dev)
5845
{
F
françois romieu 已提交
5846 5847
	struct rtl8169_private *tp = netdev_priv(dev);

5848
	if (!netif_running(dev))
5849
		return;
5850 5851 5852

	netif_device_detach(dev);
	netif_stop_queue(dev);
5853 5854 5855

	rtl_lock_work(tp);
	napi_disable(&tp->napi);
5856
	clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5857 5858 5859
	rtl_unlock_work(tp);

	rtl_pll_power_down(tp);
5860 5861 5862 5863 5864 5865 5866 5867
}

#ifdef CONFIG_PM

static int rtl8169_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct net_device *dev = pci_get_drvdata(pdev);
5868

5869
	rtl8169_net_suspend(dev);
5870

5871 5872 5873
	return 0;
}

5874 5875
static void __rtl8169_resume(struct net_device *dev)
{
F
françois romieu 已提交
5876 5877
	struct rtl8169_private *tp = netdev_priv(dev);

5878
	netif_device_attach(dev);
F
françois romieu 已提交
5879 5880 5881

	rtl_pll_power_up(tp);

5882
	set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5883

5884
	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5885 5886
}

5887
static int rtl8169_resume(struct device *device)
5888
{
5889
	struct pci_dev *pdev = to_pci_dev(device);
5890
	struct net_device *dev = pci_get_drvdata(pdev);
S
Stanislaw Gruszka 已提交
5891 5892 5893
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl8169_init_phy(dev, tp);
5894

5895 5896
	if (netif_running(dev))
		__rtl8169_resume(dev);
5897

5898 5899 5900 5901 5902 5903 5904 5905 5906 5907 5908 5909
	return 0;
}

static int rtl8169_runtime_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct net_device *dev = pci_get_drvdata(pdev);
	struct rtl8169_private *tp = netdev_priv(dev);

	if (!tp->TxDescArray)
		return 0;

5910
	rtl_lock_work(tp);
5911 5912
	tp->saved_wolopts = __rtl8169_get_wol(tp);
	__rtl8169_set_wol(tp, WAKE_ANY);
5913
	rtl_unlock_work(tp);
5914 5915 5916 5917 5918 5919 5920 5921 5922 5923 5924 5925 5926 5927 5928

	rtl8169_net_suspend(dev);

	return 0;
}

static int rtl8169_runtime_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct net_device *dev = pci_get_drvdata(pdev);
	struct rtl8169_private *tp = netdev_priv(dev);

	if (!tp->TxDescArray)
		return 0;

5929
	rtl_lock_work(tp);
5930 5931
	__rtl8169_set_wol(tp, tp->saved_wolopts);
	tp->saved_wolopts = 0;
5932
	rtl_unlock_work(tp);
5933

S
Stanislaw Gruszka 已提交
5934 5935
	rtl8169_init_phy(dev, tp);

5936
	__rtl8169_resume(dev);
5937 5938 5939 5940

	return 0;
}

5941 5942 5943 5944 5945 5946
static int rtl8169_runtime_idle(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct net_device *dev = pci_get_drvdata(pdev);
	struct rtl8169_private *tp = netdev_priv(dev);

5947
	return tp->TxDescArray ? -EBUSY : 0;
5948 5949
}

5950
static const struct dev_pm_ops rtl8169_pm_ops = {
F
Francois Romieu 已提交
5951 5952 5953 5954 5955 5956 5957 5958 5959
	.suspend		= rtl8169_suspend,
	.resume			= rtl8169_resume,
	.freeze			= rtl8169_suspend,
	.thaw			= rtl8169_resume,
	.poweroff		= rtl8169_suspend,
	.restore		= rtl8169_resume,
	.runtime_suspend	= rtl8169_runtime_suspend,
	.runtime_resume		= rtl8169_runtime_resume,
	.runtime_idle		= rtl8169_runtime_idle,
5960 5961 5962 5963 5964 5965 5966 5967 5968 5969
};

#define RTL8169_PM_OPS	(&rtl8169_pm_ops)

#else /* !CONFIG_PM */

#define RTL8169_PM_OPS	NULL

#endif /* !CONFIG_PM */

5970 5971 5972 5973 5974 5975 5976 5977 5978 5979 5980 5981 5982 5983 5984 5985 5986 5987 5988 5989
static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	/* WoL fails with 8168b when the receiver is disabled. */
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_11:
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
		pci_clear_master(tp->pci_dev);

		RTL_W8(ChipCmd, CmdRxEnb);
		/* PCI commit */
		RTL_R8(ChipCmd);
		break;
	default:
		break;
	}
}

F
Francois Romieu 已提交
5990 5991
static void rtl_shutdown(struct pci_dev *pdev)
{
5992
	struct net_device *dev = pci_get_drvdata(pdev);
5993
	struct rtl8169_private *tp = netdev_priv(dev);
5994 5995 5996
	struct device *d = &pdev->dev;

	pm_runtime_get_sync(d);
5997 5998

	rtl8169_net_suspend(dev);
F
Francois Romieu 已提交
5999

F
Francois Romieu 已提交
6000
	/* Restore original MAC address */
6001 6002
	rtl_rar_set(tp, dev->perm_addr);

6003
	rtl8169_hw_reset(tp);
6004

6005
	if (system_state == SYSTEM_POWER_OFF) {
6006 6007 6008
		if (__rtl8169_get_wol(tp) & WAKE_ANY) {
			rtl_wol_suspend_quirk(tp);
			rtl_wol_shutdown_quirk(tp);
6009 6010
		}

6011 6012 6013
		pci_wake_from_d3(pdev, true);
		pci_set_power_state(pdev, PCI_D3hot);
	}
6014 6015

	pm_runtime_put_noidle(d);
6016
}
6017

6018 6019 6020 6021 6022 6023 6024 6025 6026 6027 6028 6029 6030 6031 6032 6033 6034 6035 6036 6037 6038 6039 6040 6041 6042 6043 6044 6045
static void __devexit rtl_remove_one(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);
	struct rtl8169_private *tp = netdev_priv(dev);

	if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_28 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_31) {
		rtl8168_driver_stop(tp);
	}

	cancel_work_sync(&tp->wk.work);

	unregister_netdev(dev);

	rtl_release_firmware(tp);

	if (pci_dev_run_wake(pdev))
		pm_runtime_get_noresume(&pdev->dev);

	/* restore original MAC address */
	rtl_rar_set(tp, dev->perm_addr);

	rtl_disable_msi(pdev, tp);
	rtl8169_release_board(pdev, dev, tp->mmio_addr);
	pci_set_drvdata(pdev, NULL);
}

6046 6047 6048 6049 6050 6051 6052 6053 6054 6055 6056 6057 6058 6059 6060 6061 6062 6063 6064
static const struct net_device_ops rtl_netdev_ops = {
	.ndo_open		= rtl8169_open,
	.ndo_stop		= rtl8169_close,
	.ndo_get_stats64	= rtl8169_get_stats64,
	.ndo_start_xmit		= rtl8169_start_xmit,
	.ndo_tx_timeout		= rtl8169_tx_timeout,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_change_mtu		= rtl8169_change_mtu,
	.ndo_fix_features	= rtl8169_fix_features,
	.ndo_set_features	= rtl8169_set_features,
	.ndo_set_mac_address	= rtl_set_mac_address,
	.ndo_do_ioctl		= rtl8169_ioctl,
	.ndo_set_rx_mode	= rtl_set_rx_mode,
#ifdef CONFIG_NET_POLL_CONTROLLER
	.ndo_poll_controller	= rtl8169_netpoll,
#endif

};

6065 6066 6067 6068 6069 6070 6071 6072 6073 6074 6075 6076 6077 6078 6079 6080 6081 6082 6083 6084 6085 6086 6087 6088
static int __devinit
rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
	const unsigned int region = cfg->region;
	struct rtl8169_private *tp;
	struct mii_if_info *mii;
	struct net_device *dev;
	void __iomem *ioaddr;
	int chipset, i;
	int rc;

	if (netif_msg_drv(&debug)) {
		printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
		       MODULENAME, RTL8169_VERSION);
	}

	dev = alloc_etherdev(sizeof (*tp));
	if (!dev) {
		rc = -ENOMEM;
		goto out;
	}

	SET_NETDEV_DEV(dev, &pdev->dev);
6089
	dev->netdev_ops = &rtl_netdev_ops;
6090 6091 6092 6093 6094 6095 6096 6097 6098 6099 6100 6101 6102 6103 6104 6105 6106 6107 6108 6109 6110 6111 6112 6113 6114 6115 6116 6117 6118 6119 6120 6121 6122 6123 6124 6125 6126 6127 6128 6129 6130 6131 6132 6133 6134 6135 6136 6137 6138 6139 6140 6141 6142 6143 6144 6145 6146 6147 6148 6149 6150 6151 6152 6153 6154 6155 6156 6157 6158 6159 6160 6161 6162 6163 6164 6165 6166 6167 6168 6169 6170 6171 6172 6173 6174 6175 6176 6177 6178 6179 6180 6181 6182 6183 6184 6185 6186 6187 6188 6189 6190 6191 6192 6193 6194 6195 6196 6197 6198 6199 6200 6201 6202 6203 6204 6205 6206 6207 6208 6209 6210 6211 6212 6213 6214 6215 6216 6217 6218 6219 6220 6221 6222 6223 6224 6225 6226 6227 6228 6229 6230 6231 6232 6233 6234 6235 6236 6237 6238 6239 6240 6241 6242 6243 6244 6245 6246 6247 6248 6249 6250 6251 6252 6253 6254 6255 6256 6257 6258 6259 6260 6261 6262 6263 6264 6265 6266 6267 6268 6269 6270 6271 6272 6273 6274 6275 6276 6277 6278 6279 6280 6281 6282 6283 6284 6285 6286 6287 6288 6289 6290 6291 6292 6293 6294 6295 6296 6297 6298 6299 6300 6301 6302 6303 6304 6305 6306 6307 6308 6309
	tp = netdev_priv(dev);
	tp->dev = dev;
	tp->pci_dev = pdev;
	tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);

	mii = &tp->mii;
	mii->dev = dev;
	mii->mdio_read = rtl_mdio_read;
	mii->mdio_write = rtl_mdio_write;
	mii->phy_id_mask = 0x1f;
	mii->reg_num_mask = 0x1f;
	mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);

	/* disable ASPM completely as that cause random device stop working
	 * problems as well as full system hangs for some PCIe devices users */
	pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
				     PCIE_LINK_STATE_CLKPM);

	/* enable device (incl. PCI PM wakeup and hotplug setup) */
	rc = pci_enable_device(pdev);
	if (rc < 0) {
		netif_err(tp, probe, dev, "enable failure\n");
		goto err_out_free_dev_1;
	}

	if (pci_set_mwi(pdev) < 0)
		netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");

	/* make sure PCI base addr 1 is MMIO */
	if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
		netif_err(tp, probe, dev,
			  "region #%d not an MMIO resource, aborting\n",
			  region);
		rc = -ENODEV;
		goto err_out_mwi_2;
	}

	/* check for weird/broken PCI region reporting */
	if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
		netif_err(tp, probe, dev,
			  "Invalid PCI region size(s), aborting\n");
		rc = -ENODEV;
		goto err_out_mwi_2;
	}

	rc = pci_request_regions(pdev, MODULENAME);
	if (rc < 0) {
		netif_err(tp, probe, dev, "could not request regions\n");
		goto err_out_mwi_2;
	}

	tp->cp_cmd = RxChkSum;

	if ((sizeof(dma_addr_t) > 4) &&
	    !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
		tp->cp_cmd |= PCIDAC;
		dev->features |= NETIF_F_HIGHDMA;
	} else {
		rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
		if (rc < 0) {
			netif_err(tp, probe, dev, "DMA configuration failed\n");
			goto err_out_free_res_3;
		}
	}

	/* ioremap MMIO region */
	ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
	if (!ioaddr) {
		netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
		rc = -EIO;
		goto err_out_free_res_3;
	}
	tp->mmio_addr = ioaddr;

	if (!pci_is_pcie(pdev))
		netif_info(tp, probe, dev, "not PCI Express\n");

	/* Identify chip attached to board */
	rtl8169_get_mac_version(tp, dev, cfg->default_ver);

	rtl_init_rxcfg(tp);

	rtl_irq_disable(tp);

	rtl_hw_reset(tp);

	rtl_ack_events(tp, 0xffff);

	pci_set_master(pdev);

	/*
	 * Pretend we are using VLANs; This bypasses a nasty bug where
	 * Interrupts stop flowing on high load on 8110SCd controllers.
	 */
	if (tp->mac_version == RTL_GIGA_MAC_VER_05)
		tp->cp_cmd |= RxVlan;

	rtl_init_mdio_ops(tp);
	rtl_init_pll_power_ops(tp);
	rtl_init_jumbo_ops(tp);

	rtl8169_print_mac_version(tp);

	chipset = tp->mac_version;
	tp->txd_version = rtl_chip_infos[chipset].txd_version;

	RTL_W8(Cfg9346, Cfg9346_Unlock);
	RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
	RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
	if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
		tp->features |= RTL_FEATURE_WOL;
	if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
		tp->features |= RTL_FEATURE_WOL;
	tp->features |= rtl_try_msi(tp, cfg);
	RTL_W8(Cfg9346, Cfg9346_Lock);

	if (rtl_tbi_enabled(tp)) {
		tp->set_speed = rtl8169_set_speed_tbi;
		tp->get_settings = rtl8169_gset_tbi;
		tp->phy_reset_enable = rtl8169_tbi_reset_enable;
		tp->phy_reset_pending = rtl8169_tbi_reset_pending;
		tp->link_ok = rtl8169_tbi_link_ok;
		tp->do_ioctl = rtl_tbi_ioctl;
	} else {
		tp->set_speed = rtl8169_set_speed_xmii;
		tp->get_settings = rtl8169_gset_xmii;
		tp->phy_reset_enable = rtl8169_xmii_reset_enable;
		tp->phy_reset_pending = rtl8169_xmii_reset_pending;
		tp->link_ok = rtl8169_xmii_link_ok;
		tp->do_ioctl = rtl_xmii_ioctl;
	}

	mutex_init(&tp->wk.mutex);

	/* Get MAC address */
	for (i = 0; i < ETH_ALEN; i++)
		dev->dev_addr[i] = RTL_R8(MAC0 + i);
	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

	SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
	dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
	dev->irq = pdev->irq;
	dev->base_addr = (unsigned long) ioaddr;

	netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);

	/* don't enable SG, IP_CSUM and TSO by default - it might not work
	 * properly for all devices */
	dev->features |= NETIF_F_RXCSUM |
		NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;

	dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
		NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
	dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
		NETIF_F_HIGHDMA;

	if (tp->mac_version == RTL_GIGA_MAC_VER_05)
		/* 8110SCd requires hardware Rx VLAN - disallow toggling */
		dev->hw_features &= ~NETIF_F_HW_VLAN_RX;

	dev->hw_features |= NETIF_F_RXALL;
	dev->hw_features |= NETIF_F_RXFCS;

	tp->hw_start = cfg->hw_start;
	tp->event_slow = cfg->event_slow;

	tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
		~(RxBOVF | RxFOVF) : ~0;

	init_timer(&tp->timer);
	tp->timer.data = (unsigned long) dev;
	tp->timer.function = rtl8169_phy_timer;

	tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;

	rc = register_netdev(dev);
	if (rc < 0)
		goto err_out_msi_4;

	pci_set_drvdata(pdev, dev);

	netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
		   rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
		   (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
	if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
		netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
			   "tx checksumming: %s]\n",
			   rtl_chip_infos[chipset].jumbo_max,
			   rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
	}

	if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_28 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_31) {
		rtl8168_driver_start(tp);
	}

	device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);

	if (pci_dev_run_wake(pdev))
		pm_runtime_put_noidle(&pdev->dev);

	netif_carrier_off(dev);

out:
	return rc;

err_out_msi_4:
	rtl_disable_msi(pdev, tp);
	iounmap(ioaddr);
err_out_free_res_3:
	pci_release_regions(pdev);
err_out_mwi_2:
	pci_clear_mwi(pdev);
	pci_disable_device(pdev);
err_out_free_dev_1:
	free_netdev(dev);
	goto out;
}

L
Linus Torvalds 已提交
6310 6311 6312
static struct pci_driver rtl8169_pci_driver = {
	.name		= MODULENAME,
	.id_table	= rtl8169_pci_tbl,
6313
	.probe		= rtl_init_one,
6314
	.remove		= __devexit_p(rtl_remove_one),
F
Francois Romieu 已提交
6315
	.shutdown	= rtl_shutdown,
6316
	.driver.pm	= RTL8169_PM_OPS,
L
Linus Torvalds 已提交
6317 6318
};

F
Francois Romieu 已提交
6319
static int __init rtl8169_init_module(void)
L
Linus Torvalds 已提交
6320
{
6321
	return pci_register_driver(&rtl8169_pci_driver);
L
Linus Torvalds 已提交
6322 6323
}

F
Francois Romieu 已提交
6324
static void __exit rtl8169_cleanup_module(void)
L
Linus Torvalds 已提交
6325 6326 6327 6328 6329 6330
{
	pci_unregister_driver(&rtl8169_pci_driver);
}

module_init(rtl8169_init_module);
module_exit(rtl8169_cleanup_module);