r8169.c 189.7 KB
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/*
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 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
 *
 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
 * Copyright (c) a lot of people too. Please respect their work.
 *
 * See MAINTAINERS file for support contact information.
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 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/if_vlan.h>
#include <linux/crc32.h>
#include <linux/in.h>
#include <linux/ip.h>
#include <linux/tcp.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/pm_runtime.h>
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#include <linux/firmware.h>
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#include <linux/pci-aspm.h>
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#include <linux/prefetch.h>
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#include <linux/ipv6.h>
#include <net/ip6_checksum.h>
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#include <asm/io.h>
#include <asm/irq.h>

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#define RTL8169_VERSION "2.3LK-NAPI"
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#define MODULENAME "r8169"
#define PFX MODULENAME ": "

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#define FIRMWARE_8168D_1	"rtl_nic/rtl8168d-1.fw"
#define FIRMWARE_8168D_2	"rtl_nic/rtl8168d-2.fw"
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#define FIRMWARE_8168E_1	"rtl_nic/rtl8168e-1.fw"
#define FIRMWARE_8168E_2	"rtl_nic/rtl8168e-2.fw"
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#define FIRMWARE_8168E_3	"rtl_nic/rtl8168e-3.fw"
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#define FIRMWARE_8168F_1	"rtl_nic/rtl8168f-1.fw"
#define FIRMWARE_8168F_2	"rtl_nic/rtl8168f-2.fw"
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#define FIRMWARE_8105E_1	"rtl_nic/rtl8105e-1.fw"
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#define FIRMWARE_8402_1		"rtl_nic/rtl8402-1.fw"
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#define FIRMWARE_8411_1		"rtl_nic/rtl8411-1.fw"
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#define FIRMWARE_8411_2		"rtl_nic/rtl8411-2.fw"
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#define FIRMWARE_8106E_1	"rtl_nic/rtl8106e-1.fw"
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#define FIRMWARE_8106E_2	"rtl_nic/rtl8106e-2.fw"
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#define FIRMWARE_8168G_2	"rtl_nic/rtl8168g-2.fw"
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#define FIRMWARE_8168G_3	"rtl_nic/rtl8168g-3.fw"
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#define FIRMWARE_8168H_1	"rtl_nic/rtl8168h-1.fw"
#define FIRMWARE_8168H_2	"rtl_nic/rtl8168h-2.fw"
#define FIRMWARE_8107E_1	"rtl_nic/rtl8107e-1.fw"
#define FIRMWARE_8107E_2	"rtl_nic/rtl8107e-2.fw"
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#ifdef RTL8169_DEBUG
#define assert(expr) \
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	if (!(expr)) {					\
		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\
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		#expr,__FILE__,__func__,__LINE__);		\
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	}
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#define dprintk(fmt, args...) \
	do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
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#else
#define assert(expr) do {} while (0)
#define dprintk(fmt, args...)	do {} while (0)
#endif /* RTL8169_DEBUG */

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#define R8169_MSG_DEFAULT \
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	(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
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#define TX_SLOTS_AVAIL(tp) \
	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)

/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
#define TX_FRAGS_READY_FOR(tp,nr_frags) \
	(TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
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/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
   The RTL chips use a 64 element hash table based on the Ethernet CRC. */
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static const int multicast_filter_limit = 32;
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#define MAX_READ_REQUEST_SHIFT	12
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#define TX_DMA_BURST	7	/* Maximum PCI burst, '7' is unlimited */
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#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */

#define R8169_REGS_SIZE		256
#define R8169_NAPI_WEIGHT	64
#define NUM_TX_DESC	64	/* Number of Tx descriptor registers */
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#define NUM_RX_DESC	256U	/* Number of Rx descriptor registers */
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#define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))
#define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))

#define RTL8169_TX_TIMEOUT	(6*HZ)
#define RTL8169_PHY_TIMEOUT	(10*HZ)

/* write/read MMIO register */
#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))
#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))
#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))
#define RTL_R8(reg)		readb (ioaddr + (reg))
#define RTL_R16(reg)		readw (ioaddr + (reg))
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#define RTL_R32(reg)		readl (ioaddr + (reg))
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enum mac_version {
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	RTL_GIGA_MAC_VER_01 = 0,
	RTL_GIGA_MAC_VER_02,
	RTL_GIGA_MAC_VER_03,
	RTL_GIGA_MAC_VER_04,
	RTL_GIGA_MAC_VER_05,
	RTL_GIGA_MAC_VER_06,
	RTL_GIGA_MAC_VER_07,
	RTL_GIGA_MAC_VER_08,
	RTL_GIGA_MAC_VER_09,
	RTL_GIGA_MAC_VER_10,
	RTL_GIGA_MAC_VER_11,
	RTL_GIGA_MAC_VER_12,
	RTL_GIGA_MAC_VER_13,
	RTL_GIGA_MAC_VER_14,
	RTL_GIGA_MAC_VER_15,
	RTL_GIGA_MAC_VER_16,
	RTL_GIGA_MAC_VER_17,
	RTL_GIGA_MAC_VER_18,
	RTL_GIGA_MAC_VER_19,
	RTL_GIGA_MAC_VER_20,
	RTL_GIGA_MAC_VER_21,
	RTL_GIGA_MAC_VER_22,
	RTL_GIGA_MAC_VER_23,
	RTL_GIGA_MAC_VER_24,
	RTL_GIGA_MAC_VER_25,
	RTL_GIGA_MAC_VER_26,
	RTL_GIGA_MAC_VER_27,
	RTL_GIGA_MAC_VER_28,
	RTL_GIGA_MAC_VER_29,
	RTL_GIGA_MAC_VER_30,
	RTL_GIGA_MAC_VER_31,
	RTL_GIGA_MAC_VER_32,
	RTL_GIGA_MAC_VER_33,
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	RTL_GIGA_MAC_VER_34,
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	RTL_GIGA_MAC_VER_35,
	RTL_GIGA_MAC_VER_36,
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	RTL_GIGA_MAC_VER_37,
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	RTL_GIGA_MAC_VER_38,
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	RTL_GIGA_MAC_VER_39,
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	RTL_GIGA_MAC_VER_40,
	RTL_GIGA_MAC_VER_41,
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	RTL_GIGA_MAC_VER_42,
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	RTL_GIGA_MAC_VER_43,
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	RTL_GIGA_MAC_VER_44,
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	RTL_GIGA_MAC_VER_45,
	RTL_GIGA_MAC_VER_46,
	RTL_GIGA_MAC_VER_47,
	RTL_GIGA_MAC_VER_48,
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	RTL_GIGA_MAC_NONE   = 0xff,
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};

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enum rtl_tx_desc_version {
	RTL_TD_0	= 0,
	RTL_TD_1	= 1,
};

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#define JUMBO_1K	ETH_DATA_LEN
#define JUMBO_4K	(4*1024 - ETH_HLEN - 2)
#define JUMBO_6K	(6*1024 - ETH_HLEN - 2)
#define JUMBO_7K	(7*1024 - ETH_HLEN - 2)
#define JUMBO_9K	(9*1024 - ETH_HLEN - 2)

#define _R(NAME,TD,FW,SZ,B) {	\
	.name = NAME,		\
	.txd_version = TD,	\
	.fw_name = FW,		\
	.jumbo_max = SZ,	\
	.jumbo_tx_csum = B	\
}
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static const struct {
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	const char *name;
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	enum rtl_tx_desc_version txd_version;
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	const char *fw_name;
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	u16 jumbo_max;
	bool jumbo_tx_csum;
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} rtl_chip_infos[] = {
	/* PCI devices. */
	[RTL_GIGA_MAC_VER_01] =
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		_R("RTL8169",		RTL_TD_0, NULL, JUMBO_7K, true),
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	[RTL_GIGA_MAC_VER_02] =
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		_R("RTL8169s",		RTL_TD_0, NULL, JUMBO_7K, true),
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	[RTL_GIGA_MAC_VER_03] =
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		_R("RTL8110s",		RTL_TD_0, NULL, JUMBO_7K, true),
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	[RTL_GIGA_MAC_VER_04] =
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		_R("RTL8169sb/8110sb",	RTL_TD_0, NULL, JUMBO_7K, true),
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	[RTL_GIGA_MAC_VER_05] =
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		_R("RTL8169sc/8110sc",	RTL_TD_0, NULL, JUMBO_7K, true),
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	[RTL_GIGA_MAC_VER_06] =
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		_R("RTL8169sc/8110sc",	RTL_TD_0, NULL, JUMBO_7K, true),
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	/* PCI-E devices. */
	[RTL_GIGA_MAC_VER_07] =
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		_R("RTL8102e",		RTL_TD_1, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_08] =
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		_R("RTL8102e",		RTL_TD_1, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_09] =
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		_R("RTL8102e",		RTL_TD_1, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_10] =
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		_R("RTL8101e",		RTL_TD_0, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_11] =
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		_R("RTL8168b/8111b",	RTL_TD_0, NULL, JUMBO_4K, false),
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	[RTL_GIGA_MAC_VER_12] =
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		_R("RTL8168b/8111b",	RTL_TD_0, NULL, JUMBO_4K, false),
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	[RTL_GIGA_MAC_VER_13] =
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		_R("RTL8101e",		RTL_TD_0, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_14] =
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		_R("RTL8100e",		RTL_TD_0, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_15] =
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		_R("RTL8100e",		RTL_TD_0, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_16] =
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		_R("RTL8101e",		RTL_TD_0, NULL, JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_17] =
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		_R("RTL8168b/8111b",	RTL_TD_0, NULL, JUMBO_4K, false),
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	[RTL_GIGA_MAC_VER_18] =
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		_R("RTL8168cp/8111cp",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_19] =
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		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_20] =
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		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_21] =
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		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_22] =
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		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_23] =
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		_R("RTL8168cp/8111cp",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_24] =
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		_R("RTL8168cp/8111cp",	RTL_TD_1, NULL, JUMBO_6K, false),
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	[RTL_GIGA_MAC_VER_25] =
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		_R("RTL8168d/8111d",	RTL_TD_1, FIRMWARE_8168D_1,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_26] =
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		_R("RTL8168d/8111d",	RTL_TD_1, FIRMWARE_8168D_2,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_27] =
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		_R("RTL8168dp/8111dp",	RTL_TD_1, NULL, JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_28] =
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		_R("RTL8168dp/8111dp",	RTL_TD_1, NULL, JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_29] =
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		_R("RTL8105e",		RTL_TD_1, FIRMWARE_8105E_1,
							JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_30] =
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		_R("RTL8105e",		RTL_TD_1, FIRMWARE_8105E_1,
							JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_31] =
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		_R("RTL8168dp/8111dp",	RTL_TD_1, NULL, JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_32] =
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		_R("RTL8168e/8111e",	RTL_TD_1, FIRMWARE_8168E_1,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_33] =
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		_R("RTL8168e/8111e",	RTL_TD_1, FIRMWARE_8168E_2,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_34] =
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		_R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_35] =
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		_R("RTL8168f/8111f",	RTL_TD_1, FIRMWARE_8168F_1,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_36] =
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		_R("RTL8168f/8111f",	RTL_TD_1, FIRMWARE_8168F_2,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_37] =
		_R("RTL8402",		RTL_TD_1, FIRMWARE_8402_1,
							JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_38] =
		_R("RTL8411",		RTL_TD_1, FIRMWARE_8411_1,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_39] =
		_R("RTL8106e",		RTL_TD_1, FIRMWARE_8106E_1,
							JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_40] =
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		_R("RTL8168g/8111g",	RTL_TD_1, FIRMWARE_8168G_2,
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							JUMBO_9K, false),
	[RTL_GIGA_MAC_VER_41] =
		_R("RTL8168g/8111g",	RTL_TD_1, NULL, JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_42] =
		_R("RTL8168g/8111g",	RTL_TD_1, FIRMWARE_8168G_3,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_43] =
		_R("RTL8106e",		RTL_TD_1, FIRMWARE_8106E_2,
							JUMBO_1K, true),
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	[RTL_GIGA_MAC_VER_44] =
		_R("RTL8411",		RTL_TD_1, FIRMWARE_8411_2,
							JUMBO_9K, false),
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	[RTL_GIGA_MAC_VER_45] =
		_R("RTL8168h/8111h",	RTL_TD_1, FIRMWARE_8168H_1,
							JUMBO_9K, false),
	[RTL_GIGA_MAC_VER_46] =
		_R("RTL8168h/8111h",	RTL_TD_1, FIRMWARE_8168H_2,
							JUMBO_9K, false),
	[RTL_GIGA_MAC_VER_47] =
		_R("RTL8107e",		RTL_TD_1, FIRMWARE_8107E_1,
							JUMBO_1K, false),
	[RTL_GIGA_MAC_VER_48] =
		_R("RTL8107e",		RTL_TD_1, FIRMWARE_8107E_2,
							JUMBO_1K, false),
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};
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#undef _R
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enum cfg_version {
	RTL_CFG_0 = 0x00,
	RTL_CFG_1,
	RTL_CFG_2
};

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static const struct pci_device_id rtl8169_pci_tbl[] = {
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_2 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_0 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_1 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },
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	{ PCI_VENDOR_ID_DLINK,			0x4300,
		PCI_VENDOR_ID_DLINK, 0x4b10,		 0, 0, RTL_CFG_1 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4302), 0, 0, RTL_CFG_0 },
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	{ PCI_DEVICE(PCI_VENDOR_ID_AT,		0xc107), 0, 0, RTL_CFG_0 },
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	{ PCI_DEVICE(0x16ec,			0x0116), 0, 0, RTL_CFG_0 },
	{ PCI_VENDOR_ID_LINKSYS,		0x1032,
		PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
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	{ 0x0001,				0x8168,
		PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
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	{0,},
};

MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);

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static int rx_buf_sz = 16383;
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static int use_dac;
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static struct {
	u32 msg_enable;
} debug = { -1 };
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enum rtl_registers {
	MAC0		= 0,	/* Ethernet hardware address. */
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	MAC4		= 4,
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	MAR0		= 8,	/* Multicast filter. */
	CounterAddrLow		= 0x10,
	CounterAddrHigh		= 0x14,
	TxDescStartAddrLow	= 0x20,
	TxDescStartAddrHigh	= 0x24,
	TxHDescStartAddrLow	= 0x28,
	TxHDescStartAddrHigh	= 0x2c,
	FLASH		= 0x30,
	ERSR		= 0x36,
	ChipCmd		= 0x37,
	TxPoll		= 0x38,
	IntrMask	= 0x3c,
	IntrStatus	= 0x3e,
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	TxConfig	= 0x40,
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#define	TXCFG_AUTO_FIFO			(1 << 7)	/* 8111e-vl */
#define	TXCFG_EMPTY			(1 << 11)	/* 8111e-vl */
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	RxConfig	= 0x44,
#define	RX128_INT_EN			(1 << 15)	/* 8111c and later */
#define	RX_MULTI_EN			(1 << 14)	/* 8111c only */
#define	RXCFG_FIFO_SHIFT		13
					/* No threshold before first PCI xfer */
#define	RX_FIFO_THRESH			(7 << RXCFG_FIFO_SHIFT)
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#define	RX_EARLY_OFF			(1 << 11)
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#define	RXCFG_DMA_SHIFT			8
					/* Unlimited maximum PCI burst. */
#define	RX_DMA_BURST			(7 << RXCFG_DMA_SHIFT)
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	RxMissed	= 0x4c,
	Cfg9346		= 0x50,
	Config0		= 0x51,
	Config1		= 0x52,
	Config2		= 0x53,
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#define PME_SIGNAL			(1 << 5)	/* 8168c and later */

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	Config3		= 0x54,
	Config4		= 0x55,
	Config5		= 0x56,
	MultiIntr	= 0x5c,
	PHYAR		= 0x60,
	PHYstatus	= 0x6c,
	RxMaxSize	= 0xda,
	CPlusCmd	= 0xe0,
	IntrMitigate	= 0xe2,
	RxDescAddrLow	= 0xe4,
	RxDescAddrHigh	= 0xe8,
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	EarlyTxThres	= 0xec,	/* 8169. Unit of 32 bytes. */

#define NoEarlyTx	0x3f	/* Max value : no early transmit. */

	MaxTxPacketSize	= 0xec,	/* 8101/8168. Unit of 128 bytes. */

#define TxPacketMax	(8064 >> 7)
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#define EarlySize	0x27
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	FuncEvent	= 0xf0,
	FuncEventMask	= 0xf4,
	FuncPresetState	= 0xf8,
	FuncForceEvent	= 0xfc,
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};

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enum rtl8110_registers {
	TBICSR			= 0x64,
	TBI_ANAR		= 0x68,
	TBI_LPAR		= 0x6a,
};

enum rtl8168_8101_registers {
	CSIDR			= 0x64,
	CSIAR			= 0x68,
#define	CSIAR_FLAG			0x80000000
#define	CSIAR_WRITE_CMD			0x80000000
#define	CSIAR_BYTE_ENABLE		0x0f
#define	CSIAR_BYTE_ENABLE_SHIFT		12
#define	CSIAR_ADDR_MASK			0x0fff
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#define CSIAR_FUNC_CARD			0x00000000
#define CSIAR_FUNC_SDIO			0x00010000
#define CSIAR_FUNC_NIC			0x00020000
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#define CSIAR_FUNC_NIC2			0x00010000
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	PMCH			= 0x6f,
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	EPHYAR			= 0x80,
#define	EPHYAR_FLAG			0x80000000
#define	EPHYAR_WRITE_CMD		0x80000000
#define	EPHYAR_REG_MASK			0x1f
#define	EPHYAR_REG_SHIFT		16
#define	EPHYAR_DATA_MASK		0xffff
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	DLLPR			= 0xd0,
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#define	PFM_EN				(1 << 6)
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#define	TX_10M_PS_EN			(1 << 7)
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	DBG_REG			= 0xd1,
#define	FIX_NAK_1			(1 << 4)
#define	FIX_NAK_2			(1 << 3)
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	TWSI			= 0xd2,
	MCU			= 0xd3,
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#define	NOW_IS_OOB			(1 << 7)
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#define	TX_EMPTY			(1 << 5)
#define	RX_EMPTY			(1 << 4)
#define	RXTX_EMPTY			(TX_EMPTY | RX_EMPTY)
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#define	EN_NDP				(1 << 3)
#define	EN_OOB_RESET			(1 << 2)
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#define	LINK_LIST_RDY			(1 << 1)
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	EFUSEAR			= 0xdc,
#define	EFUSEAR_FLAG			0x80000000
#define	EFUSEAR_WRITE_CMD		0x80000000
#define	EFUSEAR_READ_CMD		0x00000000
#define	EFUSEAR_REG_MASK		0x03ff
#define	EFUSEAR_REG_SHIFT		8
#define	EFUSEAR_DATA_MASK		0xff
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	MISC_1			= 0xf2,
#define	PFM_D3COLD_EN			(1 << 6)
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};

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enum rtl8168_registers {
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	LED_FREQ		= 0x1a,
	EEE_LED			= 0x1b,
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	ERIDR			= 0x70,
	ERIAR			= 0x74,
#define ERIAR_FLAG			0x80000000
#define ERIAR_WRITE_CMD			0x80000000
#define ERIAR_READ_CMD			0x00000000
#define ERIAR_ADDR_BYTE_ALIGN		4
#define ERIAR_TYPE_SHIFT		16
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#define ERIAR_EXGMAC			(0x00 << ERIAR_TYPE_SHIFT)
#define ERIAR_MSIX			(0x01 << ERIAR_TYPE_SHIFT)
#define ERIAR_ASF			(0x02 << ERIAR_TYPE_SHIFT)
#define ERIAR_MASK_SHIFT		12
#define ERIAR_MASK_0001			(0x1 << ERIAR_MASK_SHIFT)
#define ERIAR_MASK_0011			(0x3 << ERIAR_MASK_SHIFT)
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#define ERIAR_MASK_0100			(0x4 << ERIAR_MASK_SHIFT)
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#define ERIAR_MASK_0101			(0x5 << ERIAR_MASK_SHIFT)
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#define ERIAR_MASK_1111			(0xf << ERIAR_MASK_SHIFT)
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	EPHY_RXER_NUM		= 0x7c,
	OCPDR			= 0xb0,	/* OCP GPHY access */
#define OCPDR_WRITE_CMD			0x80000000
#define OCPDR_READ_CMD			0x00000000
#define OCPDR_REG_MASK			0x7f
#define OCPDR_GPHY_REG_SHIFT		16
#define OCPDR_DATA_MASK			0xffff
	OCPAR			= 0xb4,
#define OCPAR_FLAG			0x80000000
#define OCPAR_GPHY_WRITE_CMD		0x8000f060
#define OCPAR_GPHY_READ_CMD		0x0000f060
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	GPHY_OCP		= 0xb8,
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	RDSAR1			= 0xd0,	/* 8168c only. Undocumented on 8168dp */
	MISC			= 0xf0,	/* 8168e only. */
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#define TXPLA_RST			(1 << 29)
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#define DISABLE_LAN_EN			(1 << 23) /* Enable GPIO pin */
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#define PWM_EN				(1 << 22)
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#define RXDV_GATED_EN			(1 << 19)
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#define EARLY_TALLY_EN			(1 << 16)
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};

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enum rtl_register_content {
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	/* InterruptStatusBits */
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	SYSErr		= 0x8000,
	PCSTimeout	= 0x4000,
	SWInt		= 0x0100,
	TxDescUnavail	= 0x0080,
	RxFIFOOver	= 0x0040,
	LinkChg		= 0x0020,
	RxOverflow	= 0x0010,
	TxErr		= 0x0008,
	TxOK		= 0x0004,
	RxErr		= 0x0002,
	RxOK		= 0x0001,
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	/* RxStatusDesc */
512
	RxBOVF	= (1 << 24),
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	RxFOVF	= (1 << 23),
	RxRWT	= (1 << 22),
	RxRES	= (1 << 21),
	RxRUNT	= (1 << 20),
	RxCRC	= (1 << 19),
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	/* ChipCmdBits */
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	StopReq		= 0x80,
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	CmdReset	= 0x10,
	CmdRxEnb	= 0x08,
	CmdTxEnb	= 0x04,
	RxBufEmpty	= 0x01,
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	/* TXPoll register p.5 */
	HPQ		= 0x80,		/* Poll cmd on the high prio queue */
	NPQ		= 0x40,		/* Poll cmd on the low prio queue */
	FSWInt		= 0x01,		/* Forced software interrupt */

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	/* Cfg9346Bits */
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	Cfg9346_Lock	= 0x00,
	Cfg9346_Unlock	= 0xc0,
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	/* rx_mode_bits */
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	AcceptErr	= 0x20,
	AcceptRunt	= 0x10,
	AcceptBroadcast	= 0x08,
	AcceptMulticast	= 0x04,
	AcceptMyPhys	= 0x02,
	AcceptAllPhys	= 0x01,
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#define RX_CONFIG_ACCEPT_MASK		0x3f
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	/* TxConfigBits */
	TxInterFrameGapShift = 24,
	TxDMAShift = 8,	/* DMA burst value (0-7) is shift this many bits */

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	/* Config1 register p.24 */
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	LEDS1		= (1 << 7),
	LEDS0		= (1 << 6),
	Speed_down	= (1 << 4),
	MEMMAP		= (1 << 3),
	IOMAP		= (1 << 2),
	VPD		= (1 << 1),
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	PMEnable	= (1 << 0),	/* Power Management Enable */

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	/* Config2 register p. 25 */
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	ClkReqEn	= (1 << 7),	/* Clock Request Enable */
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	MSIEnable	= (1 << 5),	/* 8169 only. Reserved in the 8168. */
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	PCI_Clock_66MHz = 0x01,
	PCI_Clock_33MHz = 0x00,

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	/* Config3 register p.25 */
	MagicPacket	= (1 << 5),	/* Wake up when receives a Magic Packet */
	LinkUp		= (1 << 4),	/* Wake up when the cable connection is re-established */
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	Jumbo_En0	= (1 << 2),	/* 8168 only. Reserved in the 8168b */
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	Rdy_to_L23	= (1 << 1),	/* L23 Enable */
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	Beacon_en	= (1 << 0),	/* 8168 only. Reserved in the 8168b */
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	/* Config4 register */
	Jumbo_En1	= (1 << 1),	/* 8168 only. Reserved in the 8168b */

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	/* Config5 register p.27 */
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	BWF		= (1 << 6),	/* Accept Broadcast wakeup frame */
	MWF		= (1 << 5),	/* Accept Multicast wakeup frame */
	UWF		= (1 << 4),	/* Accept Unicast wakeup frame */
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	Spi_en		= (1 << 3),
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	LanWake		= (1 << 1),	/* LanWake enable/disable */
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	PMEStatus	= (1 << 0),	/* PME status can be reset by PCI RST# */
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	ASPM_en		= (1 << 0),	/* ASPM enable */
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	/* TBICSR p.28 */
	TBIReset	= 0x80000000,
	TBILoopback	= 0x40000000,
	TBINwEnable	= 0x20000000,
	TBINwRestart	= 0x10000000,
	TBILinkOk	= 0x02000000,
	TBINwComplete	= 0x01000000,

	/* CPlusCmd p.31 */
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	EnableBist	= (1 << 15),	// 8168 8101
	Mac_dbgo_oe	= (1 << 14),	// 8168 8101
	Normal_mode	= (1 << 13),	// unused
	Force_half_dup	= (1 << 12),	// 8168 8101
	Force_rxflow_en	= (1 << 11),	// 8168 8101
	Force_txflow_en	= (1 << 10),	// 8168 8101
	Cxpl_dbg_sel	= (1 << 9),	// 8168 8101
	ASF		= (1 << 8),	// 8168 8101
	PktCntrDisable	= (1 << 7),	// 8168 8101
	Mac_dbgo_sel	= 0x001c,	// 8168
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	RxVlan		= (1 << 6),
	RxChkSum	= (1 << 5),
	PCIDAC		= (1 << 4),
	PCIMulRW	= (1 << 3),
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	INTT_0		= 0x0000,	// 8168
	INTT_1		= 0x0001,	// 8168
	INTT_2		= 0x0002,	// 8168
	INTT_3		= 0x0003,	// 8168
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	/* rtl8169_PHYstatus */
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	TBI_Enable	= 0x80,
	TxFlowCtrl	= 0x40,
	RxFlowCtrl	= 0x20,
	_1000bpsF	= 0x10,
	_100bps		= 0x08,
	_10bps		= 0x04,
	LinkStatus	= 0x02,
	FullDup		= 0x01,
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	/* _TBICSRBit */
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	TBILinkOK	= 0x02000000,
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	/* DumpCounterCommand */
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	CounterDump	= 0x8,
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	/* magic enable v2 */
	MagicPacket_v2	= (1 << 16),	/* Wake up when receives a Magic Packet */
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};

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enum rtl_desc_bit {
	/* First doubleword. */
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	DescOwn		= (1 << 31), /* Descriptor is owned by NIC */
	RingEnd		= (1 << 30), /* End of descriptor ring */
	FirstFrag	= (1 << 29), /* First segment of a packet */
	LastFrag	= (1 << 28), /* Final segment of a packet */
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};

/* Generic case. */
enum rtl_tx_desc_bit {
	/* First doubleword. */
	TD_LSO		= (1 << 27),		/* Large Send Offload */
#define TD_MSS_MAX			0x07ffu	/* MSS value */
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	/* Second doubleword. */
	TxVlanTag	= (1 << 17),		/* Add VLAN tag */
};

/* 8169, 8168b and 810x except 8102e. */
enum rtl_tx_desc_bit_0 {
	/* First doubleword. */
#define TD0_MSS_SHIFT			16	/* MSS position (11 bits) */
	TD0_TCP_CS	= (1 << 16),		/* Calculate TCP/IP checksum */
	TD0_UDP_CS	= (1 << 17),		/* Calculate UDP/IP checksum */
	TD0_IP_CS	= (1 << 18),		/* Calculate IP checksum */
};

/* 8102e, 8168c and beyond. */
enum rtl_tx_desc_bit_1 {
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	/* First doubleword. */
	TD1_GTSENV4	= (1 << 26),		/* Giant Send for IPv4 */
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	TD1_GTSENV6	= (1 << 25),		/* Giant Send for IPv6 */
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#define GTTCPHO_SHIFT			18
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#define GTTCPHO_MAX			0x7fU
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	/* Second doubleword. */
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#define TCPHO_SHIFT			18
#define TCPHO_MAX			0x3ffU
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#define TD1_MSS_SHIFT			18	/* MSS position (11 bits) */
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	TD1_IPv6_CS	= (1 << 28),		/* Calculate IPv6 checksum */
	TD1_IPv4_CS	= (1 << 29),		/* Calculate IPv4 checksum */
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	TD1_TCP_CS	= (1 << 30),		/* Calculate TCP/IP checksum */
	TD1_UDP_CS	= (1 << 31),		/* Calculate UDP/IP checksum */
};
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enum rtl_rx_desc_bit {
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	/* Rx private */
	PID1		= (1 << 18), /* Protocol ID bit 1/2 */
	PID0		= (1 << 17), /* Protocol ID bit 2/2 */

#define RxProtoUDP	(PID1)
#define RxProtoTCP	(PID0)
#define RxProtoIP	(PID1 | PID0)
#define RxProtoMask	RxProtoIP

	IPFail		= (1 << 16), /* IP checksum failed */
	UDPFail		= (1 << 15), /* UDP/IP checksum failed */
	TCPFail		= (1 << 14), /* TCP/IP checksum failed */
	RxVlanTag	= (1 << 16), /* VLAN tag available */
};

#define RsvdMask	0x3fffc000

struct TxDesc {
694 695 696
	__le32 opts1;
	__le32 opts2;
	__le64 addr;
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};

struct RxDesc {
700 701 702
	__le32 opts1;
	__le32 opts2;
	__le64 addr;
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};

struct ring_info {
	struct sk_buff	*skb;
	u32		len;
	u8		__pad[sizeof(void *) - sizeof(u32)];
};

711
enum features {
712 713 714
	RTL_FEATURE_WOL		= (1 << 0),
	RTL_FEATURE_MSI		= (1 << 1),
	RTL_FEATURE_GMII	= (1 << 2),
715 716
};

717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732
struct rtl8169_counters {
	__le64	tx_packets;
	__le64	rx_packets;
	__le64	tx_errors;
	__le32	rx_errors;
	__le16	rx_missed;
	__le16	align_errors;
	__le32	tx_one_collision;
	__le32	tx_multi_collision;
	__le64	rx_unicast;
	__le64	rx_broadcast;
	__le32	rx_multicast;
	__le16	tx_aborted;
	__le16	tx_underun;
};

733
enum rtl_flag {
734
	RTL_FLAG_TASK_ENABLED,
735 736 737 738 739 740
	RTL_FLAG_TASK_SLOW_PENDING,
	RTL_FLAG_TASK_RESET_PENDING,
	RTL_FLAG_TASK_PHY_PENDING,
	RTL_FLAG_MAX
};

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struct rtl8169_stats {
	u64			packets;
	u64			bytes;
	struct u64_stats_sync	syncp;
};

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struct rtl8169_private {
	void __iomem *mmio_addr;	/* memory map physical address */
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	struct pci_dev *pci_dev;
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	struct net_device *dev;
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	struct napi_struct napi;
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	u32 msg_enable;
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	u16 txd_version;
	u16 mac_version;
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	u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
	u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
	u32 dirty_tx;
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	struct rtl8169_stats rx_stats;
	struct rtl8169_stats tx_stats;
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	struct TxDesc *TxDescArray;	/* 256-aligned Tx descriptor ring */
	struct RxDesc *RxDescArray;	/* 256-aligned Rx descriptor ring */
	dma_addr_t TxPhyAddr;
	dma_addr_t RxPhyAddr;
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	void *Rx_databuff[NUM_RX_DESC];	/* Rx data buffers */
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	struct ring_info tx_skb[NUM_TX_DESC];	/* Tx data buffers */
	struct timer_list timer;
	u16 cp_cmd;
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	u16 event_slow;
770 771

	struct mdio_ops {
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		void (*write)(struct rtl8169_private *, int, int);
		int (*read)(struct rtl8169_private *, int);
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	} mdio_ops;

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	struct pll_power_ops {
		void (*down)(struct rtl8169_private *);
		void (*up)(struct rtl8169_private *);
	} pll_power_ops;

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	struct jumbo_ops {
		void (*enable)(struct rtl8169_private *);
		void (*disable)(struct rtl8169_private *);
	} jumbo_ops;

786
	struct csi_ops {
787 788
		void (*write)(struct rtl8169_private *, int, int);
		u32 (*read)(struct rtl8169_private *, int);
789 790
	} csi_ops;

791
	int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
792
	int (*get_settings)(struct net_device *, struct ethtool_cmd *);
793
	void (*phy_reset_enable)(struct rtl8169_private *tp);
794
	void (*hw_start)(struct net_device *);
795
	unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
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	unsigned int (*link_ok)(void __iomem *);
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	int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
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	bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
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	struct {
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		DECLARE_BITMAP(flags, RTL_FLAG_MAX);
		struct mutex mutex;
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		struct work_struct work;
	} wk;

806
	unsigned features;
807 808

	struct mii_if_info mii;
809
	struct rtl8169_counters counters;
810
	u32 saved_wolopts;
811
	u32 opts1_mask;
812

813 814
	struct rtl_fw {
		const struct firmware *fw;
815 816 817 818 819 820 821 822 823

#define RTL_VER_SIZE		32

		char version[RTL_VER_SIZE];

		struct rtl_fw_phy_action {
			__le32 *code;
			size_t size;
		} phy_action;
824
	} *rtl_fw;
825
#define RTL_FIRMWARE_UNKNOWN	ERR_PTR(-EAGAIN)
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	u32 ocp_base;
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};

830
MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
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MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
module_param(use_dac, int, 0);
833
MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
834 835
module_param_named(debug, debug.msg_enable, int, 0);
MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
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MODULE_LICENSE("GPL");
MODULE_VERSION(RTL8169_VERSION);
838 839
MODULE_FIRMWARE(FIRMWARE_8168D_1);
MODULE_FIRMWARE(FIRMWARE_8168D_2);
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MODULE_FIRMWARE(FIRMWARE_8168E_1);
MODULE_FIRMWARE(FIRMWARE_8168E_2);
842
MODULE_FIRMWARE(FIRMWARE_8168E_3);
843
MODULE_FIRMWARE(FIRMWARE_8105E_1);
844 845
MODULE_FIRMWARE(FIRMWARE_8168F_1);
MODULE_FIRMWARE(FIRMWARE_8168F_2);
846
MODULE_FIRMWARE(FIRMWARE_8402_1);
847
MODULE_FIRMWARE(FIRMWARE_8411_1);
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MODULE_FIRMWARE(FIRMWARE_8411_2);
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MODULE_FIRMWARE(FIRMWARE_8106E_1);
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MODULE_FIRMWARE(FIRMWARE_8106E_2);
851
MODULE_FIRMWARE(FIRMWARE_8168G_2);
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MODULE_FIRMWARE(FIRMWARE_8168G_3);
853 854
MODULE_FIRMWARE(FIRMWARE_8168H_1);
MODULE_FIRMWARE(FIRMWARE_8168H_2);
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856 857 858 859 860 861 862 863 864 865
static void rtl_lock_work(struct rtl8169_private *tp)
{
	mutex_lock(&tp->wk.mutex);
}

static void rtl_unlock_work(struct rtl8169_private *tp)
{
	mutex_unlock(&tp->wk.mutex);
}

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static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
{
868 869
	pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
					   PCI_EXP_DEVCTL_READRQ, force);
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}

872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892
struct rtl_cond {
	bool (*check)(struct rtl8169_private *);
	const char *msg;
};

static void rtl_udelay(unsigned int d)
{
	udelay(d);
}

static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
			  void (*delay)(unsigned int), unsigned int d, int n,
			  bool high)
{
	int i;

	for (i = 0; i < n; i++) {
		delay(d);
		if (c->check(tp) == high)
			return true;
	}
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	netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
		  c->msg, !high, n, d);
895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942
	return false;
}

static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
				      const struct rtl_cond *c,
				      unsigned int d, int n)
{
	return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
}

static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
				     const struct rtl_cond *c,
				     unsigned int d, int n)
{
	return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
}

static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
				      const struct rtl_cond *c,
				      unsigned int d, int n)
{
	return rtl_loop_wait(tp, c, msleep, d, n, true);
}

static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
				     const struct rtl_cond *c,
				     unsigned int d, int n)
{
	return rtl_loop_wait(tp, c, msleep, d, n, false);
}

#define DECLARE_RTL_COND(name)				\
static bool name ## _check(struct rtl8169_private *);	\
							\
static const struct rtl_cond name = {			\
	.check	= name ## _check,			\
	.msg	= #name					\
};							\
							\
static bool name ## _check(struct rtl8169_private *tp)

DECLARE_RTL_COND(rtl_ocpar_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R32(OCPAR) & OCPAR_FLAG;
}

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static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
948 949 950

	return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
		RTL_R32(OCPDR) : ~0;
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}

static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W32(OCPDR, data);
	RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
959 960 961 962 963 964 965 966 967

	rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
}

DECLARE_RTL_COND(rtl_eriar_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R32(ERIAR) & ERIAR_FLAG;
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}

970
static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
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{
972
	void __iomem *ioaddr = tp->mmio_addr;
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	RTL_W8(ERIDR, cmd);
	RTL_W32(ERIAR, 0x800010e8);
	msleep(2);
977 978 979

	if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
		return;
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981
	ocp_write(tp, 0x1, 0x30, 0x00000001);
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}

#define OOB_CMD_RESET		0x00
#define OOB_CMD_DRIVER_START	0x05
#define OOB_CMD_DRIVER_STOP	0x06

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static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
{
	return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
}

993
DECLARE_RTL_COND(rtl_ocp_read_cond)
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{
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	u16 reg;
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	reg = rtl8168_get_ocp_reg(tp);
998

999
	return ocp_read(tp, 0x0f, reg) & 0x00000800;
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}

1002
static void rtl8168_driver_start(struct rtl8169_private *tp)
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{
1004
	rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
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1006 1007
	rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
}
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1009 1010 1011
static void rtl8168_driver_stop(struct rtl8169_private *tp)
{
	rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1012

1013
	rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
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}

1016 1017
static int r8168dp_check_dash(struct rtl8169_private *tp)
{
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	u16 reg = rtl8168_get_ocp_reg(tp);
1019

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	return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1021
}
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static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
{
	if (reg & 0xffff0001) {
		netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
		return true;
	}
	return false;
}

DECLARE_RTL_COND(rtl_ocp_gphy_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
}

static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
{
	void __iomem *ioaddr = tp->mmio_addr;

	if (rtl_ocp_reg_failure(tp, reg))
		return;

	RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);

	rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
}

static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
{
	void __iomem *ioaddr = tp->mmio_addr;

	if (rtl_ocp_reg_failure(tp, reg))
		return 0;

	RTL_W32(GPHY_OCP, reg << 15);

	return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
		(RTL_R32(GPHY_OCP) & 0xffff) : ~0;
}

static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
{
	void __iomem *ioaddr = tp->mmio_addr;

	if (rtl_ocp_reg_failure(tp, reg))
		return;

	RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
}

static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
{
	void __iomem *ioaddr = tp->mmio_addr;

	if (rtl_ocp_reg_failure(tp, reg))
		return 0;

	RTL_W32(OCPDR, reg << 15);

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	return RTL_R32(OCPDR);
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}

#define OCP_STD_PHY_BASE	0xa400

static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
{
	if (reg == 0x1f) {
		tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
		return;
	}

	if (tp->ocp_base != OCP_STD_PHY_BASE)
		reg -= 0x10;

	r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
}

static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
{
	if (tp->ocp_base != OCP_STD_PHY_BASE)
		reg -= 0x10;

	return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
}

1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123
static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
{
	if (reg == 0x1f) {
		tp->ocp_base = value << 4;
		return;
	}

	r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
}

static int mac_mcu_read(struct rtl8169_private *tp, int reg)
{
	return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
}

1124 1125 1126 1127 1128 1129 1130
DECLARE_RTL_COND(rtl_phyar_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R32(PHYAR) & 0x80000000;
}

1131
static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
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{
1133
	void __iomem *ioaddr = tp->mmio_addr;
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1135
	RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
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1137
	rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1138
	/*
1139 1140
	 * According to hardware specs a 20us delay is required after write
	 * complete indication, but before sending next command.
1141
	 */
1142
	udelay(20);
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}

1145
static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
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{
1147
	void __iomem *ioaddr = tp->mmio_addr;
1148
	int value;
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1150
	RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
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1152 1153 1154
	value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
		RTL_R32(PHYAR) & 0xffff : ~0;

1155 1156 1157 1158 1159 1160
	/*
	 * According to hardware specs a 20us delay is required after read
	 * complete indication, but before sending next command.
	 */
	udelay(20);

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	return value;
}

1164
static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1165
{
1166
	void __iomem *ioaddr = tp->mmio_addr;
1167

1168
	RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1169 1170 1171
	RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
	RTL_W32(EPHY_RXER_NUM, 0);

1172
	rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1173 1174
}

1175
static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1176
{
1177 1178
	r8168dp_1_mdio_access(tp, reg,
			      OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1179 1180
}

1181
static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1182
{
1183
	void __iomem *ioaddr = tp->mmio_addr;
1184

1185
	r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1186 1187 1188 1189 1190

	mdelay(1);
	RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
	RTL_W32(EPHY_RXER_NUM, 0);

1191 1192
	return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
		RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1193 1194
}

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#define R8168DP_1_MDIO_ACCESS_BIT	0x00020000

static void r8168dp_2_mdio_start(void __iomem *ioaddr)
{
	RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
}

static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
{
	RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
}

1207
static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
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{
1209 1210
	void __iomem *ioaddr = tp->mmio_addr;

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	r8168dp_2_mdio_start(ioaddr);

1213
	r8169_mdio_write(tp, reg, value);
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	r8168dp_2_mdio_stop(ioaddr);
}

1218
static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
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{
1220
	void __iomem *ioaddr = tp->mmio_addr;
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	int value;

	r8168dp_2_mdio_start(ioaddr);

1225
	value = r8169_mdio_read(tp, reg);
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	r8168dp_2_mdio_stop(ioaddr);

	return value;
}

1232
static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1233
{
1234
	tp->mdio_ops.write(tp, location, val);
1235 1236
}

1237 1238
static int rtl_readphy(struct rtl8169_private *tp, int location)
{
1239
	return tp->mdio_ops.read(tp, location);
1240 1241 1242 1243 1244 1245 1246 1247
}

static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
{
	rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
}

static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1248 1249 1250
{
	int val;

1251 1252
	val = rtl_readphy(tp, reg_addr);
	rtl_writephy(tp, reg_addr, (val | p) & ~m);
1253 1254
}

1255 1256 1257 1258 1259
static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
			   int val)
{
	struct rtl8169_private *tp = netdev_priv(dev);

1260
	rtl_writephy(tp, location, val);
1261 1262 1263 1264 1265 1266
}

static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
{
	struct rtl8169_private *tp = netdev_priv(dev);

1267
	return rtl_readphy(tp, location);
1268 1269
}

1270 1271 1272 1273 1274 1275 1276
DECLARE_RTL_COND(rtl_ephyar_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R32(EPHYAR) & EPHYAR_FLAG;
}

1277
static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1278
{
1279
	void __iomem *ioaddr = tp->mmio_addr;
1280 1281 1282 1283

	RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
		(reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);

1284 1285 1286
	rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);

	udelay(10);
1287 1288
}

1289
static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1290
{
1291
	void __iomem *ioaddr = tp->mmio_addr;
1292 1293 1294

	RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);

1295 1296
	return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
		RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1297 1298
}

1299 1300
static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
			  u32 val, int type)
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{
1302
	void __iomem *ioaddr = tp->mmio_addr;
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	BUG_ON((addr & 3) || (mask == 0));
	RTL_W32(ERIDR, val);
	RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);

1308
	rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
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}

1311
static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
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{
1313
	void __iomem *ioaddr = tp->mmio_addr;
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	RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);

1317 1318
	return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
		RTL_R32(ERIDR) : ~0;
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}

1321 1322
static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
			 u32 m, int type)
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{
	u32 val;

1326 1327
	val = rtl_eri_read(tp, addr, type);
	rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
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}

1330 1331 1332 1333 1334 1335
struct exgmac_reg {
	u16 addr;
	u16 mask;
	u32 val;
};

1336
static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1337 1338 1339
				   const struct exgmac_reg *r, int len)
{
	while (len-- > 0) {
1340
		rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1341 1342 1343 1344
		r++;
	}
}

1345 1346 1347 1348 1349 1350 1351
DECLARE_RTL_COND(rtl_efusear_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
}

1352
static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1353
{
1354
	void __iomem *ioaddr = tp->mmio_addr;
1355 1356 1357

	RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);

1358 1359
	return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
		RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1360 1361
}

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1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384
static u16 rtl_get_events(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R16(IntrStatus);
}

static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W16(IntrStatus, bits);
	mmiowb();
}

static void rtl_irq_disable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W16(IntrMask, 0);
	mmiowb();
}

1385 1386 1387 1388 1389 1390 1391
static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W16(IntrMask, bits);
}

1392 1393 1394 1395 1396 1397 1398 1399 1400
#define RTL_EVENT_NAPI_RX	(RxOK | RxErr)
#define RTL_EVENT_NAPI_TX	(TxOK | TxErr)
#define RTL_EVENT_NAPI		(RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)

static void rtl_irq_enable_all(struct rtl8169_private *tp)
{
	rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
}

F
françois romieu 已提交
1401
static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
1402
{
F
françois romieu 已提交
1403
	void __iomem *ioaddr = tp->mmio_addr;
L
Linus Torvalds 已提交
1404

F
Francois Romieu 已提交
1405
	rtl_irq_disable(tp);
1406
	rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
F
françois romieu 已提交
1407
	RTL_R8(ChipCmd);
L
Linus Torvalds 已提交
1408 1409
}

1410
static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
1411
{
1412 1413
	void __iomem *ioaddr = tp->mmio_addr;

L
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1414 1415 1416
	return RTL_R32(TBICSR) & TBIReset;
}

1417
static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
1418
{
1419
	return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
L
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1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431
}

static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
{
	return RTL_R32(TBICSR) & TBILinkOk;
}

static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
{
	return RTL_R8(PHYstatus) & LinkStatus;
}

1432
static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
1433
{
1434 1435
	void __iomem *ioaddr = tp->mmio_addr;

L
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1436 1437 1438
	RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
}

1439
static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
L
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1440 1441 1442
{
	unsigned int val;

1443 1444
	val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
	rtl_writephy(tp, MII_BMCR, val & 0xffff);
L
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1445 1446
}

H
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1447 1448 1449 1450 1451 1452 1453 1454
static void rtl_link_chg_patch(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;
	struct net_device *dev = tp->dev;

	if (!netif_running(dev))
		return;

1455 1456
	if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_38) {
H
Hayes Wang 已提交
1457
		if (RTL_R8(PHYstatus) & _1000bpsF) {
1458 1459 1460 1461
			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
				      ERIAR_EXGMAC);
			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
				      ERIAR_EXGMAC);
H
Hayes Wang 已提交
1462
		} else if (RTL_R8(PHYstatus) & _100bps) {
1463 1464 1465 1466
			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
				      ERIAR_EXGMAC);
			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
				      ERIAR_EXGMAC);
H
Hayes Wang 已提交
1467
		} else {
1468 1469 1470 1471
			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
				      ERIAR_EXGMAC);
			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
				      ERIAR_EXGMAC);
H
Hayes Wang 已提交
1472 1473
		}
		/* Reset packet filter */
1474
		rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
H
Hayes Wang 已提交
1475
			     ERIAR_EXGMAC);
1476
		rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
H
Hayes Wang 已提交
1477
			     ERIAR_EXGMAC);
1478 1479 1480
	} else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_36) {
		if (RTL_R8(PHYstatus) & _1000bpsF) {
1481 1482 1483 1484
			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
				      ERIAR_EXGMAC);
			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
				      ERIAR_EXGMAC);
1485
		} else {
1486 1487 1488 1489
			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
				      ERIAR_EXGMAC);
			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
				      ERIAR_EXGMAC);
1490
		}
1491 1492
	} else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
		if (RTL_R8(PHYstatus) & _10bps) {
1493 1494 1495 1496
			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
				      ERIAR_EXGMAC);
			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
				      ERIAR_EXGMAC);
1497
		} else {
1498 1499
			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
				      ERIAR_EXGMAC);
1500
		}
H
Hayes Wang 已提交
1501 1502 1503
	}
}

1504
static void __rtl8169_check_link_status(struct net_device *dev,
F
Francois Romieu 已提交
1505 1506
					struct rtl8169_private *tp,
					void __iomem *ioaddr, bool pm)
L
Linus Torvalds 已提交
1507 1508
{
	if (tp->link_ok(ioaddr)) {
H
Hayes Wang 已提交
1509
		rtl_link_chg_patch(tp);
1510
		/* This is to cancel a scheduled suspend if there's one. */
1511 1512
		if (pm)
			pm_request_resume(&tp->pci_dev->dev);
L
Linus Torvalds 已提交
1513
		netif_carrier_on(dev);
1514 1515
		if (net_ratelimit())
			netif_info(tp, ifup, dev, "link up\n");
1516
	} else {
L
Linus Torvalds 已提交
1517
		netif_carrier_off(dev);
1518
		netif_info(tp, ifdown, dev, "link down\n");
1519
		if (pm)
1520
			pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1521
	}
L
Linus Torvalds 已提交
1522 1523
}

1524 1525 1526 1527 1528 1529 1530
static void rtl8169_check_link_status(struct net_device *dev,
				      struct rtl8169_private *tp,
				      void __iomem *ioaddr)
{
	__rtl8169_check_link_status(dev, tp, ioaddr, false);
}

1531 1532 1533
#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)

static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
F
Francois Romieu 已提交
1534 1535 1536
{
	void __iomem *ioaddr = tp->mmio_addr;
	u8 options;
1537
	u32 wolopts = 0;
F
Francois Romieu 已提交
1538 1539 1540

	options = RTL_R8(Config1);
	if (!(options & PMEnable))
1541
		return 0;
F
Francois Romieu 已提交
1542 1543 1544

	options = RTL_R8(Config3);
	if (options & LinkUp)
1545
		wolopts |= WAKE_PHY;
1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
		if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
			wolopts |= WAKE_MAGIC;
		break;
	default:
		if (options & MagicPacket)
			wolopts |= WAKE_MAGIC;
		break;
	}
F
Francois Romieu 已提交
1557 1558 1559

	options = RTL_R8(Config5);
	if (options & UWF)
1560
		wolopts |= WAKE_UCAST;
F
Francois Romieu 已提交
1561
	if (options & BWF)
1562
		wolopts |= WAKE_BCAST;
F
Francois Romieu 已提交
1563
	if (options & MWF)
1564
		wolopts |= WAKE_MCAST;
F
Francois Romieu 已提交
1565

1566
	return wolopts;
F
Francois Romieu 已提交
1567 1568
}

1569
static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
F
Francois Romieu 已提交
1570 1571
{
	struct rtl8169_private *tp = netdev_priv(dev);
1572

1573
	rtl_lock_work(tp);
1574 1575 1576 1577

	wol->supported = WAKE_ANY;
	wol->wolopts = __rtl8169_get_wol(tp);

1578
	rtl_unlock_work(tp);
1579 1580 1581 1582
}

static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
{
F
Francois Romieu 已提交
1583
	void __iomem *ioaddr = tp->mmio_addr;
1584
	unsigned int i, tmp;
1585
	static const struct {
F
Francois Romieu 已提交
1586 1587 1588 1589 1590 1591 1592 1593
		u32 opt;
		u16 reg;
		u8  mask;
	} cfg[] = {
		{ WAKE_PHY,   Config3, LinkUp },
		{ WAKE_UCAST, Config5, UWF },
		{ WAKE_BCAST, Config5, BWF },
		{ WAKE_MCAST, Config5, MWF },
1594 1595
		{ WAKE_ANY,   Config5, LanWake },
		{ WAKE_MAGIC, Config3, MagicPacket }
F
Francois Romieu 已提交
1596
	};
1597
	u8 options;
F
Francois Romieu 已提交
1598 1599 1600

	RTL_W8(Cfg9346, Cfg9346_Unlock);

1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
		tmp = ARRAY_SIZE(cfg) - 1;
		if (wolopts & WAKE_MAGIC)
			rtl_w1w0_eri(tp,
				     0x0dc,
				     ERIAR_MASK_0100,
				     MagicPacket_v2,
				     0x0000,
				     ERIAR_EXGMAC);
		else
			rtl_w1w0_eri(tp,
				     0x0dc,
				     ERIAR_MASK_0100,
				     0x0000,
				     MagicPacket_v2,
				     ERIAR_EXGMAC);
		break;
	default:
		tmp = ARRAY_SIZE(cfg);
		break;
	}

	for (i = 0; i < tmp; i++) {
1626
		options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1627
		if (wolopts & cfg[i].opt)
F
Francois Romieu 已提交
1628 1629 1630 1631
			options |= cfg[i].mask;
		RTL_W8(cfg[i].reg, options);
	}

1632 1633 1634 1635 1636 1637 1638 1639
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
		options = RTL_R8(Config1) & ~PMEnable;
		if (wolopts)
			options |= PMEnable;
		RTL_W8(Config1, options);
		break;
	default:
1640 1641 1642 1643
		options = RTL_R8(Config2) & ~PME_SIGNAL;
		if (wolopts)
			options |= PME_SIGNAL;
		RTL_W8(Config2, options);
1644 1645 1646
		break;
	}

F
Francois Romieu 已提交
1647
	RTL_W8(Cfg9346, Cfg9346_Lock);
1648 1649 1650 1651 1652 1653
}

static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
	struct rtl8169_private *tp = netdev_priv(dev);

1654
	rtl_lock_work(tp);
F
Francois Romieu 已提交
1655

1656 1657 1658 1659
	if (wol->wolopts)
		tp->features |= RTL_FEATURE_WOL;
	else
		tp->features &= ~RTL_FEATURE_WOL;
1660
	__rtl8169_set_wol(tp, wol->wolopts);
1661 1662

	rtl_unlock_work(tp);
F
Francois Romieu 已提交
1663

1664 1665
	device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);

F
Francois Romieu 已提交
1666 1667 1668
	return 0;
}

1669 1670
static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
{
1671
	return rtl_chip_infos[tp->mac_version].fw_name;
1672 1673
}

L
Linus Torvalds 已提交
1674 1675 1676 1677
static void rtl8169_get_drvinfo(struct net_device *dev,
				struct ethtool_drvinfo *info)
{
	struct rtl8169_private *tp = netdev_priv(dev);
1678
	struct rtl_fw *rtl_fw = tp->rtl_fw;
L
Linus Torvalds 已提交
1679

1680 1681 1682
	strlcpy(info->driver, MODULENAME, sizeof(info->driver));
	strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
	strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1683
	BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1684 1685 1686
	if (!IS_ERR_OR_NULL(rtl_fw))
		strlcpy(info->fw_version, rtl_fw->version,
			sizeof(info->fw_version));
L
Linus Torvalds 已提交
1687 1688 1689 1690 1691 1692 1693 1694
}

static int rtl8169_get_regs_len(struct net_device *dev)
{
	return R8169_REGS_SIZE;
}

static int rtl8169_set_speed_tbi(struct net_device *dev,
1695
				 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
L
Linus Torvalds 已提交
1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	int ret = 0;
	u32 reg;

	reg = RTL_R32(TBICSR);
	if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
	    (duplex == DUPLEX_FULL)) {
		RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
	} else if (autoneg == AUTONEG_ENABLE)
		RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
	else {
1709 1710
		netif_warn(tp, link, dev,
			   "incorrect speed setting refused in TBI mode\n");
L
Linus Torvalds 已提交
1711 1712 1713 1714 1715 1716 1717
		ret = -EOPNOTSUPP;
	}

	return ret;
}

static int rtl8169_set_speed_xmii(struct net_device *dev,
1718
				  u8 autoneg, u16 speed, u8 duplex, u32 adv)
L
Linus Torvalds 已提交
1719 1720
{
	struct rtl8169_private *tp = netdev_priv(dev);
1721
	int giga_ctrl, bmcr;
1722
	int rc = -EINVAL;
L
Linus Torvalds 已提交
1723

1724
	rtl_writephy(tp, 0x1f, 0x0000);
L
Linus Torvalds 已提交
1725 1726

	if (autoneg == AUTONEG_ENABLE) {
1727 1728
		int auto_nego;

1729
		auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741
		auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
				ADVERTISE_100HALF | ADVERTISE_100FULL);

		if (adv & ADVERTISED_10baseT_Half)
			auto_nego |= ADVERTISE_10HALF;
		if (adv & ADVERTISED_10baseT_Full)
			auto_nego |= ADVERTISE_10FULL;
		if (adv & ADVERTISED_100baseT_Half)
			auto_nego |= ADVERTISE_100HALF;
		if (adv & ADVERTISED_100baseT_Full)
			auto_nego |= ADVERTISE_100FULL;

1742
		auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
L
Linus Torvalds 已提交
1743

1744
		giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1745
		giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1746

1747
		/* The 8100e/8101e/8102e do Fast Ethernet only. */
1748
		if (tp->mii.supports_gmii) {
1749 1750 1751 1752 1753 1754
			if (adv & ADVERTISED_1000baseT_Half)
				giga_ctrl |= ADVERTISE_1000HALF;
			if (adv & ADVERTISED_1000baseT_Full)
				giga_ctrl |= ADVERTISE_1000FULL;
		} else if (adv & (ADVERTISED_1000baseT_Half |
				  ADVERTISED_1000baseT_Full)) {
1755 1756
			netif_info(tp, link, dev,
				   "PHY does not support 1000Mbps\n");
1757
			goto out;
1758
		}
L
Linus Torvalds 已提交
1759

1760 1761
		bmcr = BMCR_ANENABLE | BMCR_ANRESTART;

1762 1763
		rtl_writephy(tp, MII_ADVERTISE, auto_nego);
		rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1764 1765 1766 1767 1768 1769 1770 1771
	} else {
		giga_ctrl = 0;

		if (speed == SPEED_10)
			bmcr = 0;
		else if (speed == SPEED_100)
			bmcr = BMCR_SPEED100;
		else
1772
			goto out;
1773 1774 1775

		if (duplex == DUPLEX_FULL)
			bmcr |= BMCR_FULLDPLX;
R
Roger So 已提交
1776 1777
	}

1778
	rtl_writephy(tp, MII_BMCR, bmcr);
1779

F
Francois Romieu 已提交
1780 1781
	if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_03) {
1782
		if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1783 1784
			rtl_writephy(tp, 0x17, 0x2138);
			rtl_writephy(tp, 0x0e, 0x0260);
1785
		} else {
1786 1787
			rtl_writephy(tp, 0x17, 0x2108);
			rtl_writephy(tp, 0x0e, 0x0000);
1788 1789 1790
		}
	}

1791 1792 1793
	rc = 0;
out:
	return rc;
L
Linus Torvalds 已提交
1794 1795 1796
}

static int rtl8169_set_speed(struct net_device *dev,
1797
			     u8 autoneg, u16 speed, u8 duplex, u32 advertising)
L
Linus Torvalds 已提交
1798 1799 1800 1801
{
	struct rtl8169_private *tp = netdev_priv(dev);
	int ret;

1802
	ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1803 1804
	if (ret < 0)
		goto out;
L
Linus Torvalds 已提交
1805

1806 1807
	if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
	    (advertising & ADVERTISED_1000baseT_Full)) {
L
Linus Torvalds 已提交
1808
		mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1809 1810
	}
out:
L
Linus Torvalds 已提交
1811 1812 1813 1814 1815 1816 1817 1818
	return ret;
}

static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	int ret;

1819 1820
	del_timer_sync(&tp->timer);

1821
	rtl_lock_work(tp);
F
Francois Romieu 已提交
1822
	ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1823
				cmd->duplex, cmd->advertising);
1824
	rtl_unlock_work(tp);
1825

L
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1826 1827 1828
	return ret;
}

1829 1830
static netdev_features_t rtl8169_fix_features(struct net_device *dev,
	netdev_features_t features)
L
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1831
{
F
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1832 1833
	struct rtl8169_private *tp = netdev_priv(dev);

F
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1834
	if (dev->mtu > TD_MSS_MAX)
1835
		features &= ~NETIF_F_ALL_TSO;
L
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1836

F
Francois Romieu 已提交
1837 1838 1839 1840
	if (dev->mtu > JUMBO_1K &&
	    !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
		features &= ~NETIF_F_IP_CSUM;

1841
	return features;
L
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1842 1843
}

1844 1845
static void __rtl8169_set_features(struct net_device *dev,
				   netdev_features_t features)
L
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1846 1847
{
	struct rtl8169_private *tp = netdev_priv(dev);
B
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1848
	netdev_features_t changed = features ^ dev->features;
1849
	void __iomem *ioaddr = tp->mmio_addr;
L
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1850

1851 1852
	if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM |
			 NETIF_F_HW_VLAN_CTAG_RX)))
B
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1853
		return;
L
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1854

1855
	if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) {
B
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1856 1857 1858 1859
		if (features & NETIF_F_RXCSUM)
			tp->cp_cmd |= RxChkSum;
		else
			tp->cp_cmd &= ~RxChkSum;
1860

1861
		if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
B
Ben Greear 已提交
1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874
			tp->cp_cmd |= RxVlan;
		else
			tp->cp_cmd &= ~RxVlan;

		RTL_W16(CPlusCmd, tp->cp_cmd);
		RTL_R16(CPlusCmd);
	}
	if (changed & NETIF_F_RXALL) {
		int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
		if (features & NETIF_F_RXALL)
			tmp |= (AcceptErr | AcceptRunt);
		RTL_W32(RxConfig, tmp);
	}
1875
}
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1876

1877 1878 1879 1880 1881 1882 1883 1884
static int rtl8169_set_features(struct net_device *dev,
				netdev_features_t features)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl_lock_work(tp);
	__rtl8169_set_features(dev, features);
	rtl_unlock_work(tp);
L
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1885 1886 1887 1888

	return 0;
}

1889

1890
static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
L
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1891
{
1892
	return (vlan_tx_tag_present(skb)) ?
L
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1893 1894 1895
		TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
}

1896
static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
L
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1897 1898 1899
{
	u32 opts2 = le32_to_cpu(desc->opts2);

1900
	if (opts2 & RxVlanTag)
1901
		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
L
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}

1904
static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
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1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	u32 status;

	cmd->supported =
		SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
	cmd->port = PORT_FIBRE;
	cmd->transceiver = XCVR_INTERNAL;

	status = RTL_R32(TBICSR);
	cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
	cmd->autoneg = !!(status & TBINwEnable);

1919
	ethtool_cmd_speed_set(cmd, SPEED_1000);
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1920
	cmd->duplex = DUPLEX_FULL; /* Always set */
1921 1922

	return 0;
L
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1923 1924
}

1925
static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
L
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1926 1927
{
	struct rtl8169_private *tp = netdev_priv(dev);
1928 1929

	return mii_ethtool_gset(&tp->mii, cmd);
L
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1930 1931 1932 1933 1934
}

static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
	struct rtl8169_private *tp = netdev_priv(dev);
1935
	int rc;
L
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1936

1937
	rtl_lock_work(tp);
1938
	rc = tp->get_settings(dev, cmd);
1939
	rtl_unlock_work(tp);
L
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1940

1941
	return rc;
L
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1942 1943 1944 1945 1946
}

static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
			     void *p)
{
1947
	struct rtl8169_private *tp = netdev_priv(dev);
P
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1948 1949 1950
	u32 __iomem *data = tp->mmio_addr;
	u32 *dw = p;
	int i;
L
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1951

1952
	rtl_lock_work(tp);
P
Peter Wu 已提交
1953 1954
	for (i = 0; i < R8169_REGS_SIZE; i += 4)
		memcpy_fromio(dw++, data++, 4);
1955
	rtl_unlock_work(tp);
L
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}

1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971
static u32 rtl8169_get_msglevel(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	return tp->msg_enable;
}

static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	tp->msg_enable = value;
}

1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987
static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
	"tx_packets",
	"rx_packets",
	"tx_errors",
	"rx_errors",
	"rx_missed",
	"align_errors",
	"tx_single_collisions",
	"tx_multi_collisions",
	"unicast",
	"broadcast",
	"multicast",
	"tx_aborted",
	"tx_underrun",
};

1988
static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1989
{
1990 1991 1992 1993 1994 1995
	switch (sset) {
	case ETH_SS_STATS:
		return ARRAY_SIZE(rtl8169_gstrings);
	default:
		return -EOPNOTSUPP;
	}
1996 1997
}

1998 1999 2000 2001 2002 2003 2004
DECLARE_RTL_COND(rtl_counters_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R32(CounterAddrLow) & CounterDump;
}

2005
static void rtl8169_update_counters(struct net_device *dev)
2006 2007 2008
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
F
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2009
	struct device *d = &tp->pci_dev->dev;
2010 2011 2012 2013
	struct rtl8169_counters *counters;
	dma_addr_t paddr;
	u32 cmd;

2014 2015 2016 2017 2018 2019
	/*
	 * Some chips are unable to dump tally counters when the receiver
	 * is disabled.
	 */
	if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
		return;
2020

2021
	counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
2022 2023 2024 2025
	if (!counters)
		return;

	RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2026
	cmd = (u64)paddr & DMA_BIT_MASK(32);
2027 2028 2029
	RTL_W32(CounterAddrLow, cmd);
	RTL_W32(CounterAddrLow, cmd | CounterDump);

2030 2031
	if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
		memcpy(&tp->counters, counters, sizeof(*counters));
2032 2033 2034 2035

	RTL_W32(CounterAddrLow, 0);
	RTL_W32(CounterAddrHigh, 0);

2036
	dma_free_coherent(d, sizeof(*counters), counters, paddr);
2037 2038
}

2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062
static void rtl8169_get_ethtool_stats(struct net_device *dev,
				      struct ethtool_stats *stats, u64 *data)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	ASSERT_RTNL();

	rtl8169_update_counters(dev);

	data[0] = le64_to_cpu(tp->counters.tx_packets);
	data[1] = le64_to_cpu(tp->counters.rx_packets);
	data[2] = le64_to_cpu(tp->counters.tx_errors);
	data[3] = le32_to_cpu(tp->counters.rx_errors);
	data[4] = le16_to_cpu(tp->counters.rx_missed);
	data[5] = le16_to_cpu(tp->counters.align_errors);
	data[6] = le32_to_cpu(tp->counters.tx_one_collision);
	data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
	data[8] = le64_to_cpu(tp->counters.rx_unicast);
	data[9] = le64_to_cpu(tp->counters.rx_broadcast);
	data[10] = le32_to_cpu(tp->counters.rx_multicast);
	data[11] = le16_to_cpu(tp->counters.tx_aborted);
	data[12] = le16_to_cpu(tp->counters.tx_underun);
}

2063 2064 2065 2066 2067 2068 2069 2070 2071
static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
{
	switch(stringset) {
	case ETH_SS_STATS:
		memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
		break;
	}
}

2072
static const struct ethtool_ops rtl8169_ethtool_ops = {
L
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2073 2074 2075 2076 2077
	.get_drvinfo		= rtl8169_get_drvinfo,
	.get_regs_len		= rtl8169_get_regs_len,
	.get_link		= ethtool_op_get_link,
	.get_settings		= rtl8169_get_settings,
	.set_settings		= rtl8169_set_settings,
2078 2079
	.get_msglevel		= rtl8169_get_msglevel,
	.set_msglevel		= rtl8169_set_msglevel,
L
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2080
	.get_regs		= rtl8169_get_regs,
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2081 2082
	.get_wol		= rtl8169_get_wol,
	.set_wol		= rtl8169_set_wol,
2083
	.get_strings		= rtl8169_get_strings,
2084
	.get_sset_count		= rtl8169_get_sset_count,
2085
	.get_ethtool_stats	= rtl8169_get_ethtool_stats,
2086
	.get_ts_info		= ethtool_op_get_ts_info,
L
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2087 2088
};

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2089
static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2090
				    struct net_device *dev, u8 default_version)
L
Linus Torvalds 已提交
2091
{
2092
	void __iomem *ioaddr = tp->mmio_addr;
2093 2094 2095 2096 2097 2098
	/*
	 * The driver currently handles the 8168Bf and the 8168Be identically
	 * but they can be identified more specifically through the test below
	 * if needed:
	 *
	 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
F
Francois Romieu 已提交
2099 2100 2101 2102
	 *
	 * Same thing for the 8101Eb and the 8101Ec:
	 *
	 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2103
	 */
2104
	static const struct rtl_mac_info {
L
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2105
		u32 mask;
F
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2106
		u32 val;
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2107 2108
		int mac_version;
	} mac_info[] = {
2109 2110 2111 2112
		/* 8168H family. */
		{ 0x7cf00000, 0x54100000,	RTL_GIGA_MAC_VER_46 },
		{ 0x7cf00000, 0x54000000,	RTL_GIGA_MAC_VER_45 },

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		/* 8168G family. */
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2114
		{ 0x7cf00000, 0x5c800000,	RTL_GIGA_MAC_VER_44 },
H
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2115
		{ 0x7cf00000, 0x50900000,	RTL_GIGA_MAC_VER_42 },
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2116 2117 2118
		{ 0x7cf00000, 0x4c100000,	RTL_GIGA_MAC_VER_41 },
		{ 0x7cf00000, 0x4c000000,	RTL_GIGA_MAC_VER_40 },

2119
		/* 8168F family. */
2120
		{ 0x7c800000, 0x48800000,	RTL_GIGA_MAC_VER_38 },
2121 2122 2123
		{ 0x7cf00000, 0x48100000,	RTL_GIGA_MAC_VER_36 },
		{ 0x7cf00000, 0x48000000,	RTL_GIGA_MAC_VER_35 },

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2124
		/* 8168E family. */
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2125
		{ 0x7c800000, 0x2c800000,	RTL_GIGA_MAC_VER_34 },
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2126 2127 2128 2129
		{ 0x7cf00000, 0x2c200000,	RTL_GIGA_MAC_VER_33 },
		{ 0x7cf00000, 0x2c100000,	RTL_GIGA_MAC_VER_32 },
		{ 0x7c800000, 0x2c000000,	RTL_GIGA_MAC_VER_33 },

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2130
		/* 8168D family. */
2131 2132 2133
		{ 0x7cf00000, 0x28300000,	RTL_GIGA_MAC_VER_26 },
		{ 0x7cf00000, 0x28100000,	RTL_GIGA_MAC_VER_25 },
		{ 0x7c800000, 0x28000000,	RTL_GIGA_MAC_VER_26 },
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2134

F
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2135 2136 2137
		/* 8168DP family. */
		{ 0x7cf00000, 0x28800000,	RTL_GIGA_MAC_VER_27 },
		{ 0x7cf00000, 0x28a00000,	RTL_GIGA_MAC_VER_28 },
2138
		{ 0x7cf00000, 0x28b00000,	RTL_GIGA_MAC_VER_31 },
F
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2139

2140
		/* 8168C family. */
2141
		{ 0x7cf00000, 0x3cb00000,	RTL_GIGA_MAC_VER_24 },
F
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2142
		{ 0x7cf00000, 0x3c900000,	RTL_GIGA_MAC_VER_23 },
2143
		{ 0x7cf00000, 0x3c800000,	RTL_GIGA_MAC_VER_18 },
2144
		{ 0x7c800000, 0x3c800000,	RTL_GIGA_MAC_VER_24 },
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2145 2146
		{ 0x7cf00000, 0x3c000000,	RTL_GIGA_MAC_VER_19 },
		{ 0x7cf00000, 0x3c200000,	RTL_GIGA_MAC_VER_20 },
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2147
		{ 0x7cf00000, 0x3c300000,	RTL_GIGA_MAC_VER_21 },
2148
		{ 0x7cf00000, 0x3c400000,	RTL_GIGA_MAC_VER_22 },
2149
		{ 0x7c800000, 0x3c000000,	RTL_GIGA_MAC_VER_22 },
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2150 2151 2152 2153 2154 2155 2156 2157

		/* 8168B family. */
		{ 0x7cf00000, 0x38000000,	RTL_GIGA_MAC_VER_12 },
		{ 0x7cf00000, 0x38500000,	RTL_GIGA_MAC_VER_17 },
		{ 0x7c800000, 0x38000000,	RTL_GIGA_MAC_VER_17 },
		{ 0x7c800000, 0x30000000,	RTL_GIGA_MAC_VER_11 },

		/* 8101 family. */
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2158 2159
		{ 0x7cf00000, 0x44900000,	RTL_GIGA_MAC_VER_39 },
		{ 0x7c800000, 0x44800000,	RTL_GIGA_MAC_VER_39 },
2160
		{ 0x7c800000, 0x44000000,	RTL_GIGA_MAC_VER_37 },
2161
		{ 0x7cf00000, 0x40b00000,	RTL_GIGA_MAC_VER_30 },
2162 2163 2164
		{ 0x7cf00000, 0x40a00000,	RTL_GIGA_MAC_VER_30 },
		{ 0x7cf00000, 0x40900000,	RTL_GIGA_MAC_VER_29 },
		{ 0x7c800000, 0x40800000,	RTL_GIGA_MAC_VER_30 },
2165 2166 2167 2168 2169 2170
		{ 0x7cf00000, 0x34a00000,	RTL_GIGA_MAC_VER_09 },
		{ 0x7cf00000, 0x24a00000,	RTL_GIGA_MAC_VER_09 },
		{ 0x7cf00000, 0x34900000,	RTL_GIGA_MAC_VER_08 },
		{ 0x7cf00000, 0x24900000,	RTL_GIGA_MAC_VER_08 },
		{ 0x7cf00000, 0x34800000,	RTL_GIGA_MAC_VER_07 },
		{ 0x7cf00000, 0x24800000,	RTL_GIGA_MAC_VER_07 },
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2171
		{ 0x7cf00000, 0x34000000,	RTL_GIGA_MAC_VER_13 },
2172
		{ 0x7cf00000, 0x34300000,	RTL_GIGA_MAC_VER_10 },
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		{ 0x7cf00000, 0x34200000,	RTL_GIGA_MAC_VER_16 },
2174 2175
		{ 0x7c800000, 0x34800000,	RTL_GIGA_MAC_VER_09 },
		{ 0x7c800000, 0x24800000,	RTL_GIGA_MAC_VER_09 },
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2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188
		{ 0x7c800000, 0x34000000,	RTL_GIGA_MAC_VER_16 },
		/* FIXME: where did these entries come from ? -- FR */
		{ 0xfc800000, 0x38800000,	RTL_GIGA_MAC_VER_15 },
		{ 0xfc800000, 0x30800000,	RTL_GIGA_MAC_VER_14 },

		/* 8110 family. */
		{ 0xfc800000, 0x98000000,	RTL_GIGA_MAC_VER_06 },
		{ 0xfc800000, 0x18000000,	RTL_GIGA_MAC_VER_05 },
		{ 0xfc800000, 0x10000000,	RTL_GIGA_MAC_VER_04 },
		{ 0xfc800000, 0x04000000,	RTL_GIGA_MAC_VER_03 },
		{ 0xfc800000, 0x00800000,	RTL_GIGA_MAC_VER_02 },
		{ 0xfc800000, 0x00000000,	RTL_GIGA_MAC_VER_01 },

2189 2190
		/* Catch-all */
		{ 0x00000000, 0x00000000,	RTL_GIGA_MAC_NONE   }
2191 2192
	};
	const struct rtl_mac_info *p = mac_info;
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2193 2194
	u32 reg;

F
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2195 2196
	reg = RTL_R32(TxConfig);
	while ((reg & p->mask) != p->val)
L
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2197 2198
		p++;
	tp->mac_version = p->mac_version;
2199 2200 2201 2202 2203

	if (tp->mac_version == RTL_GIGA_MAC_NONE) {
		netif_notice(tp, probe, dev,
			     "unknown MAC, using family default\n");
		tp->mac_version = default_version;
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	} else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
		tp->mac_version = tp->mii.supports_gmii ?
				  RTL_GIGA_MAC_VER_42 :
				  RTL_GIGA_MAC_VER_43;
2208 2209 2210 2211 2212 2213 2214 2215
	} else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
		tp->mac_version = tp->mii.supports_gmii ?
				  RTL_GIGA_MAC_VER_45 :
				  RTL_GIGA_MAC_VER_47;
	} else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
		tp->mac_version = tp->mii.supports_gmii ?
				  RTL_GIGA_MAC_VER_46 :
				  RTL_GIGA_MAC_VER_48;
2216
	}
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}

static void rtl8169_print_mac_version(struct rtl8169_private *tp)
{
2221
	dprintk("mac_version = 0x%02x\n", tp->mac_version);
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2222 2223
}

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2224 2225 2226 2227 2228
struct phy_reg {
	u16 reg;
	u16 val;
};

2229 2230
static void rtl_writephy_batch(struct rtl8169_private *tp,
			       const struct phy_reg *regs, int len)
F
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2231 2232
{
	while (len-- > 0) {
2233
		rtl_writephy(tp, regs->reg, regs->val);
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2234 2235 2236 2237
		regs++;
	}
}

2238 2239 2240 2241
#define PHY_READ		0x00000000
#define PHY_DATA_OR		0x10000000
#define PHY_DATA_AND		0x20000000
#define PHY_BJMPN		0x30000000
2242
#define PHY_MDIO_CHG		0x40000000
2243 2244 2245 2246 2247 2248 2249 2250 2251
#define PHY_CLEAR_READCOUNT	0x70000000
#define PHY_WRITE		0x80000000
#define PHY_READCOUNT_EQ_SKIP	0x90000000
#define PHY_COMP_EQ_SKIPN	0xa0000000
#define PHY_COMP_NEQ_SKIPN	0xb0000000
#define PHY_WRITE_PREVIOUS	0xc0000000
#define PHY_SKIPN		0xd0000000
#define PHY_DELAY_MS		0xe0000000

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Hayes Wang 已提交
2252 2253 2254 2255 2256 2257 2258 2259
struct fw_info {
	u32	magic;
	char	version[RTL_VER_SIZE];
	__le32	fw_start;
	__le32	fw_len;
	u8	chksum;
} __packed;

2260 2261 2262
#define FW_OPCODE_SIZE	sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))

static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2263
{
2264
	const struct firmware *fw = rtl_fw->fw;
H
Hayes Wang 已提交
2265
	struct fw_info *fw_info = (struct fw_info *)fw->data;
2266 2267 2268 2269 2270 2271
	struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
	char *version = rtl_fw->version;
	bool rc = false;

	if (fw->size < FW_OPCODE_SIZE)
		goto out;
H
Hayes Wang 已提交
2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297

	if (!fw_info->magic) {
		size_t i, size, start;
		u8 checksum = 0;

		if (fw->size < sizeof(*fw_info))
			goto out;

		for (i = 0; i < fw->size; i++)
			checksum += fw->data[i];
		if (checksum != 0)
			goto out;

		start = le32_to_cpu(fw_info->fw_start);
		if (start > fw->size)
			goto out;

		size = le32_to_cpu(fw_info->fw_len);
		if (size > (fw->size - start) / FW_OPCODE_SIZE)
			goto out;

		memcpy(version, fw_info->version, RTL_VER_SIZE);

		pa->code = (__le32 *)(fw->data + start);
		pa->size = size;
	} else {
2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312
		if (fw->size % FW_OPCODE_SIZE)
			goto out;

		strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);

		pa->code = (__le32 *)fw->data;
		pa->size = fw->size / FW_OPCODE_SIZE;
	}
	version[RTL_VER_SIZE - 1] = 0;

	rc = true;
out:
	return rc;
}

2313 2314
static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
			   struct rtl_fw_phy_action *pa)
2315
{
2316
	bool rc = false;
2317
	size_t index;
2318

2319 2320
	for (index = 0; index < pa->size; index++) {
		u32 action = le32_to_cpu(pa->code[index]);
2321
		u32 regno = (action & 0x0fff0000) >> 16;
2322

2323 2324 2325 2326
		switch(action & 0xf0000000) {
		case PHY_READ:
		case PHY_DATA_OR:
		case PHY_DATA_AND:
2327
		case PHY_MDIO_CHG:
2328 2329 2330 2331 2332 2333 2334 2335
		case PHY_CLEAR_READCOUNT:
		case PHY_WRITE:
		case PHY_WRITE_PREVIOUS:
		case PHY_DELAY_MS:
			break;

		case PHY_BJMPN:
			if (regno > index) {
2336
				netif_err(tp, ifup, tp->dev,
F
Francois Romieu 已提交
2337
					  "Out of range of firmware\n");
2338
				goto out;
2339 2340 2341
			}
			break;
		case PHY_READCOUNT_EQ_SKIP:
2342
			if (index + 2 >= pa->size) {
2343
				netif_err(tp, ifup, tp->dev,
F
Francois Romieu 已提交
2344
					  "Out of range of firmware\n");
2345
				goto out;
2346 2347 2348 2349 2350
			}
			break;
		case PHY_COMP_EQ_SKIPN:
		case PHY_COMP_NEQ_SKIPN:
		case PHY_SKIPN:
2351
			if (index + 1 + regno >= pa->size) {
2352
				netif_err(tp, ifup, tp->dev,
F
Francois Romieu 已提交
2353
					  "Out of range of firmware\n");
2354
				goto out;
2355
			}
2356 2357
			break;

2358
		default:
2359
			netif_err(tp, ifup, tp->dev,
2360
				  "Invalid action 0x%08x\n", action);
2361
			goto out;
2362 2363
		}
	}
2364 2365 2366 2367
	rc = true;
out:
	return rc;
}
2368

2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387
static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
{
	struct net_device *dev = tp->dev;
	int rc = -EINVAL;

	if (!rtl_fw_format_ok(tp, rtl_fw)) {
		netif_err(tp, ifup, dev, "invalid firwmare\n");
		goto out;
	}

	if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
		rc = 0;
out:
	return rc;
}

static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
{
	struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2388
	struct mdio_ops org, *ops = &tp->mdio_ops;
2389 2390 2391 2392
	u32 predata, count;
	size_t index;

	predata = count = 0;
2393 2394
	org.write = ops->write;
	org.read = ops->read;
2395

2396 2397
	for (index = 0; index < pa->size; ) {
		u32 action = le32_to_cpu(pa->code[index]);
2398
		u32 data = action & 0x0000ffff;
2399 2400 2401 2402
		u32 regno = (action & 0x0fff0000) >> 16;

		if (!action)
			break;
2403 2404

		switch(action & 0xf0000000) {
2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420
		case PHY_READ:
			predata = rtl_readphy(tp, regno);
			count++;
			index++;
			break;
		case PHY_DATA_OR:
			predata |= data;
			index++;
			break;
		case PHY_DATA_AND:
			predata &= data;
			index++;
			break;
		case PHY_BJMPN:
			index -= regno;
			break;
2421 2422 2423 2424 2425 2426 2427 2428 2429
		case PHY_MDIO_CHG:
			if (data == 0) {
				ops->write = org.write;
				ops->read = org.read;
			} else if (data == 1) {
				ops->write = mac_mcu_write;
				ops->read = mac_mcu_read;
			}

2430 2431 2432 2433 2434 2435
			index++;
			break;
		case PHY_CLEAR_READCOUNT:
			count = 0;
			index++;
			break;
2436
		case PHY_WRITE:
2437 2438 2439 2440
			rtl_writephy(tp, regno, data);
			index++;
			break;
		case PHY_READCOUNT_EQ_SKIP:
F
Francois Romieu 已提交
2441
			index += (count == data) ? 2 : 1;
2442
			break;
2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464
		case PHY_COMP_EQ_SKIPN:
			if (predata == data)
				index += regno;
			index++;
			break;
		case PHY_COMP_NEQ_SKIPN:
			if (predata != data)
				index += regno;
			index++;
			break;
		case PHY_WRITE_PREVIOUS:
			rtl_writephy(tp, regno, predata);
			index++;
			break;
		case PHY_SKIPN:
			index += regno + 1;
			break;
		case PHY_DELAY_MS:
			mdelay(data);
			index++;
			break;

2465 2466 2467 2468
		default:
			BUG();
		}
	}
2469 2470 2471

	ops->write = org.write;
	ops->read = org.read;
2472 2473
}

2474 2475
static void rtl_release_firmware(struct rtl8169_private *tp)
{
2476 2477 2478 2479 2480
	if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
		release_firmware(tp->rtl_fw->fw);
		kfree(tp->rtl_fw);
	}
	tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2481 2482
}

2483
static void rtl_apply_firmware(struct rtl8169_private *tp)
2484
{
2485
	struct rtl_fw *rtl_fw = tp->rtl_fw;
2486 2487

	/* TODO: release firmware once rtl_phy_write_fw signals failures. */
2488
	if (!IS_ERR_OR_NULL(rtl_fw))
2489
		rtl_phy_write_fw(tp, rtl_fw);
2490 2491 2492 2493 2494 2495 2496 2497
}

static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
{
	if (rtl_readphy(tp, reg) != val)
		netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
	else
		rtl_apply_firmware(tp);
2498 2499
}

2500
static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
2501
{
2502
	static const struct phy_reg phy_reg_init[] = {
F
françois romieu 已提交
2503 2504 2505 2506 2507
		{ 0x1f, 0x0001 },
		{ 0x06, 0x006e },
		{ 0x08, 0x0708 },
		{ 0x15, 0x4000 },
		{ 0x18, 0x65c7 },
L
Linus Torvalds 已提交
2508

F
françois romieu 已提交
2509 2510 2511 2512 2513 2514 2515
		{ 0x1f, 0x0001 },
		{ 0x03, 0x00a1 },
		{ 0x02, 0x0008 },
		{ 0x01, 0x0120 },
		{ 0x00, 0x1000 },
		{ 0x04, 0x0800 },
		{ 0x04, 0x0000 },
L
Linus Torvalds 已提交
2516

F
françois romieu 已提交
2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562
		{ 0x03, 0xff41 },
		{ 0x02, 0xdf60 },
		{ 0x01, 0x0140 },
		{ 0x00, 0x0077 },
		{ 0x04, 0x7800 },
		{ 0x04, 0x7000 },

		{ 0x03, 0x802f },
		{ 0x02, 0x4f02 },
		{ 0x01, 0x0409 },
		{ 0x00, 0xf0f9 },
		{ 0x04, 0x9800 },
		{ 0x04, 0x9000 },

		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0xff95 },
		{ 0x00, 0xba00 },
		{ 0x04, 0xa800 },
		{ 0x04, 0xa000 },

		{ 0x03, 0xff41 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x0140 },
		{ 0x00, 0x00bb },
		{ 0x04, 0xb800 },
		{ 0x04, 0xb000 },

		{ 0x03, 0xdf41 },
		{ 0x02, 0xdc60 },
		{ 0x01, 0x6340 },
		{ 0x00, 0x007d },
		{ 0x04, 0xd800 },
		{ 0x04, 0xd000 },

		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x100a },
		{ 0x00, 0xa0ff },
		{ 0x04, 0xf800 },
		{ 0x04, 0xf000 },

		{ 0x1f, 0x0000 },
		{ 0x0b, 0x0000 },
		{ 0x00, 0x9200 }
	};
L
Linus Torvalds 已提交
2563

2564
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
L
Linus Torvalds 已提交
2565 2566
}

2567
static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2568
{
2569
	static const struct phy_reg phy_reg_init[] = {
F
Francois Romieu 已提交
2570 2571 2572 2573 2574
		{ 0x1f, 0x0002 },
		{ 0x01, 0x90d0 },
		{ 0x1f, 0x0000 }
	};

2575
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2576 2577
}

2578
static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2579 2580 2581
{
	struct pci_dev *pdev = tp->pci_dev;

2582 2583
	if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
	    (pdev->subsystem_device != 0xe000))
2584 2585
		return;

2586 2587 2588
	rtl_writephy(tp, 0x1f, 0x0001);
	rtl_writephy(tp, 0x10, 0xf01b);
	rtl_writephy(tp, 0x1f, 0x0000);
2589 2590
}

2591
static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2592
{
2593
	static const struct phy_reg phy_reg_init[] = {
2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632
		{ 0x1f, 0x0001 },
		{ 0x04, 0x0000 },
		{ 0x03, 0x00a1 },
		{ 0x02, 0x0008 },
		{ 0x01, 0x0120 },
		{ 0x00, 0x1000 },
		{ 0x04, 0x0800 },
		{ 0x04, 0x9000 },
		{ 0x03, 0x802f },
		{ 0x02, 0x4f02 },
		{ 0x01, 0x0409 },
		{ 0x00, 0xf099 },
		{ 0x04, 0x9800 },
		{ 0x04, 0xa000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0xff95 },
		{ 0x00, 0xba00 },
		{ 0x04, 0xa800 },
		{ 0x04, 0xf000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x101a },
		{ 0x00, 0xa0ff },
		{ 0x04, 0xf800 },
		{ 0x04, 0x0000 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x10, 0xf41b },
		{ 0x14, 0xfb54 },
		{ 0x18, 0xf5c7 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },
		{ 0x1f, 0x0000 }
	};

2633
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2634

2635
	rtl8169scd_hw_phy_config_quirk(tp);
2636 2637
}

2638
static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2639
{
2640
	static const struct phy_reg phy_reg_init[] = {
2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687
		{ 0x1f, 0x0001 },
		{ 0x04, 0x0000 },
		{ 0x03, 0x00a1 },
		{ 0x02, 0x0008 },
		{ 0x01, 0x0120 },
		{ 0x00, 0x1000 },
		{ 0x04, 0x0800 },
		{ 0x04, 0x9000 },
		{ 0x03, 0x802f },
		{ 0x02, 0x4f02 },
		{ 0x01, 0x0409 },
		{ 0x00, 0xf099 },
		{ 0x04, 0x9800 },
		{ 0x04, 0xa000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0xff95 },
		{ 0x00, 0xba00 },
		{ 0x04, 0xa800 },
		{ 0x04, 0xf000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x101a },
		{ 0x00, 0xa0ff },
		{ 0x04, 0xf800 },
		{ 0x04, 0x0000 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x0b, 0x8480 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x18, 0x67c7 },
		{ 0x04, 0x2000 },
		{ 0x03, 0x002f },
		{ 0x02, 0x4360 },
		{ 0x01, 0x0109 },
		{ 0x00, 0x3022 },
		{ 0x04, 0x2800 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },
		{ 0x1f, 0x0000 }
	};

2688
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2689 2690
}

2691
static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2692
{
2693
	static const struct phy_reg phy_reg_init[] = {
2694 2695 2696 2697
		{ 0x10, 0xf41b },
		{ 0x1f, 0x0000 }
	};

2698 2699
	rtl_writephy(tp, 0x1f, 0x0001);
	rtl_patchphy(tp, 0x16, 1 << 0);
2700

2701
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2702 2703
}

2704
static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2705
{
2706
	static const struct phy_reg phy_reg_init[] = {
2707 2708 2709 2710 2711
		{ 0x1f, 0x0001 },
		{ 0x10, 0xf41b },
		{ 0x1f, 0x0000 }
	};

2712
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2713 2714
}

2715
static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
F
Francois Romieu 已提交
2716
{
2717
	static const struct phy_reg phy_reg_init[] = {
F
Francois Romieu 已提交
2718 2719 2720 2721 2722 2723 2724
		{ 0x1f, 0x0000 },
		{ 0x1d, 0x0f00 },
		{ 0x1f, 0x0002 },
		{ 0x0c, 0x1ec8 },
		{ 0x1f, 0x0000 }
	};

2725
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
F
Francois Romieu 已提交
2726 2727
}

2728
static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
F
Francois Romieu 已提交
2729
{
2730
	static const struct phy_reg phy_reg_init[] = {
F
Francois Romieu 已提交
2731 2732 2733 2734 2735
		{ 0x1f, 0x0001 },
		{ 0x1d, 0x3d98 },
		{ 0x1f, 0x0000 }
	};

2736 2737 2738
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_patchphy(tp, 0x14, 1 << 5);
	rtl_patchphy(tp, 0x0d, 1 << 5);
F
Francois Romieu 已提交
2739

2740
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
F
Francois Romieu 已提交
2741 2742
}

2743
static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
F
Francois Romieu 已提交
2744
{
2745
	static const struct phy_reg phy_reg_init[] = {
2746 2747
		{ 0x1f, 0x0001 },
		{ 0x12, 0x2300 },
F
Francois Romieu 已提交
2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758
		{ 0x1f, 0x0002 },
		{ 0x00, 0x88d4 },
		{ 0x01, 0x82b1 },
		{ 0x03, 0x7002 },
		{ 0x08, 0x9e30 },
		{ 0x09, 0x01f0 },
		{ 0x0a, 0x5500 },
		{ 0x0c, 0x00c8 },
		{ 0x1f, 0x0003 },
		{ 0x12, 0xc096 },
		{ 0x16, 0x000a },
2759 2760 2761 2762
		{ 0x1f, 0x0000 },
		{ 0x1f, 0x0000 },
		{ 0x09, 0x2000 },
		{ 0x09, 0x0000 }
F
Francois Romieu 已提交
2763 2764
	};

2765
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2766

2767 2768 2769
	rtl_patchphy(tp, 0x14, 1 << 5);
	rtl_patchphy(tp, 0x0d, 1 << 5);
	rtl_writephy(tp, 0x1f, 0x0000);
F
Francois Romieu 已提交
2770 2771
}

2772
static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2773
{
2774
	static const struct phy_reg phy_reg_init[] = {
2775
		{ 0x1f, 0x0001 },
2776
		{ 0x12, 0x2300 },
2777 2778 2779 2780 2781 2782 2783
		{ 0x03, 0x802f },
		{ 0x02, 0x4f02 },
		{ 0x01, 0x0409 },
		{ 0x00, 0xf099 },
		{ 0x04, 0x9800 },
		{ 0x04, 0x9000 },
		{ 0x1d, 0x3d98 },
2784 2785
		{ 0x1f, 0x0002 },
		{ 0x0c, 0x7eb8 },
2786 2787 2788
		{ 0x06, 0x0761 },
		{ 0x1f, 0x0003 },
		{ 0x16, 0x0f0a },
2789 2790 2791
		{ 0x1f, 0x0000 }
	};

2792
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2793

2794 2795 2796 2797
	rtl_patchphy(tp, 0x16, 1 << 0);
	rtl_patchphy(tp, 0x14, 1 << 5);
	rtl_patchphy(tp, 0x0d, 1 << 5);
	rtl_writephy(tp, 0x1f, 0x0000);
2798 2799
}

2800
static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
F
Francois Romieu 已提交
2801
{
2802
	static const struct phy_reg phy_reg_init[] = {
F
Francois Romieu 已提交
2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813
		{ 0x1f, 0x0001 },
		{ 0x12, 0x2300 },
		{ 0x1d, 0x3d98 },
		{ 0x1f, 0x0002 },
		{ 0x0c, 0x7eb8 },
		{ 0x06, 0x5461 },
		{ 0x1f, 0x0003 },
		{ 0x16, 0x0f0a },
		{ 0x1f, 0x0000 }
	};

2814
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
F
Francois Romieu 已提交
2815

2816 2817 2818 2819
	rtl_patchphy(tp, 0x16, 1 << 0);
	rtl_patchphy(tp, 0x14, 1 << 5);
	rtl_patchphy(tp, 0x0d, 1 << 5);
	rtl_writephy(tp, 0x1f, 0x0000);
F
Francois Romieu 已提交
2820 2821
}

2822
static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2823
{
2824
	rtl8168c_3_hw_phy_config(tp);
2825 2826
}

2827
static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
F
Francois Romieu 已提交
2828
{
2829
	static const struct phy_reg phy_reg_init_0[] = {
2830
		/* Channel Estimation */
F
Francois Romieu 已提交
2831
		{ 0x1f, 0x0001 },
2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842
		{ 0x06, 0x4064 },
		{ 0x07, 0x2863 },
		{ 0x08, 0x059c },
		{ 0x09, 0x26b4 },
		{ 0x0a, 0x6a19 },
		{ 0x0b, 0xdcc8 },
		{ 0x10, 0xf06d },
		{ 0x14, 0x7f68 },
		{ 0x18, 0x7fd9 },
		{ 0x1c, 0xf0ff },
		{ 0x1d, 0x3d9c },
F
Francois Romieu 已提交
2843
		{ 0x1f, 0x0003 },
2844 2845 2846
		{ 0x12, 0xf49f },
		{ 0x13, 0x070b },
		{ 0x1a, 0x05ad },
2847 2848 2849 2850
		{ 0x14, 0x94c0 },

		/*
		 * Tx Error Issue
F
Francois Romieu 已提交
2851
		 * Enhance line driver power
2852
		 */
F
Francois Romieu 已提交
2853
		{ 0x1f, 0x0002 },
2854 2855 2856
		{ 0x06, 0x5561 },
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8332 },
2857 2858 2859 2860 2861 2862 2863 2864
		{ 0x06, 0x5561 },

		/*
		 * Can not link to 1Gbps with bad cable
		 * Decrease SNR threshold form 21.07dB to 19.04dB
		 */
		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },
2865

F
Francois Romieu 已提交
2866
		{ 0x1f, 0x0000 },
2867
		{ 0x0d, 0xf880 }
2868 2869
	};

2870
	rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2871

2872 2873 2874 2875
	/*
	 * Rx Error Issue
	 * Fine Tune Switching regulator parameter
	 */
2876 2877 2878
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
	rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2879

2880
	if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2881
		static const struct phy_reg phy_reg_init[] = {
2882 2883 2884 2885 2886 2887 2888 2889 2890
			{ 0x1f, 0x0002 },
			{ 0x05, 0x669a },
			{ 0x1f, 0x0005 },
			{ 0x05, 0x8330 },
			{ 0x06, 0x669a },
			{ 0x1f, 0x0002 }
		};
		int val;

2891
		rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2892

2893
		val = rtl_readphy(tp, 0x0d);
2894 2895

		if ((val & 0x00ff) != 0x006c) {
2896
			static const u32 set[] = {
2897 2898 2899 2900 2901
				0x0065, 0x0066, 0x0067, 0x0068,
				0x0069, 0x006a, 0x006b, 0x006c
			};
			int i;

2902
			rtl_writephy(tp, 0x1f, 0x0002);
2903 2904 2905

			val &= 0xff00;
			for (i = 0; i < ARRAY_SIZE(set); i++)
2906
				rtl_writephy(tp, 0x0d, val | set[i]);
2907 2908
		}
	} else {
2909
		static const struct phy_reg phy_reg_init[] = {
2910 2911 2912 2913 2914 2915 2916
			{ 0x1f, 0x0002 },
			{ 0x05, 0x6662 },
			{ 0x1f, 0x0005 },
			{ 0x05, 0x8330 },
			{ 0x06, 0x6662 }
		};

2917
		rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2918 2919
	}

2920
	/* RSET couple improve */
2921 2922 2923
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_patchphy(tp, 0x0d, 0x0300);
	rtl_patchphy(tp, 0x0f, 0x0010);
2924

2925
	/* Fine tune PLL performance */
2926 2927 2928
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
	rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2929

2930 2931
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x001b);
2932 2933

	rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2934

2935
	rtl_writephy(tp, 0x1f, 0x0000);
2936 2937
}

2938
static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2939
{
2940
	static const struct phy_reg phy_reg_init_0[] = {
2941
		/* Channel Estimation */
2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959
		{ 0x1f, 0x0001 },
		{ 0x06, 0x4064 },
		{ 0x07, 0x2863 },
		{ 0x08, 0x059c },
		{ 0x09, 0x26b4 },
		{ 0x0a, 0x6a19 },
		{ 0x0b, 0xdcc8 },
		{ 0x10, 0xf06d },
		{ 0x14, 0x7f68 },
		{ 0x18, 0x7fd9 },
		{ 0x1c, 0xf0ff },
		{ 0x1d, 0x3d9c },
		{ 0x1f, 0x0003 },
		{ 0x12, 0xf49f },
		{ 0x13, 0x070b },
		{ 0x1a, 0x05ad },
		{ 0x14, 0x94c0 },

2960 2961
		/*
		 * Tx Error Issue
F
Francois Romieu 已提交
2962
		 * Enhance line driver power
2963
		 */
2964 2965 2966 2967
		{ 0x1f, 0x0002 },
		{ 0x06, 0x5561 },
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8332 },
2968 2969 2970 2971 2972 2973 2974 2975
		{ 0x06, 0x5561 },

		/*
		 * Can not link to 1Gbps with bad cable
		 * Decrease SNR threshold form 21.07dB to 19.04dB
		 */
		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },
2976 2977

		{ 0x1f, 0x0000 },
2978
		{ 0x0d, 0xf880 }
F
Francois Romieu 已提交
2979 2980
	};

2981
	rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
F
Francois Romieu 已提交
2982

2983
	if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2984
		static const struct phy_reg phy_reg_init[] = {
2985 2986
			{ 0x1f, 0x0002 },
			{ 0x05, 0x669a },
F
Francois Romieu 已提交
2987
			{ 0x1f, 0x0005 },
2988 2989 2990 2991 2992 2993 2994
			{ 0x05, 0x8330 },
			{ 0x06, 0x669a },

			{ 0x1f, 0x0002 }
		};
		int val;

2995
		rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2996

2997
		val = rtl_readphy(tp, 0x0d);
2998
		if ((val & 0x00ff) != 0x006c) {
J
Joe Perches 已提交
2999
			static const u32 set[] = {
3000 3001 3002 3003 3004
				0x0065, 0x0066, 0x0067, 0x0068,
				0x0069, 0x006a, 0x006b, 0x006c
			};
			int i;

3005
			rtl_writephy(tp, 0x1f, 0x0002);
3006 3007 3008

			val &= 0xff00;
			for (i = 0; i < ARRAY_SIZE(set); i++)
3009
				rtl_writephy(tp, 0x0d, val | set[i]);
3010 3011
		}
	} else {
3012
		static const struct phy_reg phy_reg_init[] = {
3013 3014
			{ 0x1f, 0x0002 },
			{ 0x05, 0x2642 },
F
Francois Romieu 已提交
3015
			{ 0x1f, 0x0005 },
3016 3017
			{ 0x05, 0x8330 },
			{ 0x06, 0x2642 }
F
Francois Romieu 已提交
3018 3019
		};

3020
		rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
F
Francois Romieu 已提交
3021 3022
	}

3023
	/* Fine tune PLL performance */
3024 3025 3026
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
	rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
3027

3028
	/* Switching regulator Slew rate */
3029 3030
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_patchphy(tp, 0x0f, 0x0017);
3031

3032 3033
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x001b);
3034 3035

	rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3036

3037
	rtl_writephy(tp, 0x1f, 0x0000);
3038 3039
}

3040
static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3041
{
3042
	static const struct phy_reg phy_reg_init[] = {
3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097
		{ 0x1f, 0x0002 },
		{ 0x10, 0x0008 },
		{ 0x0d, 0x006c },

		{ 0x1f, 0x0000 },
		{ 0x0d, 0xf880 },

		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },

		{ 0x1f, 0x0001 },
		{ 0x0b, 0xa4d8 },
		{ 0x09, 0x281c },
		{ 0x07, 0x2883 },
		{ 0x0a, 0x6b35 },
		{ 0x1d, 0x3da4 },
		{ 0x1c, 0xeffd },
		{ 0x14, 0x7f52 },
		{ 0x18, 0x7fc6 },
		{ 0x08, 0x0601 },
		{ 0x06, 0x4063 },
		{ 0x10, 0xf074 },
		{ 0x1f, 0x0003 },
		{ 0x13, 0x0789 },
		{ 0x12, 0xf4bd },
		{ 0x1a, 0x04fd },
		{ 0x14, 0x84b0 },
		{ 0x1f, 0x0000 },
		{ 0x00, 0x9200 },

		{ 0x1f, 0x0005 },
		{ 0x01, 0x0340 },
		{ 0x1f, 0x0001 },
		{ 0x04, 0x4000 },
		{ 0x03, 0x1d21 },
		{ 0x02, 0x0c32 },
		{ 0x01, 0x0200 },
		{ 0x00, 0x5554 },
		{ 0x04, 0x4800 },
		{ 0x04, 0x4000 },
		{ 0x04, 0xf000 },
		{ 0x03, 0xdf01 },
		{ 0x02, 0xdf20 },
		{ 0x01, 0x101a },
		{ 0x00, 0xa0ff },
		{ 0x04, 0xf800 },
		{ 0x04, 0xf000 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0007 },
		{ 0x1e, 0x0023 },
		{ 0x16, 0x0000 },
		{ 0x1f, 0x0000 }
	};

3098
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
F
Francois Romieu 已提交
3099 3100
}

F
françois romieu 已提交
3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116
static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
{
	static const struct phy_reg phy_reg_init[] = {
		{ 0x1f, 0x0001 },
		{ 0x17, 0x0cc0 },

		{ 0x1f, 0x0007 },
		{ 0x1e, 0x002d },
		{ 0x18, 0x0040 },
		{ 0x1f, 0x0000 }
	};

	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
	rtl_patchphy(tp, 0x0d, 1 << 5);
}

H
Hayes Wang 已提交
3117
static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
H
hayeswang 已提交
3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146
{
	static const struct phy_reg phy_reg_init[] = {
		/* Enable Delay cap */
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8b80 },
		{ 0x06, 0xc896 },
		{ 0x1f, 0x0000 },

		/* Channel estimation fine tune */
		{ 0x1f, 0x0001 },
		{ 0x0b, 0x6c20 },
		{ 0x07, 0x2872 },
		{ 0x1c, 0xefff },
		{ 0x1f, 0x0003 },
		{ 0x14, 0x6420 },
		{ 0x1f, 0x0000 },

		/* Update PFM & 10M TX idle timer */
		{ 0x1f, 0x0007 },
		{ 0x1e, 0x002f },
		{ 0x15, 0x1919 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0007 },
		{ 0x1e, 0x00ac },
		{ 0x18, 0x0006 },
		{ 0x1f, 0x0000 }
	};

F
Francois Romieu 已提交
3147 3148
	rtl_apply_firmware(tp);

H
hayeswang 已提交
3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));

	/* DCO enable for 10M IDLE Power */
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x0023);
	rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* For impedance matching */
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
F
Francois Romieu 已提交
3160
	rtl_writephy(tp, 0x1f, 0x0000);
H
hayeswang 已提交
3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189

	/* PHY auto speed down */
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x002d);
	rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);

	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b86);
	rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b85);
	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x0020);
	rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
	rtl_writephy(tp, 0x1f, 0x0006);
	rtl_writephy(tp, 0x00, 0x5a00);
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, 0x0d, 0x0007);
	rtl_writephy(tp, 0x0e, 0x003c);
	rtl_writephy(tp, 0x0d, 0x4007);
	rtl_writephy(tp, 0x0e, 0x0000);
	rtl_writephy(tp, 0x0d, 0x0000);
}

3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206
static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
{
	const u16 w[] = {
		addr[0] | (addr[1] << 8),
		addr[2] | (addr[3] << 8),
		addr[4] | (addr[5] << 8)
	};
	const struct exgmac_reg e[] = {
		{ .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
		{ .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
		{ .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
		{ .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
	};

	rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
}

H
Hayes Wang 已提交
3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267
static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
{
	static const struct phy_reg phy_reg_init[] = {
		/* Enable Delay cap */
		{ 0x1f, 0x0004 },
		{ 0x1f, 0x0007 },
		{ 0x1e, 0x00ac },
		{ 0x18, 0x0006 },
		{ 0x1f, 0x0002 },
		{ 0x1f, 0x0000 },
		{ 0x1f, 0x0000 },

		/* Channel estimation fine tune */
		{ 0x1f, 0x0003 },
		{ 0x09, 0xa20f },
		{ 0x1f, 0x0000 },
		{ 0x1f, 0x0000 },

		/* Green Setting */
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8b5b },
		{ 0x06, 0x9222 },
		{ 0x05, 0x8b6d },
		{ 0x06, 0x8000 },
		{ 0x05, 0x8b76 },
		{ 0x06, 0x8000 },
		{ 0x1f, 0x0000 }
	};

	rtl_apply_firmware(tp);

	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));

	/* For 4-corner performance improve */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b80);
	rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* PHY auto speed down */
	rtl_writephy(tp, 0x1f, 0x0004);
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x002d);
	rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);

	/* improve 10M EEE waveform */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b86);
	rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* Improve 2-pair detection performance */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b85);
	rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* EEE setting */
3268
	rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
H
Hayes Wang 已提交
3269 3270 3271 3272 3273 3274
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b85);
	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
	rtl_writephy(tp, 0x1f, 0x0004);
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x0020);
3275
	rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
H
Hayes Wang 已提交
3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288
	rtl_writephy(tp, 0x1f, 0x0002);
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, 0x0d, 0x0007);
	rtl_writephy(tp, 0x0e, 0x003c);
	rtl_writephy(tp, 0x0d, 0x4007);
	rtl_writephy(tp, 0x0e, 0x0000);
	rtl_writephy(tp, 0x0d, 0x0000);

	/* Green feature */
	rtl_writephy(tp, 0x1f, 0x0003);
	rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
	rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
	rtl_writephy(tp, 0x1f, 0x0000);
H
hayeswang 已提交
3289

3290 3291
	/* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
	rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
H
Hayes Wang 已提交
3292 3293
}

3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315
static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
{
	/* For 4-corner performance improve */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b80);
	rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* PHY auto speed down */
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x002d);
	rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);

	/* Improve 10M EEE waveform */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b86);
	rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);
}

3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356
static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
{
	static const struct phy_reg phy_reg_init[] = {
		/* Channel estimation fine tune */
		{ 0x1f, 0x0003 },
		{ 0x09, 0xa20f },
		{ 0x1f, 0x0000 },

		/* Modify green table for giga & fnet */
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8b55 },
		{ 0x06, 0x0000 },
		{ 0x05, 0x8b5e },
		{ 0x06, 0x0000 },
		{ 0x05, 0x8b67 },
		{ 0x06, 0x0000 },
		{ 0x05, 0x8b70 },
		{ 0x06, 0x0000 },
		{ 0x1f, 0x0000 },
		{ 0x1f, 0x0007 },
		{ 0x1e, 0x0078 },
		{ 0x17, 0x0000 },
		{ 0x19, 0x00fb },
		{ 0x1f, 0x0000 },

		/* Modify green table for 10M */
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8b79 },
		{ 0x06, 0xaa00 },
		{ 0x1f, 0x0000 },

		/* Disable hiimpedance detection (RTCT) */
		{ 0x1f, 0x0003 },
		{ 0x01, 0x328a },
		{ 0x1f, 0x0000 }
	};

	rtl_apply_firmware(tp);

	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));

3357
	rtl8168f_hw_phy_config(tp);
3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369

	/* Improve 2-pair detection performance */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b85);
	rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);
}

static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
{
	rtl_apply_firmware(tp);

3370
	rtl8168f_hw_phy_config(tp);
3371 3372
}

3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447
static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
{
	static const struct phy_reg phy_reg_init[] = {
		/* Channel estimation fine tune */
		{ 0x1f, 0x0003 },
		{ 0x09, 0xa20f },
		{ 0x1f, 0x0000 },

		/* Modify green table for giga & fnet */
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8b55 },
		{ 0x06, 0x0000 },
		{ 0x05, 0x8b5e },
		{ 0x06, 0x0000 },
		{ 0x05, 0x8b67 },
		{ 0x06, 0x0000 },
		{ 0x05, 0x8b70 },
		{ 0x06, 0x0000 },
		{ 0x1f, 0x0000 },
		{ 0x1f, 0x0007 },
		{ 0x1e, 0x0078 },
		{ 0x17, 0x0000 },
		{ 0x19, 0x00aa },
		{ 0x1f, 0x0000 },

		/* Modify green table for 10M */
		{ 0x1f, 0x0005 },
		{ 0x05, 0x8b79 },
		{ 0x06, 0xaa00 },
		{ 0x1f, 0x0000 },

		/* Disable hiimpedance detection (RTCT) */
		{ 0x1f, 0x0003 },
		{ 0x01, 0x328a },
		{ 0x1f, 0x0000 }
	};


	rtl_apply_firmware(tp);

	rtl8168f_hw_phy_config(tp);

	/* Improve 2-pair detection performance */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b85);
	rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));

	/* Modify green table for giga */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b54);
	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
	rtl_writephy(tp, 0x05, 0x8b5d);
	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
	rtl_writephy(tp, 0x05, 0x8a7c);
	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
	rtl_writephy(tp, 0x05, 0x8a7f);
	rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
	rtl_writephy(tp, 0x05, 0x8a82);
	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
	rtl_writephy(tp, 0x05, 0x8a85);
	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
	rtl_writephy(tp, 0x05, 0x8a88);
	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* uc same-seed solution */
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b85);
	rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* eee setting */
3448
	rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469
	rtl_writephy(tp, 0x1f, 0x0005);
	rtl_writephy(tp, 0x05, 0x8b85);
	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
	rtl_writephy(tp, 0x1f, 0x0004);
	rtl_writephy(tp, 0x1f, 0x0007);
	rtl_writephy(tp, 0x1e, 0x0020);
	rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, 0x0d, 0x0007);
	rtl_writephy(tp, 0x0e, 0x003c);
	rtl_writephy(tp, 0x0d, 0x4007);
	rtl_writephy(tp, 0x0e, 0x0000);
	rtl_writephy(tp, 0x0d, 0x0000);

	/* Green feature */
	rtl_writephy(tp, 0x1f, 0x0003);
	rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
	rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
	rtl_writephy(tp, 0x1f, 0x0000);
}

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static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
{
	rtl_apply_firmware(tp);

3474 3475 3476 3477 3478 3479 3480 3481
	rtl_writephy(tp, 0x1f, 0x0a46);
	if (rtl_readphy(tp, 0x10) & 0x0100) {
		rtl_writephy(tp, 0x1f, 0x0bcc);
		rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
	} else {
		rtl_writephy(tp, 0x1f, 0x0bcc);
		rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
	}
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3483 3484 3485 3486 3487
	rtl_writephy(tp, 0x1f, 0x0a46);
	if (rtl_readphy(tp, 0x13) & 0x0100) {
		rtl_writephy(tp, 0x1f, 0x0c41);
		rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
	} else {
3488 3489
		rtl_writephy(tp, 0x1f, 0x0c41);
		rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
3490
	}
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3492 3493 3494
	/* Enable PHY auto speed down */
	rtl_writephy(tp, 0x1f, 0x0a44);
	rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
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3496 3497 3498 3499 3500 3501 3502 3503 3504
	rtl_writephy(tp, 0x1f, 0x0bcc);
	rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0a44);
	rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x8084);
	rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
	rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);

3505 3506 3507
	/* EEE auto-fallback function */
	rtl_writephy(tp, 0x1f, 0x0a4b);
	rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
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3509 3510 3511 3512 3513 3514 3515 3516
	/* Enable UC LPF tune function */
	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x8012);
	rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);

	rtl_writephy(tp, 0x1f, 0x0c42);
	rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);

3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527
	/* Improve SWR Efficiency */
	rtl_writephy(tp, 0x1f, 0x0bcd);
	rtl_writephy(tp, 0x14, 0x5065);
	rtl_writephy(tp, 0x14, 0xd065);
	rtl_writephy(tp, 0x1f, 0x0bc8);
	rtl_writephy(tp, 0x11, 0x5655);
	rtl_writephy(tp, 0x1f, 0x0bcd);
	rtl_writephy(tp, 0x14, 0x1065);
	rtl_writephy(tp, 0x14, 0x9065);
	rtl_writephy(tp, 0x14, 0x1065);

3528 3529 3530 3531 3532
	/* Check ALDPS bit, disable it if enabled */
	rtl_writephy(tp, 0x1f, 0x0a43);
	if (rtl_readphy(tp, 0x10) & 0x0004)
		rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);

3533
	rtl_writephy(tp, 0x1f, 0x0000);
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}

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static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
{
	rtl_apply_firmware(tp);
}

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static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
{
	u16 dout_tapbin;
	u32 data;

	rtl_apply_firmware(tp);

	/* CHN EST parameters adjust - giga master */
	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x809b);
	rtl_w1w0_phy(tp, 0x14, 0x8000, 0xf800);
	rtl_writephy(tp, 0x13, 0x80a2);
	rtl_w1w0_phy(tp, 0x14, 0x8000, 0xff00);
	rtl_writephy(tp, 0x13, 0x80a4);
	rtl_w1w0_phy(tp, 0x14, 0x8500, 0xff00);
	rtl_writephy(tp, 0x13, 0x809c);
	rtl_w1w0_phy(tp, 0x14, 0xbd00, 0xff00);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* CHN EST parameters adjust - giga slave */
	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x80ad);
	rtl_w1w0_phy(tp, 0x14, 0x7000, 0xf800);
	rtl_writephy(tp, 0x13, 0x80b4);
	rtl_w1w0_phy(tp, 0x14, 0x5000, 0xff00);
	rtl_writephy(tp, 0x13, 0x80ac);
	rtl_w1w0_phy(tp, 0x14, 0x4000, 0xff00);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* CHN EST parameters adjust - fnet */
	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x808e);
	rtl_w1w0_phy(tp, 0x14, 0x1200, 0xff00);
	rtl_writephy(tp, 0x13, 0x8090);
	rtl_w1w0_phy(tp, 0x14, 0xe500, 0xff00);
	rtl_writephy(tp, 0x13, 0x8092);
	rtl_w1w0_phy(tp, 0x14, 0x9f00, 0xff00);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* enable R-tune & PGA-retune function */
	dout_tapbin = 0;
	rtl_writephy(tp, 0x1f, 0x0a46);
	data = rtl_readphy(tp, 0x13);
	data &= 3;
	data <<= 2;
	dout_tapbin |= data;
	data = rtl_readphy(tp, 0x12);
	data &= 0xc000;
	data >>= 14;
	dout_tapbin |= data;
	dout_tapbin = ~(dout_tapbin^0x08);
	dout_tapbin <<= 12;
	dout_tapbin &= 0xf000;
	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x827a);
	rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);
	rtl_writephy(tp, 0x13, 0x827b);
	rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);
	rtl_writephy(tp, 0x13, 0x827c);
	rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);
	rtl_writephy(tp, 0x13, 0x827d);
	rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);

	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x0811);
	rtl_w1w0_phy(tp, 0x14, 0x0800, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0a42);
	rtl_w1w0_phy(tp, 0x16, 0x0002, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* enable GPHY 10M */
	rtl_writephy(tp, 0x1f, 0x0a44);
	rtl_w1w0_phy(tp, 0x11, 0x0800, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* SAR ADC performance */
	rtl_writephy(tp, 0x1f, 0x0bca);
	rtl_w1w0_phy(tp, 0x17, 0x4000, 0x3000);
	rtl_writephy(tp, 0x1f, 0x0000);

	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x803f);
	rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
	rtl_writephy(tp, 0x13, 0x8047);
	rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
	rtl_writephy(tp, 0x13, 0x804f);
	rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
	rtl_writephy(tp, 0x13, 0x8057);
	rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
	rtl_writephy(tp, 0x13, 0x805f);
	rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
	rtl_writephy(tp, 0x13, 0x8067);
	rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
	rtl_writephy(tp, 0x13, 0x806f);
	rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* disable phy pfm mode */
	rtl_writephy(tp, 0x1f, 0x0a44);
	rtl_w1w0_phy(tp, 0x14, 0x0000, 0x0080);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* Check ALDPS bit, disable it if enabled */
	rtl_writephy(tp, 0x1f, 0x0a43);
	if (rtl_readphy(tp, 0x10) & 0x0004)
		rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);

	rtl_writephy(tp, 0x1f, 0x0000);
}

static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
{
	u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
	u16 rlen;
	u32 data;

	rtl_apply_firmware(tp);

	/* CHIN EST parameter update */
	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x808a);
	rtl_w1w0_phy(tp, 0x14, 0x000a, 0x003f);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* enable R-tune & PGA-retune function */
	rtl_writephy(tp, 0x1f, 0x0a43);
	rtl_writephy(tp, 0x13, 0x0811);
	rtl_w1w0_phy(tp, 0x14, 0x0800, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0a42);
	rtl_w1w0_phy(tp, 0x16, 0x0002, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* enable GPHY 10M */
	rtl_writephy(tp, 0x1f, 0x0a44);
	rtl_w1w0_phy(tp, 0x11, 0x0800, 0x0000);
	rtl_writephy(tp, 0x1f, 0x0000);

	r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
	data = r8168_mac_ocp_read(tp, 0xdd02);
	ioffset_p3 = ((data & 0x80)>>7);
	ioffset_p3 <<= 3;

	data = r8168_mac_ocp_read(tp, 0xdd00);
	ioffset_p3 |= ((data & (0xe000))>>13);
	ioffset_p2 = ((data & (0x1e00))>>9);
	ioffset_p1 = ((data & (0x01e0))>>5);
	ioffset_p0 = ((data & 0x0010)>>4);
	ioffset_p0 <<= 3;
	ioffset_p0 |= (data & (0x07));
	data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);

	if ((ioffset_p3 != 0x0F) || (ioffset_p2 != 0x0F) ||
	    (ioffset_p1 != 0x0F) || (ioffset_p0 == 0x0F)) {
		rtl_writephy(tp, 0x1f, 0x0bcf);
		rtl_writephy(tp, 0x16, data);
		rtl_writephy(tp, 0x1f, 0x0000);
	}

	/* Modify rlen (TX LPF corner frequency) level */
	rtl_writephy(tp, 0x1f, 0x0bcd);
	data = rtl_readphy(tp, 0x16);
	data &= 0x000f;
	rlen = 0;
	if (data > 3)
		rlen = data - 3;
	data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
	rtl_writephy(tp, 0x17, data);
	rtl_writephy(tp, 0x1f, 0x0bcd);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* disable phy pfm mode */
	rtl_writephy(tp, 0x1f, 0x0a44);
	rtl_w1w0_phy(tp, 0x14, 0x0000, 0x0080);
	rtl_writephy(tp, 0x1f, 0x0000);

	/* Check ALDPS bit, disable it if enabled */
	rtl_writephy(tp, 0x1f, 0x0a43);
	if (rtl_readphy(tp, 0x10) & 0x0004)
		rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);

	rtl_writephy(tp, 0x1f, 0x0000);
}

3724
static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3725
{
3726
	static const struct phy_reg phy_reg_init[] = {
3727 3728 3729 3730 3731 3732
		{ 0x1f, 0x0003 },
		{ 0x08, 0x441d },
		{ 0x01, 0x9100 },
		{ 0x1f, 0x0000 }
	};

3733 3734 3735 3736
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_patchphy(tp, 0x11, 1 << 12);
	rtl_patchphy(tp, 0x19, 1 << 13);
	rtl_patchphy(tp, 0x10, 1 << 15);
3737

3738
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3739 3740
}

3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757
static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
{
	static const struct phy_reg phy_reg_init[] = {
		{ 0x1f, 0x0005 },
		{ 0x1a, 0x0000 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0004 },
		{ 0x1c, 0x0000 },
		{ 0x1f, 0x0000 },

		{ 0x1f, 0x0001 },
		{ 0x15, 0x7701 },
		{ 0x1f, 0x0000 }
	};

	/* Disable ALDPS before ram code */
3758 3759 3760
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, 0x18, 0x0310);
	msleep(100);
3761

3762
	rtl_apply_firmware(tp);
3763 3764 3765 3766

	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
}

3767 3768 3769
static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
{
	/* Disable ALDPS before setting firmware */
3770 3771 3772
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, 0x18, 0x0310);
	msleep(20);
3773 3774 3775 3776

	rtl_apply_firmware(tp);

	/* EEE setting */
3777
	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3778 3779 3780 3781 3782 3783
	rtl_writephy(tp, 0x1f, 0x0004);
	rtl_writephy(tp, 0x10, 0x401f);
	rtl_writephy(tp, 0x19, 0x7030);
	rtl_writephy(tp, 0x1f, 0x0000);
}

H
Hayes Wang 已提交
3784 3785 3786 3787 3788 3789 3790 3791 3792 3793
static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
{
	static const struct phy_reg phy_reg_init[] = {
		{ 0x1f, 0x0004 },
		{ 0x10, 0xc07f },
		{ 0x19, 0x7030 },
		{ 0x1f, 0x0000 }
	};

	/* Disable ALDPS before ram code */
3794 3795 3796
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, 0x18, 0x0310);
	msleep(100);
H
Hayes Wang 已提交
3797 3798 3799

	rtl_apply_firmware(tp);

3800
	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
H
Hayes Wang 已提交
3801 3802
	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));

3803
	rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
H
Hayes Wang 已提交
3804 3805
}

3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816
static void rtl_hw_phy_config(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl8169_print_mac_version(tp);

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_01:
		break;
	case RTL_GIGA_MAC_VER_02:
	case RTL_GIGA_MAC_VER_03:
3817
		rtl8169s_hw_phy_config(tp);
3818 3819
		break;
	case RTL_GIGA_MAC_VER_04:
3820
		rtl8169sb_hw_phy_config(tp);
3821
		break;
3822
	case RTL_GIGA_MAC_VER_05:
3823
		rtl8169scd_hw_phy_config(tp);
3824
		break;
3825
	case RTL_GIGA_MAC_VER_06:
3826
		rtl8169sce_hw_phy_config(tp);
3827
		break;
3828 3829 3830
	case RTL_GIGA_MAC_VER_07:
	case RTL_GIGA_MAC_VER_08:
	case RTL_GIGA_MAC_VER_09:
3831
		rtl8102e_hw_phy_config(tp);
3832
		break;
3833
	case RTL_GIGA_MAC_VER_11:
3834
		rtl8168bb_hw_phy_config(tp);
3835 3836
		break;
	case RTL_GIGA_MAC_VER_12:
3837
		rtl8168bef_hw_phy_config(tp);
3838 3839
		break;
	case RTL_GIGA_MAC_VER_17:
3840
		rtl8168bef_hw_phy_config(tp);
3841
		break;
F
Francois Romieu 已提交
3842
	case RTL_GIGA_MAC_VER_18:
3843
		rtl8168cp_1_hw_phy_config(tp);
F
Francois Romieu 已提交
3844 3845
		break;
	case RTL_GIGA_MAC_VER_19:
3846
		rtl8168c_1_hw_phy_config(tp);
F
Francois Romieu 已提交
3847
		break;
3848
	case RTL_GIGA_MAC_VER_20:
3849
		rtl8168c_2_hw_phy_config(tp);
3850
		break;
F
Francois Romieu 已提交
3851
	case RTL_GIGA_MAC_VER_21:
3852
		rtl8168c_3_hw_phy_config(tp);
F
Francois Romieu 已提交
3853
		break;
3854
	case RTL_GIGA_MAC_VER_22:
3855
		rtl8168c_4_hw_phy_config(tp);
3856
		break;
F
Francois Romieu 已提交
3857
	case RTL_GIGA_MAC_VER_23:
3858
	case RTL_GIGA_MAC_VER_24:
3859
		rtl8168cp_2_hw_phy_config(tp);
F
Francois Romieu 已提交
3860
		break;
F
Francois Romieu 已提交
3861
	case RTL_GIGA_MAC_VER_25:
3862
		rtl8168d_1_hw_phy_config(tp);
3863 3864
		break;
	case RTL_GIGA_MAC_VER_26:
3865
		rtl8168d_2_hw_phy_config(tp);
3866 3867
		break;
	case RTL_GIGA_MAC_VER_27:
3868
		rtl8168d_3_hw_phy_config(tp);
F
Francois Romieu 已提交
3869
		break;
F
françois romieu 已提交
3870 3871 3872
	case RTL_GIGA_MAC_VER_28:
		rtl8168d_4_hw_phy_config(tp);
		break;
3873 3874 3875 3876
	case RTL_GIGA_MAC_VER_29:
	case RTL_GIGA_MAC_VER_30:
		rtl8105e_hw_phy_config(tp);
		break;
F
Francois Romieu 已提交
3877 3878 3879
	case RTL_GIGA_MAC_VER_31:
		/* None. */
		break;
H
hayeswang 已提交
3880 3881
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
H
Hayes Wang 已提交
3882 3883 3884 3885
		rtl8168e_1_hw_phy_config(tp);
		break;
	case RTL_GIGA_MAC_VER_34:
		rtl8168e_2_hw_phy_config(tp);
H
hayeswang 已提交
3886
		break;
3887 3888 3889 3890 3891 3892
	case RTL_GIGA_MAC_VER_35:
		rtl8168f_1_hw_phy_config(tp);
		break;
	case RTL_GIGA_MAC_VER_36:
		rtl8168f_2_hw_phy_config(tp);
		break;
F
Francois Romieu 已提交
3893

3894 3895 3896 3897
	case RTL_GIGA_MAC_VER_37:
		rtl8402_hw_phy_config(tp);
		break;

3898 3899 3900 3901
	case RTL_GIGA_MAC_VER_38:
		rtl8411_hw_phy_config(tp);
		break;

H
Hayes Wang 已提交
3902 3903 3904 3905
	case RTL_GIGA_MAC_VER_39:
		rtl8106e_hw_phy_config(tp);
		break;

H
Hayes Wang 已提交
3906 3907 3908
	case RTL_GIGA_MAC_VER_40:
		rtl8168g_1_hw_phy_config(tp);
		break;
H
hayeswang 已提交
3909
	case RTL_GIGA_MAC_VER_42:
H
hayeswang 已提交
3910
	case RTL_GIGA_MAC_VER_43:
H
hayeswang 已提交
3911
	case RTL_GIGA_MAC_VER_44:
H
hayeswang 已提交
3912 3913
		rtl8168g_2_hw_phy_config(tp);
		break;
3914 3915 3916 3917 3918 3919 3920 3921
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_47:
		rtl8168h_1_hw_phy_config(tp);
		break;
	case RTL_GIGA_MAC_VER_46:
	case RTL_GIGA_MAC_VER_48:
		rtl8168h_2_hw_phy_config(tp);
		break;
H
Hayes Wang 已提交
3922 3923

	case RTL_GIGA_MAC_VER_41:
3924 3925 3926 3927 3928
	default:
		break;
	}
}

3929
static void rtl_phy_work(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
3930 3931 3932 3933 3934
{
	struct timer_list *timer = &tp->timer;
	void __iomem *ioaddr = tp->mmio_addr;
	unsigned long timeout = RTL8169_PHY_TIMEOUT;

3935
	assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
L
Linus Torvalds 已提交
3936

3937
	if (tp->phy_reset_pending(tp)) {
3938
		/*
L
Linus Torvalds 已提交
3939 3940 3941 3942 3943 3944 3945 3946
		 * A busy loop could burn quite a few cycles on nowadays CPU.
		 * Let's delay the execution of the timer for a few ticks.
		 */
		timeout = HZ/10;
		goto out_mod_timer;
	}

	if (tp->link_ok(ioaddr))
3947
		return;
L
Linus Torvalds 已提交
3948

3949
	netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
L
Linus Torvalds 已提交
3950

3951
	tp->phy_reset_enable(tp);
L
Linus Torvalds 已提交
3952 3953 3954

out_mod_timer:
	mod_timer(timer, jiffies + timeout);
3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967
}

static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
{
	if (!test_and_set_bit(flag, tp->wk.flags))
		schedule_work(&tp->wk.work);
}

static void rtl8169_phy_timer(unsigned long __opaque)
{
	struct net_device *dev = (struct net_device *)__opaque;
	struct rtl8169_private *tp = netdev_priv(dev);

3968
	rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
L
Linus Torvalds 已提交
3969 3970 3971 3972 3973 3974 3975
}

static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
				  void __iomem *ioaddr)
{
	iounmap(ioaddr);
	pci_release_regions(pdev);
3976
	pci_clear_mwi(pdev);
L
Linus Torvalds 已提交
3977 3978 3979 3980
	pci_disable_device(pdev);
	free_netdev(dev);
}

3981 3982 3983 3984 3985
DECLARE_RTL_COND(rtl_phy_reset_cond)
{
	return tp->phy_reset_pending(tp);
}

3986 3987 3988
static void rtl8169_phy_reset(struct net_device *dev,
			      struct rtl8169_private *tp)
{
3989
	tp->phy_reset_enable(tp);
3990
	rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
3991 3992
}

3993 3994 3995 3996 3997 3998 3999 4000
static bool rtl_tbi_enabled(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
	    (RTL_R8(PHYstatus) & TBI_Enable);
}

4001 4002 4003 4004
static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

4005
	rtl_hw_phy_config(dev);
4006

4007 4008 4009 4010
	if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
		dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
		RTL_W8(0x82, 0x01);
	}
4011

4012 4013 4014 4015
	pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);

	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
		pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4016

4017
	if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4018 4019 4020
		dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
		RTL_W8(0x82, 0x01);
		dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4021
		rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4022 4023
	}

4024 4025
	rtl8169_phy_reset(dev, tp);

4026
	rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
F
Francois Romieu 已提交
4027 4028 4029 4030 4031
			  ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
			  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
			  (tp->mii.supports_gmii ?
			   ADVERTISED_1000baseT_Half |
			   ADVERTISED_1000baseT_Full : 0));
4032

4033
	if (rtl_tbi_enabled(tp))
4034
		netif_info(tp, link, dev, "TBI auto-negotiating\n");
4035 4036
}

4037 4038 4039 4040
static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
{
	void __iomem *ioaddr = tp->mmio_addr;

4041
	rtl_lock_work(tp);
4042 4043

	RTL_W8(Cfg9346, Cfg9346_Unlock);
4044

4045
	RTL_W32(MAC4, addr[4] | addr[5] << 8);
4046 4047
	RTL_R32(MAC4);

4048
	RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4049 4050
	RTL_R32(MAC0);

4051 4052
	if (tp->mac_version == RTL_GIGA_MAC_VER_34)
		rtl_rar_exgmac_set(tp, addr);
4053

4054 4055
	RTL_W8(Cfg9346, Cfg9346_Lock);

4056
	rtl_unlock_work(tp);
4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073
}

static int rtl_set_mac_address(struct net_device *dev, void *p)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct sockaddr *addr = p;

	if (!is_valid_ether_addr(addr->sa_data))
		return -EADDRNOTAVAIL;

	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);

	rtl_rar_set(tp, dev->dev_addr);

	return 0;
}

4074 4075 4076 4077 4078
static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct mii_ioctl_data *data = if_mii(ifr);

F
Francois Romieu 已提交
4079 4080
	return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
}
4081

F
Francois Romieu 已提交
4082 4083
static int rtl_xmii_ioctl(struct rtl8169_private *tp,
			  struct mii_ioctl_data *data, int cmd)
F
Francois Romieu 已提交
4084
{
4085 4086 4087 4088 4089 4090
	switch (cmd) {
	case SIOCGMIIPHY:
		data->phy_id = 32; /* Internal PHY */
		return 0;

	case SIOCGMIIREG:
4091
		data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4092 4093 4094
		return 0;

	case SIOCSMIIREG:
4095
		rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4096 4097 4098 4099 4100
		return 0;
	}
	return -EOPNOTSUPP;
}

F
Francois Romieu 已提交
4101 4102 4103 4104 4105
static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
{
	return -EOPNOTSUPP;
}

F
Francois Romieu 已提交
4106 4107 4108 4109 4110 4111 4112 4113
static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
{
	if (tp->features & RTL_FEATURE_MSI) {
		pci_disable_msi(pdev);
		tp->features &= ~RTL_FEATURE_MSI;
	}
}

B
Bill Pemberton 已提交
4114
static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4115 4116 4117 4118 4119 4120 4121 4122
{
	struct mdio_ops *ops = &tp->mdio_ops;

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_27:
		ops->write	= r8168dp_1_mdio_write;
		ops->read	= r8168dp_1_mdio_read;
		break;
F
françois romieu 已提交
4123
	case RTL_GIGA_MAC_VER_28:
4124
	case RTL_GIGA_MAC_VER_31:
F
françois romieu 已提交
4125 4126 4127
		ops->write	= r8168dp_2_mdio_write;
		ops->read	= r8168dp_2_mdio_read;
		break;
H
Hayes Wang 已提交
4128 4129
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
H
hayeswang 已提交
4130
	case RTL_GIGA_MAC_VER_42:
H
hayeswang 已提交
4131
	case RTL_GIGA_MAC_VER_43:
H
hayeswang 已提交
4132
	case RTL_GIGA_MAC_VER_44:
4133 4134 4135 4136
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
H
Hayes Wang 已提交
4137 4138 4139
		ops->write	= r8168g_mdio_write;
		ops->read	= r8168g_mdio_read;
		break;
4140 4141 4142 4143 4144 4145 4146
	default:
		ops->write	= r8169_mdio_write;
		ops->read	= r8169_mdio_read;
		break;
	}
}

H
hayeswang 已提交
4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170
static void rtl_speed_down(struct rtl8169_private *tp)
{
	u32 adv;
	int lpa;

	rtl_writephy(tp, 0x1f, 0x0000);
	lpa = rtl_readphy(tp, MII_LPA);

	if (lpa & (LPA_10HALF | LPA_10FULL))
		adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
	else if (lpa & (LPA_100HALF | LPA_100FULL))
		adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
		      ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
	else
		adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
		      ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
		      (tp->mii.supports_gmii ?
		       ADVERTISED_1000baseT_Half |
		       ADVERTISED_1000baseT_Full : 0);

	rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
			  adv);
}

4171 4172 4173 4174 4175
static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	switch (tp->mac_version) {
4176 4177
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
4178 4179 4180 4181 4182
	case RTL_GIGA_MAC_VER_29:
	case RTL_GIGA_MAC_VER_30:
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
	case RTL_GIGA_MAC_VER_34:
4183
	case RTL_GIGA_MAC_VER_37:
4184
	case RTL_GIGA_MAC_VER_38:
H
Hayes Wang 已提交
4185
	case RTL_GIGA_MAC_VER_39:
H
Hayes Wang 已提交
4186 4187
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
H
hayeswang 已提交
4188
	case RTL_GIGA_MAC_VER_42:
H
hayeswang 已提交
4189
	case RTL_GIGA_MAC_VER_43:
H
hayeswang 已提交
4190
	case RTL_GIGA_MAC_VER_44:
4191 4192 4193 4194
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207
		RTL_W32(RxConfig, RTL_R32(RxConfig) |
			AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
		break;
	default:
		break;
	}
}

static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
{
	if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
		return false;

H
hayeswang 已提交
4208
	rtl_speed_down(tp);
4209 4210 4211 4212 4213
	rtl_wol_suspend_quirk(tp);

	return true;
}

F
françois romieu 已提交
4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227
static void r810x_phy_power_down(struct rtl8169_private *tp)
{
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
}

static void r810x_phy_power_up(struct rtl8169_private *tp)
{
	rtl_writephy(tp, 0x1f, 0x0000);
	rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
}

static void r810x_pll_power_down(struct rtl8169_private *tp)
{
H
Hayes Wang 已提交
4228 4229
	void __iomem *ioaddr = tp->mmio_addr;

4230
	if (rtl_wol_pll_power_down(tp))
F
françois romieu 已提交
4231 4232 4233
		return;

	r810x_phy_power_down(tp);
H
Hayes Wang 已提交
4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_07:
	case RTL_GIGA_MAC_VER_08:
	case RTL_GIGA_MAC_VER_09:
	case RTL_GIGA_MAC_VER_10:
	case RTL_GIGA_MAC_VER_13:
	case RTL_GIGA_MAC_VER_16:
		break;
	default:
		RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
		break;
	}
F
françois romieu 已提交
4247 4248 4249 4250
}

static void r810x_pll_power_up(struct rtl8169_private *tp)
{
H
Hayes Wang 已提交
4251 4252
	void __iomem *ioaddr = tp->mmio_addr;

F
françois romieu 已提交
4253
	r810x_phy_power_up(tp);
H
Hayes Wang 已提交
4254 4255 4256 4257 4258 4259 4260 4261 4262

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_07:
	case RTL_GIGA_MAC_VER_08:
	case RTL_GIGA_MAC_VER_09:
	case RTL_GIGA_MAC_VER_10:
	case RTL_GIGA_MAC_VER_13:
	case RTL_GIGA_MAC_VER_16:
		break;
4263 4264 4265 4266
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
		RTL_W8(PMCH, RTL_R8(PMCH) | 0xC0);
		break;
H
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4267 4268 4269 4270
	default:
		RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
		break;
	}
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4271 4272 4273 4274 4275
}

static void r8168_phy_power_up(struct rtl8169_private *tp)
{
	rtl_writephy(tp, 0x1f, 0x0000);
H
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4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_11:
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
	case RTL_GIGA_MAC_VER_18:
	case RTL_GIGA_MAC_VER_19:
	case RTL_GIGA_MAC_VER_20:
	case RTL_GIGA_MAC_VER_21:
	case RTL_GIGA_MAC_VER_22:
	case RTL_GIGA_MAC_VER_23:
	case RTL_GIGA_MAC_VER_24:
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
	case RTL_GIGA_MAC_VER_27:
	case RTL_GIGA_MAC_VER_28:
	case RTL_GIGA_MAC_VER_31:
		rtl_writephy(tp, 0x0e, 0x0000);
		break;
	default:
		break;
	}
F
françois romieu 已提交
4297 4298 4299 4300 4301 4302
	rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
}

static void r8168_phy_power_down(struct rtl8169_private *tp)
{
	rtl_writephy(tp, 0x1f, 0x0000);
H
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4303 4304 4305
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
4306 4307
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
H
hayeswang 已提交
4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330
		rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
		break;

	case RTL_GIGA_MAC_VER_11:
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
	case RTL_GIGA_MAC_VER_18:
	case RTL_GIGA_MAC_VER_19:
	case RTL_GIGA_MAC_VER_20:
	case RTL_GIGA_MAC_VER_21:
	case RTL_GIGA_MAC_VER_22:
	case RTL_GIGA_MAC_VER_23:
	case RTL_GIGA_MAC_VER_24:
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
	case RTL_GIGA_MAC_VER_27:
	case RTL_GIGA_MAC_VER_28:
	case RTL_GIGA_MAC_VER_31:
		rtl_writephy(tp, 0x0e, 0x0200);
	default:
		rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
		break;
	}
F
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4331 4332 4333 4334 4335 4336
}

static void r8168_pll_power_down(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

F
Francois Romieu 已提交
4337 4338 4339
	if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
	     tp->mac_version == RTL_GIGA_MAC_VER_28 ||
	     tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4340
	    r8168dp_check_dash(tp)) {
F
françois romieu 已提交
4341
		return;
4342
	}
F
françois romieu 已提交
4343

F
Francois Romieu 已提交
4344 4345
	if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
	     tp->mac_version == RTL_GIGA_MAC_VER_24) &&
F
françois romieu 已提交
4346 4347 4348 4349
	    (RTL_R16(CPlusCmd) & ASF)) {
		return;
	}

H
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4350 4351
	if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_33)
4352
		rtl_ephy_write(tp, 0x19, 0xff64);
H
hayeswang 已提交
4353

4354
	if (rtl_wol_pll_power_down(tp))
F
françois romieu 已提交
4355 4356 4357 4358 4359 4360 4361
		return;

	r8168_phy_power_down(tp);

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
4362 4363
	case RTL_GIGA_MAC_VER_27:
	case RTL_GIGA_MAC_VER_28:
4364
	case RTL_GIGA_MAC_VER_31:
H
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4365 4366
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
4367 4368
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
F
françois romieu 已提交
4369 4370
		RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
		break;
4371 4372 4373 4374 4375
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
		rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
			     0xfc000000, ERIAR_EXGMAC);
		break;
F
françois romieu 已提交
4376 4377 4378 4379 4380 4381 4382 4383 4384 4385
	}
}

static void r8168_pll_power_up(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
4386 4387
	case RTL_GIGA_MAC_VER_27:
	case RTL_GIGA_MAC_VER_28:
4388
	case RTL_GIGA_MAC_VER_31:
H
hayeswang 已提交
4389 4390
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
F
françois romieu 已提交
4391 4392
		RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
		break;
4393 4394 4395 4396
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
		RTL_W8(PMCH, RTL_R8(PMCH) | 0xC0);
		break;
4397 4398 4399 4400 4401
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
		rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
			     0x00000000, ERIAR_EXGMAC);
		break;
F
françois romieu 已提交
4402 4403 4404 4405 4406
	}

	r8168_phy_power_up(tp);
}

F
Francois Romieu 已提交
4407 4408
static void rtl_generic_op(struct rtl8169_private *tp,
			   void (*op)(struct rtl8169_private *))
F
françois romieu 已提交
4409 4410 4411 4412 4413 4414 4415
{
	if (op)
		op(tp);
}

static void rtl_pll_power_down(struct rtl8169_private *tp)
{
F
Francois Romieu 已提交
4416
	rtl_generic_op(tp, tp->pll_power_ops.down);
F
françois romieu 已提交
4417 4418 4419 4420
}

static void rtl_pll_power_up(struct rtl8169_private *tp)
{
F
Francois Romieu 已提交
4421
	rtl_generic_op(tp, tp->pll_power_ops.up);
F
françois romieu 已提交
4422 4423
}

B
Bill Pemberton 已提交
4424
static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
F
françois romieu 已提交
4425 4426 4427 4428 4429 4430 4431 4432 4433
{
	struct pll_power_ops *ops = &tp->pll_power_ops;

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_07:
	case RTL_GIGA_MAC_VER_08:
	case RTL_GIGA_MAC_VER_09:
	case RTL_GIGA_MAC_VER_10:
	case RTL_GIGA_MAC_VER_16:
4434 4435
	case RTL_GIGA_MAC_VER_29:
	case RTL_GIGA_MAC_VER_30:
4436
	case RTL_GIGA_MAC_VER_37:
H
Hayes Wang 已提交
4437
	case RTL_GIGA_MAC_VER_39:
H
hayeswang 已提交
4438
	case RTL_GIGA_MAC_VER_43:
4439 4440
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
F
françois romieu 已提交
4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454 4455 4456 4457
		ops->down	= r810x_pll_power_down;
		ops->up		= r810x_pll_power_up;
		break;

	case RTL_GIGA_MAC_VER_11:
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
	case RTL_GIGA_MAC_VER_18:
	case RTL_GIGA_MAC_VER_19:
	case RTL_GIGA_MAC_VER_20:
	case RTL_GIGA_MAC_VER_21:
	case RTL_GIGA_MAC_VER_22:
	case RTL_GIGA_MAC_VER_23:
	case RTL_GIGA_MAC_VER_24:
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
	case RTL_GIGA_MAC_VER_27:
F
françois romieu 已提交
4458
	case RTL_GIGA_MAC_VER_28:
4459
	case RTL_GIGA_MAC_VER_31:
H
hayeswang 已提交
4460 4461
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
H
Hayes Wang 已提交
4462
	case RTL_GIGA_MAC_VER_34:
4463 4464
	case RTL_GIGA_MAC_VER_35:
	case RTL_GIGA_MAC_VER_36:
4465
	case RTL_GIGA_MAC_VER_38:
H
Hayes Wang 已提交
4466 4467
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
H
hayeswang 已提交
4468
	case RTL_GIGA_MAC_VER_42:
H
hayeswang 已提交
4469
	case RTL_GIGA_MAC_VER_44:
4470 4471
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
F
françois romieu 已提交
4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482
		ops->down	= r8168_pll_power_down;
		ops->up		= r8168_pll_power_up;
		break;

	default:
		ops->down	= NULL;
		ops->up		= NULL;
		break;
	}
}

4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509 4510
static void rtl_init_rxcfg(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_01:
	case RTL_GIGA_MAC_VER_02:
	case RTL_GIGA_MAC_VER_03:
	case RTL_GIGA_MAC_VER_04:
	case RTL_GIGA_MAC_VER_05:
	case RTL_GIGA_MAC_VER_06:
	case RTL_GIGA_MAC_VER_10:
	case RTL_GIGA_MAC_VER_11:
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_13:
	case RTL_GIGA_MAC_VER_14:
	case RTL_GIGA_MAC_VER_15:
	case RTL_GIGA_MAC_VER_16:
	case RTL_GIGA_MAC_VER_17:
		RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
		break;
	case RTL_GIGA_MAC_VER_18:
	case RTL_GIGA_MAC_VER_19:
	case RTL_GIGA_MAC_VER_20:
	case RTL_GIGA_MAC_VER_21:
	case RTL_GIGA_MAC_VER_22:
	case RTL_GIGA_MAC_VER_23:
	case RTL_GIGA_MAC_VER_24:
4511
	case RTL_GIGA_MAC_VER_34:
4512
	case RTL_GIGA_MAC_VER_35:
4513 4514
		RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
		break;
4515
	case RTL_GIGA_MAC_VER_40:
4516 4517
		RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
		break;
4518
	case RTL_GIGA_MAC_VER_41:
H
hayeswang 已提交
4519
	case RTL_GIGA_MAC_VER_42:
H
hayeswang 已提交
4520
	case RTL_GIGA_MAC_VER_43:
H
hayeswang 已提交
4521
	case RTL_GIGA_MAC_VER_44:
4522 4523 4524 4525
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
4526 4527
		RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
		break;
4528 4529 4530 4531 4532 4533
	default:
		RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
		break;
	}
}

4534 4535
static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
{
4536
	tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4537 4538
}

F
Francois Romieu 已提交
4539 4540
static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
{
4541 4542 4543
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Cfg9346, Cfg9346_Unlock);
F
Francois Romieu 已提交
4544
	rtl_generic_op(tp, tp->jumbo_ops.enable);
4545
	RTL_W8(Cfg9346, Cfg9346_Lock);
F
Francois Romieu 已提交
4546 4547 4548 4549
}

static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
{
4550 4551 4552
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Cfg9346, Cfg9346_Unlock);
F
Francois Romieu 已提交
4553
	rtl_generic_op(tp, tp->jumbo_ops.disable);
4554
	RTL_W8(Cfg9346, Cfg9346_Lock);
F
Francois Romieu 已提交
4555 4556 4557 4558 4559 4560 4561 4562 4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594 4595
}

static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
	RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
	rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
}

static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
	RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
	rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
}

static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
}

static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
}

static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(MaxTxPacketSize, 0x3f);
	RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
	RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4596
	rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
F
Francois Romieu 已提交
4597 4598 4599 4600 4601 4602 4603 4604 4605
}

static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(MaxTxPacketSize, 0x0c);
	RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
	RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4606
	rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
F
Francois Romieu 已提交
4607 4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638
}

static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
{
	rtl_tx_performance_tweak(tp->pci_dev,
		(0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
}

static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
{
	rtl_tx_performance_tweak(tp->pci_dev,
		(0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
}

static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	r8168b_0_hw_jumbo_enable(tp);

	RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
}

static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	r8168b_0_hw_jumbo_disable(tp);

	RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
}

B
Bill Pemberton 已提交
4639
static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
F
Francois Romieu 已提交
4640 4641 4642 4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 4668 4669 4670 4671 4672 4673 4674 4675 4676 4677 4678 4679 4680 4681
{
	struct jumbo_ops *ops = &tp->jumbo_ops;

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_11:
		ops->disable	= r8168b_0_hw_jumbo_disable;
		ops->enable	= r8168b_0_hw_jumbo_enable;
		break;
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
		ops->disable	= r8168b_1_hw_jumbo_disable;
		ops->enable	= r8168b_1_hw_jumbo_enable;
		break;
	case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
	case RTL_GIGA_MAC_VER_19:
	case RTL_GIGA_MAC_VER_20:
	case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
	case RTL_GIGA_MAC_VER_22:
	case RTL_GIGA_MAC_VER_23:
	case RTL_GIGA_MAC_VER_24:
	case RTL_GIGA_MAC_VER_25:
	case RTL_GIGA_MAC_VER_26:
		ops->disable	= r8168c_hw_jumbo_disable;
		ops->enable	= r8168c_hw_jumbo_enable;
		break;
	case RTL_GIGA_MAC_VER_27:
	case RTL_GIGA_MAC_VER_28:
		ops->disable	= r8168dp_hw_jumbo_disable;
		ops->enable	= r8168dp_hw_jumbo_enable;
		break;
	case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
	case RTL_GIGA_MAC_VER_34:
		ops->disable	= r8168e_hw_jumbo_disable;
		ops->enable	= r8168e_hw_jumbo_enable;
		break;

	/*
	 * No action needed for jumbo frames with 8169.
	 * No jumbo for 810x at all.
	 */
H
Hayes Wang 已提交
4682 4683
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
H
hayeswang 已提交
4684
	case RTL_GIGA_MAC_VER_42:
H
hayeswang 已提交
4685
	case RTL_GIGA_MAC_VER_43:
H
hayeswang 已提交
4686
	case RTL_GIGA_MAC_VER_44:
4687 4688 4689 4690
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
F
Francois Romieu 已提交
4691 4692 4693 4694 4695 4696 4697
	default:
		ops->disable	= NULL;
		ops->enable	= NULL;
		break;
	}
}

4698 4699 4700 4701 4702 4703 4704
DECLARE_RTL_COND(rtl_chipcmd_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R8(ChipCmd) & CmdReset;
}

4705 4706 4707 4708 4709 4710
static void rtl_hw_reset(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(ChipCmd, CmdReset);

4711
	rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4712 4713
}

4714
static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4715
{
4716 4717 4718
	struct rtl_fw *rtl_fw;
	const char *name;
	int rc = -ENOMEM;
4719

4720 4721 4722
	name = rtl_lookup_firmware_name(tp);
	if (!name)
		goto out_no_firmware;
4723

4724 4725 4726
	rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
	if (!rtl_fw)
		goto err_warn;
4727

4728 4729 4730 4731
	rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
	if (rc < 0)
		goto err_free;

4732 4733 4734 4735
	rc = rtl_check_firmware(tp, rtl_fw);
	if (rc < 0)
		goto err_release_firmware;

4736 4737 4738 4739
	tp->rtl_fw = rtl_fw;
out:
	return;

4740 4741
err_release_firmware:
	release_firmware(rtl_fw->fw);
4742 4743 4744 4745 4746 4747 4748 4749 4750 4751 4752 4753 4754 4755
err_free:
	kfree(rtl_fw);
err_warn:
	netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
		   name, rc);
out_no_firmware:
	tp->rtl_fw = NULL;
	goto out;
}

static void rtl_request_firmware(struct rtl8169_private *tp)
{
	if (IS_ERR(tp->rtl_fw))
		rtl_request_uncached_firmware(tp);
4756 4757
}

4758 4759 4760 4761
static void rtl_rx_close(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

4762
	RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4763 4764
}

4765 4766 4767 4768 4769 4770 4771 4772 4773 4774 4775 4776 4777 4778
DECLARE_RTL_COND(rtl_npq_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R8(TxPoll) & NPQ;
}

DECLARE_RTL_COND(rtl_txcfg_empty_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R32(TxConfig) & TXCFG_EMPTY;
}

F
françois romieu 已提交
4779
static void rtl8169_hw_reset(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
4780
{
F
françois romieu 已提交
4781 4782
	void __iomem *ioaddr = tp->mmio_addr;

L
Linus Torvalds 已提交
4783
	/* Disable interrupts */
F
françois romieu 已提交
4784
	rtl8169_irq_mask_and_ack(tp);
L
Linus Torvalds 已提交
4785

4786 4787
	rtl_rx_close(tp);

4788
	if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4789 4790
	    tp->mac_version == RTL_GIGA_MAC_VER_28 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_31) {
4791
		rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4792
	} else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4793 4794 4795 4796 4797 4798 4799 4800 4801 4802 4803 4804 4805
		   tp->mac_version == RTL_GIGA_MAC_VER_35 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_36 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_37 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_38 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_40 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_41 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_42 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_43 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_44 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_45 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_46 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_47 ||
		   tp->mac_version == RTL_GIGA_MAC_VER_48) {
4806
		RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4807
		rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4808 4809 4810
	} else {
		RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
		udelay(100);
F
françois romieu 已提交
4811 4812
	}

4813
	rtl_hw_reset(tp);
L
Linus Torvalds 已提交
4814 4815
}

4816
static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4817 4818 4819 4820 4821 4822 4823 4824
{
	void __iomem *ioaddr = tp->mmio_addr;

	/* Set DMA burst size and Interframe Gap Time */
	RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
		(InterFrameGap << TxInterFrameGapShift));
}

4825
static void rtl_hw_start(struct net_device *dev)
L
Linus Torvalds 已提交
4826 4827 4828
{
	struct rtl8169_private *tp = netdev_priv(dev);

4829 4830
	tp->hw_start(dev);

4831
	rtl_irq_enable_all(tp);
4832 4833
}

4834 4835 4836 4837 4838 4839 4840 4841 4842
static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
					 void __iomem *ioaddr)
{
	/*
	 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
	 * register to be written before TxDescAddrLow to work.
	 * Switching from MMIO to I/O access fixes the issue as well.
	 */
	RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4843
	RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4844
	RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4845
	RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4846 4847 4848 4849 4850 4851 4852 4853 4854 4855 4856
}

static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
{
	u16 cmd;

	cmd = RTL_R16(CPlusCmd);
	RTL_W16(CPlusCmd, cmd);
	return cmd;
}

4857
static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4858 4859
{
	/* Low hurts. Let's disable the filtering. */
4860
	RTL_W16(RxMaxSize, rx_buf_sz + 1);
4861 4862
}

4863 4864
static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
{
4865
	static const struct rtl_cfg2_info {
4866 4867 4868 4869 4870 4871 4872 4873
		u32 mac_version;
		u32 clk;
		u32 val;
	} cfg2_info [] = {
		{ RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
		{ RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
		{ RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
		{ RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4874 4875
	};
	const struct rtl_cfg2_info *p = cfg2_info;
4876 4877 4878 4879
	unsigned int i;
	u32 clk;

	clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4880
	for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4881 4882 4883 4884 4885 4886 4887
		if ((p->mac_version == mac_version) && (p->clk == clk)) {
			RTL_W32(0x7c, p->val);
			break;
		}
	}
}

4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918 4919 4920 4921 4922 4923 4924 4925 4926 4927 4928 4929 4930 4931
static void rtl_set_rx_mode(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	u32 mc_filter[2];	/* Multicast hash filter */
	int rx_mode;
	u32 tmp = 0;

	if (dev->flags & IFF_PROMISC) {
		/* Unconditionally log net taps. */
		netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
		rx_mode =
		    AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
		    AcceptAllPhys;
		mc_filter[1] = mc_filter[0] = 0xffffffff;
	} else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
		   (dev->flags & IFF_ALLMULTI)) {
		/* Too many to filter perfectly -- accept all multicasts. */
		rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
		mc_filter[1] = mc_filter[0] = 0xffffffff;
	} else {
		struct netdev_hw_addr *ha;

		rx_mode = AcceptBroadcast | AcceptMyPhys;
		mc_filter[1] = mc_filter[0] = 0;
		netdev_for_each_mc_addr(ha, dev) {
			int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
			rx_mode |= AcceptMulticast;
		}
	}

	if (dev->features & NETIF_F_RXALL)
		rx_mode |= (AcceptErr | AcceptRunt);

	tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;

	if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
		u32 data = mc_filter[0];

		mc_filter[0] = swab32(mc_filter[1]);
		mc_filter[1] = swab32(data);
	}

4932 4933 4934
	if (tp->mac_version == RTL_GIGA_MAC_VER_35)
		mc_filter[1] = mc_filter[0] = 0xffffffff;

4935 4936 4937 4938 4939 4940
	RTL_W32(MAR0 + 4, mc_filter[1]);
	RTL_W32(MAR0 + 0, mc_filter[0]);

	RTL_W32(RxConfig, tmp);
}

4941 4942 4943 4944 4945 4946
static void rtl_hw_start_8169(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

4947 4948 4949 4950 4951
	if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
		RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
	}

L
Linus Torvalds 已提交
4952
	RTL_W8(Cfg9346, Cfg9346_Unlock);
F
Francois Romieu 已提交
4953 4954 4955 4956
	if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_02 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_03 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_04)
4957 4958
		RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);

4959 4960
	rtl_init_rxcfg(tp);

4961
	RTL_W8(EarlyTxThres, NoEarlyTx);
L
Linus Torvalds 已提交
4962

E
Eric Dumazet 已提交
4963
	rtl_set_rx_max_size(ioaddr, rx_buf_sz);
L
Linus Torvalds 已提交
4964

F
Francois Romieu 已提交
4965 4966 4967 4968
	if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_02 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_03 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_04)
4969
		rtl_set_rx_tx_config_registers(tp);
L
Linus Torvalds 已提交
4970

4971
	tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
L
Linus Torvalds 已提交
4972

F
Francois Romieu 已提交
4973 4974
	if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_03) {
4975
		dprintk("Set MAC Reg C+CR Offset 0xE0. "
L
Linus Torvalds 已提交
4976
			"Bit-3 and bit-14 MUST be 1\n");
4977
		tp->cp_cmd |= (1 << 14);
L
Linus Torvalds 已提交
4978 4979
	}

4980 4981
	RTL_W16(CPlusCmd, tp->cp_cmd);

4982 4983
	rtl8169_set_magic_reg(ioaddr, tp->mac_version);

L
Linus Torvalds 已提交
4984 4985 4986 4987 4988 4989
	/*
	 * Undocumented corner. Supposedly:
	 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
	 */
	RTL_W16(IntrMitigate, 0x0000);

4990
	rtl_set_rx_tx_desc_registers(tp, ioaddr);
4991

F
Francois Romieu 已提交
4992 4993 4994 4995
	if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
	    tp->mac_version != RTL_GIGA_MAC_VER_02 &&
	    tp->mac_version != RTL_GIGA_MAC_VER_03 &&
	    tp->mac_version != RTL_GIGA_MAC_VER_04) {
4996 4997 4998 4999
		RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
		rtl_set_rx_tx_config_registers(tp);
	}

L
Linus Torvalds 已提交
5000
	RTL_W8(Cfg9346, Cfg9346_Lock);
F
Francois Romieu 已提交
5001 5002 5003

	/* Initially a 10 us delay. Turned it into a PCI commit. - FR */
	RTL_R8(IntrMask);
L
Linus Torvalds 已提交
5004 5005 5006

	RTL_W32(RxMissed, 0);

5007
	rtl_set_rx_mode(dev);
L
Linus Torvalds 已提交
5008 5009 5010

	/* no early-rx interrupts */
	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5011
}
L
Linus Torvalds 已提交
5012

5013 5014 5015
static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
{
	if (tp->csi_ops.write)
5016
		tp->csi_ops.write(tp, addr, value);
5017 5018 5019 5020
}

static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
{
5021
	return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5022 5023 5024
}

static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5025 5026 5027
{
	u32 csi;

5028 5029 5030 5031 5032 5033 5034
	csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
	rtl_csi_write(tp, 0x070c, csi | bits);
}

static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
{
	rtl_csi_access_enable(tp, 0x17000000);
5035 5036
}

5037
static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
F
françois romieu 已提交
5038
{
5039
	rtl_csi_access_enable(tp, 0x27000000);
F
françois romieu 已提交
5040 5041
}

5042 5043 5044 5045 5046 5047 5048
DECLARE_RTL_COND(rtl_csiar_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R32(CSIAR) & CSIAR_FLAG;
}

5049
static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5050
{
5051
	void __iomem *ioaddr = tp->mmio_addr;
5052 5053 5054 5055 5056

	RTL_W32(CSIDR, value);
	RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);

5057
	rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5058 5059
}

5060
static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5061
{
5062
	void __iomem *ioaddr = tp->mmio_addr;
5063 5064 5065 5066

	RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);

5067 5068
	return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
		RTL_R32(CSIDR) : ~0;
5069 5070
}

5071
static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5072
{
5073
	void __iomem *ioaddr = tp->mmio_addr;
5074 5075 5076 5077 5078 5079

	RTL_W32(CSIDR, value);
	RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
		CSIAR_FUNC_NIC);

5080
	rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5081 5082
}

5083
static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5084
{
5085
	void __iomem *ioaddr = tp->mmio_addr;
5086 5087 5088 5089

	RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);

5090 5091
	return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
		RTL_R32(CSIDR) : ~0;
5092 5093
}

H
hayeswang 已提交
5094 5095 5096 5097 5098 5099 5100 5101 5102 5103 5104 5105 5106 5107 5108 5109 5110 5111 5112 5113 5114 5115 5116
static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W32(CSIDR, value);
	RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
		CSIAR_FUNC_NIC2);

	rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
}

static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
{
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);

	return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
		RTL_R32(CSIDR) : ~0;
}

B
Bill Pemberton 已提交
5117
static void rtl_init_csi_ops(struct rtl8169_private *tp)
5118 5119 5120 5121 5122 5123 5124 5125 5126 5127 5128 5129 5130 5131 5132 5133 5134 5135 5136 5137 5138 5139
{
	struct csi_ops *ops = &tp->csi_ops;

	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_01:
	case RTL_GIGA_MAC_VER_02:
	case RTL_GIGA_MAC_VER_03:
	case RTL_GIGA_MAC_VER_04:
	case RTL_GIGA_MAC_VER_05:
	case RTL_GIGA_MAC_VER_06:
	case RTL_GIGA_MAC_VER_10:
	case RTL_GIGA_MAC_VER_11:
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_13:
	case RTL_GIGA_MAC_VER_14:
	case RTL_GIGA_MAC_VER_15:
	case RTL_GIGA_MAC_VER_16:
	case RTL_GIGA_MAC_VER_17:
		ops->write	= NULL;
		ops->read	= NULL;
		break;

5140
	case RTL_GIGA_MAC_VER_37:
5141
	case RTL_GIGA_MAC_VER_38:
5142 5143 5144 5145
		ops->write	= r8402_csi_write;
		ops->read	= r8402_csi_read;
		break;

H
hayeswang 已提交
5146 5147 5148 5149 5150
	case RTL_GIGA_MAC_VER_44:
		ops->write	= r8411_csi_write;
		ops->read	= r8411_csi_read;
		break;

5151 5152 5153 5154 5155
	default:
		ops->write	= r8169_csi_write;
		ops->read	= r8169_csi_read;
		break;
	}
5156 5157 5158 5159 5160 5161 5162 5163
}

struct ephy_info {
	unsigned int offset;
	u16 mask;
	u16 bits;
};

5164 5165
static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
			  int len)
5166 5167 5168 5169
{
	u16 w;

	while (len-- > 0) {
5170 5171
		w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
		rtl_ephy_write(tp, e->offset, w);
5172 5173 5174 5175
		e++;
	}
}

5176 5177
static void rtl_disable_clock_request(struct pci_dev *pdev)
{
5178 5179
	pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
				   PCI_EXP_LNKCTL_CLKREQ_EN);
5180 5181
}

F
françois romieu 已提交
5182 5183
static void rtl_enable_clock_request(struct pci_dev *pdev)
{
5184 5185
	pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
				 PCI_EXP_LNKCTL_CLKREQ_EN);
F
françois romieu 已提交
5186 5187
}

H
hayeswang 已提交
5188 5189 5190 5191 5192 5193 5194 5195 5196 5197 5198 5199 5200 5201 5202
static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
{
	void __iomem *ioaddr = tp->mmio_addr;
	u8 data;

	data = RTL_R8(Config3);

	if (enable)
		data |= Rdy_to_L23;
	else
		data &= ~Rdy_to_L23;

	RTL_W8(Config3, data);
}

5203 5204 5205 5206 5207 5208 5209 5210 5211 5212 5213
#define R8168_CPCMD_QUIRK_MASK (\
	EnableBist | \
	Mac_dbgo_oe | \
	Force_half_dup | \
	Force_rxflow_en | \
	Force_txflow_en | \
	Cxpl_dbg_sel | \
	ASF | \
	PktCntrDisable | \
	Mac_dbgo_sel)

5214
static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5215
{
5216 5217 5218
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

5219 5220 5221 5222
	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);

5223 5224 5225 5226
	if (tp->dev->mtu <= ETH_DATA_LEN) {
		rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
					 PCI_EXP_DEVCTL_NOSNOOP_EN);
	}
5227 5228
}

5229
static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5230
{
5231 5232 5233
	void __iomem *ioaddr = tp->mmio_addr;

	rtl_hw_start_8168bb(tp);
5234

5235
	RTL_W8(MaxTxPacketSize, TxPacketMax);
5236 5237

	RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5238 5239
}

5240
static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5241
{
5242 5243 5244
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

5245 5246 5247 5248
	RTL_W8(Config1, RTL_R8(Config1) | Speed_down);

	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

5249 5250
	if (tp->dev->mtu <= ETH_DATA_LEN)
		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5251 5252 5253 5254

	rtl_disable_clock_request(pdev);

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5255 5256
}

5257
static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5258
{
5259
	static const struct ephy_info e_info_8168cp[] = {
5260 5261 5262 5263 5264 5265 5266
		{ 0x01, 0,	0x0001 },
		{ 0x02, 0x0800,	0x1000 },
		{ 0x03, 0,	0x0042 },
		{ 0x06, 0x0080,	0x0000 },
		{ 0x07, 0,	0x2000 }
	};

5267
	rtl_csi_access_enable_2(tp);
5268

5269
	rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5270

5271
	__rtl_hw_start_8168cp(tp);
5272 5273
}

5274
static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
F
Francois Romieu 已提交
5275
{
5276 5277 5278 5279
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

	rtl_csi_access_enable_2(tp);
F
Francois Romieu 已提交
5280 5281 5282

	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

5283 5284
	if (tp->dev->mtu <= ETH_DATA_LEN)
		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
F
Francois Romieu 已提交
5285 5286 5287 5288

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
}

5289
static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5290
{
5291 5292 5293 5294
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

	rtl_csi_access_enable_2(tp);
5295 5296 5297 5298 5299 5300

	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

	/* Magic. */
	RTL_W8(DBG_REG, 0x20);

5301
	RTL_W8(MaxTxPacketSize, TxPacketMax);
5302

5303 5304
	if (tp->dev->mtu <= ETH_DATA_LEN)
		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5305 5306 5307 5308

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
}

5309
static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5310
{
5311
	void __iomem *ioaddr = tp->mmio_addr;
5312
	static const struct ephy_info e_info_8168c_1[] = {
5313 5314 5315 5316 5317
		{ 0x02, 0x0800,	0x1000 },
		{ 0x03, 0,	0x0002 },
		{ 0x06, 0x0080,	0x0000 }
	};

5318
	rtl_csi_access_enable_2(tp);
5319 5320 5321

	RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);

5322
	rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5323

5324
	__rtl_hw_start_8168cp(tp);
5325 5326
}

5327
static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5328
{
5329
	static const struct ephy_info e_info_8168c_2[] = {
5330 5331 5332 5333
		{ 0x01, 0,	0x0001 },
		{ 0x03, 0x0400,	0x0220 }
	};

5334
	rtl_csi_access_enable_2(tp);
5335

5336
	rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5337

5338
	__rtl_hw_start_8168cp(tp);
5339 5340
}

5341
static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
F
Francois Romieu 已提交
5342
{
5343
	rtl_hw_start_8168c_2(tp);
F
Francois Romieu 已提交
5344 5345
}

5346
static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5347
{
5348
	rtl_csi_access_enable_2(tp);
5349

5350
	__rtl_hw_start_8168cp(tp);
5351 5352
}

5353
static void rtl_hw_start_8168d(struct rtl8169_private *tp)
F
Francois Romieu 已提交
5354
{
5355 5356 5357 5358
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

	rtl_csi_access_enable_2(tp);
F
Francois Romieu 已提交
5359 5360 5361

	rtl_disable_clock_request(pdev);

5362
	RTL_W8(MaxTxPacketSize, TxPacketMax);
F
Francois Romieu 已提交
5363

5364 5365
	if (tp->dev->mtu <= ETH_DATA_LEN)
		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
F
Francois Romieu 已提交
5366 5367 5368 5369

	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
}

5370
static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5371
{
5372 5373 5374 5375
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

	rtl_csi_access_enable_1(tp);
5376

5377 5378
	if (tp->dev->mtu <= ETH_DATA_LEN)
		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5379 5380 5381 5382 5383 5384

	RTL_W8(MaxTxPacketSize, TxPacketMax);

	rtl_disable_clock_request(pdev);
}

5385
static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
F
françois romieu 已提交
5386
{
5387 5388
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;
F
françois romieu 已提交
5389 5390 5391 5392 5393 5394 5395
	static const struct ephy_info e_info_8168d_4[] = {
		{ 0x0b, ~0,	0x48 },
		{ 0x19, 0x20,	0x50 },
		{ 0x0c, ~0,	0x20 }
	};
	int i;

5396
	rtl_csi_access_enable_1(tp);
F
françois romieu 已提交
5397 5398 5399 5400 5401 5402 5403 5404 5405

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	RTL_W8(MaxTxPacketSize, TxPacketMax);

	for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
		const struct ephy_info *e = e_info_8168d_4 + i;
		u16 w;

5406 5407
		w = rtl_ephy_read(tp, e->offset);
		rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
F
françois romieu 已提交
5408 5409 5410 5411 5412
	}

	rtl_enable_clock_request(pdev);
}

5413
static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
H
hayeswang 已提交
5414
{
5415 5416
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;
H
Hayes Wang 已提交
5417
	static const struct ephy_info e_info_8168e_1[] = {
H
hayeswang 已提交
5418 5419 5420 5421 5422 5423 5424 5425 5426 5427 5428 5429 5430 5431 5432
		{ 0x00, 0x0200,	0x0100 },
		{ 0x00, 0x0000,	0x0004 },
		{ 0x06, 0x0002,	0x0001 },
		{ 0x06, 0x0000,	0x0030 },
		{ 0x07, 0x0000,	0x2000 },
		{ 0x00, 0x0000,	0x0020 },
		{ 0x03, 0x5800,	0x2000 },
		{ 0x03, 0x0000,	0x0001 },
		{ 0x01, 0x0800,	0x1000 },
		{ 0x07, 0x0000,	0x4000 },
		{ 0x1e, 0x0000,	0x2000 },
		{ 0x19, 0xffff,	0xfe6c },
		{ 0x0a, 0x0000,	0x0040 }
	};

5433
	rtl_csi_access_enable_2(tp);
H
hayeswang 已提交
5434

5435
	rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
H
hayeswang 已提交
5436

5437 5438
	if (tp->dev->mtu <= ETH_DATA_LEN)
		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
H
hayeswang 已提交
5439 5440 5441 5442 5443 5444

	RTL_W8(MaxTxPacketSize, TxPacketMax);

	rtl_disable_clock_request(pdev);

	/* Reset tx FIFO pointer */
F
Francois Romieu 已提交
5445 5446
	RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
	RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
H
hayeswang 已提交
5447

F
Francois Romieu 已提交
5448
	RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
H
hayeswang 已提交
5449 5450
}

5451
static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
H
Hayes Wang 已提交
5452
{
5453 5454
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;
H
Hayes Wang 已提交
5455 5456 5457 5458 5459
	static const struct ephy_info e_info_8168e_2[] = {
		{ 0x09, 0x0000,	0x0080 },
		{ 0x19, 0x0000,	0x0224 }
	};

5460
	rtl_csi_access_enable_1(tp);
H
Hayes Wang 已提交
5461

5462
	rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
H
Hayes Wang 已提交
5463

5464 5465
	if (tp->dev->mtu <= ETH_DATA_LEN)
		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
H
Hayes Wang 已提交
5466

5467 5468 5469 5470 5471 5472 5473 5474
	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
H
Hayes Wang 已提交
5475

5476
	RTL_W8(MaxTxPacketSize, EarlySize);
H
Hayes Wang 已提交
5477

5478 5479
	rtl_disable_clock_request(pdev);

H
Hayes Wang 已提交
5480 5481 5482 5483 5484 5485 5486 5487
	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
	RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);

	/* Adjust EEE LED frequency */
	RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);

	RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
	RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5488
	RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
H
Hayes Wang 已提交
5489 5490
}

5491
static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5492
{
5493 5494
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;
5495

5496
	rtl_csi_access_enable_2(tp);
5497 5498 5499

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

5500 5501 5502 5503 5504 5505 5506 5507 5508 5509
	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5510 5511 5512

	RTL_W8(MaxTxPacketSize, EarlySize);

5513 5514
	rtl_disable_clock_request(pdev);

5515 5516 5517
	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
	RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
	RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5518 5519
	RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
	RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5520 5521
}

5522 5523 5524 5525 5526 5527 5528 5529 5530 5531 5532 5533
static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;
	static const struct ephy_info e_info_8168f_1[] = {
		{ 0x06, 0x00c0,	0x0020 },
		{ 0x08, 0x0001,	0x0002 },
		{ 0x09, 0x0000,	0x0080 },
		{ 0x19, 0x0000,	0x0224 }
	};

	rtl_hw_start_8168f(tp);

5534
	rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5535

5536
	rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5537 5538 5539 5540 5541

	/* Adjust EEE LED frequency */
	RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
}

5542 5543 5544 5545 5546 5547 5548 5549 5550 5551
static void rtl_hw_start_8411(struct rtl8169_private *tp)
{
	static const struct ephy_info e_info_8168f_1[] = {
		{ 0x06, 0x00c0,	0x0020 },
		{ 0x0f, 0xffff,	0x5200 },
		{ 0x1e, 0x0000,	0x4000 },
		{ 0x19, 0x0000,	0x0224 }
	};

	rtl_hw_start_8168f(tp);
H
hayeswang 已提交
5552
	rtl_pcie_state_l2l3_enable(tp, false);
5553

5554
	rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5555

5556
	rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5557 5558
}

H
Hayes Wang 已提交
5559 5560 5561 5562 5563
static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

5564 5565
	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);

H
Hayes Wang 已提交
5566 5567 5568 5569 5570 5571 5572 5573 5574 5575 5576
	rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);

	rtl_csi_access_enable_1(tp);

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5577
	rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
H
Hayes Wang 已提交
5578 5579

	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5580
	RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
H
Hayes Wang 已提交
5581 5582 5583 5584 5585 5586 5587 5588
	RTL_W8(MaxTxPacketSize, EarlySize);

	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	/* Adjust EEE LED frequency */
	RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);

5589 5590
	rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
H
hayeswang 已提交
5591 5592

	rtl_pcie_state_l2l3_enable(tp, false);
H
Hayes Wang 已提交
5593 5594
}

H
hayeswang 已提交
5595 5596 5597 5598 5599 5600 5601 5602 5603 5604 5605 5606 5607 5608 5609 5610 5611 5612
static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;
	static const struct ephy_info e_info_8168g_2[] = {
		{ 0x00, 0x0000,	0x0008 },
		{ 0x0c, 0x3df0,	0x0200 },
		{ 0x19, 0xffff,	0xfc00 },
		{ 0x1e, 0xffff,	0x20eb }
	};

	rtl_hw_start_8168g_1(tp);

	/* disable aspm and clock request before access ephy */
	RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
	RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
	rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
}

H
hayeswang 已提交
5613 5614 5615 5616 5617 5618 5619 5620 5621 5622 5623 5624 5625 5626 5627 5628 5629 5630 5631
static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;
	static const struct ephy_info e_info_8411_2[] = {
		{ 0x00, 0x0000,	0x0008 },
		{ 0x0c, 0x3df0,	0x0200 },
		{ 0x0f, 0xffff,	0x5200 },
		{ 0x19, 0x0020,	0x0000 },
		{ 0x1e, 0x0000,	0x2000 }
	};

	rtl_hw_start_8168g_1(tp);

	/* disable aspm and clock request before access ephy */
	RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
	RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
	rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
}

5632 5633 5634 5635 5636 5637 5638 5639 5640 5641 5642 5643 5644 5645 5646 5647 5648 5649 5650 5651 5652 5653 5654 5655 5656 5657 5658 5659 5660 5661 5662 5663 5664 5665 5666 5667 5668 5669 5670 5671 5672 5673 5674 5675 5676 5677 5678 5679 5680 5681 5682 5683 5684 5685 5686 5687 5688 5689 5690 5691 5692 5693 5694 5695 5696 5697 5698 5699 5700 5701 5702 5703 5704 5705 5706 5707 5708 5709 5710 5711 5712 5713 5714 5715 5716 5717 5718 5719 5720 5721 5722 5723 5724 5725 5726 5727 5728 5729 5730
static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;
	u16 rg_saw_cnt;
	u32 data;
	static const struct ephy_info e_info_8168h_1[] = {
		{ 0x1e, 0x0800,	0x0001 },
		{ 0x1d, 0x0000,	0x0800 },
		{ 0x05, 0xffff,	0x2089 },
		{ 0x06, 0xffff,	0x5881 },
		{ 0x04, 0xffff,	0x154a },
		{ 0x01, 0xffff,	0x068b }
	};

	/* disable aspm and clock request before access ephy */
	RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
	RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
	rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));

	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);

	rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);

	rtl_csi_access_enable_1(tp);

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);

	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);

	rtl_w1w0_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);

	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
	RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
	RTL_W8(MaxTxPacketSize, EarlySize);

	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	/* Adjust EEE LED frequency */
	RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);

	RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
	RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);

	RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);

	rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);

	rtl_pcie_state_l2l3_enable(tp, false);

	rtl_writephy(tp, 0x1f, 0x0c42);
	rg_saw_cnt = rtl_readphy(tp, 0x13);
	rtl_writephy(tp, 0x1f, 0x0000);
	if (rg_saw_cnt > 0) {
		u16 sw_cnt_1ms_ini;

		sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
		sw_cnt_1ms_ini &= 0x0fff;
		data = r8168_mac_ocp_read(tp, 0xd412);
		data &= 0x0fff;
		data |= sw_cnt_1ms_ini;
		r8168_mac_ocp_write(tp, 0xd412, data);
	}

	data = r8168_mac_ocp_read(tp, 0xe056);
	data &= 0xf0;
	data |= 0x07;
	r8168_mac_ocp_write(tp, 0xe056, data);

	data = r8168_mac_ocp_read(tp, 0xe052);
	data &= 0x8008;
	data |= 0x6000;
	r8168_mac_ocp_write(tp, 0xe052, data);

	data = r8168_mac_ocp_read(tp, 0xe0d6);
	data &= 0x01ff;
	data |= 0x017f;
	r8168_mac_ocp_write(tp, 0xe0d6, data);

	data = r8168_mac_ocp_read(tp, 0xd420);
	data &= 0x0fff;
	data |= 0x047f;
	r8168_mac_ocp_write(tp, 0xd420, data);

	r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
	r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
	r8168_mac_ocp_write(tp, 0xc094, 0x0000);
	r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
}

5731 5732
static void rtl_hw_start_8168(struct net_device *dev)
{
5733 5734 5735 5736 5737
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;

	RTL_W8(Cfg9346, Cfg9346_Unlock);

5738
	RTL_W8(MaxTxPacketSize, TxPacketMax);
5739

E
Eric Dumazet 已提交
5740
	rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5741

5742
	tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
5743 5744 5745

	RTL_W16(CPlusCmd, tp->cp_cmd);

5746
	RTL_W16(IntrMitigate, 0x5151);
5747

5748
	/* Work around for RxFIFO overflow. */
F
françois romieu 已提交
5749
	if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5750 5751
		tp->event_slow |= RxFIFOOver | PCSTimeout;
		tp->event_slow &= ~RxOverflow;
5752 5753 5754
	}

	rtl_set_rx_tx_desc_registers(tp, ioaddr);
5755

H
hayeswang 已提交
5756
	rtl_set_rx_tx_config_registers(tp);
5757 5758 5759

	RTL_R8(IntrMask);

5760 5761
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_11:
5762
		rtl_hw_start_8168bb(tp);
5763
		break;
5764 5765 5766

	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
5767
		rtl_hw_start_8168bef(tp);
5768
		break;
5769 5770

	case RTL_GIGA_MAC_VER_18:
5771
		rtl_hw_start_8168cp_1(tp);
5772
		break;
5773 5774

	case RTL_GIGA_MAC_VER_19:
5775
		rtl_hw_start_8168c_1(tp);
5776
		break;
5777 5778

	case RTL_GIGA_MAC_VER_20:
5779
		rtl_hw_start_8168c_2(tp);
5780
		break;
5781

F
Francois Romieu 已提交
5782
	case RTL_GIGA_MAC_VER_21:
5783
		rtl_hw_start_8168c_3(tp);
5784
		break;
F
Francois Romieu 已提交
5785

5786
	case RTL_GIGA_MAC_VER_22:
5787
		rtl_hw_start_8168c_4(tp);
5788
		break;
5789

F
Francois Romieu 已提交
5790
	case RTL_GIGA_MAC_VER_23:
5791
		rtl_hw_start_8168cp_2(tp);
5792
		break;
F
Francois Romieu 已提交
5793

5794
	case RTL_GIGA_MAC_VER_24:
5795
		rtl_hw_start_8168cp_3(tp);
5796
		break;
5797

F
Francois Romieu 已提交
5798
	case RTL_GIGA_MAC_VER_25:
5799 5800
	case RTL_GIGA_MAC_VER_26:
	case RTL_GIGA_MAC_VER_27:
5801
		rtl_hw_start_8168d(tp);
5802
		break;
F
Francois Romieu 已提交
5803

F
françois romieu 已提交
5804
	case RTL_GIGA_MAC_VER_28:
5805
		rtl_hw_start_8168d_4(tp);
5806
		break;
F
Francois Romieu 已提交
5807

5808
	case RTL_GIGA_MAC_VER_31:
5809
		rtl_hw_start_8168dp(tp);
5810 5811
		break;

H
hayeswang 已提交
5812 5813
	case RTL_GIGA_MAC_VER_32:
	case RTL_GIGA_MAC_VER_33:
5814
		rtl_hw_start_8168e_1(tp);
H
Hayes Wang 已提交
5815 5816
		break;
	case RTL_GIGA_MAC_VER_34:
5817
		rtl_hw_start_8168e_2(tp);
H
hayeswang 已提交
5818
		break;
F
françois romieu 已提交
5819

5820 5821
	case RTL_GIGA_MAC_VER_35:
	case RTL_GIGA_MAC_VER_36:
5822
		rtl_hw_start_8168f_1(tp);
5823 5824
		break;

5825 5826 5827 5828
	case RTL_GIGA_MAC_VER_38:
		rtl_hw_start_8411(tp);
		break;

H
Hayes Wang 已提交
5829 5830 5831 5832
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
		rtl_hw_start_8168g_1(tp);
		break;
H
hayeswang 已提交
5833 5834 5835
	case RTL_GIGA_MAC_VER_42:
		rtl_hw_start_8168g_2(tp);
		break;
H
Hayes Wang 已提交
5836

H
hayeswang 已提交
5837 5838 5839 5840
	case RTL_GIGA_MAC_VER_44:
		rtl_hw_start_8411_2(tp);
		break;

5841 5842 5843 5844 5845
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
		rtl_hw_start_8168h_1(tp);
		break;

5846 5847 5848
	default:
		printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
			dev->name, tp->mac_version);
5849
		break;
5850
	}
5851

H
hayeswang 已提交
5852 5853
	RTL_W8(Cfg9346, Cfg9346_Lock);

5854 5855
	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);

H
hayeswang 已提交
5856
	rtl_set_rx_mode(dev);
5857

5858
	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5859
}
L
Linus Torvalds 已提交
5860

5861 5862 5863 5864
#define R810X_CPCMD_QUIRK_MASK (\
	EnableBist | \
	Mac_dbgo_oe | \
	Force_half_dup | \
F
françois romieu 已提交
5865
	Force_rxflow_en | \
5866 5867 5868 5869
	Force_txflow_en | \
	Cxpl_dbg_sel | \
	ASF | \
	PktCntrDisable | \
5870
	Mac_dbgo_sel)
5871

5872
static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5873
{
5874 5875
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;
5876
	static const struct ephy_info e_info_8102e_1[] = {
5877 5878 5879 5880 5881 5882 5883 5884 5885 5886 5887
		{ 0x01,	0, 0x6e65 },
		{ 0x02,	0, 0x091f },
		{ 0x03,	0, 0xc2f9 },
		{ 0x06,	0, 0xafb5 },
		{ 0x07,	0, 0x0e00 },
		{ 0x19,	0, 0xec80 },
		{ 0x01,	0, 0x2e65 },
		{ 0x01,	0, 0x6e65 }
	};
	u8 cfg1;

5888
	rtl_csi_access_enable_2(tp);
5889 5890 5891 5892 5893 5894 5895 5896 5897 5898 5899 5900 5901

	RTL_W8(DBG_REG, FIX_NAK_1);

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	RTL_W8(Config1,
	       LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);

	cfg1 = RTL_R8(Config1);
	if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
		RTL_W8(Config1, cfg1 & ~LEDS0);

5902
	rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5903 5904
}

5905
static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5906
{
5907 5908 5909 5910
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

	rtl_csi_access_enable_2(tp);
5911 5912 5913 5914 5915 5916 5917

	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

	RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
}

5918
static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5919
{
5920
	rtl_hw_start_8102e_2(tp);
5921

5922
	rtl_ephy_write(tp, 0x03, 0xc2f9);
5923 5924
}

5925
static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5926
{
5927
	void __iomem *ioaddr = tp->mmio_addr;
5928 5929 5930 5931 5932 5933 5934 5935 5936 5937 5938
	static const struct ephy_info e_info_8105e_1[] = {
		{ 0x07,	0, 0x4000 },
		{ 0x19,	0, 0x0200 },
		{ 0x19,	0, 0x0020 },
		{ 0x1e,	0, 0x2000 },
		{ 0x03,	0, 0x0001 },
		{ 0x19,	0, 0x0100 },
		{ 0x19,	0, 0x0004 },
		{ 0x0a,	0, 0x0020 }
	};

F
Francois Romieu 已提交
5939
	/* Force LAN exit from ASPM if Rx/Tx are not idle */
5940 5941
	RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);

F
Francois Romieu 已提交
5942
	/* Disable Early Tally Counter */
5943 5944 5945
	RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);

	RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
H
Hayes Wang 已提交
5946
	RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5947

5948
	rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
H
hayeswang 已提交
5949 5950

	rtl_pcie_state_l2l3_enable(tp, false);
5951 5952
}

5953
static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5954
{
5955
	rtl_hw_start_8105e_1(tp);
5956
	rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5957 5958
}

5959 5960 5961 5962 5963 5964 5965 5966 5967 5968 5969 5970 5971 5972 5973 5974
static void rtl_hw_start_8402(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;
	static const struct ephy_info e_info_8402[] = {
		{ 0x19,	0xffff, 0xff64 },
		{ 0x1e,	0, 0x4000 }
	};

	rtl_csi_access_enable_2(tp);

	/* Force LAN exit from ASPM if Rx/Tx are not idle */
	RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);

	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
	RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);

5975
	rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5976 5977 5978

	rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);

5979 5980 5981 5982 5983 5984 5985
	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
	rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
H
hayeswang 已提交
5986 5987

	rtl_pcie_state_l2l3_enable(tp, false);
5988 5989
}

H
Hayes Wang 已提交
5990 5991 5992 5993 5994 5995 5996
static void rtl_hw_start_8106(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	/* Force LAN exit from ASPM if Rx/Tx are not idle */
	RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);

5997
	RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
H
Hayes Wang 已提交
5998 5999
	RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
	RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
H
hayeswang 已提交
6000 6001

	rtl_pcie_state_l2l3_enable(tp, false);
H
Hayes Wang 已提交
6002 6003
}

6004 6005
static void rtl_hw_start_8101(struct net_device *dev)
{
6006 6007 6008 6009
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;

6010 6011
	if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
		tp->event_slow &= ~RxFIFOOver;
F
françois romieu 已提交
6012

F
Francois Romieu 已提交
6013
	if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6014
	    tp->mac_version == RTL_GIGA_MAC_VER_16)
6015 6016
		pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
					 PCI_EXP_DEVCTL_NOSNOOP_EN);
6017

6018 6019
	RTL_W8(Cfg9346, Cfg9346_Unlock);

H
hayeswang 已提交
6020 6021 6022 6023 6024 6025 6026 6027 6028 6029 6030
	RTL_W8(MaxTxPacketSize, TxPacketMax);

	rtl_set_rx_max_size(ioaddr, rx_buf_sz);

	tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
	RTL_W16(CPlusCmd, tp->cp_cmd);

	rtl_set_rx_tx_desc_registers(tp, ioaddr);

	rtl_set_rx_tx_config_registers(tp);

6031 6032
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_07:
6033
		rtl_hw_start_8102e_1(tp);
6034 6035 6036
		break;

	case RTL_GIGA_MAC_VER_08:
6037
		rtl_hw_start_8102e_3(tp);
6038 6039 6040
		break;

	case RTL_GIGA_MAC_VER_09:
6041
		rtl_hw_start_8102e_2(tp);
6042
		break;
6043 6044

	case RTL_GIGA_MAC_VER_29:
6045
		rtl_hw_start_8105e_1(tp);
6046 6047
		break;
	case RTL_GIGA_MAC_VER_30:
6048
		rtl_hw_start_8105e_2(tp);
6049
		break;
6050 6051 6052 6053

	case RTL_GIGA_MAC_VER_37:
		rtl_hw_start_8402(tp);
		break;
H
Hayes Wang 已提交
6054 6055 6056 6057

	case RTL_GIGA_MAC_VER_39:
		rtl_hw_start_8106(tp);
		break;
H
hayeswang 已提交
6058 6059 6060
	case RTL_GIGA_MAC_VER_43:
		rtl_hw_start_8168g_2(tp);
		break;
6061 6062 6063 6064
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
		rtl_hw_start_8168h_1(tp);
		break;
6065 6066
	}

6067
	RTL_W8(Cfg9346, Cfg9346_Lock);
6068 6069 6070 6071 6072 6073 6074

	RTL_W16(IntrMitigate, 0x0000);

	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);

	rtl_set_rx_mode(dev);

H
hayeswang 已提交
6075 6076
	RTL_R8(IntrMask);

6077
	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
L
Linus Torvalds 已提交
6078 6079 6080 6081
}

static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
{
F
Francois Romieu 已提交
6082 6083 6084 6085
	struct rtl8169_private *tp = netdev_priv(dev);

	if (new_mtu < ETH_ZLEN ||
	    new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
L
Linus Torvalds 已提交
6086 6087
		return -EINVAL;

F
Francois Romieu 已提交
6088 6089 6090 6091 6092
	if (new_mtu > ETH_DATA_LEN)
		rtl_hw_jumbo_enable(tp);
	else
		rtl_hw_jumbo_disable(tp);

L
Linus Torvalds 已提交
6093
	dev->mtu = new_mtu;
6094 6095
	netdev_update_features(dev);

S
Stanislaw Gruszka 已提交
6096
	return 0;
L
Linus Torvalds 已提交
6097 6098 6099 6100
}

static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
{
A
Al Viro 已提交
6101
	desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
L
Linus Torvalds 已提交
6102 6103 6104
	desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
}

E
Eric Dumazet 已提交
6105 6106
static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
				     void **data_buff, struct RxDesc *desc)
L
Linus Torvalds 已提交
6107
{
6108
	dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6109
			 DMA_FROM_DEVICE);
6110

E
Eric Dumazet 已提交
6111 6112
	kfree(*data_buff);
	*data_buff = NULL;
L
Linus Torvalds 已提交
6113 6114 6115 6116 6117 6118 6119 6120 6121 6122 6123 6124 6125 6126 6127 6128 6129 6130
	rtl8169_make_unusable_by_asic(desc);
}

static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
{
	u32 eor = le32_to_cpu(desc->opts1) & RingEnd;

	desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
}

static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
				       u32 rx_buf_sz)
{
	desc->addr = cpu_to_le64(mapping);
	wmb();
	rtl8169_mark_to_asic(desc, rx_buf_sz);
}

E
Eric Dumazet 已提交
6131 6132 6133 6134 6135
static inline void *rtl8169_align(void *data)
{
	return (void *)ALIGN((long)data, 16);
}

S
Stanislaw Gruszka 已提交
6136 6137
static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
					     struct RxDesc *desc)
L
Linus Torvalds 已提交
6138
{
E
Eric Dumazet 已提交
6139
	void *data;
L
Linus Torvalds 已提交
6140
	dma_addr_t mapping;
6141
	struct device *d = &tp->pci_dev->dev;
S
Stanislaw Gruszka 已提交
6142
	struct net_device *dev = tp->dev;
E
Eric Dumazet 已提交
6143
	int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
L
Linus Torvalds 已提交
6144

E
Eric Dumazet 已提交
6145 6146 6147
	data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
	if (!data)
		return NULL;
6148

E
Eric Dumazet 已提交
6149 6150 6151 6152 6153 6154
	if (rtl8169_align(data) != data) {
		kfree(data);
		data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
		if (!data)
			return NULL;
	}
6155

6156
	mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6157
				 DMA_FROM_DEVICE);
6158 6159 6160
	if (unlikely(dma_mapping_error(d, mapping))) {
		if (net_ratelimit())
			netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6161
		goto err_out;
6162
	}
L
Linus Torvalds 已提交
6163 6164

	rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
E
Eric Dumazet 已提交
6165
	return data;
6166 6167 6168 6169

err_out:
	kfree(data);
	return NULL;
L
Linus Torvalds 已提交
6170 6171 6172 6173
}

static void rtl8169_rx_clear(struct rtl8169_private *tp)
{
F
Francois Romieu 已提交
6174
	unsigned int i;
L
Linus Torvalds 已提交
6175 6176

	for (i = 0; i < NUM_RX_DESC; i++) {
E
Eric Dumazet 已提交
6177 6178
		if (tp->Rx_databuff[i]) {
			rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
L
Linus Torvalds 已提交
6179 6180 6181 6182 6183
					    tp->RxDescArray + i);
		}
	}
}

S
Stanislaw Gruszka 已提交
6184
static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
L
Linus Torvalds 已提交
6185
{
S
Stanislaw Gruszka 已提交
6186 6187
	desc->opts1 |= cpu_to_le32(RingEnd);
}
6188

S
Stanislaw Gruszka 已提交
6189 6190 6191
static int rtl8169_rx_fill(struct rtl8169_private *tp)
{
	unsigned int i;
L
Linus Torvalds 已提交
6192

S
Stanislaw Gruszka 已提交
6193 6194
	for (i = 0; i < NUM_RX_DESC; i++) {
		void *data;
6195

E
Eric Dumazet 已提交
6196
		if (tp->Rx_databuff[i])
L
Linus Torvalds 已提交
6197
			continue;
6198

S
Stanislaw Gruszka 已提交
6199
		data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
E
Eric Dumazet 已提交
6200 6201
		if (!data) {
			rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
S
Stanislaw Gruszka 已提交
6202
			goto err_out;
E
Eric Dumazet 已提交
6203 6204
		}
		tp->Rx_databuff[i] = data;
L
Linus Torvalds 已提交
6205 6206
	}

S
Stanislaw Gruszka 已提交
6207 6208 6209 6210 6211 6212
	rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
	return 0;

err_out:
	rtl8169_rx_clear(tp);
	return -ENOMEM;
L
Linus Torvalds 已提交
6213 6214 6215 6216 6217 6218 6219 6220 6221
}

static int rtl8169_init_ring(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl8169_init_ring_indexes(tp);

	memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
E
Eric Dumazet 已提交
6222
	memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
L
Linus Torvalds 已提交
6223

S
Stanislaw Gruszka 已提交
6224
	return rtl8169_rx_fill(tp);
L
Linus Torvalds 已提交
6225 6226
}

6227
static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
L
Linus Torvalds 已提交
6228 6229 6230 6231
				 struct TxDesc *desc)
{
	unsigned int len = tx_skb->len;

6232 6233
	dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);

L
Linus Torvalds 已提交
6234 6235 6236 6237 6238 6239
	desc->opts1 = 0x00;
	desc->opts2 = 0x00;
	desc->addr = 0x00;
	tx_skb->len = 0;
}

6240 6241
static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
				   unsigned int n)
L
Linus Torvalds 已提交
6242 6243 6244
{
	unsigned int i;

6245 6246
	for (i = 0; i < n; i++) {
		unsigned int entry = (start + i) % NUM_TX_DESC;
L
Linus Torvalds 已提交
6247 6248 6249 6250 6251 6252
		struct ring_info *tx_skb = tp->tx_skb + entry;
		unsigned int len = tx_skb->len;

		if (len) {
			struct sk_buff *skb = tx_skb->skb;

6253
			rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
L
Linus Torvalds 已提交
6254 6255
					     tp->TxDescArray + entry);
			if (skb) {
6256
				tp->dev->stats.tx_dropped++;
6257
				dev_kfree_skb_any(skb);
L
Linus Torvalds 已提交
6258 6259 6260 6261
				tx_skb->skb = NULL;
			}
		}
	}
6262 6263 6264 6265 6266
}

static void rtl8169_tx_clear(struct rtl8169_private *tp)
{
	rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
L
Linus Torvalds 已提交
6267 6268 6269
	tp->cur_tx = tp->dirty_tx = 0;
}

6270
static void rtl_reset_work(struct rtl8169_private *tp)
L
Linus Torvalds 已提交
6271
{
D
David Howells 已提交
6272
	struct net_device *dev = tp->dev;
6273
	int i;
L
Linus Torvalds 已提交
6274

6275 6276 6277
	napi_disable(&tp->napi);
	netif_stop_queue(dev);
	synchronize_sched();
L
Linus Torvalds 已提交
6278

6279 6280
	rtl8169_hw_reset(tp);

6281 6282 6283
	for (i = 0; i < NUM_RX_DESC; i++)
		rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);

L
Linus Torvalds 已提交
6284
	rtl8169_tx_clear(tp);
6285
	rtl8169_init_ring_indexes(tp);
L
Linus Torvalds 已提交
6286

6287
	napi_enable(&tp->napi);
6288 6289 6290
	rtl_hw_start(dev);
	netif_wake_queue(dev);
	rtl8169_check_link_status(dev, tp, tp->mmio_addr);
L
Linus Torvalds 已提交
6291 6292 6293 6294
}

static void rtl8169_tx_timeout(struct net_device *dev)
{
6295 6296 6297
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
L
Linus Torvalds 已提交
6298 6299 6300
}

static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
F
Francois Romieu 已提交
6301
			      u32 *opts)
L
Linus Torvalds 已提交
6302 6303 6304
{
	struct skb_shared_info *info = skb_shinfo(skb);
	unsigned int cur_frag, entry;
6305
	struct TxDesc *uninitialized_var(txd);
6306
	struct device *d = &tp->pci_dev->dev;
L
Linus Torvalds 已提交
6307 6308 6309

	entry = tp->cur_tx;
	for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
E
Eric Dumazet 已提交
6310
		const skb_frag_t *frag = info->frags + cur_frag;
L
Linus Torvalds 已提交
6311 6312 6313 6314 6315 6316 6317
		dma_addr_t mapping;
		u32 status, len;
		void *addr;

		entry = (entry + 1) % NUM_TX_DESC;

		txd = tp->TxDescArray + entry;
E
Eric Dumazet 已提交
6318
		len = skb_frag_size(frag);
6319
		addr = skb_frag_address(frag);
6320
		mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6321 6322 6323 6324
		if (unlikely(dma_mapping_error(d, mapping))) {
			if (net_ratelimit())
				netif_err(tp, drv, tp->dev,
					  "Failed to map TX fragments DMA!\n");
6325
			goto err_out;
6326
		}
L
Linus Torvalds 已提交
6327

F
Francois Romieu 已提交
6328
		/* Anti gcc 2.95.3 bugware (sic) */
F
Francois Romieu 已提交
6329 6330
		status = opts[0] | len |
			(RingEnd * !((entry + 1) % NUM_TX_DESC));
L
Linus Torvalds 已提交
6331 6332

		txd->opts1 = cpu_to_le32(status);
F
Francois Romieu 已提交
6333
		txd->opts2 = cpu_to_le32(opts[1]);
L
Linus Torvalds 已提交
6334 6335 6336 6337 6338 6339 6340 6341 6342 6343 6344
		txd->addr = cpu_to_le64(mapping);

		tp->tx_skb[entry].len = len;
	}

	if (cur_frag) {
		tp->tx_skb[entry].skb = skb;
		txd->opts1 |= cpu_to_le32(LastFrag);
	}

	return cur_frag;
6345 6346 6347 6348

err_out:
	rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
	return -EIO;
L
Linus Torvalds 已提交
6349 6350
}

6351 6352 6353 6354 6355 6356 6357 6358 6359 6360 6361 6362 6363
static bool rtl_skb_pad(struct sk_buff *skb)
{
	if (skb_padto(skb, ETH_ZLEN))
		return false;
	skb_put(skb, ETH_ZLEN - skb->len);
	return true;
}

static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
{
	return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
}

H
hayeswang 已提交
6364 6365 6366 6367 6368 6369 6370 6371 6372 6373 6374 6375 6376 6377 6378 6379 6380 6381 6382 6383 6384 6385 6386 6387 6388 6389 6390 6391 6392 6393 6394 6395 6396 6397 6398 6399 6400 6401 6402 6403 6404 6405 6406 6407 6408 6409 6410 6411 6412 6413 6414 6415 6416 6417 6418 6419 6420 6421 6422 6423 6424 6425 6426 6427 6428 6429 6430 6431 6432 6433 6434 6435 6436 6437 6438 6439
static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
				      struct net_device *dev);
/* r8169_csum_workaround()
 * The hw limites the value the transport offset. When the offset is out of the
 * range, calculate the checksum by sw.
 */
static void r8169_csum_workaround(struct rtl8169_private *tp,
				  struct sk_buff *skb)
{
	if (skb_shinfo(skb)->gso_size) {
		netdev_features_t features = tp->dev->features;
		struct sk_buff *segs, *nskb;

		features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
		segs = skb_gso_segment(skb, features);
		if (IS_ERR(segs) || !segs)
			goto drop;

		do {
			nskb = segs;
			segs = segs->next;
			nskb->next = NULL;
			rtl8169_start_xmit(nskb, tp->dev);
		} while (segs);

		dev_kfree_skb(skb);
	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
		if (skb_checksum_help(skb) < 0)
			goto drop;

		rtl8169_start_xmit(skb, tp->dev);
	} else {
		struct net_device_stats *stats;

drop:
		stats = &tp->dev->stats;
		stats->tx_dropped++;
		dev_kfree_skb(skb);
	}
}

/* msdn_giant_send_check()
 * According to the document of microsoft, the TCP Pseudo Header excludes the
 * packet length for IPv6 TCP large packets.
 */
static int msdn_giant_send_check(struct sk_buff *skb)
{
	const struct ipv6hdr *ipv6h;
	struct tcphdr *th;
	int ret;

	ret = skb_cow_head(skb, 0);
	if (ret)
		return ret;

	ipv6h = ipv6_hdr(skb);
	th = tcp_hdr(skb);

	th->check = 0;
	th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);

	return ret;
}

static inline __be16 get_protocol(struct sk_buff *skb)
{
	__be16 protocol;

	if (skb->protocol == htons(ETH_P_8021Q))
		protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
	else
		protocol = skb->protocol;

	return protocol;
}

H
hayeswang 已提交
6440 6441
static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
				struct sk_buff *skb, u32 *opts)
L
Linus Torvalds 已提交
6442
{
6443 6444
	u32 mss = skb_shinfo(skb)->gso_size;

F
Francois Romieu 已提交
6445 6446
	if (mss) {
		opts[0] |= TD_LSO;
H
hayeswang 已提交
6447 6448 6449 6450 6451 6452 6453 6454 6455 6456 6457 6458 6459 6460 6461 6462 6463 6464
		opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
		const struct iphdr *ip = ip_hdr(skb);

		if (ip->protocol == IPPROTO_TCP)
			opts[0] |= TD0_IP_CS | TD0_TCP_CS;
		else if (ip->protocol == IPPROTO_UDP)
			opts[0] |= TD0_IP_CS | TD0_UDP_CS;
		else
			WARN_ON_ONCE(1);
	}

	return true;
}

static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
				struct sk_buff *skb, u32 *opts)
{
H
hayeswang 已提交
6465
	u32 transport_offset = (u32)skb_transport_offset(skb);
H
hayeswang 已提交
6466 6467 6468
	u32 mss = skb_shinfo(skb)->gso_size;

	if (mss) {
H
hayeswang 已提交
6469 6470 6471 6472 6473 6474 6475 6476 6477 6478 6479 6480 6481 6482 6483 6484 6485 6486 6487 6488 6489 6490 6491 6492
		if (transport_offset > GTTCPHO_MAX) {
			netif_warn(tp, tx_err, tp->dev,
				   "Invalid transport offset 0x%x for TSO\n",
				   transport_offset);
			return false;
		}

		switch (get_protocol(skb)) {
		case htons(ETH_P_IP):
			opts[0] |= TD1_GTSENV4;
			break;

		case htons(ETH_P_IPV6):
			if (msdn_giant_send_check(skb))
				return false;

			opts[0] |= TD1_GTSENV6;
			break;

		default:
			WARN_ON_ONCE(1);
			break;
		}

H
hayeswang 已提交
6493
		opts[0] |= transport_offset << GTTCPHO_SHIFT;
H
hayeswang 已提交
6494
		opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
F
Francois Romieu 已提交
6495
	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
H
hayeswang 已提交
6496
		u8 ip_protocol;
L
Linus Torvalds 已提交
6497

6498 6499 6500
		if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
			return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);

H
hayeswang 已提交
6501 6502 6503 6504 6505 6506 6507 6508 6509 6510 6511 6512 6513 6514 6515 6516 6517 6518 6519 6520 6521 6522 6523 6524 6525 6526 6527
		if (transport_offset > TCPHO_MAX) {
			netif_warn(tp, tx_err, tp->dev,
				   "Invalid transport offset 0x%x\n",
				   transport_offset);
			return false;
		}

		switch (get_protocol(skb)) {
		case htons(ETH_P_IP):
			opts[1] |= TD1_IPv4_CS;
			ip_protocol = ip_hdr(skb)->protocol;
			break;

		case htons(ETH_P_IPV6):
			opts[1] |= TD1_IPv6_CS;
			ip_protocol = ipv6_hdr(skb)->nexthdr;
			break;

		default:
			ip_protocol = IPPROTO_RAW;
			break;
		}

		if (ip_protocol == IPPROTO_TCP)
			opts[1] |= TD1_TCP_CS;
		else if (ip_protocol == IPPROTO_UDP)
			opts[1] |= TD1_UDP_CS;
F
Francois Romieu 已提交
6528 6529
		else
			WARN_ON_ONCE(1);
H
hayeswang 已提交
6530 6531

		opts[1] |= transport_offset << TCPHO_SHIFT;
6532 6533 6534
	} else {
		if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
			return rtl_skb_pad(skb);
L
Linus Torvalds 已提交
6535
	}
H
hayeswang 已提交
6536

6537
	return true;
L
Linus Torvalds 已提交
6538 6539
}

6540 6541
static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
				      struct net_device *dev)
L
Linus Torvalds 已提交
6542 6543
{
	struct rtl8169_private *tp = netdev_priv(dev);
6544
	unsigned int entry = tp->cur_tx % NUM_TX_DESC;
L
Linus Torvalds 已提交
6545 6546
	struct TxDesc *txd = tp->TxDescArray + entry;
	void __iomem *ioaddr = tp->mmio_addr;
6547
	struct device *d = &tp->pci_dev->dev;
L
Linus Torvalds 已提交
6548 6549
	dma_addr_t mapping;
	u32 status, len;
F
Francois Romieu 已提交
6550
	u32 opts[2];
6551
	int frags;
6552

6553
	if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6554
		netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6555
		goto err_stop_0;
L
Linus Torvalds 已提交
6556 6557 6558
	}

	if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6559 6560
		goto err_stop_0;

6561 6562 6563
	opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
	opts[0] = DescOwn;

H
hayeswang 已提交
6564 6565 6566 6567
	if (!tp->tso_csum(tp, skb, opts)) {
		r8169_csum_workaround(tp, skb);
		return NETDEV_TX_OK;
	}
6568

6569
	len = skb_headlen(skb);
6570
	mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6571 6572 6573
	if (unlikely(dma_mapping_error(d, mapping))) {
		if (net_ratelimit())
			netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6574
		goto err_dma_0;
6575
	}
6576 6577 6578

	tp->tx_skb[entry].len = len;
	txd->addr = cpu_to_le64(mapping);
L
Linus Torvalds 已提交
6579

F
Francois Romieu 已提交
6580
	frags = rtl8169_xmit_frags(tp, skb, opts);
6581 6582 6583
	if (frags < 0)
		goto err_dma_1;
	else if (frags)
F
Francois Romieu 已提交
6584
		opts[0] |= FirstFrag;
6585
	else {
F
Francois Romieu 已提交
6586
		opts[0] |= FirstFrag | LastFrag;
L
Linus Torvalds 已提交
6587 6588 6589
		tp->tx_skb[entry].skb = skb;
	}

F
Francois Romieu 已提交
6590 6591
	txd->opts2 = cpu_to_le32(opts[1]);

6592 6593
	skb_tx_timestamp(skb);

L
Linus Torvalds 已提交
6594 6595
	wmb();

F
Francois Romieu 已提交
6596
	/* Anti gcc 2.95.3 bugware (sic) */
F
Francois Romieu 已提交
6597
	status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
L
Linus Torvalds 已提交
6598 6599 6600 6601
	txd->opts1 = cpu_to_le32(status);

	tp->cur_tx += frags + 1;

6602
	wmb();
L
Linus Torvalds 已提交
6603

F
Francois Romieu 已提交
6604
	RTL_W8(TxPoll, NPQ);
L
Linus Torvalds 已提交
6605

6606 6607
	mmiowb();

6608
	if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6609 6610 6611 6612
		/* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
		 * not miss a ring update when it notices a stopped queue.
		 */
		smp_wmb();
L
Linus Torvalds 已提交
6613
		netif_stop_queue(dev);
6614 6615 6616 6617 6618 6619 6620
		/* Sync with rtl_tx:
		 * - publish queue status and cur_tx ring index (write barrier)
		 * - refresh dirty_tx ring index (read barrier).
		 * May the current thread have a pessimistic view of the ring
		 * status and forget to wake up queue, a racing rtl_tx thread
		 * can't.
		 */
F
Francois Romieu 已提交
6621
		smp_mb();
6622
		if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
L
Linus Torvalds 已提交
6623 6624 6625
			netif_wake_queue(dev);
	}

6626
	return NETDEV_TX_OK;
L
Linus Torvalds 已提交
6627

6628
err_dma_1:
6629
	rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6630
err_dma_0:
6631
	dev_kfree_skb_any(skb);
6632 6633 6634 6635
	dev->stats.tx_dropped++;
	return NETDEV_TX_OK;

err_stop_0:
L
Linus Torvalds 已提交
6636
	netif_stop_queue(dev);
6637
	dev->stats.tx_dropped++;
6638
	return NETDEV_TX_BUSY;
L
Linus Torvalds 已提交
6639 6640 6641 6642 6643 6644 6645 6646 6647 6648 6649
}

static void rtl8169_pcierr_interrupt(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct pci_dev *pdev = tp->pci_dev;
	u16 pci_status, pci_cmd;

	pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
	pci_read_config_word(pdev, PCI_STATUS, &pci_status);

6650 6651
	netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
		  pci_cmd, pci_status);
L
Linus Torvalds 已提交
6652 6653 6654 6655

	/*
	 * The recovery sequence below admits a very elaborated explanation:
	 * - it seems to work;
6656 6657
	 * - I did not see what else could be done;
	 * - it makes iop3xx happy.
L
Linus Torvalds 已提交
6658 6659 6660
	 *
	 * Feel free to adjust to your needs.
	 */
6661
	if (pdev->broken_parity_status)
6662 6663 6664 6665 6666
		pci_cmd &= ~PCI_COMMAND_PARITY;
	else
		pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;

	pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
L
Linus Torvalds 已提交
6667 6668 6669 6670 6671 6672 6673

	pci_write_config_word(pdev, PCI_STATUS,
		pci_status & (PCI_STATUS_DETECTED_PARITY |
		PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
		PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));

	/* The infamous DAC f*ckup only happens at boot time */
6674
	if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
F
françois romieu 已提交
6675 6676
		void __iomem *ioaddr = tp->mmio_addr;

6677
		netif_info(tp, intr, dev, "disabling PCI DAC\n");
L
Linus Torvalds 已提交
6678 6679 6680 6681 6682
		tp->cp_cmd &= ~PCIDAC;
		RTL_W16(CPlusCmd, tp->cp_cmd);
		dev->features &= ~NETIF_F_HIGHDMA;
	}

F
françois romieu 已提交
6683
	rtl8169_hw_reset(tp);
6684

6685
	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
L
Linus Torvalds 已提交
6686 6687
}

6688
static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
L
Linus Torvalds 已提交
6689 6690 6691 6692 6693 6694 6695 6696 6697 6698 6699 6700 6701 6702 6703 6704 6705
{
	unsigned int dirty_tx, tx_left;

	dirty_tx = tp->dirty_tx;
	smp_rmb();
	tx_left = tp->cur_tx - dirty_tx;

	while (tx_left > 0) {
		unsigned int entry = dirty_tx % NUM_TX_DESC;
		struct ring_info *tx_skb = tp->tx_skb + entry;
		u32 status;

		rmb();
		status = le32_to_cpu(tp->TxDescArray[entry].opts1);
		if (status & DescOwn)
			break;

6706 6707
		rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
				     tp->TxDescArray + entry);
L
Linus Torvalds 已提交
6708
		if (status & LastFrag) {
6709 6710 6711 6712
			u64_stats_update_begin(&tp->tx_stats.syncp);
			tp->tx_stats.packets++;
			tp->tx_stats.bytes += tx_skb->skb->len;
			u64_stats_update_end(&tp->tx_stats.syncp);
6713
			dev_kfree_skb_any(tx_skb->skb);
L
Linus Torvalds 已提交
6714 6715 6716 6717 6718 6719 6720 6721
			tx_skb->skb = NULL;
		}
		dirty_tx++;
		tx_left--;
	}

	if (tp->dirty_tx != dirty_tx) {
		tp->dirty_tx = dirty_tx;
6722 6723 6724 6725 6726 6727 6728
		/* Sync with rtl8169_start_xmit:
		 * - publish dirty_tx ring index (write barrier)
		 * - refresh cur_tx ring index and queue status (read barrier)
		 * May the current thread miss the stopped queue condition,
		 * a racing xmit thread can only have a right view of the
		 * ring status.
		 */
F
Francois Romieu 已提交
6729
		smp_mb();
L
Linus Torvalds 已提交
6730
		if (netif_queue_stopped(dev) &&
6731
		    TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
L
Linus Torvalds 已提交
6732 6733
			netif_wake_queue(dev);
		}
6734 6735 6736 6737 6738 6739
		/*
		 * 8168 hack: TxPoll requests are lost when the Tx packets are
		 * too close. Let's kick an extra TxPoll request when a burst
		 * of start_xmit activity is detected (if it is not detected,
		 * it is slow enough). -- FR
		 */
6740 6741 6742
		if (tp->cur_tx != dirty_tx) {
			void __iomem *ioaddr = tp->mmio_addr;

6743
			RTL_W8(TxPoll, NPQ);
6744
		}
L
Linus Torvalds 已提交
6745 6746 6747
	}
}

6748 6749 6750 6751 6752
static inline int rtl8169_fragmented_frame(u32 status)
{
	return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
}

E
Eric Dumazet 已提交
6753
static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
L
Linus Torvalds 已提交
6754 6755 6756 6757
{
	u32 status = opts1 & RxProtoMask;

	if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
S
Shan Wei 已提交
6758
	    ((status == RxProtoUDP) && !(opts1 & UDPFail)))
L
Linus Torvalds 已提交
6759 6760
		skb->ip_summed = CHECKSUM_UNNECESSARY;
	else
6761
		skb_checksum_none_assert(skb);
L
Linus Torvalds 已提交
6762 6763
}

E
Eric Dumazet 已提交
6764 6765 6766 6767
static struct sk_buff *rtl8169_try_rx_copy(void *data,
					   struct rtl8169_private *tp,
					   int pkt_size,
					   dma_addr_t addr)
L
Linus Torvalds 已提交
6768
{
S
Stephen Hemminger 已提交
6769
	struct sk_buff *skb;
6770
	struct device *d = &tp->pci_dev->dev;
S
Stephen Hemminger 已提交
6771

E
Eric Dumazet 已提交
6772
	data = rtl8169_align(data);
6773
	dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
E
Eric Dumazet 已提交
6774 6775 6776 6777
	prefetch(data);
	skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
	if (skb)
		memcpy(skb->data, data, pkt_size);
6778 6779
	dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);

E
Eric Dumazet 已提交
6780
	return skb;
L
Linus Torvalds 已提交
6781 6782
}

6783
static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
L
Linus Torvalds 已提交
6784 6785
{
	unsigned int cur_rx, rx_left;
E
Eric Dumazet 已提交
6786
	unsigned int count;
L
Linus Torvalds 已提交
6787 6788 6789

	cur_rx = tp->cur_rx;

6790
	for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
L
Linus Torvalds 已提交
6791
		unsigned int entry = cur_rx % NUM_RX_DESC;
6792
		struct RxDesc *desc = tp->RxDescArray + entry;
L
Linus Torvalds 已提交
6793 6794 6795
		u32 status;

		rmb();
6796
		status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
L
Linus Torvalds 已提交
6797 6798 6799

		if (status & DescOwn)
			break;
R
Richard Dawe 已提交
6800
		if (unlikely(status & RxRES)) {
6801 6802
			netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
				   status);
6803
			dev->stats.rx_errors++;
L
Linus Torvalds 已提交
6804
			if (status & (RxRWT | RxRUNT))
6805
				dev->stats.rx_length_errors++;
L
Linus Torvalds 已提交
6806
			if (status & RxCRC)
6807
				dev->stats.rx_crc_errors++;
6808
			if (status & RxFOVF) {
6809
				rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6810
				dev->stats.rx_fifo_errors++;
6811
			}
B
Ben Greear 已提交
6812 6813 6814 6815
			if ((status & (RxRUNT | RxCRC)) &&
			    !(status & (RxRWT | RxFOVF)) &&
			    (dev->features & NETIF_F_RXALL))
				goto process_pkt;
L
Linus Torvalds 已提交
6816
		} else {
E
Eric Dumazet 已提交
6817
			struct sk_buff *skb;
B
Ben Greear 已提交
6818 6819 6820 6821 6822
			dma_addr_t addr;
			int pkt_size;

process_pkt:
			addr = le64_to_cpu(desc->addr);
B
Ben Greear 已提交
6823 6824 6825 6826
			if (likely(!(dev->features & NETIF_F_RXFCS)))
				pkt_size = (status & 0x00003fff) - 4;
			else
				pkt_size = status & 0x00003fff;
L
Linus Torvalds 已提交
6827

6828 6829 6830 6831 6832 6833
			/*
			 * The driver does not support incoming fragmented
			 * frames. They are seen as a symptom of over-mtu
			 * sized frames.
			 */
			if (unlikely(rtl8169_fragmented_frame(status))) {
6834 6835
				dev->stats.rx_dropped++;
				dev->stats.rx_length_errors++;
6836
				goto release_descriptor;
6837 6838
			}

E
Eric Dumazet 已提交
6839 6840 6841 6842
			skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
						  tp, pkt_size, addr);
			if (!skb) {
				dev->stats.rx_dropped++;
6843
				goto release_descriptor;
L
Linus Torvalds 已提交
6844 6845
			}

E
Eric Dumazet 已提交
6846
			rtl8169_rx_csum(skb, status);
L
Linus Torvalds 已提交
6847 6848 6849
			skb_put(skb, pkt_size);
			skb->protocol = eth_type_trans(skb, dev);

6850 6851
			rtl8169_rx_vlan_tag(desc, skb);

6852
			napi_gro_receive(&tp->napi, skb);
L
Linus Torvalds 已提交
6853

J
Junchang Wang 已提交
6854 6855 6856 6857
			u64_stats_update_begin(&tp->rx_stats.syncp);
			tp->rx_stats.packets++;
			tp->rx_stats.bytes += pkt_size;
			u64_stats_update_end(&tp->rx_stats.syncp);
L
Linus Torvalds 已提交
6858
		}
6859 6860 6861 6862
release_descriptor:
		desc->opts2 = 0;
		wmb();
		rtl8169_mark_to_asic(desc, rx_buf_sz);
L
Linus Torvalds 已提交
6863 6864 6865 6866 6867 6868 6869 6870
	}

	count = cur_rx - tp->cur_rx;
	tp->cur_rx = cur_rx;

	return count;
}

F
Francois Romieu 已提交
6871
static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
L
Linus Torvalds 已提交
6872
{
F
Francois Romieu 已提交
6873
	struct net_device *dev = dev_instance;
L
Linus Torvalds 已提交
6874 6875
	struct rtl8169_private *tp = netdev_priv(dev);
	int handled = 0;
F
Francois Romieu 已提交
6876
	u16 status;
L
Linus Torvalds 已提交
6877

F
Francois Romieu 已提交
6878
	status = rtl_get_events(tp);
6879 6880 6881 6882
	if (status && status != 0xffff) {
		status &= RTL_EVENT_NAPI | tp->event_slow;
		if (status) {
			handled = 1;
L
Linus Torvalds 已提交
6883

6884 6885
			rtl_irq_disable(tp);
			napi_schedule(&tp->napi);
6886
		}
6887 6888 6889
	}
	return IRQ_RETVAL(handled);
}
L
Linus Torvalds 已提交
6890

6891 6892 6893 6894 6895 6896 6897 6898 6899 6900
/*
 * Workqueue context.
 */
static void rtl_slow_event_work(struct rtl8169_private *tp)
{
	struct net_device *dev = tp->dev;
	u16 status;

	status = rtl_get_events(tp) & tp->event_slow;
	rtl_ack_events(tp, status);
L
Linus Torvalds 已提交
6901

6902 6903 6904 6905 6906
	if (unlikely(status & RxFIFOOver)) {
		switch (tp->mac_version) {
		/* Work around for rx fifo overflow */
		case RTL_GIGA_MAC_VER_11:
			netif_stop_queue(dev);
6907 6908
			/* XXX - Hack alert. See rtl_task(). */
			set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6909
		default:
6910 6911
			break;
		}
6912
	}
L
Linus Torvalds 已提交
6913

6914 6915
	if (unlikely(status & SYSErr))
		rtl8169_pcierr_interrupt(dev);
6916

6917 6918
	if (status & LinkChg)
		__rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
L
Linus Torvalds 已提交
6919

6920
	rtl_irq_enable_all(tp);
L
Linus Torvalds 已提交
6921 6922
}

6923 6924
static void rtl_task(struct work_struct *work)
{
6925 6926 6927 6928
	static const struct {
		int bitnr;
		void (*action)(struct rtl8169_private *);
	} rtl_work[] = {
6929
		/* XXX - keep rtl_slow_event_work() as first element. */
6930 6931 6932 6933
		{ RTL_FLAG_TASK_SLOW_PENDING,	rtl_slow_event_work },
		{ RTL_FLAG_TASK_RESET_PENDING,	rtl_reset_work },
		{ RTL_FLAG_TASK_PHY_PENDING,	rtl_phy_work }
	};
6934 6935
	struct rtl8169_private *tp =
		container_of(work, struct rtl8169_private, wk.work);
6936 6937 6938 6939 6940
	struct net_device *dev = tp->dev;
	int i;

	rtl_lock_work(tp);

6941 6942
	if (!netif_running(dev) ||
	    !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6943 6944 6945 6946 6947 6948 6949 6950 6951
		goto out_unlock;

	for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
		bool pending;

		pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
		if (pending)
			rtl_work[i].action(tp);
	}
6952

6953 6954
out_unlock:
	rtl_unlock_work(tp);
6955 6956
}

6957
static int rtl8169_poll(struct napi_struct *napi, int budget)
L
Linus Torvalds 已提交
6958
{
6959 6960
	struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
	struct net_device *dev = tp->dev;
6961 6962 6963 6964 6965 6966 6967 6968 6969 6970 6971 6972
	u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
	int work_done= 0;
	u16 status;

	status = rtl_get_events(tp);
	rtl_ack_events(tp, status & ~tp->event_slow);

	if (status & RTL_EVENT_NAPI_RX)
		work_done = rtl_rx(dev, tp, (u32) budget);

	if (status & RTL_EVENT_NAPI_TX)
		rtl_tx(dev, tp);
L
Linus Torvalds 已提交
6973

6974 6975 6976 6977 6978
	if (status & tp->event_slow) {
		enable_mask &= ~tp->event_slow;

		rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
	}
L
Linus Torvalds 已提交
6979

6980
	if (work_done < budget) {
6981
		napi_complete(napi);
6982

6983 6984
		rtl_irq_enable(tp, enable_mask);
		mmiowb();
L
Linus Torvalds 已提交
6985 6986
	}

6987
	return work_done;
L
Linus Torvalds 已提交
6988 6989
}

6990 6991 6992 6993 6994 6995 6996 6997 6998 6999 7000
static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	if (tp->mac_version > RTL_GIGA_MAC_VER_06)
		return;

	dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
	RTL_W32(RxMissed, 0);
}

L
Linus Torvalds 已提交
7001 7002 7003 7004 7005
static void rtl8169_down(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;

7006
	del_timer_sync(&tp->timer);
L
Linus Torvalds 已提交
7007

7008
	napi_disable(&tp->napi);
7009
	netif_stop_queue(dev);
L
Linus Torvalds 已提交
7010

7011
	rtl8169_hw_reset(tp);
S
Stanislaw Gruszka 已提交
7012 7013
	/*
	 * At this point device interrupts can not be enabled in any function,
7014 7015
	 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
	 * and napi is disabled (rtl8169_poll).
S
Stanislaw Gruszka 已提交
7016
	 */
7017
	rtl8169_rx_missed(dev, ioaddr);
L
Linus Torvalds 已提交
7018 7019

	/* Give a racing hard_start_xmit a few cycles to complete. */
7020
	synchronize_sched();
L
Linus Torvalds 已提交
7021 7022 7023 7024

	rtl8169_tx_clear(tp);

	rtl8169_rx_clear(tp);
F
françois romieu 已提交
7025 7026

	rtl_pll_power_down(tp);
L
Linus Torvalds 已提交
7027 7028 7029 7030 7031 7032 7033
}

static int rtl8169_close(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	struct pci_dev *pdev = tp->pci_dev;

7034 7035
	pm_runtime_get_sync(&pdev->dev);

F
Francois Romieu 已提交
7036
	/* Update counters before going down */
7037 7038
	rtl8169_update_counters(dev);

7039
	rtl_lock_work(tp);
7040
	clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7041

L
Linus Torvalds 已提交
7042
	rtl8169_down(dev);
7043
	rtl_unlock_work(tp);
L
Linus Torvalds 已提交
7044

7045 7046
	cancel_work_sync(&tp->wk.work);

7047
	free_irq(pdev->irq, dev);
L
Linus Torvalds 已提交
7048

7049 7050 7051 7052
	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
			  tp->RxPhyAddr);
	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
			  tp->TxPhyAddr);
L
Linus Torvalds 已提交
7053 7054 7055
	tp->TxDescArray = NULL;
	tp->RxDescArray = NULL;

7056 7057
	pm_runtime_put_sync(&pdev->dev);

L
Linus Torvalds 已提交
7058 7059 7060
	return 0;
}

7061 7062 7063 7064 7065 7066 7067 7068 7069
#ifdef CONFIG_NET_POLL_CONTROLLER
static void rtl8169_netpoll(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl8169_interrupt(tp->pci_dev->irq, dev);
}
#endif

7070 7071 7072 7073 7074 7075 7076 7077 7078 7079
static int rtl_open(struct net_device *dev)
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
	struct pci_dev *pdev = tp->pci_dev;
	int retval = -ENOMEM;

	pm_runtime_get_sync(&pdev->dev);

	/*
7080
	 * Rx and Tx descriptors needs 256 bytes alignment.
7081 7082 7083 7084 7085 7086 7087 7088 7089 7090 7091 7092 7093 7094 7095 7096 7097 7098 7099 7100 7101 7102
	 * dma_alloc_coherent provides more.
	 */
	tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
					     &tp->TxPhyAddr, GFP_KERNEL);
	if (!tp->TxDescArray)
		goto err_pm_runtime_put;

	tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
					     &tp->RxPhyAddr, GFP_KERNEL);
	if (!tp->RxDescArray)
		goto err_free_tx_0;

	retval = rtl8169_init_ring(dev);
	if (retval < 0)
		goto err_free_rx_1;

	INIT_WORK(&tp->wk.work, rtl_task);

	smp_mb();

	rtl_request_firmware(tp);

7103
	retval = request_irq(pdev->irq, rtl8169_interrupt,
7104 7105 7106 7107 7108 7109 7110 7111 7112 7113 7114 7115 7116 7117 7118 7119 7120 7121 7122 7123 7124 7125 7126 7127 7128 7129 7130 7131 7132 7133 7134 7135 7136 7137 7138 7139 7140 7141 7142 7143 7144 7145 7146 7147 7148 7149
			     (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
			     dev->name, dev);
	if (retval < 0)
		goto err_release_fw_2;

	rtl_lock_work(tp);

	set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);

	napi_enable(&tp->napi);

	rtl8169_init_phy(dev, tp);

	__rtl8169_set_features(dev, dev->features);

	rtl_pll_power_up(tp);

	rtl_hw_start(dev);

	netif_start_queue(dev);

	rtl_unlock_work(tp);

	tp->saved_wolopts = 0;
	pm_runtime_put_noidle(&pdev->dev);

	rtl8169_check_link_status(dev, tp, ioaddr);
out:
	return retval;

err_release_fw_2:
	rtl_release_firmware(tp);
	rtl8169_rx_clear(tp);
err_free_rx_1:
	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
			  tp->RxPhyAddr);
	tp->RxDescArray = NULL;
err_free_tx_0:
	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
			  tp->TxPhyAddr);
	tp->TxDescArray = NULL;
err_pm_runtime_put:
	pm_runtime_put_noidle(&pdev->dev);
	goto out;
}

J
Junchang Wang 已提交
7150 7151
static struct rtnl_link_stats64 *
rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
L
Linus Torvalds 已提交
7152 7153 7154
{
	struct rtl8169_private *tp = netdev_priv(dev);
	void __iomem *ioaddr = tp->mmio_addr;
J
Junchang Wang 已提交
7155
	unsigned int start;
L
Linus Torvalds 已提交
7156

7157
	if (netif_running(dev))
7158
		rtl8169_rx_missed(dev, ioaddr);
7159

J
Junchang Wang 已提交
7160
	do {
7161
		start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
J
Junchang Wang 已提交
7162 7163
		stats->rx_packets = tp->rx_stats.packets;
		stats->rx_bytes	= tp->rx_stats.bytes;
7164
	} while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
J
Junchang Wang 已提交
7165 7166 7167


	do {
7168
		start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
J
Junchang Wang 已提交
7169 7170
		stats->tx_packets = tp->tx_stats.packets;
		stats->tx_bytes	= tp->tx_stats.bytes;
7171
	} while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
J
Junchang Wang 已提交
7172 7173 7174 7175 7176 7177 7178 7179 7180 7181

	stats->rx_dropped	= dev->stats.rx_dropped;
	stats->tx_dropped	= dev->stats.tx_dropped;
	stats->rx_length_errors = dev->stats.rx_length_errors;
	stats->rx_errors	= dev->stats.rx_errors;
	stats->rx_crc_errors	= dev->stats.rx_crc_errors;
	stats->rx_fifo_errors	= dev->stats.rx_fifo_errors;
	stats->rx_missed_errors = dev->stats.rx_missed_errors;

	return stats;
L
Linus Torvalds 已提交
7182 7183
}

7184
static void rtl8169_net_suspend(struct net_device *dev)
7185
{
F
françois romieu 已提交
7186 7187
	struct rtl8169_private *tp = netdev_priv(dev);

7188
	if (!netif_running(dev))
7189
		return;
7190 7191 7192

	netif_device_detach(dev);
	netif_stop_queue(dev);
7193 7194 7195

	rtl_lock_work(tp);
	napi_disable(&tp->napi);
7196
	clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7197 7198 7199
	rtl_unlock_work(tp);

	rtl_pll_power_down(tp);
7200 7201 7202 7203 7204 7205 7206 7207
}

#ifdef CONFIG_PM

static int rtl8169_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct net_device *dev = pci_get_drvdata(pdev);
7208

7209
	rtl8169_net_suspend(dev);
7210

7211 7212 7213
	return 0;
}

7214 7215
static void __rtl8169_resume(struct net_device *dev)
{
F
françois romieu 已提交
7216 7217
	struct rtl8169_private *tp = netdev_priv(dev);

7218
	netif_device_attach(dev);
F
françois romieu 已提交
7219 7220 7221

	rtl_pll_power_up(tp);

A
Artem Savkov 已提交
7222 7223
	rtl_lock_work(tp);
	napi_enable(&tp->napi);
7224
	set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
A
Artem Savkov 已提交
7225
	rtl_unlock_work(tp);
7226

7227
	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7228 7229
}

7230
static int rtl8169_resume(struct device *device)
7231
{
7232
	struct pci_dev *pdev = to_pci_dev(device);
7233
	struct net_device *dev = pci_get_drvdata(pdev);
S
Stanislaw Gruszka 已提交
7234 7235 7236
	struct rtl8169_private *tp = netdev_priv(dev);

	rtl8169_init_phy(dev, tp);
7237

7238 7239
	if (netif_running(dev))
		__rtl8169_resume(dev);
7240

7241 7242 7243 7244 7245 7246 7247 7248 7249 7250 7251 7252
	return 0;
}

static int rtl8169_runtime_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct net_device *dev = pci_get_drvdata(pdev);
	struct rtl8169_private *tp = netdev_priv(dev);

	if (!tp->TxDescArray)
		return 0;

7253
	rtl_lock_work(tp);
7254 7255
	tp->saved_wolopts = __rtl8169_get_wol(tp);
	__rtl8169_set_wol(tp, WAKE_ANY);
7256
	rtl_unlock_work(tp);
7257 7258 7259 7260 7261 7262 7263 7264 7265 7266 7267 7268 7269 7270 7271

	rtl8169_net_suspend(dev);

	return 0;
}

static int rtl8169_runtime_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct net_device *dev = pci_get_drvdata(pdev);
	struct rtl8169_private *tp = netdev_priv(dev);

	if (!tp->TxDescArray)
		return 0;

7272
	rtl_lock_work(tp);
7273 7274
	__rtl8169_set_wol(tp, tp->saved_wolopts);
	tp->saved_wolopts = 0;
7275
	rtl_unlock_work(tp);
7276

S
Stanislaw Gruszka 已提交
7277 7278
	rtl8169_init_phy(dev, tp);

7279
	__rtl8169_resume(dev);
7280 7281 7282 7283

	return 0;
}

7284 7285 7286 7287 7288 7289
static int rtl8169_runtime_idle(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct net_device *dev = pci_get_drvdata(pdev);
	struct rtl8169_private *tp = netdev_priv(dev);

7290
	return tp->TxDescArray ? -EBUSY : 0;
7291 7292
}

7293
static const struct dev_pm_ops rtl8169_pm_ops = {
F
Francois Romieu 已提交
7294 7295 7296 7297 7298 7299 7300 7301 7302
	.suspend		= rtl8169_suspend,
	.resume			= rtl8169_resume,
	.freeze			= rtl8169_suspend,
	.thaw			= rtl8169_resume,
	.poweroff		= rtl8169_suspend,
	.restore		= rtl8169_resume,
	.runtime_suspend	= rtl8169_runtime_suspend,
	.runtime_resume		= rtl8169_runtime_resume,
	.runtime_idle		= rtl8169_runtime_idle,
7303 7304 7305 7306 7307 7308 7309 7310 7311 7312
};

#define RTL8169_PM_OPS	(&rtl8169_pm_ops)

#else /* !CONFIG_PM */

#define RTL8169_PM_OPS	NULL

#endif /* !CONFIG_PM */

7313 7314 7315 7316 7317 7318 7319 7320 7321 7322 7323 7324 7325 7326 7327 7328 7329 7330 7331 7332
static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
{
	void __iomem *ioaddr = tp->mmio_addr;

	/* WoL fails with 8168b when the receiver is disabled. */
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_11:
	case RTL_GIGA_MAC_VER_12:
	case RTL_GIGA_MAC_VER_17:
		pci_clear_master(tp->pci_dev);

		RTL_W8(ChipCmd, CmdRxEnb);
		/* PCI commit */
		RTL_R8(ChipCmd);
		break;
	default:
		break;
	}
}

F
Francois Romieu 已提交
7333 7334
static void rtl_shutdown(struct pci_dev *pdev)
{
7335
	struct net_device *dev = pci_get_drvdata(pdev);
7336
	struct rtl8169_private *tp = netdev_priv(dev);
7337 7338 7339
	struct device *d = &pdev->dev;

	pm_runtime_get_sync(d);
7340 7341

	rtl8169_net_suspend(dev);
F
Francois Romieu 已提交
7342

F
Francois Romieu 已提交
7343
	/* Restore original MAC address */
7344 7345
	rtl_rar_set(tp, dev->perm_addr);

7346
	rtl8169_hw_reset(tp);
7347

7348
	if (system_state == SYSTEM_POWER_OFF) {
7349 7350 7351
		if (__rtl8169_get_wol(tp) & WAKE_ANY) {
			rtl_wol_suspend_quirk(tp);
			rtl_wol_shutdown_quirk(tp);
7352 7353
		}

7354 7355 7356
		pci_wake_from_d3(pdev, true);
		pci_set_power_state(pdev, PCI_D3hot);
	}
7357 7358

	pm_runtime_put_noidle(d);
7359
}
7360

B
Bill Pemberton 已提交
7361
static void rtl_remove_one(struct pci_dev *pdev)
7362 7363 7364 7365 7366 7367 7368 7369 7370 7371
{
	struct net_device *dev = pci_get_drvdata(pdev);
	struct rtl8169_private *tp = netdev_priv(dev);

	if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_28 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_31) {
		rtl8168_driver_stop(tp);
	}

7372 7373
	netif_napi_del(&tp->napi);

7374 7375 7376 7377 7378 7379 7380 7381 7382 7383 7384 7385 7386 7387
	unregister_netdev(dev);

	rtl_release_firmware(tp);

	if (pci_dev_run_wake(pdev))
		pm_runtime_get_noresume(&pdev->dev);

	/* restore original MAC address */
	rtl_rar_set(tp, dev->perm_addr);

	rtl_disable_msi(pdev, tp);
	rtl8169_release_board(pdev, dev, tp->mmio_addr);
}

7388
static const struct net_device_ops rtl_netdev_ops = {
7389
	.ndo_open		= rtl_open,
7390 7391 7392 7393 7394 7395 7396 7397 7398 7399 7400 7401 7402 7403 7404 7405 7406
	.ndo_stop		= rtl8169_close,
	.ndo_get_stats64	= rtl8169_get_stats64,
	.ndo_start_xmit		= rtl8169_start_xmit,
	.ndo_tx_timeout		= rtl8169_tx_timeout,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_change_mtu		= rtl8169_change_mtu,
	.ndo_fix_features	= rtl8169_fix_features,
	.ndo_set_features	= rtl8169_set_features,
	.ndo_set_mac_address	= rtl_set_mac_address,
	.ndo_do_ioctl		= rtl8169_ioctl,
	.ndo_set_rx_mode	= rtl_set_rx_mode,
#ifdef CONFIG_NET_POLL_CONTROLLER
	.ndo_poll_controller	= rtl8169_netpoll,
#endif

};

7407 7408 7409 7410 7411 7412 7413 7414 7415 7416 7417 7418 7419 7420 7421 7422 7423 7424 7425 7426 7427 7428 7429 7430 7431 7432 7433 7434 7435 7436 7437 7438 7439 7440 7441 7442 7443 7444 7445 7446 7447 7448 7449 7450 7451 7452 7453 7454 7455 7456 7457 7458 7459 7460 7461 7462 7463
static const struct rtl_cfg_info {
	void (*hw_start)(struct net_device *);
	unsigned int region;
	unsigned int align;
	u16 event_slow;
	unsigned features;
	u8 default_ver;
} rtl_cfg_infos [] = {
	[RTL_CFG_0] = {
		.hw_start	= rtl_hw_start_8169,
		.region		= 1,
		.align		= 0,
		.event_slow	= SYSErr | LinkChg | RxOverflow | RxFIFOOver,
		.features	= RTL_FEATURE_GMII,
		.default_ver	= RTL_GIGA_MAC_VER_01,
	},
	[RTL_CFG_1] = {
		.hw_start	= rtl_hw_start_8168,
		.region		= 2,
		.align		= 8,
		.event_slow	= SYSErr | LinkChg | RxOverflow,
		.features	= RTL_FEATURE_GMII | RTL_FEATURE_MSI,
		.default_ver	= RTL_GIGA_MAC_VER_11,
	},
	[RTL_CFG_2] = {
		.hw_start	= rtl_hw_start_8101,
		.region		= 2,
		.align		= 8,
		.event_slow	= SYSErr | LinkChg | RxOverflow | RxFIFOOver |
				  PCSTimeout,
		.features	= RTL_FEATURE_MSI,
		.default_ver	= RTL_GIGA_MAC_VER_13,
	}
};

/* Cfg9346_Unlock assumed. */
static unsigned rtl_try_msi(struct rtl8169_private *tp,
			    const struct rtl_cfg_info *cfg)
{
	void __iomem *ioaddr = tp->mmio_addr;
	unsigned msi = 0;
	u8 cfg2;

	cfg2 = RTL_R8(Config2) & ~MSIEnable;
	if (cfg->features & RTL_FEATURE_MSI) {
		if (pci_enable_msi(tp->pci_dev)) {
			netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
		} else {
			cfg2 |= MSIEnable;
			msi = RTL_FEATURE_MSI;
		}
	}
	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
		RTL_W8(Config2, cfg2);
	return msi;
}

H
Hayes Wang 已提交
7464 7465 7466 7467 7468 7469 7470 7471 7472 7473 7474 7475 7476 7477
DECLARE_RTL_COND(rtl_link_list_ready_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return RTL_R8(MCU) & LINK_LIST_RDY;
}

DECLARE_RTL_COND(rtl_rxtx_empty_cond)
{
	void __iomem *ioaddr = tp->mmio_addr;

	return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
}

B
Bill Pemberton 已提交
7478
static void rtl_hw_init_8168g(struct rtl8169_private *tp)
H
Hayes Wang 已提交
7479 7480 7481 7482 7483 7484 7485 7486 7487 7488 7489 7490 7491 7492 7493 7494 7495 7496
{
	void __iomem *ioaddr = tp->mmio_addr;
	u32 data;

	tp->ocp_base = OCP_STD_PHY_BASE;

	RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);

	if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
		return;

	if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
		return;

	RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
	msleep(1);
	RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);

7497
	data = r8168_mac_ocp_read(tp, 0xe8de);
H
Hayes Wang 已提交
7498 7499 7500 7501 7502 7503
	data &= ~(1 << 14);
	r8168_mac_ocp_write(tp, 0xe8de, data);

	if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
		return;

7504
	data = r8168_mac_ocp_read(tp, 0xe8de);
H
Hayes Wang 已提交
7505 7506 7507 7508 7509 7510 7511
	data |= (1 << 15);
	r8168_mac_ocp_write(tp, 0xe8de, data);

	if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
		return;
}

B
Bill Pemberton 已提交
7512
static void rtl_hw_initialize(struct rtl8169_private *tp)
H
Hayes Wang 已提交
7513 7514 7515 7516
{
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_40:
	case RTL_GIGA_MAC_VER_41:
H
hayeswang 已提交
7517
	case RTL_GIGA_MAC_VER_42:
H
hayeswang 已提交
7518
	case RTL_GIGA_MAC_VER_43:
H
hayeswang 已提交
7519
	case RTL_GIGA_MAC_VER_44:
7520 7521 7522 7523
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
	case RTL_GIGA_MAC_VER_47:
	case RTL_GIGA_MAC_VER_48:
H
Hayes Wang 已提交
7524 7525 7526 7527 7528 7529 7530 7531
		rtl_hw_init_8168g(tp);
		break;

	default:
		break;
	}
}

B
Bill Pemberton 已提交
7532
static int
7533 7534 7535 7536 7537 7538 7539 7540 7541 7542 7543 7544 7545 7546 7547 7548 7549 7550 7551 7552 7553 7554 7555
rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
	const unsigned int region = cfg->region;
	struct rtl8169_private *tp;
	struct mii_if_info *mii;
	struct net_device *dev;
	void __iomem *ioaddr;
	int chipset, i;
	int rc;

	if (netif_msg_drv(&debug)) {
		printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
		       MODULENAME, RTL8169_VERSION);
	}

	dev = alloc_etherdev(sizeof (*tp));
	if (!dev) {
		rc = -ENOMEM;
		goto out;
	}

	SET_NETDEV_DEV(dev, &pdev->dev);
7556
	dev->netdev_ops = &rtl_netdev_ops;
7557 7558 7559 7560 7561 7562 7563 7564 7565 7566 7567 7568 7569 7570 7571 7572 7573 7574 7575 7576 7577 7578 7579 7580 7581 7582 7583 7584 7585 7586 7587 7588 7589 7590 7591 7592 7593 7594 7595 7596 7597 7598 7599 7600 7601 7602 7603 7604 7605 7606 7607 7608 7609 7610 7611 7612 7613 7614 7615 7616 7617 7618 7619 7620 7621 7622 7623 7624 7625 7626 7627 7628 7629 7630 7631 7632 7633 7634 7635 7636 7637 7638 7639 7640
	tp = netdev_priv(dev);
	tp->dev = dev;
	tp->pci_dev = pdev;
	tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);

	mii = &tp->mii;
	mii->dev = dev;
	mii->mdio_read = rtl_mdio_read;
	mii->mdio_write = rtl_mdio_write;
	mii->phy_id_mask = 0x1f;
	mii->reg_num_mask = 0x1f;
	mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);

	/* disable ASPM completely as that cause random device stop working
	 * problems as well as full system hangs for some PCIe devices users */
	pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
				     PCIE_LINK_STATE_CLKPM);

	/* enable device (incl. PCI PM wakeup and hotplug setup) */
	rc = pci_enable_device(pdev);
	if (rc < 0) {
		netif_err(tp, probe, dev, "enable failure\n");
		goto err_out_free_dev_1;
	}

	if (pci_set_mwi(pdev) < 0)
		netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");

	/* make sure PCI base addr 1 is MMIO */
	if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
		netif_err(tp, probe, dev,
			  "region #%d not an MMIO resource, aborting\n",
			  region);
		rc = -ENODEV;
		goto err_out_mwi_2;
	}

	/* check for weird/broken PCI region reporting */
	if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
		netif_err(tp, probe, dev,
			  "Invalid PCI region size(s), aborting\n");
		rc = -ENODEV;
		goto err_out_mwi_2;
	}

	rc = pci_request_regions(pdev, MODULENAME);
	if (rc < 0) {
		netif_err(tp, probe, dev, "could not request regions\n");
		goto err_out_mwi_2;
	}

	tp->cp_cmd = RxChkSum;

	if ((sizeof(dma_addr_t) > 4) &&
	    !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
		tp->cp_cmd |= PCIDAC;
		dev->features |= NETIF_F_HIGHDMA;
	} else {
		rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
		if (rc < 0) {
			netif_err(tp, probe, dev, "DMA configuration failed\n");
			goto err_out_free_res_3;
		}
	}

	/* ioremap MMIO region */
	ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
	if (!ioaddr) {
		netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
		rc = -EIO;
		goto err_out_free_res_3;
	}
	tp->mmio_addr = ioaddr;

	if (!pci_is_pcie(pdev))
		netif_info(tp, probe, dev, "not PCI Express\n");

	/* Identify chip attached to board */
	rtl8169_get_mac_version(tp, dev, cfg->default_ver);

	rtl_init_rxcfg(tp);

	rtl_irq_disable(tp);

H
Hayes Wang 已提交
7641 7642
	rtl_hw_initialize(tp);

7643 7644 7645 7646 7647 7648 7649 7650 7651 7652 7653 7654 7655 7656 7657 7658
	rtl_hw_reset(tp);

	rtl_ack_events(tp, 0xffff);

	pci_set_master(pdev);

	/*
	 * Pretend we are using VLANs; This bypasses a nasty bug where
	 * Interrupts stop flowing on high load on 8110SCd controllers.
	 */
	if (tp->mac_version == RTL_GIGA_MAC_VER_05)
		tp->cp_cmd |= RxVlan;

	rtl_init_mdio_ops(tp);
	rtl_init_pll_power_ops(tp);
	rtl_init_jumbo_ops(tp);
7659
	rtl_init_csi_ops(tp);
7660 7661 7662 7663 7664 7665 7666 7667

	rtl8169_print_mac_version(tp);

	chipset = tp->mac_version;
	tp->txd_version = rtl_chip_infos[chipset].txd_version;

	RTL_W8(Cfg9346, Cfg9346_Unlock);
	RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
7668
	RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
7669 7670 7671 7672 7673 7674 7675 7676 7677 7678 7679 7680 7681
	switch (tp->mac_version) {
	case RTL_GIGA_MAC_VER_45:
	case RTL_GIGA_MAC_VER_46:
		if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
			tp->features |= RTL_FEATURE_WOL;
		if ((RTL_R8(Config3) & LinkUp) != 0)
			tp->features |= RTL_FEATURE_WOL;
		break;
	default:
		if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
			tp->features |= RTL_FEATURE_WOL;
		break;
	}
7682 7683 7684 7685 7686 7687 7688 7689 7690 7691 7692 7693 7694 7695 7696 7697 7698 7699 7700 7701 7702 7703
	if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
		tp->features |= RTL_FEATURE_WOL;
	tp->features |= rtl_try_msi(tp, cfg);
	RTL_W8(Cfg9346, Cfg9346_Lock);

	if (rtl_tbi_enabled(tp)) {
		tp->set_speed = rtl8169_set_speed_tbi;
		tp->get_settings = rtl8169_gset_tbi;
		tp->phy_reset_enable = rtl8169_tbi_reset_enable;
		tp->phy_reset_pending = rtl8169_tbi_reset_pending;
		tp->link_ok = rtl8169_tbi_link_ok;
		tp->do_ioctl = rtl_tbi_ioctl;
	} else {
		tp->set_speed = rtl8169_set_speed_xmii;
		tp->get_settings = rtl8169_gset_xmii;
		tp->phy_reset_enable = rtl8169_xmii_reset_enable;
		tp->phy_reset_pending = rtl8169_xmii_reset_pending;
		tp->link_ok = rtl8169_xmii_link_ok;
		tp->do_ioctl = rtl_xmii_ioctl;
	}

	mutex_init(&tp->wk.mutex);
7704 7705
	u64_stats_init(&tp->rx_stats.syncp);
	u64_stats_init(&tp->tx_stats.syncp);
7706 7707

	/* Get MAC address */
7708 7709 7710 7711 7712 7713 7714 7715 7716 7717 7718 7719
	if (tp->mac_version == RTL_GIGA_MAC_VER_45 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_46 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_47 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_48) {
		u16 mac_addr[3];

		*(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xE0, ERIAR_EXGMAC);
		*(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xE4, ERIAR_EXGMAC);

		if (is_valid_ether_addr((u8 *)mac_addr))
			rtl_rar_set(tp, (u8 *)mac_addr);
	}
7720 7721 7722
	for (i = 0; i < ETH_ALEN; i++)
		dev->dev_addr[i] = RTL_R8(MAC0 + i);

7723
	dev->ethtool_ops = &rtl8169_ethtool_ops;
7724 7725 7726 7727 7728 7729 7730
	dev->watchdog_timeo = RTL8169_TX_TIMEOUT;

	netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);

	/* don't enable SG, IP_CSUM and TSO by default - it might not work
	 * properly for all devices */
	dev->features |= NETIF_F_RXCSUM |
7731
		NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7732 7733

	dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7734 7735
		NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
		NETIF_F_HW_VLAN_CTAG_RX;
7736 7737 7738 7739 7740
	dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
		NETIF_F_HIGHDMA;

	if (tp->mac_version == RTL_GIGA_MAC_VER_05)
		/* 8110SCd requires hardware Rx VLAN - disallow toggling */
7741
		dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7742

H
hayeswang 已提交
7743 7744
	if (tp->txd_version == RTL_TD_0)
		tp->tso_csum = rtl8169_tso_csum_v1;
H
hayeswang 已提交
7745
	else if (tp->txd_version == RTL_TD_1) {
H
hayeswang 已提交
7746
		tp->tso_csum = rtl8169_tso_csum_v2;
H
hayeswang 已提交
7747 7748
		dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
	} else
H
hayeswang 已提交
7749 7750
		WARN_ON_ONCE(1);

7751 7752 7753 7754 7755 7756 7757 7758 7759 7760 7761 7762 7763 7764 7765 7766 7767 7768 7769 7770 7771
	dev->hw_features |= NETIF_F_RXALL;
	dev->hw_features |= NETIF_F_RXFCS;

	tp->hw_start = cfg->hw_start;
	tp->event_slow = cfg->event_slow;

	tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
		~(RxBOVF | RxFOVF) : ~0;

	init_timer(&tp->timer);
	tp->timer.data = (unsigned long) dev;
	tp->timer.function = rtl8169_phy_timer;

	tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;

	rc = register_netdev(dev);
	if (rc < 0)
		goto err_out_msi_4;

	pci_set_drvdata(pdev, dev);

7772 7773 7774
	netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
		   rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
		   (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
7775 7776 7777 7778 7779 7780 7781 7782 7783 7784 7785 7786 7787 7788 7789 7790 7791 7792 7793 7794 7795 7796 7797 7798
	if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
		netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
			   "tx checksumming: %s]\n",
			   rtl_chip_infos[chipset].jumbo_max,
			   rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
	}

	if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_28 ||
	    tp->mac_version == RTL_GIGA_MAC_VER_31) {
		rtl8168_driver_start(tp);
	}

	device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);

	if (pci_dev_run_wake(pdev))
		pm_runtime_put_noidle(&pdev->dev);

	netif_carrier_off(dev);

out:
	return rc;

err_out_msi_4:
7799
	netif_napi_del(&tp->napi);
7800 7801 7802 7803 7804 7805 7806 7807 7808 7809 7810 7811
	rtl_disable_msi(pdev, tp);
	iounmap(ioaddr);
err_out_free_res_3:
	pci_release_regions(pdev);
err_out_mwi_2:
	pci_clear_mwi(pdev);
	pci_disable_device(pdev);
err_out_free_dev_1:
	free_netdev(dev);
	goto out;
}

L
Linus Torvalds 已提交
7812 7813 7814
static struct pci_driver rtl8169_pci_driver = {
	.name		= MODULENAME,
	.id_table	= rtl8169_pci_tbl,
7815
	.probe		= rtl_init_one,
B
Bill Pemberton 已提交
7816
	.remove		= rtl_remove_one,
F
Francois Romieu 已提交
7817
	.shutdown	= rtl_shutdown,
7818
	.driver.pm	= RTL8169_PM_OPS,
L
Linus Torvalds 已提交
7819 7820
};

7821
module_pci_driver(rtl8169_pci_driver);