emulate.c 107.4 KB
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/******************************************************************************
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 * emulate.c
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 *
 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
 *
 * Copyright (c) 2005 Keir Fraser
 *
 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
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 * privileged instructions:
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 *
 * Copyright (C) 2006 Qumranet
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 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
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 *
 *   Avi Kivity <avi@qumranet.com>
 *   Yaniv Kamay <yaniv@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
 */

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#include <linux/kvm_host.h>
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#include "kvm_cache_regs.h"
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#include <linux/module.h>
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#include <asm/kvm_emulate.h>
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#include "x86.h"
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#include "tss.h"
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/*
 * Opcode effective-address decode tables.
 * Note that we only emulate instructions that have at least one memory
 * operand (excluding implicit stack references). We assume that stack
 * references and instruction fetches will never occur in special memory
 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
 * not be handled.
 */

/* Operand sizes: 8-bit operands or specified/overridden size. */
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#define ByteOp      (1<<0)	/* 8-bit operands. */
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/* Destination operand type. */
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#define ImplicitOps (1<<1)	/* Implicit in opcode. No generic decode. */
#define DstReg      (2<<1)	/* Register operand. */
#define DstMem      (3<<1)	/* Memory operand. */
#define DstAcc      (4<<1)	/* Destination Accumulator */
#define DstDI       (5<<1)	/* Destination is in ES:(E)DI */
#define DstMem64    (6<<1)	/* 64bit memory operand */
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#define DstImmUByte (7<<1)	/* 8-bit unsigned immediate operand */
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#define DstDX       (8<<1)	/* Destination is in DX register */
#define DstMask     (0xf<<1)
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/* Source operand type. */
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#define SrcNone     (0<<5)	/* No source operand. */
#define SrcReg      (1<<5)	/* Register operand. */
#define SrcMem      (2<<5)	/* Memory operand. */
#define SrcMem16    (3<<5)	/* Memory operand (16-bit). */
#define SrcMem32    (4<<5)	/* Memory operand (32-bit). */
#define SrcImm      (5<<5)	/* Immediate operand. */
#define SrcImmByte  (6<<5)	/* 8-bit sign-extended immediate operand. */
#define SrcOne      (7<<5)	/* Implied '1' */
#define SrcImmUByte (8<<5)      /* 8-bit unsigned immediate operand. */
#define SrcImmU     (9<<5)      /* Immediate operand, unsigned */
#define SrcSI       (0xa<<5)	/* Source is in the DS:RSI */
#define SrcImmFAddr (0xb<<5)	/* Source is immediate far address */
#define SrcMemFAddr (0xc<<5)	/* Source is far address in memory */
#define SrcAcc      (0xd<<5)	/* Source Accumulator */
#define SrcImmU16   (0xe<<5)    /* Immediate operand, unsigned, 16 bits */
#define SrcDX       (0xf<<5)	/* Source is in DX register */
#define SrcMask     (0xf<<5)
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/* Generic ModRM decode. */
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#define ModRM       (1<<9)
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/* Destination is only written; never read. */
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#define Mov         (1<<10)
#define BitOp       (1<<11)
#define MemAbs      (1<<12)      /* Memory operand is absolute displacement */
#define String      (1<<13)     /* String instruction (rep capable) */
#define Stack       (1<<14)     /* Stack instruction (push/pop) */
#define GroupMask   (7<<15)     /* Opcode uses one of the group mechanisms */
#define Group       (1<<15)     /* Bits 3:5 of modrm byte extend opcode */
#define GroupDual   (2<<15)     /* Alternate decoding of mod == 3 */
#define Prefix      (3<<15)     /* Instruction varies with 66/f2/f3 prefix */
#define RMExt       (4<<15)     /* Opcode extension in ModRM r/m if mod == 3 */
#define Sse         (1<<18)     /* SSE Vector instruction */
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/* Misc flags */
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#define Prot        (1<<21) /* instruction generates #UD if not in prot-mode */
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#define VendorSpecific (1<<22) /* Vendor specific instruction */
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#define NoAccess    (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
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#define Op3264      (1<<24) /* Operand is 64b in long mode, 32b otherwise */
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#define Undefined   (1<<25) /* No Such Instruction */
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#define Lock        (1<<26) /* lock prefix is allowed for the instruction */
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#define Priv        (1<<27) /* instruction generates #GP if current CPL != 0 */
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#define No64	    (1<<28)
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/* Source 2 operand type */
#define Src2None    (0<<29)
#define Src2CL      (1<<29)
#define Src2ImmByte (2<<29)
#define Src2One     (3<<29)
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#define Src2Imm     (4<<29)
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#define Src2Mask    (7<<29)
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#define X2(x...) x, x
#define X3(x...) X2(x), x
#define X4(x...) X2(x), X2(x)
#define X5(x...) X4(x), x
#define X6(x...) X4(x), X2(x)
#define X7(x...) X4(x), X3(x)
#define X8(x...) X4(x), X4(x)
#define X16(x...) X8(x), X8(x)
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struct opcode {
	u32 flags;
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	u8 intercept;
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	union {
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		int (*execute)(struct x86_emulate_ctxt *ctxt);
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		struct opcode *group;
		struct group_dual *gdual;
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		struct gprefix *gprefix;
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	} u;
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	int (*check_perm)(struct x86_emulate_ctxt *ctxt);
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};

struct group_dual {
	struct opcode mod012[8];
	struct opcode mod3[8];
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};

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struct gprefix {
	struct opcode pfx_no;
	struct opcode pfx_66;
	struct opcode pfx_f2;
	struct opcode pfx_f3;
};

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/* EFLAGS bit definitions. */
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#define EFLG_ID (1<<21)
#define EFLG_VIP (1<<20)
#define EFLG_VIF (1<<19)
#define EFLG_AC (1<<18)
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#define EFLG_VM (1<<17)
#define EFLG_RF (1<<16)
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#define EFLG_IOPL (3<<12)
#define EFLG_NT (1<<14)
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#define EFLG_OF (1<<11)
#define EFLG_DF (1<<10)
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#define EFLG_IF (1<<9)
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#define EFLG_TF (1<<8)
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#define EFLG_SF (1<<7)
#define EFLG_ZF (1<<6)
#define EFLG_AF (1<<4)
#define EFLG_PF (1<<2)
#define EFLG_CF (1<<0)

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#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
#define EFLG_RESERVED_ONE_MASK 2

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/*
 * Instruction emulation:
 * Most instructions are emulated directly via a fragment of inline assembly
 * code. This allows us to save/restore EFLAGS and thus very easily pick up
 * any modified flags.
 */

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#if defined(CONFIG_X86_64)
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#define _LO32 "k"		/* force 32-bit operand */
#define _STK  "%%rsp"		/* stack pointer */
#elif defined(__i386__)
#define _LO32 ""		/* force 32-bit operand */
#define _STK  "%%esp"		/* stack pointer */
#endif

/*
 * These EFLAGS bits are restored from saved value during emulation, and
 * any changes are written back to the saved value after emulation.
 */
#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)

/* Before executing instruction: restore necessary bits in EFLAGS. */
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#define _PRE_EFLAGS(_sav, _msk, _tmp)					\
	/* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
	"movl %"_sav",%"_LO32 _tmp"; "                                  \
	"push %"_tmp"; "                                                \
	"push %"_tmp"; "                                                \
	"movl %"_msk",%"_LO32 _tmp"; "                                  \
	"andl %"_LO32 _tmp",("_STK"); "                                 \
	"pushf; "                                                       \
	"notl %"_LO32 _tmp"; "                                          \
	"andl %"_LO32 _tmp",("_STK"); "                                 \
	"andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); "	\
	"pop  %"_tmp"; "                                                \
	"orl  %"_LO32 _tmp",("_STK"); "                                 \
	"popf; "                                                        \
	"pop  %"_sav"; "
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/* After executing instruction: write-back necessary bits in EFLAGS. */
#define _POST_EFLAGS(_sav, _msk, _tmp) \
	/* _sav |= EFLAGS & _msk; */		\
	"pushf; "				\
	"pop  %"_tmp"; "			\
	"andl %"_msk",%"_LO32 _tmp"; "		\
	"orl  %"_LO32 _tmp",%"_sav"; "

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#ifdef CONFIG_X86_64
#define ON64(x) x
#else
#define ON64(x)
#endif

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#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype)	\
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	do {								\
		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "4", "2")			\
			_op _suffix " %"_x"3,%1; "			\
			_POST_EFLAGS("0", "4", "2")			\
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			: "=m" ((ctxt)->eflags),			\
			  "+q" (*(_dsttype*)&(ctxt)->dst.val),		\
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			  "=&r" (_tmp)					\
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			: _y ((ctxt)->src.val), "i" (EFLAGS_MASK));	\
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	} while (0)
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/* Raw emulation: instruction has two explicit operands. */
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#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy)		\
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	do {								\
		unsigned long _tmp;					\
									\
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		switch ((ctxt)->dst.bytes) {				\
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		case 2:							\
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			____emulate_2op(ctxt,_op,_wx,_wy,"w",u16);	\
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			break;						\
		case 4:							\
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			____emulate_2op(ctxt,_op,_lx,_ly,"l",u32);	\
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			break;						\
		case 8:							\
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			ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
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			break;						\
		}							\
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	} while (0)

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#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy)		     \
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	do {								     \
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		unsigned long _tmp;					     \
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		switch ((ctxt)->dst.bytes) {				     \
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		case 1:							     \
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			____emulate_2op(ctxt,_op,_bx,_by,"b",u8);	     \
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			break;						     \
		default:						     \
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			__emulate_2op_nobyte(ctxt, _op,			     \
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					     _wx, _wy, _lx, _ly, _qx, _qy);  \
			break;						     \
		}							     \
	} while (0)

/* Source operand is byte-sized and may be restricted to just %cl. */
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#define emulate_2op_SrcB(ctxt, _op)					\
	__emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
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/* Source operand is byte, word, long or quad sized. */
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#define emulate_2op_SrcV(ctxt, _op)					\
	__emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
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/* Source operand is word, long or quad sized. */
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#define emulate_2op_SrcV_nobyte(ctxt, _op)				\
	__emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
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/* Instruction has three operands and one operand is stored in ECX register */
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#define __emulate_2op_cl(ctxt, _op, _suffix, _type)		\
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	do {								\
		unsigned long _tmp;					\
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		_type _clv  = (ctxt)->src2.val;				\
		_type _srcv = (ctxt)->src.val;				\
		_type _dstv = (ctxt)->dst.val;				\
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									\
		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "5", "2")			\
			_op _suffix " %4,%1 \n"				\
			_POST_EFLAGS("0", "5", "2")			\
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			: "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
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			: "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK)	\
			);						\
									\
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		(ctxt)->src2.val  = (unsigned long) _clv;		\
		(ctxt)->src2.val = (unsigned long) _srcv;		\
		(ctxt)->dst.val = (unsigned long) _dstv;		\
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	} while (0)

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#define emulate_2op_cl(ctxt, _op)					\
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	do {								\
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		switch ((ctxt)->dst.bytes) {				\
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		case 2:							\
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			__emulate_2op_cl(ctxt, _op, "w", u16);		\
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			break;						\
		case 4:							\
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			__emulate_2op_cl(ctxt, _op, "l", u32);		\
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			break;						\
		case 8:							\
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			ON64(__emulate_2op_cl(ctxt, _op, "q", ulong));	\
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			break;						\
		}							\
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	} while (0)

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#define __emulate_1op(ctxt, _op, _suffix)				\
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	do {								\
		unsigned long _tmp;					\
									\
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		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "3", "2")			\
			_op _suffix " %1; "				\
			_POST_EFLAGS("0", "3", "2")			\
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			: "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
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			  "=&r" (_tmp)					\
			: "i" (EFLAGS_MASK));				\
	} while (0)

/* Instruction has only one explicit operand (no source operand). */
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#define emulate_1op(ctxt, _op)						\
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	do {								\
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		switch ((ctxt)->dst.bytes) {				\
		case 1:	__emulate_1op(ctxt, _op, "b"); break;		\
		case 2:	__emulate_1op(ctxt, _op, "w"); break;		\
		case 4:	__emulate_1op(ctxt, _op, "l"); break;		\
		case 8:	ON64(__emulate_1op(ctxt, _op, "q")); break;	\
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		}							\
	} while (0)

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#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
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	do {								\
		unsigned long _tmp;					\
									\
		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "5", "1")			\
			"1: \n\t"					\
			_op _suffix " %6; "				\
			"2: \n\t"					\
			_POST_EFLAGS("0", "5", "1")			\
			".pushsection .fixup,\"ax\" \n\t"		\
			"3: movb $1, %4 \n\t"				\
			"jmp 2b \n\t"					\
			".popsection \n\t"				\
			_ASM_EXTABLE(1b, 3b)				\
			: "=m" (_eflags), "=&r" (_tmp),			\
			  "+a" (_rax), "+d" (_rdx), "+qm"(_ex)		\
			: "i" (EFLAGS_MASK), "m" ((_src).val),		\
			  "a" (_rax), "d" (_rdx));			\
	} while (0)

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/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
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#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _ex)	\
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	do {								\
		switch((_src).bytes) {					\
		case 1:							\
			__emulate_1op_rax_rdx(_op, _src, _rax, _rdx,	\
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					      _eflags, "b", _ex);	\
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			break;						\
		case 2:							\
			__emulate_1op_rax_rdx(_op, _src, _rax, _rdx,	\
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					      _eflags, "w", _ex);	\
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			break;						\
		case 4:							\
			__emulate_1op_rax_rdx(_op, _src, _rax, _rdx,	\
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					      _eflags, "l", _ex);	\
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			break;						\
		case 8: ON64(						\
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			__emulate_1op_rax_rdx(_op, _src, _rax, _rdx,	\
					      _eflags, "q", _ex));	\
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			break;						\
		}							\
	} while (0)

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static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
				    enum x86_intercept intercept,
				    enum x86_intercept_stage stage)
{
	struct x86_instruction_info info = {
		.intercept  = intercept,
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		.rep_prefix = ctxt->rep_prefix,
		.modrm_mod  = ctxt->modrm_mod,
		.modrm_reg  = ctxt->modrm_reg,
		.modrm_rm   = ctxt->modrm_rm,
		.src_val    = ctxt->src.val64,
		.src_bytes  = ctxt->src.bytes,
		.dst_bytes  = ctxt->dst.bytes,
		.ad_bytes   = ctxt->ad_bytes,
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		.next_rip   = ctxt->eip,
	};

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	return ctxt->ops->intercept(ctxt, &info, stage);
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}

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static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
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{
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	return (1UL << (ctxt->ad_bytes << 3)) - 1;
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}

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/* Access/update address held in a register, based on addressing mode. */
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static inline unsigned long
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address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
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{
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	if (ctxt->ad_bytes == sizeof(unsigned long))
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		return reg;
	else
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		return reg & ad_mask(ctxt);
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}

static inline unsigned long
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register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
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{
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	return address_mask(ctxt, reg);
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}

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static inline void
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register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
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{
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	if (ctxt->ad_bytes == sizeof(unsigned long))
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		*reg += inc;
	else
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		*reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
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}
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static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
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{
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	register_address_increment(ctxt, &ctxt->_eip, rel);
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}
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static u32 desc_limit_scaled(struct desc_struct *desc)
{
	u32 limit = get_desc_limit(desc);

	return desc->g ? (limit << 12) | 0xfff : limit;
}

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static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
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{
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	ctxt->has_seg_override = true;
	ctxt->seg_override = seg;
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}

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static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
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{
	if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
		return 0;

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	return ctxt->ops->get_cached_segment_base(ctxt, seg);
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}

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static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
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{
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	if (!ctxt->has_seg_override)
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		return 0;

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	return ctxt->seg_override;
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}

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static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
			     u32 error, bool valid)
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{
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	ctxt->exception.vector = vec;
	ctxt->exception.error_code = error;
	ctxt->exception.error_code_valid = valid;
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	return X86EMUL_PROPAGATE_FAULT;
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}

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static int emulate_db(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, DB_VECTOR, 0, false);
}

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static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
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{
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	return emulate_exception(ctxt, GP_VECTOR, err, true);
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}

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static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
{
	return emulate_exception(ctxt, SS_VECTOR, err, true);
}

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static int emulate_ud(struct x86_emulate_ctxt *ctxt)
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{
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	return emulate_exception(ctxt, UD_VECTOR, 0, false);
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}

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static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
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{
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	return emulate_exception(ctxt, TS_VECTOR, err, true);
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}

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static int emulate_de(struct x86_emulate_ctxt *ctxt)
{
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	return emulate_exception(ctxt, DE_VECTOR, 0, false);
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}

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static int emulate_nm(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, NM_VECTOR, 0, false);
}

497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516
static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
{
	u16 selector;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
	return selector;
}

static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
				 unsigned seg)
{
	u16 dummy;
	u32 base3;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
	ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
}

517
static int __linearize(struct x86_emulate_ctxt *ctxt,
518
		     struct segmented_address addr,
519
		     unsigned size, bool write, bool fetch,
520 521
		     ulong *linear)
{
522 523
	struct desc_struct desc;
	bool usable;
524
	ulong la;
525
	u32 lim;
526
	u16 sel;
527
	unsigned cpl, rpl;
528

529
	la = seg_base(ctxt, addr.seg) + addr.ea;
530 531 532 533 534 535 536 537
	switch (ctxt->mode) {
	case X86EMUL_MODE_REAL:
		break;
	case X86EMUL_MODE_PROT64:
		if (((signed long)la << 16) >> 16 != la)
			return emulate_gp(ctxt, 0);
		break;
	default:
538 539
		usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
						addr.seg);
540 541 542 543 544 545
		if (!usable)
			goto bad;
		/* code segment or read-only data segment */
		if (((desc.type & 8) || !(desc.type & 2)) && write)
			goto bad;
		/* unreadable code segment */
546
		if (!fetch && (desc.type & 8) && !(desc.type & 2))
547 548 549 550 551 552 553 554 555 556 557 558 559 560
			goto bad;
		lim = desc_limit_scaled(&desc);
		if ((desc.type & 8) || !(desc.type & 4)) {
			/* expand-up segment */
			if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
				goto bad;
		} else {
			/* exapand-down segment */
			if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
				goto bad;
			lim = desc.d ? 0xffffffff : 0xffff;
			if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
				goto bad;
		}
561
		cpl = ctxt->ops->cpl(ctxt);
562
		rpl = sel & 3;
563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578
		cpl = max(cpl, rpl);
		if (!(desc.type & 8)) {
			/* data segment */
			if (cpl > desc.dpl)
				goto bad;
		} else if ((desc.type & 8) && !(desc.type & 4)) {
			/* nonconforming code segment */
			if (cpl != desc.dpl)
				goto bad;
		} else if ((desc.type & 8) && (desc.type & 4)) {
			/* conforming code segment */
			if (cpl < desc.dpl)
				goto bad;
		}
		break;
	}
579
	if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
580 581 582
		la &= (u32)-1;
	*linear = la;
	return X86EMUL_CONTINUE;
583 584 585 586 587
bad:
	if (addr.seg == VCPU_SREG_SS)
		return emulate_ss(ctxt, addr.seg);
	else
		return emulate_gp(ctxt, addr.seg);
588 589
}

590 591 592 593 594 595 596 597 598
static int linearize(struct x86_emulate_ctxt *ctxt,
		     struct segmented_address addr,
		     unsigned size, bool write,
		     ulong *linear)
{
	return __linearize(ctxt, addr, size, write, false, linear);
}


599 600 601 602 603
static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
			      struct segmented_address addr,
			      void *data,
			      unsigned size)
{
604 605 606
	int rc;
	ulong linear;

607
	rc = linearize(ctxt, addr, size, false, &linear);
608 609
	if (rc != X86EMUL_CONTINUE)
		return rc;
610
	return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
611 612
}

613 614 615 616 617 618 619 620
/*
 * Fetch the next byte of the instruction being emulated which is pointed to
 * by ctxt->_eip, then increment ctxt->_eip.
 *
 * Also prefetch the remaining bytes of the instruction without crossing page
 * boundary if they are not in fetch_cache yet.
 */
static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
621
{
622
	struct fetch_cache *fc = &ctxt->fetch;
623
	int rc;
624
	int size, cur_size;
625

626
	if (ctxt->_eip == fc->end) {
627
		unsigned long linear;
628 629
		struct segmented_address addr = { .seg = VCPU_SREG_CS,
						  .ea  = ctxt->_eip };
630
		cur_size = fc->end - fc->start;
631 632
		size = min(15UL - cur_size,
			   PAGE_SIZE - offset_in_page(ctxt->_eip));
633
		rc = __linearize(ctxt, addr, size, false, true, &linear);
634
		if (unlikely(rc != X86EMUL_CONTINUE))
635
			return rc;
636 637
		rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
				      size, &ctxt->exception);
638
		if (unlikely(rc != X86EMUL_CONTINUE))
639
			return rc;
640
		fc->end += size;
641
	}
642 643
	*dest = fc->data[ctxt->_eip - fc->start];
	ctxt->_eip++;
644
	return X86EMUL_CONTINUE;
645 646 647
}

static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
648
			 void *dest, unsigned size)
649
{
650
	int rc;
651

652
	/* x86 instructions are limited to 15 bytes. */
653
	if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
654
		return X86EMUL_UNHANDLEABLE;
655
	while (size--) {
656
		rc = do_insn_fetch_byte(ctxt, dest++);
657
		if (rc != X86EMUL_CONTINUE)
658 659
			return rc;
	}
660
	return X86EMUL_CONTINUE;
661 662
}

663
/* Fetch next part of the instruction being emulated. */
664
#define insn_fetch(_type, _ctxt)					\
665
({	unsigned long _x;						\
666
	rc = do_insn_fetch(_ctxt, &_x, sizeof(_type));			\
667 668 669 670 671
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
	(_type)_x;							\
})

672 673
#define insn_fetch_arr(_arr, _size, _ctxt)				\
({	rc = do_insn_fetch(_ctxt, _arr, (_size));			\
674 675 676 677
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
})

678 679 680 681 682 683 684
/*
 * Given the 'reg' portion of a ModRM byte, and a register block, return a
 * pointer into the block that addresses the relevant register.
 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
 */
static void *decode_register(u8 modrm_reg, unsigned long *regs,
			     int highbyte_regs)
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{
	void *p;

	p = &regs[modrm_reg];
	if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
		p = (unsigned char *)&regs[modrm_reg & 3] + 1;
	return p;
}

static int read_descriptor(struct x86_emulate_ctxt *ctxt,
695
			   struct segmented_address addr,
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			   u16 *size, unsigned long *address, int op_bytes)
{
	int rc;

	if (op_bytes == 2)
		op_bytes = 3;
	*address = 0;
703
	rc = segmented_read_std(ctxt, addr, size, 2);
704
	if (rc != X86EMUL_CONTINUE)
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705
		return rc;
706
	addr.ea += 2;
707
	rc = segmented_read_std(ctxt, addr, address, op_bytes);
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708 709 710
	return rc;
}

711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745
static int test_cc(unsigned int condition, unsigned int flags)
{
	int rc = 0;

	switch ((condition & 15) >> 1) {
	case 0: /* o */
		rc |= (flags & EFLG_OF);
		break;
	case 1: /* b/c/nae */
		rc |= (flags & EFLG_CF);
		break;
	case 2: /* z/e */
		rc |= (flags & EFLG_ZF);
		break;
	case 3: /* be/na */
		rc |= (flags & (EFLG_CF|EFLG_ZF));
		break;
	case 4: /* s */
		rc |= (flags & EFLG_SF);
		break;
	case 5: /* p/pe */
		rc |= (flags & EFLG_PF);
		break;
	case 7: /* le/ng */
		rc |= (flags & EFLG_ZF);
		/* fall through */
	case 6: /* l/nge */
		rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
		break;
	}

	/* Odd condition identifiers (lsb == 1) have inverted sense. */
	return (!!rc ^ (condition & 1));
}

746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763
static void fetch_register_operand(struct operand *op)
{
	switch (op->bytes) {
	case 1:
		op->val = *(u8 *)op->addr.reg;
		break;
	case 2:
		op->val = *(u16 *)op->addr.reg;
		break;
	case 4:
		op->val = *(u32 *)op->addr.reg;
		break;
	case 8:
		op->val = *(u64 *)op->addr.reg;
		break;
	}
}

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764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820
static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
	case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
	case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
	case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
	case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
	case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
	case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
	case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
	case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
#ifdef CONFIG_X86_64
	case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
	case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
	case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
	case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
	case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
	case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
	case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
	case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
#endif
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
			  int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
	case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
	case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
	case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
	case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
	case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
	case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
	case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
	case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
#ifdef CONFIG_X86_64
	case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
	case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
	case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
	case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
	case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
	case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
	case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
	case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
#endif
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
				    struct operand *op,
821 822
				    int inhibit_bytereg)
{
823 824
	unsigned reg = ctxt->modrm_reg;
	int highbyte_regs = ctxt->rex_prefix == 0;
825

826 827
	if (!(ctxt->d & ModRM))
		reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
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828

829
	if (ctxt->d & Sse) {
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830 831 832 833 834 835 836
		op->type = OP_XMM;
		op->bytes = 16;
		op->addr.xmm = reg;
		read_sse_reg(ctxt, &op->vec_val, reg);
		return;
	}

837
	op->type = OP_REG;
838 839
	if ((ctxt->d & ByteOp) && !inhibit_bytereg) {
		op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
840 841
		op->bytes = 1;
	} else {
842 843
		op->addr.reg = decode_register(reg, ctxt->regs, 0);
		op->bytes = ctxt->op_bytes;
844
	}
845
	fetch_register_operand(op);
846 847 848
	op->orig_val = op->val;
}

849
static int decode_modrm(struct x86_emulate_ctxt *ctxt,
850
			struct operand *op)
851 852
{
	u8 sib;
853
	int index_reg = 0, base_reg = 0, scale;
854
	int rc = X86EMUL_CONTINUE;
855
	ulong modrm_ea = 0;
856

857 858 859 860
	if (ctxt->rex_prefix) {
		ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1;	/* REX.R */
		index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
		ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
861 862
	}

863
	ctxt->modrm = insn_fetch(u8, ctxt);
864 865 866 867
	ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
	ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
	ctxt->modrm_rm |= (ctxt->modrm & 0x07);
	ctxt->modrm_seg = VCPU_SREG_DS;
868

869
	if (ctxt->modrm_mod == 3) {
870
		op->type = OP_REG;
871 872 873 874
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.reg = decode_register(ctxt->modrm_rm,
					       ctxt->regs, ctxt->d & ByteOp);
		if (ctxt->d & Sse) {
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875 876
			op->type = OP_XMM;
			op->bytes = 16;
877 878
			op->addr.xmm = ctxt->modrm_rm;
			read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
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Avi Kivity 已提交
879 880
			return rc;
		}
881
		fetch_register_operand(op);
882 883 884
		return rc;
	}

885 886
	op->type = OP_MEM;

887 888 889 890 891
	if (ctxt->ad_bytes == 2) {
		unsigned bx = ctxt->regs[VCPU_REGS_RBX];
		unsigned bp = ctxt->regs[VCPU_REGS_RBP];
		unsigned si = ctxt->regs[VCPU_REGS_RSI];
		unsigned di = ctxt->regs[VCPU_REGS_RDI];
892 893

		/* 16-bit ModR/M decode. */
894
		switch (ctxt->modrm_mod) {
895
		case 0:
896
			if (ctxt->modrm_rm == 6)
897
				modrm_ea += insn_fetch(u16, ctxt);
898 899
			break;
		case 1:
900
			modrm_ea += insn_fetch(s8, ctxt);
901 902
			break;
		case 2:
903
			modrm_ea += insn_fetch(u16, ctxt);
904 905
			break;
		}
906
		switch (ctxt->modrm_rm) {
907
		case 0:
908
			modrm_ea += bx + si;
909 910
			break;
		case 1:
911
			modrm_ea += bx + di;
912 913
			break;
		case 2:
914
			modrm_ea += bp + si;
915 916
			break;
		case 3:
917
			modrm_ea += bp + di;
918 919
			break;
		case 4:
920
			modrm_ea += si;
921 922
			break;
		case 5:
923
			modrm_ea += di;
924 925
			break;
		case 6:
926
			if (ctxt->modrm_mod != 0)
927
				modrm_ea += bp;
928 929
			break;
		case 7:
930
			modrm_ea += bx;
931 932
			break;
		}
933 934 935
		if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
		    (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
			ctxt->modrm_seg = VCPU_SREG_SS;
936
		modrm_ea = (u16)modrm_ea;
937 938
	} else {
		/* 32/64-bit ModR/M decode. */
939
		if ((ctxt->modrm_rm & 7) == 4) {
940
			sib = insn_fetch(u8, ctxt);
941 942 943 944
			index_reg |= (sib >> 3) & 7;
			base_reg |= sib & 7;
			scale = sib >> 6;

945
			if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
946
				modrm_ea += insn_fetch(s32, ctxt);
947
			else
948
				modrm_ea += ctxt->regs[base_reg];
949
			if (index_reg != 4)
950 951
				modrm_ea += ctxt->regs[index_reg] << scale;
		} else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
952
			if (ctxt->mode == X86EMUL_MODE_PROT64)
953
				ctxt->rip_relative = 1;
954
		} else
955 956
			modrm_ea += ctxt->regs[ctxt->modrm_rm];
		switch (ctxt->modrm_mod) {
957
		case 0:
958
			if (ctxt->modrm_rm == 5)
959
				modrm_ea += insn_fetch(s32, ctxt);
960 961
			break;
		case 1:
962
			modrm_ea += insn_fetch(s8, ctxt);
963 964
			break;
		case 2:
965
			modrm_ea += insn_fetch(s32, ctxt);
966 967 968
			break;
		}
	}
969
	op->addr.mem.ea = modrm_ea;
970 971 972 973 974
done:
	return rc;
}

static int decode_abs(struct x86_emulate_ctxt *ctxt,
975
		      struct operand *op)
976
{
977
	int rc = X86EMUL_CONTINUE;
978

979
	op->type = OP_MEM;
980
	switch (ctxt->ad_bytes) {
981
	case 2:
982
		op->addr.mem.ea = insn_fetch(u16, ctxt);
983 984
		break;
	case 4:
985
		op->addr.mem.ea = insn_fetch(u32, ctxt);
986 987
		break;
	case 8:
988
		op->addr.mem.ea = insn_fetch(u64, ctxt);
989 990 991 992 993 994
		break;
	}
done:
	return rc;
}

995
static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
996
{
997
	long sv = 0, mask;
998

999 1000
	if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
		mask = ~(ctxt->dst.bytes * 8 - 1);
1001

1002 1003 1004 1005
		if (ctxt->src.bytes == 2)
			sv = (s16)ctxt->src.val & (s16)mask;
		else if (ctxt->src.bytes == 4)
			sv = (s32)ctxt->src.val & (s32)mask;
1006

1007
		ctxt->dst.addr.mem.ea += (sv >> 3);
1008
	}
1009 1010

	/* only subword offset */
1011
	ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
1012 1013
}

1014 1015
static int read_emulated(struct x86_emulate_ctxt *ctxt,
			 unsigned long addr, void *dest, unsigned size)
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Avi Kivity 已提交
1016
{
1017
	int rc;
1018
	struct read_cache *mc = &ctxt->mem_read;
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1019

1020 1021 1022 1023 1024
	while (size) {
		int n = min(size, 8u);
		size -= n;
		if (mc->pos < mc->end)
			goto read_cached;
1025

1026 1027
		rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
					      &ctxt->exception);
1028 1029 1030
		if (rc != X86EMUL_CONTINUE)
			return rc;
		mc->end += n;
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1031

1032 1033 1034 1035 1036
	read_cached:
		memcpy(dest, mc->data + mc->pos, n);
		mc->pos += n;
		dest += n;
		addr += n;
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1037
	}
1038 1039
	return X86EMUL_CONTINUE;
}
A
Avi Kivity 已提交
1040

1041 1042 1043 1044 1045
static int segmented_read(struct x86_emulate_ctxt *ctxt,
			  struct segmented_address addr,
			  void *data,
			  unsigned size)
{
1046 1047 1048
	int rc;
	ulong linear;

1049
	rc = linearize(ctxt, addr, size, false, &linear);
1050 1051
	if (rc != X86EMUL_CONTINUE)
		return rc;
1052
	return read_emulated(ctxt, linear, data, size);
1053 1054 1055 1056 1057 1058 1059
}

static int segmented_write(struct x86_emulate_ctxt *ctxt,
			   struct segmented_address addr,
			   const void *data,
			   unsigned size)
{
1060 1061 1062
	int rc;
	ulong linear;

1063
	rc = linearize(ctxt, addr, size, true, &linear);
1064 1065
	if (rc != X86EMUL_CONTINUE)
		return rc;
1066 1067
	return ctxt->ops->write_emulated(ctxt, linear, data, size,
					 &ctxt->exception);
1068 1069 1070 1071 1072 1073 1074
}

static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
			     struct segmented_address addr,
			     const void *orig_data, const void *data,
			     unsigned size)
{
1075 1076 1077
	int rc;
	ulong linear;

1078
	rc = linearize(ctxt, addr, size, true, &linear);
1079 1080
	if (rc != X86EMUL_CONTINUE)
		return rc;
1081 1082
	return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
					   size, &ctxt->exception);
1083 1084
}

1085 1086 1087 1088
static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
			   unsigned int size, unsigned short port,
			   void *dest)
{
1089
	struct read_cache *rc = &ctxt->io_read;
1090

1091 1092
	if (rc->pos == rc->end) { /* refill pio read ahead */
		unsigned int in_page, n;
1093 1094
		unsigned int count = ctxt->rep_prefix ?
			address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
1095
		in_page = (ctxt->eflags & EFLG_DF) ?
1096 1097
			offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
			PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
1098 1099 1100 1101 1102
		n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
			count);
		if (n == 0)
			n = 1;
		rc->pos = rc->end = 0;
1103
		if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1104 1105
			return 0;
		rc->end = n * size;
A
Avi Kivity 已提交
1106 1107
	}

1108 1109 1110 1111
	memcpy(dest, rc->data + rc->pos, size);
	rc->pos += size;
	return 1;
}
A
Avi Kivity 已提交
1112

1113 1114 1115
static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
				     u16 selector, struct desc_ptr *dt)
{
1116 1117
	struct x86_emulate_ops *ops = ctxt->ops;

1118 1119
	if (selector & 1 << 2) {
		struct desc_struct desc;
1120 1121
		u16 sel;

1122
		memset (dt, 0, sizeof *dt);
1123
		if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
1124
			return;
1125

1126 1127 1128
		dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
		dt->address = get_desc_base(&desc);
	} else
1129
		ops->get_gdt(ctxt, dt);
1130
}
1131

1132 1133 1134 1135 1136 1137 1138
/* allowed just for 8 bytes segments */
static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   u16 selector, struct desc_struct *desc)
{
	struct desc_ptr dt;
	u16 index = selector >> 3;
	ulong addr;
1139

1140
	get_descriptor_table_ptr(ctxt, selector, &dt);
1141

1142 1143
	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, selector & 0xfffc);
1144

1145 1146 1147
	addr = dt.address + index * 8;
	return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
				   &ctxt->exception);
1148
}
1149

1150 1151 1152 1153 1154 1155 1156
/* allowed just for 8 bytes segments */
static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				    u16 selector, struct desc_struct *desc)
{
	struct desc_ptr dt;
	u16 index = selector >> 3;
	ulong addr;
A
Avi Kivity 已提交
1157

1158
	get_descriptor_table_ptr(ctxt, selector, &dt);
1159

1160 1161
	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, selector & 0xfffc);
A
Avi Kivity 已提交
1162

1163
	addr = dt.address + index * 8;
1164 1165
	return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
				    &ctxt->exception);
1166
}
1167

1168
/* Does not support long mode */
1169 1170 1171 1172 1173 1174 1175 1176 1177
static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   u16 selector, int seg)
{
	struct desc_struct seg_desc;
	u8 dpl, rpl, cpl;
	unsigned err_vec = GP_VECTOR;
	u32 err_code = 0;
	bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
	int ret;
1178

1179
	memset(&seg_desc, 0, sizeof seg_desc);
1180

1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203
	if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
	    || ctxt->mode == X86EMUL_MODE_REAL) {
		/* set real mode segment descriptor */
		set_desc_base(&seg_desc, selector << 4);
		set_desc_limit(&seg_desc, 0xffff);
		seg_desc.type = 3;
		seg_desc.p = 1;
		seg_desc.s = 1;
		goto load;
	}

	/* NULL selector is not valid for TR, CS and SS */
	if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
	    && null_selector)
		goto exception;

	/* TR should be in GDT only */
	if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
		goto exception;

	if (null_selector) /* for NULL selector skip all following checks */
		goto load;

1204
	ret = read_segment_descriptor(ctxt, selector, &seg_desc);
1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221
	if (ret != X86EMUL_CONTINUE)
		return ret;

	err_code = selector & 0xfffc;
	err_vec = GP_VECTOR;

	/* can't load system descriptor into segment selecor */
	if (seg <= VCPU_SREG_GS && !seg_desc.s)
		goto exception;

	if (!seg_desc.p) {
		err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
		goto exception;
	}

	rpl = selector & 3;
	dpl = seg_desc.dpl;
1222
	cpl = ctxt->ops->cpl(ctxt);
1223 1224 1225 1226 1227 1228 1229 1230 1231

	switch (seg) {
	case VCPU_SREG_SS:
		/*
		 * segment is not a writable data segment or segment
		 * selector's RPL != CPL or segment selector's RPL != CPL
		 */
		if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
			goto exception;
A
Avi Kivity 已提交
1232
		break;
1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247
	case VCPU_SREG_CS:
		if (!(seg_desc.type & 8))
			goto exception;

		if (seg_desc.type & 4) {
			/* conforming */
			if (dpl > cpl)
				goto exception;
		} else {
			/* nonconforming */
			if (rpl > cpl || dpl != cpl)
				goto exception;
		}
		/* CS(RPL) <- CPL */
		selector = (selector & 0xfffc) | cpl;
A
Avi Kivity 已提交
1248
		break;
1249 1250 1251 1252 1253 1254 1255 1256 1257
	case VCPU_SREG_TR:
		if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
			goto exception;
		break;
	case VCPU_SREG_LDTR:
		if (seg_desc.s || seg_desc.type != 2)
			goto exception;
		break;
	default: /*  DS, ES, FS, or GS */
1258
		/*
1259 1260 1261
		 * segment is not a data or readable code segment or
		 * ((segment is a data or nonconforming code segment)
		 * and (both RPL and CPL > DPL))
1262
		 */
1263 1264 1265 1266
		if ((seg_desc.type & 0xa) == 0x8 ||
		    (((seg_desc.type & 0xc) != 0xc) &&
		     (rpl > dpl && cpl > dpl)))
			goto exception;
A
Avi Kivity 已提交
1267
		break;
1268 1269 1270 1271 1272
	}

	if (seg_desc.s) {
		/* mark segment as accessed */
		seg_desc.type |= 1;
1273
		ret = write_segment_descriptor(ctxt, selector, &seg_desc);
1274 1275 1276 1277
		if (ret != X86EMUL_CONTINUE)
			return ret;
	}
load:
1278
	ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
1279 1280 1281 1282 1283 1284
	return X86EMUL_CONTINUE;
exception:
	emulate_exception(ctxt, err_vec, err_code, true);
	return X86EMUL_PROPAGATE_FAULT;
}

1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303
static void write_register_operand(struct operand *op)
{
	/* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
	switch (op->bytes) {
	case 1:
		*(u8 *)op->addr.reg = (u8)op->val;
		break;
	case 2:
		*(u16 *)op->addr.reg = (u16)op->val;
		break;
	case 4:
		*op->addr.reg = (u32)op->val;
		break;	/* 64b: zero-extend */
	case 8:
		*op->addr.reg = op->val;
		break;
	}
}

1304
static int writeback(struct x86_emulate_ctxt *ctxt)
1305 1306 1307
{
	int rc;

1308
	switch (ctxt->dst.type) {
1309
	case OP_REG:
1310
		write_register_operand(&ctxt->dst);
A
Avi Kivity 已提交
1311
		break;
1312
	case OP_MEM:
1313
		if (ctxt->lock_prefix)
1314
			rc = segmented_cmpxchg(ctxt,
1315 1316 1317 1318
					       ctxt->dst.addr.mem,
					       &ctxt->dst.orig_val,
					       &ctxt->dst.val,
					       ctxt->dst.bytes);
1319
		else
1320
			rc = segmented_write(ctxt,
1321 1322 1323
					     ctxt->dst.addr.mem,
					     &ctxt->dst.val,
					     ctxt->dst.bytes);
1324 1325
		if (rc != X86EMUL_CONTINUE)
			return rc;
1326
		break;
A
Avi Kivity 已提交
1327
	case OP_XMM:
1328
		write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
A
Avi Kivity 已提交
1329
		break;
1330 1331
	case OP_NONE:
		/* no writeback */
1332
		break;
1333
	default:
1334
		break;
A
Avi Kivity 已提交
1335
	}
1336 1337
	return X86EMUL_CONTINUE;
}
A
Avi Kivity 已提交
1338

1339
static int em_push(struct x86_emulate_ctxt *ctxt)
1340
{
1341
	struct segmented_address addr;
1342

1343 1344
	register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes);
	addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
1345 1346 1347
	addr.seg = VCPU_SREG_SS;

	/* Disable writeback. */
1348 1349
	ctxt->dst.type = OP_NONE;
	return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes);
1350
}
1351

1352 1353 1354 1355
static int emulate_pop(struct x86_emulate_ctxt *ctxt,
		       void *dest, int len)
{
	int rc;
1356
	struct segmented_address addr;
1357

1358
	addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
1359
	addr.seg = VCPU_SREG_SS;
1360
	rc = segmented_read(ctxt, addr, dest, len);
1361 1362 1363
	if (rc != X86EMUL_CONTINUE)
		return rc;

1364
	register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
1365
	return rc;
1366 1367
}

1368 1369
static int em_pop(struct x86_emulate_ctxt *ctxt)
{
1370
	return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1371 1372
}

1373
static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1374
			void *dest, int len)
1375 1376
{
	int rc;
1377 1378
	unsigned long val, change_mask;
	int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1379
	int cpl = ctxt->ops->cpl(ctxt);
1380

1381
	rc = emulate_pop(ctxt, &val, len);
1382 1383
	if (rc != X86EMUL_CONTINUE)
		return rc;
1384

1385 1386
	change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
		| EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1387

1388 1389 1390 1391 1392 1393 1394 1395 1396 1397
	switch(ctxt->mode) {
	case X86EMUL_MODE_PROT64:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT16:
		if (cpl == 0)
			change_mask |= EFLG_IOPL;
		if (cpl <= iopl)
			change_mask |= EFLG_IF;
		break;
	case X86EMUL_MODE_VM86:
1398 1399
		if (iopl < 3)
			return emulate_gp(ctxt, 0);
1400 1401 1402 1403 1404
		change_mask |= EFLG_IF;
		break;
	default: /* real mode */
		change_mask |= (EFLG_IOPL | EFLG_IF);
		break;
1405
	}
1406 1407 1408 1409 1410

	*(unsigned long *)dest =
		(ctxt->eflags & ~change_mask) | (val & change_mask);

	return rc;
1411 1412
}

1413 1414
static int em_popf(struct x86_emulate_ctxt *ctxt)
{
1415 1416 1417 1418
	ctxt->dst.type = OP_REG;
	ctxt->dst.addr.reg = &ctxt->eflags;
	ctxt->dst.bytes = ctxt->op_bytes;
	return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1419 1420
}

1421
static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1422
{
1423
	ctxt->src.val = get_segment_selector(ctxt, seg);
1424

1425
	return em_push(ctxt);
1426 1427
}

1428
static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1429
{
1430 1431
	unsigned long selector;
	int rc;
1432

1433
	rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
1434 1435 1436
	if (rc != X86EMUL_CONTINUE)
		return rc;

1437
	rc = load_segment_descriptor(ctxt, (u16)selector, seg);
1438
	return rc;
1439 1440
}

1441
static int em_pusha(struct x86_emulate_ctxt *ctxt)
1442
{
1443
	unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
1444 1445
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RAX;
1446

1447 1448
	while (reg <= VCPU_REGS_RDI) {
		(reg == VCPU_REGS_RSP) ?
1449
		(ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
1450

1451
		rc = em_push(ctxt);
1452 1453
		if (rc != X86EMUL_CONTINUE)
			return rc;
1454

1455
		++reg;
1456 1457
	}

1458
	return rc;
1459 1460
}

1461 1462
static int em_pushf(struct x86_emulate_ctxt *ctxt)
{
1463
	ctxt->src.val =  (unsigned long)ctxt->eflags;
1464 1465 1466
	return em_push(ctxt);
}

1467
static int em_popa(struct x86_emulate_ctxt *ctxt)
1468
{
1469 1470
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RDI;
1471

1472 1473
	while (reg >= VCPU_REGS_RAX) {
		if (reg == VCPU_REGS_RSP) {
1474 1475
			register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
							ctxt->op_bytes);
1476 1477
			--reg;
		}
1478

1479
		rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
1480 1481 1482
		if (rc != X86EMUL_CONTINUE)
			break;
		--reg;
1483
	}
1484
	return rc;
1485 1486
}

1487
int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1488
{
1489
	struct x86_emulate_ops *ops = ctxt->ops;
1490
	int rc;
1491 1492 1493 1494 1495 1496
	struct desc_ptr dt;
	gva_t cs_addr;
	gva_t eip_addr;
	u16 cs, eip;

	/* TODO: Add limit checks */
1497
	ctxt->src.val = ctxt->eflags;
1498
	rc = em_push(ctxt);
1499 1500
	if (rc != X86EMUL_CONTINUE)
		return rc;
1501 1502 1503

	ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);

1504
	ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
1505
	rc = em_push(ctxt);
1506 1507
	if (rc != X86EMUL_CONTINUE)
		return rc;
1508

1509
	ctxt->src.val = ctxt->_eip;
1510
	rc = em_push(ctxt);
1511 1512 1513
	if (rc != X86EMUL_CONTINUE)
		return rc;

1514
	ops->get_idt(ctxt, &dt);
1515 1516 1517 1518

	eip_addr = dt.address + (irq << 2);
	cs_addr = dt.address + (irq << 2) + 2;

1519
	rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
1520 1521 1522
	if (rc != X86EMUL_CONTINUE)
		return rc;

1523
	rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
1524 1525 1526
	if (rc != X86EMUL_CONTINUE)
		return rc;

1527
	rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
1528 1529 1530
	if (rc != X86EMUL_CONTINUE)
		return rc;

1531
	ctxt->_eip = eip;
1532 1533 1534 1535

	return rc;
}

1536
static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
1537 1538 1539
{
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
1540
		return emulate_int_real(ctxt, irq);
1541 1542 1543 1544 1545 1546 1547 1548 1549 1550
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
	default:
		/* Protected mode interrupts unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
	}
}

1551
static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
1552
{
1553 1554 1555 1556 1557 1558 1559 1560
	int rc = X86EMUL_CONTINUE;
	unsigned long temp_eip = 0;
	unsigned long temp_eflags = 0;
	unsigned long cs = 0;
	unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
			     EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
			     EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
	unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1561

1562
	/* TODO: Add stack limit check */
1563

1564
	rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
1565

1566 1567
	if (rc != X86EMUL_CONTINUE)
		return rc;
1568

1569 1570
	if (temp_eip & ~0xffff)
		return emulate_gp(ctxt, 0);
1571

1572
	rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1573

1574 1575
	if (rc != X86EMUL_CONTINUE)
		return rc;
1576

1577
	rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
1578

1579 1580
	if (rc != X86EMUL_CONTINUE)
		return rc;
1581

1582
	rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
1583

1584 1585
	if (rc != X86EMUL_CONTINUE)
		return rc;
1586

1587
	ctxt->_eip = temp_eip;
1588 1589


1590
	if (ctxt->op_bytes == 4)
1591
		ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1592
	else if (ctxt->op_bytes == 2) {
1593 1594
		ctxt->eflags &= ~0xffff;
		ctxt->eflags |= temp_eflags;
1595
	}
1596 1597 1598 1599 1600

	ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
	ctxt->eflags |= EFLG_RESERVED_ONE_MASK;

	return rc;
1601 1602
}

1603
static int em_iret(struct x86_emulate_ctxt *ctxt)
1604
{
1605 1606
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
1607
		return emulate_iret_real(ctxt);
1608 1609 1610 1611
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
1612
	default:
1613 1614
		/* iret from protected mode unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
1615 1616 1617
	}
}

1618 1619 1620 1621 1622
static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
{
	int rc;
	unsigned short sel;

1623
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
1624

1625
	rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
1626 1627 1628
	if (rc != X86EMUL_CONTINUE)
		return rc;

1629 1630
	ctxt->_eip = 0;
	memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
1631 1632 1633
	return X86EMUL_CONTINUE;
}

1634
static int em_grp1a(struct x86_emulate_ctxt *ctxt)
1635
{
1636
	return emulate_pop(ctxt, &ctxt->dst.val, ctxt->dst.bytes);
1637 1638
}

1639
static int em_grp2(struct x86_emulate_ctxt *ctxt)
1640
{
1641
	switch (ctxt->modrm_reg) {
1642
	case 0:	/* rol */
1643
		emulate_2op_SrcB(ctxt, "rol");
1644 1645
		break;
	case 1:	/* ror */
1646
		emulate_2op_SrcB(ctxt, "ror");
1647 1648
		break;
	case 2:	/* rcl */
1649
		emulate_2op_SrcB(ctxt, "rcl");
1650 1651
		break;
	case 3:	/* rcr */
1652
		emulate_2op_SrcB(ctxt, "rcr");
1653 1654 1655
		break;
	case 4:	/* sal/shl */
	case 6:	/* sal/shl */
1656
		emulate_2op_SrcB(ctxt, "sal");
1657 1658
		break;
	case 5:	/* shr */
1659
		emulate_2op_SrcB(ctxt, "shr");
1660 1661
		break;
	case 7:	/* sar */
1662
		emulate_2op_SrcB(ctxt, "sar");
1663 1664
		break;
	}
1665
	return X86EMUL_CONTINUE;
1666 1667
}

1668
static int em_grp3(struct x86_emulate_ctxt *ctxt)
1669
{
1670 1671
	unsigned long *rax = &ctxt->regs[VCPU_REGS_RAX];
	unsigned long *rdx = &ctxt->regs[VCPU_REGS_RDX];
1672
	u8 de = 0;
1673

1674
	switch (ctxt->modrm_reg) {
1675
	case 0 ... 1:	/* test */
1676
		emulate_2op_SrcV(ctxt, "test");
1677 1678
		break;
	case 2:	/* not */
1679
		ctxt->dst.val = ~ctxt->dst.val;
1680 1681
		break;
	case 3:	/* neg */
1682
		emulate_1op(ctxt, "neg");
1683
		break;
1684
	case 4: /* mul */
1685 1686
		emulate_1op_rax_rdx("mul", ctxt->src, *rax, *rdx,
				    ctxt->eflags, de);
1687 1688
		break;
	case 5: /* imul */
1689 1690
		emulate_1op_rax_rdx("imul", ctxt->src, *rax, *rdx,
				    ctxt->eflags, de);
1691 1692
		break;
	case 6: /* div */
1693 1694
		emulate_1op_rax_rdx("div", ctxt->src, *rax, *rdx,
				    ctxt->eflags, de);
1695 1696
		break;
	case 7: /* idiv */
1697 1698
		emulate_1op_rax_rdx("idiv", ctxt->src, *rax, *rdx,
				    ctxt->eflags, de);
1699
		break;
1700
	default:
1701
		return X86EMUL_UNHANDLEABLE;
1702
	}
1703 1704
	if (de)
		return emulate_de(ctxt);
1705
	return X86EMUL_CONTINUE;
1706 1707
}

1708
static int em_grp45(struct x86_emulate_ctxt *ctxt)
1709
{
1710
	int rc = X86EMUL_CONTINUE;
1711

1712
	switch (ctxt->modrm_reg) {
1713
	case 0:	/* inc */
1714
		emulate_1op(ctxt, "inc");
1715 1716
		break;
	case 1:	/* dec */
1717
		emulate_1op(ctxt, "dec");
1718
		break;
1719 1720
	case 2: /* call near abs */ {
		long int old_eip;
1721 1722 1723
		old_eip = ctxt->_eip;
		ctxt->_eip = ctxt->src.val;
		ctxt->src.val = old_eip;
1724
		rc = em_push(ctxt);
1725 1726
		break;
	}
1727
	case 4: /* jmp abs */
1728
		ctxt->_eip = ctxt->src.val;
1729
		break;
1730 1731 1732
	case 5: /* jmp far */
		rc = em_jmp_far(ctxt);
		break;
1733
	case 6:	/* push */
1734
		rc = em_push(ctxt);
1735 1736
		break;
	}
1737
	return rc;
1738 1739
}

1740
static int em_grp9(struct x86_emulate_ctxt *ctxt)
1741
{
1742
	u64 old = ctxt->dst.orig_val64;
1743

1744 1745 1746 1747
	if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
	    ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
		ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
		ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1748
		ctxt->eflags &= ~EFLG_ZF;
1749
	} else {
1750 1751
		ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
			(u32) ctxt->regs[VCPU_REGS_RBX];
1752

1753
		ctxt->eflags |= EFLG_ZF;
1754
	}
1755
	return X86EMUL_CONTINUE;
1756 1757
}

1758 1759
static int em_ret(struct x86_emulate_ctxt *ctxt)
{
1760 1761 1762
	ctxt->dst.type = OP_REG;
	ctxt->dst.addr.reg = &ctxt->_eip;
	ctxt->dst.bytes = ctxt->op_bytes;
1763 1764 1765
	return em_pop(ctxt);
}

1766
static int em_ret_far(struct x86_emulate_ctxt *ctxt)
1767 1768 1769 1770
{
	int rc;
	unsigned long cs;

1771
	rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1772
	if (rc != X86EMUL_CONTINUE)
1773
		return rc;
1774 1775 1776
	if (ctxt->op_bytes == 4)
		ctxt->_eip = (u32)ctxt->_eip;
	rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1777
	if (rc != X86EMUL_CONTINUE)
1778
		return rc;
1779
	rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
1780 1781 1782
	return rc;
}

1783
static int emulate_load_segment(struct x86_emulate_ctxt *ctxt, int seg)
1784 1785 1786 1787
{
	unsigned short sel;
	int rc;

1788
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
1789

1790
	rc = load_segment_descriptor(ctxt, sel, seg);
1791 1792 1793
	if (rc != X86EMUL_CONTINUE)
		return rc;

1794
	ctxt->dst.val = ctxt->src.val;
1795 1796 1797
	return rc;
}

1798
static void
1799
setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1800
			struct desc_struct *cs, struct desc_struct *ss)
1801
{
1802 1803
	u16 selector;

1804
	memset(cs, 0, sizeof(struct desc_struct));
1805
	ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
1806
	memset(ss, 0, sizeof(struct desc_struct));
1807 1808

	cs->l = 0;		/* will be adjusted later */
1809
	set_desc_base(cs, 0);	/* flat segment */
1810
	cs->g = 1;		/* 4kb granularity */
1811
	set_desc_limit(cs, 0xfffff);	/* 4GB limit */
1812 1813 1814
	cs->type = 0x0b;	/* Read, Execute, Accessed */
	cs->s = 1;
	cs->dpl = 0;		/* will be adjusted later */
1815 1816
	cs->p = 1;
	cs->d = 1;
1817

1818 1819
	set_desc_base(ss, 0);	/* flat segment */
	set_desc_limit(ss, 0xfffff);	/* 4GB limit */
1820 1821 1822
	ss->g = 1;		/* 4kb granularity */
	ss->s = 1;
	ss->type = 0x03;	/* Read/Write, Accessed */
1823
	ss->d = 1;		/* 32bit stack segment */
1824
	ss->dpl = 0;
1825
	ss->p = 1;
1826 1827
}

1828
static int em_syscall(struct x86_emulate_ctxt *ctxt)
1829
{
1830
	struct x86_emulate_ops *ops = ctxt->ops;
1831
	struct desc_struct cs, ss;
1832
	u64 msr_data;
1833
	u16 cs_sel, ss_sel;
1834
	u64 efer = 0;
1835 1836

	/* syscall is not available in real mode */
1837
	if (ctxt->mode == X86EMUL_MODE_REAL ||
1838 1839
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_ud(ctxt);
1840

1841
	ops->get_msr(ctxt, MSR_EFER, &efer);
1842
	setup_syscalls_segments(ctxt, &cs, &ss);
1843

1844
	ops->get_msr(ctxt, MSR_STAR, &msr_data);
1845
	msr_data >>= 32;
1846 1847
	cs_sel = (u16)(msr_data & 0xfffc);
	ss_sel = (u16)(msr_data + 8);
1848

1849
	if (efer & EFER_LMA) {
1850
		cs.d = 0;
1851 1852
		cs.l = 1;
	}
1853 1854
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
1855

1856
	ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
1857
	if (efer & EFER_LMA) {
1858
#ifdef CONFIG_X86_64
1859
		ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1860

1861
		ops->get_msr(ctxt,
1862 1863
			     ctxt->mode == X86EMUL_MODE_PROT64 ?
			     MSR_LSTAR : MSR_CSTAR, &msr_data);
1864
		ctxt->_eip = msr_data;
1865

1866
		ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
1867 1868 1869 1870
		ctxt->eflags &= ~(msr_data | EFLG_RF);
#endif
	} else {
		/* legacy mode */
1871
		ops->get_msr(ctxt, MSR_STAR, &msr_data);
1872
		ctxt->_eip = (u32)msr_data;
1873 1874 1875 1876

		ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
	}

1877
	return X86EMUL_CONTINUE;
1878 1879
}

1880
static int em_sysenter(struct x86_emulate_ctxt *ctxt)
1881
{
1882
	struct x86_emulate_ops *ops = ctxt->ops;
1883
	struct desc_struct cs, ss;
1884
	u64 msr_data;
1885
	u16 cs_sel, ss_sel;
1886
	u64 efer = 0;
1887

1888
	ops->get_msr(ctxt, MSR_EFER, &efer);
1889
	/* inject #GP if in real mode */
1890 1891
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return emulate_gp(ctxt, 0);
1892 1893 1894 1895

	/* XXX sysenter/sysexit have not been tested in 64bit mode.
	* Therefore, we inject an #UD.
	*/
1896 1897
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return emulate_ud(ctxt);
1898

1899
	setup_syscalls_segments(ctxt, &cs, &ss);
1900

1901
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
1902 1903
	switch (ctxt->mode) {
	case X86EMUL_MODE_PROT32:
1904 1905
		if ((msr_data & 0xfffc) == 0x0)
			return emulate_gp(ctxt, 0);
1906 1907
		break;
	case X86EMUL_MODE_PROT64:
1908 1909
		if (msr_data == 0x0)
			return emulate_gp(ctxt, 0);
1910 1911 1912 1913
		break;
	}

	ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1914 1915 1916 1917
	cs_sel = (u16)msr_data;
	cs_sel &= ~SELECTOR_RPL_MASK;
	ss_sel = cs_sel + 8;
	ss_sel &= ~SELECTOR_RPL_MASK;
1918
	if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
1919
		cs.d = 0;
1920 1921 1922
		cs.l = 1;
	}

1923 1924
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
1925

1926
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
1927
	ctxt->_eip = msr_data;
1928

1929
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
1930
	ctxt->regs[VCPU_REGS_RSP] = msr_data;
1931

1932
	return X86EMUL_CONTINUE;
1933 1934
}

1935
static int em_sysexit(struct x86_emulate_ctxt *ctxt)
1936
{
1937
	struct x86_emulate_ops *ops = ctxt->ops;
1938
	struct desc_struct cs, ss;
1939 1940
	u64 msr_data;
	int usermode;
X
Xiao Guangrong 已提交
1941
	u16 cs_sel = 0, ss_sel = 0;
1942

1943 1944
	/* inject #GP if in real mode or Virtual 8086 mode */
	if (ctxt->mode == X86EMUL_MODE_REAL ||
1945 1946
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_gp(ctxt, 0);
1947

1948
	setup_syscalls_segments(ctxt, &cs, &ss);
1949

1950
	if ((ctxt->rex_prefix & 0x8) != 0x0)
1951 1952 1953 1954 1955 1956
		usermode = X86EMUL_MODE_PROT64;
	else
		usermode = X86EMUL_MODE_PROT32;

	cs.dpl = 3;
	ss.dpl = 3;
1957
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
1958 1959
	switch (usermode) {
	case X86EMUL_MODE_PROT32:
1960
		cs_sel = (u16)(msr_data + 16);
1961 1962
		if ((msr_data & 0xfffc) == 0x0)
			return emulate_gp(ctxt, 0);
1963
		ss_sel = (u16)(msr_data + 24);
1964 1965
		break;
	case X86EMUL_MODE_PROT64:
1966
		cs_sel = (u16)(msr_data + 32);
1967 1968
		if (msr_data == 0x0)
			return emulate_gp(ctxt, 0);
1969 1970
		ss_sel = cs_sel + 8;
		cs.d = 0;
1971 1972 1973
		cs.l = 1;
		break;
	}
1974 1975
	cs_sel |= SELECTOR_RPL_MASK;
	ss_sel |= SELECTOR_RPL_MASK;
1976

1977 1978
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
1979

1980 1981
	ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
	ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
1982

1983
	return X86EMUL_CONTINUE;
1984 1985
}

1986
static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
1987 1988 1989 1990 1991 1992 1993
{
	int iopl;
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return false;
	if (ctxt->mode == X86EMUL_MODE_VM86)
		return true;
	iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1994
	return ctxt->ops->cpl(ctxt) > iopl;
1995 1996 1997 1998 1999
}

static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
					    u16 port, u16 len)
{
2000
	struct x86_emulate_ops *ops = ctxt->ops;
2001
	struct desc_struct tr_seg;
2002
	u32 base3;
2003
	int r;
2004
	u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2005
	unsigned mask = (1 << len) - 1;
2006
	unsigned long base;
2007

2008
	ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2009
	if (!tr_seg.p)
2010
		return false;
2011
	if (desc_limit_scaled(&tr_seg) < 103)
2012
		return false;
2013 2014 2015 2016
	base = get_desc_base(&tr_seg);
#ifdef CONFIG_X86_64
	base |= ((u64)base3) << 32;
#endif
2017
	r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2018 2019
	if (r != X86EMUL_CONTINUE)
		return false;
2020
	if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2021
		return false;
2022
	r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2023 2024 2025 2026 2027 2028 2029 2030 2031 2032
	if (r != X86EMUL_CONTINUE)
		return false;
	if ((perm >> bit_idx) & mask)
		return false;
	return true;
}

static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
				 u16 port, u16 len)
{
2033 2034 2035
	if (ctxt->perm_ok)
		return true;

2036 2037
	if (emulator_bad_iopl(ctxt))
		if (!emulator_io_port_access_allowed(ctxt, port, len))
2038
			return false;
2039 2040 2041

	ctxt->perm_ok = true;

2042 2043 2044
	return true;
}

2045 2046 2047
static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
				struct tss_segment_16 *tss)
{
2048
	tss->ip = ctxt->_eip;
2049
	tss->flag = ctxt->eflags;
2050 2051 2052 2053 2054 2055 2056 2057
	tss->ax = ctxt->regs[VCPU_REGS_RAX];
	tss->cx = ctxt->regs[VCPU_REGS_RCX];
	tss->dx = ctxt->regs[VCPU_REGS_RDX];
	tss->bx = ctxt->regs[VCPU_REGS_RBX];
	tss->sp = ctxt->regs[VCPU_REGS_RSP];
	tss->bp = ctxt->regs[VCPU_REGS_RBP];
	tss->si = ctxt->regs[VCPU_REGS_RSI];
	tss->di = ctxt->regs[VCPU_REGS_RDI];
2058

2059 2060 2061 2062 2063
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2064 2065 2066 2067 2068 2069 2070
}

static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
				 struct tss_segment_16 *tss)
{
	int ret;

2071
	ctxt->_eip = tss->ip;
2072
	ctxt->eflags = tss->flag | 2;
2073 2074 2075 2076 2077 2078 2079 2080
	ctxt->regs[VCPU_REGS_RAX] = tss->ax;
	ctxt->regs[VCPU_REGS_RCX] = tss->cx;
	ctxt->regs[VCPU_REGS_RDX] = tss->dx;
	ctxt->regs[VCPU_REGS_RBX] = tss->bx;
	ctxt->regs[VCPU_REGS_RSP] = tss->sp;
	ctxt->regs[VCPU_REGS_RBP] = tss->bp;
	ctxt->regs[VCPU_REGS_RSI] = tss->si;
	ctxt->regs[VCPU_REGS_RDI] = tss->di;
2081 2082 2083 2084 2085

	/*
	 * SDM says that segment selectors are loaded before segment
	 * descriptors
	 */
2086 2087 2088 2089 2090
	set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2091 2092 2093 2094 2095

	/*
	 * Now load segment descriptors. If fault happenes at this stage
	 * it is handled in a context of new task
	 */
2096
	ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
2097 2098
	if (ret != X86EMUL_CONTINUE)
		return ret;
2099
	ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
2100 2101
	if (ret != X86EMUL_CONTINUE)
		return ret;
2102
	ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
2103 2104
	if (ret != X86EMUL_CONTINUE)
		return ret;
2105
	ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
2106 2107
	if (ret != X86EMUL_CONTINUE)
		return ret;
2108
	ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
2109 2110 2111 2112 2113 2114 2115 2116 2117 2118
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_16(struct x86_emulate_ctxt *ctxt,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
2119
	struct x86_emulate_ops *ops = ctxt->ops;
2120 2121
	struct tss_segment_16 tss_seg;
	int ret;
2122
	u32 new_tss_base = get_desc_base(new_desc);
2123

2124
	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2125
			    &ctxt->exception);
2126
	if (ret != X86EMUL_CONTINUE)
2127 2128 2129
		/* FIXME: need to provide precise fault address */
		return ret;

2130
	save_state_to_tss16(ctxt, &tss_seg);
2131

2132
	ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2133
			     &ctxt->exception);
2134
	if (ret != X86EMUL_CONTINUE)
2135 2136 2137
		/* FIXME: need to provide precise fault address */
		return ret;

2138
	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2139
			    &ctxt->exception);
2140
	if (ret != X86EMUL_CONTINUE)
2141 2142 2143 2144 2145 2146
		/* FIXME: need to provide precise fault address */
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

2147
		ret = ops->write_std(ctxt, new_tss_base,
2148 2149
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
2150
				     &ctxt->exception);
2151
		if (ret != X86EMUL_CONTINUE)
2152 2153 2154 2155
			/* FIXME: need to provide precise fault address */
			return ret;
	}

2156
	return load_state_from_tss16(ctxt, &tss_seg);
2157 2158 2159 2160 2161
}

static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
				struct tss_segment_32 *tss)
{
2162
	tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
2163
	tss->eip = ctxt->_eip;
2164
	tss->eflags = ctxt->eflags;
2165 2166 2167 2168 2169 2170 2171 2172
	tss->eax = ctxt->regs[VCPU_REGS_RAX];
	tss->ecx = ctxt->regs[VCPU_REGS_RCX];
	tss->edx = ctxt->regs[VCPU_REGS_RDX];
	tss->ebx = ctxt->regs[VCPU_REGS_RBX];
	tss->esp = ctxt->regs[VCPU_REGS_RSP];
	tss->ebp = ctxt->regs[VCPU_REGS_RBP];
	tss->esi = ctxt->regs[VCPU_REGS_RSI];
	tss->edi = ctxt->regs[VCPU_REGS_RDI];
2173

2174 2175 2176 2177 2178 2179 2180
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
	tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
	tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2181 2182 2183 2184 2185 2186 2187
}

static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
				 struct tss_segment_32 *tss)
{
	int ret;

2188
	if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
2189
		return emulate_gp(ctxt, 0);
2190
	ctxt->_eip = tss->eip;
2191
	ctxt->eflags = tss->eflags | 2;
2192 2193 2194 2195 2196 2197 2198 2199
	ctxt->regs[VCPU_REGS_RAX] = tss->eax;
	ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
	ctxt->regs[VCPU_REGS_RDX] = tss->edx;
	ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
	ctxt->regs[VCPU_REGS_RSP] = tss->esp;
	ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
	ctxt->regs[VCPU_REGS_RSI] = tss->esi;
	ctxt->regs[VCPU_REGS_RDI] = tss->edi;
2200 2201 2202 2203 2204

	/*
	 * SDM says that segment selectors are loaded before segment
	 * descriptors
	 */
2205 2206 2207 2208 2209 2210 2211
	set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
	set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
	set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
2212 2213 2214 2215 2216

	/*
	 * Now load segment descriptors. If fault happenes at this stage
	 * it is handled in a context of new task
	 */
2217
	ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2218 2219
	if (ret != X86EMUL_CONTINUE)
		return ret;
2220
	ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
2221 2222
	if (ret != X86EMUL_CONTINUE)
		return ret;
2223
	ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
2224 2225
	if (ret != X86EMUL_CONTINUE)
		return ret;
2226
	ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
2227 2228
	if (ret != X86EMUL_CONTINUE)
		return ret;
2229
	ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
2230 2231
	if (ret != X86EMUL_CONTINUE)
		return ret;
2232
	ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
2233 2234
	if (ret != X86EMUL_CONTINUE)
		return ret;
2235
	ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
2236 2237 2238 2239 2240 2241 2242 2243 2244 2245
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_32(struct x86_emulate_ctxt *ctxt,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
2246
	struct x86_emulate_ops *ops = ctxt->ops;
2247 2248
	struct tss_segment_32 tss_seg;
	int ret;
2249
	u32 new_tss_base = get_desc_base(new_desc);
2250

2251
	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2252
			    &ctxt->exception);
2253
	if (ret != X86EMUL_CONTINUE)
2254 2255 2256
		/* FIXME: need to provide precise fault address */
		return ret;

2257
	save_state_to_tss32(ctxt, &tss_seg);
2258

2259
	ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2260
			     &ctxt->exception);
2261
	if (ret != X86EMUL_CONTINUE)
2262 2263 2264
		/* FIXME: need to provide precise fault address */
		return ret;

2265
	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2266
			    &ctxt->exception);
2267
	if (ret != X86EMUL_CONTINUE)
2268 2269 2270 2271 2272 2273
		/* FIXME: need to provide precise fault address */
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

2274
		ret = ops->write_std(ctxt, new_tss_base,
2275 2276
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
2277
				     &ctxt->exception);
2278
		if (ret != X86EMUL_CONTINUE)
2279 2280 2281 2282
			/* FIXME: need to provide precise fault address */
			return ret;
	}

2283
	return load_state_from_tss32(ctxt, &tss_seg);
2284 2285 2286
}

static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2287 2288
				   u16 tss_selector, int reason,
				   bool has_error_code, u32 error_code)
2289
{
2290
	struct x86_emulate_ops *ops = ctxt->ops;
2291 2292
	struct desc_struct curr_tss_desc, next_tss_desc;
	int ret;
2293
	u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
2294
	ulong old_tss_base =
2295
		ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
2296
	u32 desc_limit;
2297 2298 2299

	/* FIXME: old_tss_base == ~0 ? */

2300
	ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
2301 2302
	if (ret != X86EMUL_CONTINUE)
		return ret;
2303
	ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
2304 2305 2306 2307 2308 2309 2310
	if (ret != X86EMUL_CONTINUE)
		return ret;

	/* FIXME: check that next_tss_desc is tss */

	if (reason != TASK_SWITCH_IRET) {
		if ((tss_selector & 3) > next_tss_desc.dpl ||
2311
		    ops->cpl(ctxt) > next_tss_desc.dpl)
2312
			return emulate_gp(ctxt, 0);
2313 2314
	}

2315 2316 2317 2318
	desc_limit = desc_limit_scaled(&next_tss_desc);
	if (!next_tss_desc.p ||
	    ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
	     desc_limit < 0x2b)) {
2319
		emulate_ts(ctxt, tss_selector & 0xfffc);
2320 2321 2322 2323 2324
		return X86EMUL_PROPAGATE_FAULT;
	}

	if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
		curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2325
		write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336
	}

	if (reason == TASK_SWITCH_IRET)
		ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;

	/* set back link to prev task only if NT bit is set in eflags
	   note that old_tss_sel is not used afetr this point */
	if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
		old_tss_sel = 0xffff;

	if (next_tss_desc.type & 8)
2337
		ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
2338 2339
				     old_tss_base, &next_tss_desc);
	else
2340
		ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
2341
				     old_tss_base, &next_tss_desc);
2342 2343
	if (ret != X86EMUL_CONTINUE)
		return ret;
2344 2345 2346 2347 2348 2349

	if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
		ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;

	if (reason != TASK_SWITCH_IRET) {
		next_tss_desc.type |= (1 << 1); /* set busy flag */
2350
		write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
2351 2352
	}

2353
	ops->set_cr(ctxt, 0,  ops->get_cr(ctxt, 0) | X86_CR0_TS);
2354
	ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
2355

2356
	if (has_error_code) {
2357 2358 2359
		ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
		ctxt->lock_prefix = 0;
		ctxt->src.val = (unsigned long) error_code;
2360
		ret = em_push(ctxt);
2361 2362
	}

2363 2364 2365 2366
	return ret;
}

int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2367 2368
			 u16 tss_selector, int reason,
			 bool has_error_code, u32 error_code)
2369 2370 2371
{
	int rc;

2372 2373
	ctxt->_eip = ctxt->eip;
	ctxt->dst.type = OP_NONE;
2374

2375
	rc = emulator_do_task_switch(ctxt, tss_selector, reason,
2376
				     has_error_code, error_code);
2377

2378
	if (rc == X86EMUL_CONTINUE)
2379
		ctxt->eip = ctxt->_eip;
2380

2381
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2382 2383
}

2384
static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
2385
			    int reg, struct operand *op)
2386 2387 2388
{
	int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;

2389 2390
	register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
	op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
2391
	op->addr.mem.seg = seg;
2392 2393
}

2394 2395 2396 2397 2398 2399
static int em_das(struct x86_emulate_ctxt *ctxt)
{
	u8 al, old_al;
	bool af, cf, old_cf;

	cf = ctxt->eflags & X86_EFLAGS_CF;
2400
	al = ctxt->dst.val;
2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417

	old_al = al;
	old_cf = cf;
	cf = false;
	af = ctxt->eflags & X86_EFLAGS_AF;
	if ((al & 0x0f) > 9 || af) {
		al -= 6;
		cf = old_cf | (al >= 250);
		af = true;
	} else {
		af = false;
	}
	if (old_al > 0x99 || old_cf) {
		al -= 0x60;
		cf = true;
	}

2418
	ctxt->dst.val = al;
2419
	/* Set PF, ZF, SF */
2420 2421 2422
	ctxt->src.type = OP_IMM;
	ctxt->src.val = 0;
	ctxt->src.bytes = 1;
2423
	emulate_2op_SrcV(ctxt, "or");
2424 2425 2426 2427 2428 2429 2430 2431
	ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
	if (cf)
		ctxt->eflags |= X86_EFLAGS_CF;
	if (af)
		ctxt->eflags |= X86_EFLAGS_AF;
	return X86EMUL_CONTINUE;
}

2432 2433 2434 2435 2436 2437
static int em_call_far(struct x86_emulate_ctxt *ctxt)
{
	u16 sel, old_cs;
	ulong old_eip;
	int rc;

2438
	old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2439
	old_eip = ctxt->_eip;
2440

2441
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2442
	if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
2443 2444
		return X86EMUL_CONTINUE;

2445 2446
	ctxt->_eip = 0;
	memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
2447

2448
	ctxt->src.val = old_cs;
2449
	rc = em_push(ctxt);
2450 2451 2452
	if (rc != X86EMUL_CONTINUE)
		return rc;

2453
	ctxt->src.val = old_eip;
2454
	return em_push(ctxt);
2455 2456
}

2457 2458 2459 2460
static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
{
	int rc;

2461 2462 2463 2464
	ctxt->dst.type = OP_REG;
	ctxt->dst.addr.reg = &ctxt->_eip;
	ctxt->dst.bytes = ctxt->op_bytes;
	rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
2465 2466
	if (rc != X86EMUL_CONTINUE)
		return rc;
2467
	register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
2468 2469 2470
	return X86EMUL_CONTINUE;
}

2471 2472
static int em_add(struct x86_emulate_ctxt *ctxt)
{
2473
	emulate_2op_SrcV(ctxt, "add");
2474 2475 2476 2477 2478
	return X86EMUL_CONTINUE;
}

static int em_or(struct x86_emulate_ctxt *ctxt)
{
2479
	emulate_2op_SrcV(ctxt, "or");
2480 2481 2482 2483 2484
	return X86EMUL_CONTINUE;
}

static int em_adc(struct x86_emulate_ctxt *ctxt)
{
2485
	emulate_2op_SrcV(ctxt, "adc");
2486 2487 2488 2489 2490
	return X86EMUL_CONTINUE;
}

static int em_sbb(struct x86_emulate_ctxt *ctxt)
{
2491
	emulate_2op_SrcV(ctxt, "sbb");
2492 2493 2494 2495 2496
	return X86EMUL_CONTINUE;
}

static int em_and(struct x86_emulate_ctxt *ctxt)
{
2497
	emulate_2op_SrcV(ctxt, "and");
2498 2499 2500 2501 2502
	return X86EMUL_CONTINUE;
}

static int em_sub(struct x86_emulate_ctxt *ctxt)
{
2503
	emulate_2op_SrcV(ctxt, "sub");
2504 2505 2506 2507 2508
	return X86EMUL_CONTINUE;
}

static int em_xor(struct x86_emulate_ctxt *ctxt)
{
2509
	emulate_2op_SrcV(ctxt, "xor");
2510 2511 2512 2513 2514
	return X86EMUL_CONTINUE;
}

static int em_cmp(struct x86_emulate_ctxt *ctxt)
{
2515
	emulate_2op_SrcV(ctxt, "cmp");
2516
	/* Disable writeback. */
2517
	ctxt->dst.type = OP_NONE;
2518 2519 2520
	return X86EMUL_CONTINUE;
}

2521 2522
static int em_test(struct x86_emulate_ctxt *ctxt)
{
2523
	emulate_2op_SrcV(ctxt, "test");
2524 2525 2526
	return X86EMUL_CONTINUE;
}

2527 2528 2529
static int em_xchg(struct x86_emulate_ctxt *ctxt)
{
	/* Write back the register source. */
2530 2531
	ctxt->src.val = ctxt->dst.val;
	write_register_operand(&ctxt->src);
2532 2533

	/* Write back the memory destination with implicit LOCK prefix. */
2534 2535
	ctxt->dst.val = ctxt->src.orig_val;
	ctxt->lock_prefix = 1;
2536 2537 2538
	return X86EMUL_CONTINUE;
}

2539
static int em_imul(struct x86_emulate_ctxt *ctxt)
2540
{
2541
	emulate_2op_SrcV_nobyte(ctxt, "imul");
2542 2543 2544
	return X86EMUL_CONTINUE;
}

2545 2546
static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
{
2547
	ctxt->dst.val = ctxt->src2.val;
2548 2549 2550
	return em_imul(ctxt);
}

2551 2552
static int em_cwd(struct x86_emulate_ctxt *ctxt)
{
2553 2554 2555 2556
	ctxt->dst.type = OP_REG;
	ctxt->dst.bytes = ctxt->src.bytes;
	ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
	ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
2557 2558 2559 2560

	return X86EMUL_CONTINUE;
}

2561 2562 2563 2564
static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
{
	u64 tsc = 0;

2565
	ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
2566 2567
	ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
	ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
2568 2569 2570
	return X86EMUL_CONTINUE;
}

2571 2572
static int em_mov(struct x86_emulate_ctxt *ctxt)
{
2573
	ctxt->dst.val = ctxt->src.val;
2574 2575 2576
	return X86EMUL_CONTINUE;
}

2577 2578
static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
{
2579
	if (ctxt->modrm_reg > VCPU_SREG_GS)
2580 2581
		return emulate_ud(ctxt);

2582
	ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
2583 2584 2585 2586 2587
	return X86EMUL_CONTINUE;
}

static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
{
2588
	u16 sel = ctxt->src.val;
2589

2590
	if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
2591 2592
		return emulate_ud(ctxt);

2593
	if (ctxt->modrm_reg == VCPU_SREG_SS)
2594 2595 2596
		ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;

	/* Disable writeback. */
2597 2598
	ctxt->dst.type = OP_NONE;
	return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
2599 2600
}

2601 2602
static int em_movdqu(struct x86_emulate_ctxt *ctxt)
{
2603
	memcpy(&ctxt->dst.vec_val, &ctxt->src.vec_val, ctxt->op_bytes);
2604 2605 2606
	return X86EMUL_CONTINUE;
}

2607 2608
static int em_invlpg(struct x86_emulate_ctxt *ctxt)
{
2609 2610 2611
	int rc;
	ulong linear;

2612
	rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
2613
	if (rc == X86EMUL_CONTINUE)
2614
		ctxt->ops->invlpg(ctxt, linear);
2615
	/* Disable writeback. */
2616
	ctxt->dst.type = OP_NONE;
2617 2618 2619
	return X86EMUL_CONTINUE;
}

2620 2621 2622 2623 2624 2625 2626 2627 2628 2629
static int em_clts(struct x86_emulate_ctxt *ctxt)
{
	ulong cr0;

	cr0 = ctxt->ops->get_cr(ctxt, 0);
	cr0 &= ~X86_CR0_TS;
	ctxt->ops->set_cr(ctxt, 0, cr0);
	return X86EMUL_CONTINUE;
}

2630 2631 2632 2633
static int em_vmcall(struct x86_emulate_ctxt *ctxt)
{
	int rc;

2634
	if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
2635 2636 2637 2638 2639 2640 2641
		return X86EMUL_UNHANDLEABLE;

	rc = ctxt->ops->fix_hypercall(ctxt);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	/* Let the processor re-execute the fixed hypercall */
2642
	ctxt->_eip = ctxt->eip;
2643
	/* Disable writeback. */
2644
	ctxt->dst.type = OP_NONE;
2645 2646 2647 2648 2649 2650 2651 2652
	return X86EMUL_CONTINUE;
}

static int em_lgdt(struct x86_emulate_ctxt *ctxt)
{
	struct desc_ptr desc_ptr;
	int rc;

2653
	rc = read_descriptor(ctxt, ctxt->src.addr.mem,
2654
			     &desc_ptr.size, &desc_ptr.address,
2655
			     ctxt->op_bytes);
2656 2657 2658 2659
	if (rc != X86EMUL_CONTINUE)
		return rc;
	ctxt->ops->set_gdt(ctxt, &desc_ptr);
	/* Disable writeback. */
2660
	ctxt->dst.type = OP_NONE;
2661 2662 2663
	return X86EMUL_CONTINUE;
}

2664
static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
2665 2666 2667
{
	int rc;

2668 2669
	rc = ctxt->ops->fix_hypercall(ctxt);

2670
	/* Disable writeback. */
2671
	ctxt->dst.type = OP_NONE;
2672 2673 2674 2675 2676 2677 2678 2679
	return rc;
}

static int em_lidt(struct x86_emulate_ctxt *ctxt)
{
	struct desc_ptr desc_ptr;
	int rc;

2680
	rc = read_descriptor(ctxt, ctxt->src.addr.mem,
2681
			     &desc_ptr.size, &desc_ptr.address,
2682
			     ctxt->op_bytes);
2683 2684 2685 2686
	if (rc != X86EMUL_CONTINUE)
		return rc;
	ctxt->ops->set_idt(ctxt, &desc_ptr);
	/* Disable writeback. */
2687
	ctxt->dst.type = OP_NONE;
2688 2689 2690 2691 2692
	return X86EMUL_CONTINUE;
}

static int em_smsw(struct x86_emulate_ctxt *ctxt)
{
2693 2694
	ctxt->dst.bytes = 2;
	ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
2695 2696 2697 2698 2699 2700
	return X86EMUL_CONTINUE;
}

static int em_lmsw(struct x86_emulate_ctxt *ctxt)
{
	ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
2701 2702
			  | (ctxt->src.val & 0x0f));
	ctxt->dst.type = OP_NONE;
2703 2704 2705
	return X86EMUL_CONTINUE;
}

2706 2707
static int em_loop(struct x86_emulate_ctxt *ctxt)
{
2708 2709 2710 2711
	register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
	if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
	    (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
		jmp_rel(ctxt, ctxt->src.val);
2712 2713 2714 2715 2716 2717

	return X86EMUL_CONTINUE;
}

static int em_jcxz(struct x86_emulate_ctxt *ctxt)
{
2718 2719
	if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
		jmp_rel(ctxt, ctxt->src.val);
2720 2721 2722 2723

	return X86EMUL_CONTINUE;
}

2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742
static int em_cli(struct x86_emulate_ctxt *ctxt)
{
	if (emulator_bad_iopl(ctxt))
		return emulate_gp(ctxt, 0);

	ctxt->eflags &= ~X86_EFLAGS_IF;
	return X86EMUL_CONTINUE;
}

static int em_sti(struct x86_emulate_ctxt *ctxt)
{
	if (emulator_bad_iopl(ctxt))
		return emulate_gp(ctxt, 0);

	ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
	ctxt->eflags |= X86_EFLAGS_IF;
	return X86EMUL_CONTINUE;
}

2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756
static bool valid_cr(int nr)
{
	switch (nr) {
	case 0:
	case 2 ... 4:
	case 8:
		return true;
	default:
		return false;
	}
}

static int check_cr_read(struct x86_emulate_ctxt *ctxt)
{
2757
	if (!valid_cr(ctxt->modrm_reg))
2758 2759 2760 2761 2762 2763 2764
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_cr_write(struct x86_emulate_ctxt *ctxt)
{
2765 2766
	u64 new_val = ctxt->src.val64;
	int cr = ctxt->modrm_reg;
2767
	u64 efer = 0;
2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784

	static u64 cr_reserved_bits[] = {
		0xffffffff00000000ULL,
		0, 0, 0, /* CR3 checked later */
		CR4_RESERVED_BITS,
		0, 0, 0,
		CR8_RESERVED_BITS,
	};

	if (!valid_cr(cr))
		return emulate_ud(ctxt);

	if (new_val & cr_reserved_bits[cr])
		return emulate_gp(ctxt, 0);

	switch (cr) {
	case 0: {
2785
		u64 cr4;
2786 2787 2788 2789
		if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
		    ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
			return emulate_gp(ctxt, 0);

2790 2791
		cr4 = ctxt->ops->get_cr(ctxt, 4);
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2792 2793 2794 2795 2796 2797 2798 2799 2800 2801

		if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
		    !(cr4 & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	case 3: {
		u64 rsvd = 0;

2802 2803
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
		if (efer & EFER_LMA)
2804
			rsvd = CR3_L_MODE_RESERVED_BITS;
2805
		else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
2806
			rsvd = CR3_PAE_RESERVED_BITS;
2807
		else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
2808 2809 2810 2811 2812 2813 2814 2815
			rsvd = CR3_NONPAE_RESERVED_BITS;

		if (new_val & rsvd)
			return emulate_gp(ctxt, 0);

		break;
		}
	case 4: {
2816
		u64 cr4;
2817

2818 2819
		cr4 = ctxt->ops->get_cr(ctxt, 4);
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830

		if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	}

	return X86EMUL_CONTINUE;
}

2831 2832 2833 2834
static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
{
	unsigned long dr7;

2835
	ctxt->ops->get_dr(ctxt, 7, &dr7);
2836 2837 2838 2839 2840 2841 2842

	/* Check if DR7.Global_Enable is set */
	return dr7 & (1 << 13);
}

static int check_dr_read(struct x86_emulate_ctxt *ctxt)
{
2843
	int dr = ctxt->modrm_reg;
2844 2845 2846 2847 2848
	u64 cr4;

	if (dr > 7)
		return emulate_ud(ctxt);

2849
	cr4 = ctxt->ops->get_cr(ctxt, 4);
2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860
	if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
		return emulate_ud(ctxt);

	if (check_dr7_gd(ctxt))
		return emulate_db(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_dr_write(struct x86_emulate_ctxt *ctxt)
{
2861 2862
	u64 new_val = ctxt->src.val64;
	int dr = ctxt->modrm_reg;
2863 2864 2865 2866 2867 2868 2869

	if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
		return emulate_gp(ctxt, 0);

	return check_dr_read(ctxt);
}

2870 2871 2872 2873
static int check_svme(struct x86_emulate_ctxt *ctxt)
{
	u64 efer;

2874
	ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2875 2876 2877 2878 2879 2880 2881 2882 2883

	if (!(efer & EFER_SVME))
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
{
2884
	u64 rax = ctxt->regs[VCPU_REGS_RAX];
2885 2886

	/* Valid physical address? */
2887
	if (rax & 0xffff000000000000ULL)
2888 2889 2890 2891 2892
		return emulate_gp(ctxt, 0);

	return check_svme(ctxt);
}

2893 2894
static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
{
2895
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
2896

2897
	if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
2898 2899 2900 2901 2902
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

2903 2904
static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
{
2905
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
2906
	u64 rcx = ctxt->regs[VCPU_REGS_RCX];
2907

2908
	if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
2909 2910 2911 2912 2913 2914
	    (rcx > 3))
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

2915 2916
static int check_perm_in(struct x86_emulate_ctxt *ctxt)
{
2917 2918
	ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
	if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
2919 2920 2921 2922 2923 2924 2925
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

static int check_perm_out(struct x86_emulate_ctxt *ctxt)
{
2926 2927
	ctxt->src.bytes = min(ctxt->src.bytes, 4u);
	if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
2928 2929 2930 2931 2932
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

2933
#define D(_y) { .flags = (_y) }
2934
#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
2935 2936
#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
		      .check_perm = (_p) }
2937
#define N    D(0)
2938
#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
2939
#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2940
#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
2941
#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2942 2943
#define II(_f, _e, _i) \
	{ .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
2944 2945 2946
#define IIP(_f, _e, _i, _p) \
	{ .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
	  .check_perm = (_p) }
2947
#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
2948

2949
#define D2bv(_f)      D((_f) | ByteOp), D(_f)
2950
#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
2951 2952
#define I2bv(_f, _e)  I((_f) | ByteOp, _e), I(_f, _e)

2953 2954 2955
#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e),		\
		I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e),	\
		I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
2956

2957 2958 2959 2960 2961 2962
static struct opcode group7_rm1[] = {
	DI(SrcNone | ModRM | Priv, monitor),
	DI(SrcNone | ModRM | Priv, mwait),
	N, N, N, N, N, N,
};

2963 2964
static struct opcode group7_rm3[] = {
	DIP(SrcNone | ModRM | Prot | Priv, vmrun,   check_svme_pa),
2965
	II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
2966 2967 2968 2969 2970 2971 2972
	DIP(SrcNone | ModRM | Prot | Priv, vmload,  check_svme_pa),
	DIP(SrcNone | ModRM | Prot | Priv, vmsave,  check_svme_pa),
	DIP(SrcNone | ModRM | Prot | Priv, stgi,    check_svme),
	DIP(SrcNone | ModRM | Prot | Priv, clgi,    check_svme),
	DIP(SrcNone | ModRM | Prot | Priv, skinit,  check_svme),
	DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
};
2973

2974 2975 2976 2977 2978
static struct opcode group7_rm7[] = {
	N,
	DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
	N, N, N, N, N, N,
};
2979

2980
static struct opcode group1[] = {
2981 2982 2983 2984 2985 2986 2987 2988
	I(Lock, em_add),
	I(Lock, em_or),
	I(Lock, em_adc),
	I(Lock, em_sbb),
	I(Lock, em_and),
	I(Lock, em_sub),
	I(Lock, em_xor),
	I(0, em_cmp),
2989 2990 2991 2992 2993 2994 2995 2996 2997
};

static struct opcode group1A[] = {
	D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
};

static struct opcode group3[] = {
	D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
	D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2998
	X4(D(SrcMem | ModRM)),
2999 3000 3001 3002 3003 3004 3005 3006 3007
};

static struct opcode group4[] = {
	D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
	N, N, N, N, N, N,
};

static struct opcode group5[] = {
	D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3008 3009
	D(SrcMem | ModRM | Stack),
	I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
3010 3011 3012 3013
	D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
	D(SrcMem | ModRM | Stack), N,
};

3014 3015 3016 3017 3018 3019 3020 3021
static struct opcode group6[] = {
	DI(ModRM | Prot,        sldt),
	DI(ModRM | Prot,        str),
	DI(ModRM | Prot | Priv, lldt),
	DI(ModRM | Prot | Priv, ltr),
	N, N, N, N,
};

3022
static struct group_dual group7 = { {
3023 3024
	DI(ModRM | Mov | DstMem | Priv, sgdt),
	DI(ModRM | Mov | DstMem | Priv, sidt),
3025 3026 3027 3028 3029
	II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
	II(ModRM | SrcMem | Priv, em_lidt, lidt),
	II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
	II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
	II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
3030
}, {
3031 3032
	I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
	EXT(0, group7_rm1),
3033
	N, EXT(0, group7_rm3),
3034 3035
	II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
	II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049
} };

static struct opcode group8[] = {
	N, N, N, N,
	D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
	D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
};

static struct group_dual group9 = { {
	N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
}, {
	N, N, N, N, N, N, N, N,
} };

3050 3051 3052 3053
static struct opcode group11[] = {
	I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
};

3054 3055 3056 3057
static struct gprefix pfx_0f_6f_0f_7f = {
	N, N, N, I(Sse, em_movdqu),
};

3058 3059
static struct opcode opcode_table[256] = {
	/* 0x00 - 0x07 */
3060
	I6ALU(Lock, em_add),
3061 3062
	D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
	/* 0x08 - 0x0F */
3063
	I6ALU(Lock, em_or),
3064 3065
	D(ImplicitOps | Stack | No64), N,
	/* 0x10 - 0x17 */
3066
	I6ALU(Lock, em_adc),
3067 3068
	D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
	/* 0x18 - 0x1F */
3069
	I6ALU(Lock, em_sbb),
3070 3071
	D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
	/* 0x20 - 0x27 */
3072
	I6ALU(Lock, em_and), N, N,
3073
	/* 0x28 - 0x2F */
3074
	I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
3075
	/* 0x30 - 0x37 */
3076
	I6ALU(Lock, em_xor), N, N,
3077
	/* 0x38 - 0x3F */
3078
	I6ALU(0, em_cmp), N, N,
3079 3080 3081
	/* 0x40 - 0x4F */
	X16(D(DstReg)),
	/* 0x50 - 0x57 */
3082
	X8(I(SrcReg | Stack, em_push)),
3083
	/* 0x58 - 0x5F */
3084
	X8(I(DstReg | Stack, em_pop)),
3085
	/* 0x60 - 0x67 */
3086 3087
	I(ImplicitOps | Stack | No64, em_pusha),
	I(ImplicitOps | Stack | No64, em_popa),
3088 3089 3090
	N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
	N, N, N, N,
	/* 0x68 - 0x6F */
3091 3092
	I(SrcImm | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
3093 3094
	I(SrcImmByte | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
3095 3096
	D2bvIP(DstDI | SrcDX | Mov | String, ins, check_perm_in), /* insb, insw/insd */
	D2bvIP(SrcSI | DstDX | String, outs, check_perm_out), /* outsb, outsw/outsd */
3097 3098 3099 3100 3101 3102 3103
	/* 0x70 - 0x7F */
	X16(D(SrcImmByte)),
	/* 0x80 - 0x87 */
	G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
	G(DstMem | SrcImm | ModRM | Group, group1),
	G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
	G(DstMem | SrcImmByte | ModRM | Group, group1),
3104
	I2bv(DstMem | SrcReg | ModRM, em_test),
3105
	I2bv(DstMem | SrcReg | ModRM | Lock, em_xchg),
3106
	/* 0x88 - 0x8F */
3107 3108
	I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
	I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
3109 3110 3111 3112
	I(DstMem | SrcNone | ModRM | Mov, em_mov_rm_sreg),
	D(ModRM | SrcMem | NoAccess | DstReg),
	I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
	G(0, group1A),
3113
	/* 0x90 - 0x97 */
3114
	DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
3115
	/* 0x98 - 0x9F */
3116
	D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
3117
	I(SrcImmFAddr | No64, em_call_far), N,
3118 3119
	II(ImplicitOps | Stack, em_pushf, pushf),
	II(ImplicitOps | Stack, em_popf, popf), N, N,
3120
	/* 0xA0 - 0xA7 */
3121 3122 3123
	I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
	I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
	I2bv(SrcSI | DstDI | Mov | String, em_mov),
3124
	I2bv(SrcSI | DstDI | String, em_cmp),
3125
	/* 0xA8 - 0xAF */
3126
	I2bv(DstAcc | SrcImm, em_test),
3127 3128
	I2bv(SrcAcc | DstDI | Mov | String, em_mov),
	I2bv(SrcSI | DstAcc | Mov | String, em_mov),
3129
	I2bv(SrcAcc | DstDI | String, em_cmp),
3130
	/* 0xB0 - 0xB7 */
3131
	X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
3132
	/* 0xB8 - 0xBF */
3133
	X8(I(DstReg | SrcImm | Mov, em_mov)),
3134
	/* 0xC0 - 0xC7 */
3135
	D2bv(DstMem | SrcImmByte | ModRM),
3136
	I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
3137
	I(ImplicitOps | Stack, em_ret),
3138
	D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
3139
	G(ByteOp, group11), G(0, group11),
3140
	/* 0xC8 - 0xCF */
3141
	N, N, N, I(ImplicitOps | Stack, em_ret_far),
3142
	D(ImplicitOps), DI(SrcImmByte, intn),
3143
	D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
3144
	/* 0xD0 - 0xD7 */
3145
	D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
3146 3147 3148 3149
	N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
3150 3151
	X3(I(SrcImmByte, em_loop)),
	I(SrcImmByte, em_jcxz),
3152 3153
	D2bvIP(SrcImmUByte | DstAcc, in,  check_perm_in),
	D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
3154 3155
	/* 0xE8 - 0xEF */
	D(SrcImm | Stack), D(SrcImm | ImplicitOps),
3156
	I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
3157 3158
	D2bvIP(SrcDX | DstAcc, in,  check_perm_in),
	D2bvIP(SrcAcc | DstDX, out, check_perm_out),
3159
	/* 0xF0 - 0xF7 */
3160
	N, DI(ImplicitOps, icebp), N, N,
3161 3162
	DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
	G(ByteOp, group3), G(0, group3),
3163
	/* 0xF8 - 0xFF */
3164 3165
	D(ImplicitOps), D(ImplicitOps),
	I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
3166 3167 3168 3169 3170
	D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
};

static struct opcode twobyte_table[256] = {
	/* 0x00 - 0x0F */
3171
	G(0, group6), GD(0, &group7), N, N,
3172 3173
	N, I(ImplicitOps | VendorSpecific, em_syscall),
	II(ImplicitOps | Priv, em_clts, clts), N,
3174
	DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3175 3176 3177 3178
	N, D(ImplicitOps | ModRM), N, N,
	/* 0x10 - 0x1F */
	N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
	/* 0x20 - 0x2F */
3179
	DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3180
	DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
3181
	DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3182
	DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
3183 3184 3185
	N, N, N, N,
	N, N, N, N, N, N, N, N,
	/* 0x30 - 0x3F */
3186 3187 3188 3189
	DI(ImplicitOps | Priv, wrmsr),
	IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
	DI(ImplicitOps | Priv, rdmsr),
	DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
3190 3191
	I(ImplicitOps | VendorSpecific, em_sysenter),
	I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
3192
	N, N,
3193 3194 3195 3196 3197 3198
	N, N, N, N, N, N, N, N,
	/* 0x40 - 0x4F */
	X16(D(DstReg | SrcMem | ModRM | Mov)),
	/* 0x50 - 0x5F */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0x60 - 0x6F */
3199 3200 3201 3202
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
3203
	/* 0x70 - 0x7F */
3204 3205 3206 3207
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
3208 3209 3210
	/* 0x80 - 0x8F */
	X16(D(SrcImm)),
	/* 0x90 - 0x9F */
3211
	X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
3212 3213
	/* 0xA0 - 0xA7 */
	D(ImplicitOps | Stack), D(ImplicitOps | Stack),
3214
	DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
3215 3216 3217 3218
	D(DstMem | SrcReg | Src2ImmByte | ModRM),
	D(DstMem | SrcReg | Src2CL | ModRM), N, N,
	/* 0xA8 - 0xAF */
	D(ImplicitOps | Stack), D(ImplicitOps | Stack),
3219
	DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3220 3221
	D(DstMem | SrcReg | Src2ImmByte | ModRM),
	D(DstMem | SrcReg | Src2CL | ModRM),
3222
	D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
3223
	/* 0xB0 - 0xB7 */
3224
	D2bv(DstMem | SrcReg | ModRM | Lock),
3225 3226 3227
	D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
	D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
	D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3228 3229
	/* 0xB8 - 0xBF */
	N, N,
3230
	G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3231 3232
	D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
	D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3233
	/* 0xC0 - 0xCF */
3234
	D2bv(DstMem | SrcReg | ModRM | Lock),
3235
	N, D(DstMem | SrcReg | ModRM | Mov),
3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250
	N, N, N, GD(0, &group9),
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xDF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xEF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xFF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
};

#undef D
#undef N
#undef G
#undef GD
#undef I
3251
#undef GP
3252
#undef EXT
3253

3254
#undef D2bv
3255
#undef D2bvIP
3256
#undef I2bv
3257
#undef I6ALU
3258

3259
static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
3260 3261 3262
{
	unsigned size;

3263
	size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275
	if (size == 8)
		size = 4;
	return size;
}

static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
		      unsigned size, bool sign_extension)
{
	int rc = X86EMUL_CONTINUE;

	op->type = OP_IMM;
	op->bytes = size;
3276
	op->addr.mem.ea = ctxt->_eip;
3277 3278 3279
	/* NB. Immediates are sign-extended as necessary. */
	switch (op->bytes) {
	case 1:
3280
		op->val = insn_fetch(s8, ctxt);
3281 3282
		break;
	case 2:
3283
		op->val = insn_fetch(s16, ctxt);
3284 3285
		break;
	case 4:
3286
		op->val = insn_fetch(s32, ctxt);
3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305
		break;
	}
	if (!sign_extension) {
		switch (op->bytes) {
		case 1:
			op->val &= 0xff;
			break;
		case 2:
			op->val &= 0xffff;
			break;
		case 4:
			op->val &= 0xffffffff;
			break;
		}
	}
done:
	return rc;
}

3306
int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
3307 3308 3309
{
	int rc = X86EMUL_CONTINUE;
	int mode = ctxt->mode;
3310
	int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
3311
	bool op_prefix = false;
3312
	struct opcode opcode;
3313
	struct operand memop = { .type = OP_NONE }, *memopp = NULL;
3314

3315 3316 3317
	ctxt->_eip = ctxt->eip;
	ctxt->fetch.start = ctxt->_eip;
	ctxt->fetch.end = ctxt->fetch.start + insn_len;
3318
	if (insn_len > 0)
3319
		memcpy(ctxt->fetch.data, insn, insn_len);
3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336

	switch (mode) {
	case X86EMUL_MODE_REAL:
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
		def_op_bytes = def_ad_bytes = 2;
		break;
	case X86EMUL_MODE_PROT32:
		def_op_bytes = def_ad_bytes = 4;
		break;
#ifdef CONFIG_X86_64
	case X86EMUL_MODE_PROT64:
		def_op_bytes = 4;
		def_ad_bytes = 8;
		break;
#endif
	default:
3337
		return EMULATION_FAILED;
3338 3339
	}

3340 3341
	ctxt->op_bytes = def_op_bytes;
	ctxt->ad_bytes = def_ad_bytes;
3342 3343 3344

	/* Legacy prefixes. */
	for (;;) {
3345
		switch (ctxt->b = insn_fetch(u8, ctxt)) {
3346
		case 0x66:	/* operand-size override */
3347
			op_prefix = true;
3348
			/* switch between 2/4 bytes */
3349
			ctxt->op_bytes = def_op_bytes ^ 6;
3350 3351 3352 3353
			break;
		case 0x67:	/* address-size override */
			if (mode == X86EMUL_MODE_PROT64)
				/* switch between 4/8 bytes */
3354
				ctxt->ad_bytes = def_ad_bytes ^ 12;
3355 3356
			else
				/* switch between 2/4 bytes */
3357
				ctxt->ad_bytes = def_ad_bytes ^ 6;
3358 3359 3360 3361 3362
			break;
		case 0x26:	/* ES override */
		case 0x2e:	/* CS override */
		case 0x36:	/* SS override */
		case 0x3e:	/* DS override */
3363
			set_seg_override(ctxt, (ctxt->b >> 3) & 3);
3364 3365 3366
			break;
		case 0x64:	/* FS override */
		case 0x65:	/* GS override */
3367
			set_seg_override(ctxt, ctxt->b & 7);
3368 3369 3370 3371
			break;
		case 0x40 ... 0x4f: /* REX */
			if (mode != X86EMUL_MODE_PROT64)
				goto done_prefixes;
3372
			ctxt->rex_prefix = ctxt->b;
3373 3374
			continue;
		case 0xf0:	/* LOCK */
3375
			ctxt->lock_prefix = 1;
3376 3377 3378
			break;
		case 0xf2:	/* REPNE/REPNZ */
		case 0xf3:	/* REP/REPE/REPZ */
3379
			ctxt->rep_prefix = ctxt->b;
3380 3381 3382 3383 3384 3385 3386
			break;
		default:
			goto done_prefixes;
		}

		/* Any legacy prefix after a REX prefix nullifies its effect. */

3387
		ctxt->rex_prefix = 0;
3388 3389 3390 3391 3392
	}

done_prefixes:

	/* REX prefix. */
3393 3394
	if (ctxt->rex_prefix & 8)
		ctxt->op_bytes = 8;	/* REX.W */
3395 3396

	/* Opcode byte(s). */
3397
	opcode = opcode_table[ctxt->b];
3398
	/* Two-byte opcode? */
3399 3400
	if (ctxt->b == 0x0f) {
		ctxt->twobyte = 1;
3401
		ctxt->b = insn_fetch(u8, ctxt);
3402
		opcode = twobyte_table[ctxt->b];
3403
	}
3404
	ctxt->d = opcode.flags;
3405

3406 3407
	while (ctxt->d & GroupMask) {
		switch (ctxt->d & GroupMask) {
3408
		case Group:
3409
			ctxt->modrm = insn_fetch(u8, ctxt);
3410 3411
			--ctxt->_eip;
			goffset = (ctxt->modrm >> 3) & 7;
3412 3413 3414
			opcode = opcode.u.group[goffset];
			break;
		case GroupDual:
3415
			ctxt->modrm = insn_fetch(u8, ctxt);
3416 3417 3418
			--ctxt->_eip;
			goffset = (ctxt->modrm >> 3) & 7;
			if ((ctxt->modrm >> 6) == 3)
3419 3420 3421 3422 3423
				opcode = opcode.u.gdual->mod3[goffset];
			else
				opcode = opcode.u.gdual->mod012[goffset];
			break;
		case RMExt:
3424
			goffset = ctxt->modrm & 7;
3425
			opcode = opcode.u.group[goffset];
3426 3427
			break;
		case Prefix:
3428
			if (ctxt->rep_prefix && op_prefix)
3429
				return EMULATION_FAILED;
3430
			simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
3431 3432 3433 3434 3435 3436 3437 3438
			switch (simd_prefix) {
			case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
			case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
			case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
			case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
			}
			break;
		default:
3439
			return EMULATION_FAILED;
3440
		}
3441

3442 3443
		ctxt->d &= ~GroupMask;
		ctxt->d |= opcode.flags;
3444 3445
	}

3446 3447 3448
	ctxt->execute = opcode.u.execute;
	ctxt->check_perm = opcode.check_perm;
	ctxt->intercept = opcode.intercept;
3449 3450

	/* Unrecognised? */
3451
	if (ctxt->d == 0 || (ctxt->d & Undefined))
3452
		return EMULATION_FAILED;
3453

3454
	if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
3455
		return EMULATION_FAILED;
3456

3457 3458
	if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
		ctxt->op_bytes = 8;
3459

3460
	if (ctxt->d & Op3264) {
3461
		if (mode == X86EMUL_MODE_PROT64)
3462
			ctxt->op_bytes = 8;
3463
		else
3464
			ctxt->op_bytes = 4;
3465 3466
	}

3467 3468
	if (ctxt->d & Sse)
		ctxt->op_bytes = 16;
A
Avi Kivity 已提交
3469

3470
	/* ModRM and SIB bytes. */
3471
	if (ctxt->d & ModRM) {
3472
		rc = decode_modrm(ctxt, &memop);
3473 3474 3475
		if (!ctxt->has_seg_override)
			set_seg_override(ctxt, ctxt->modrm_seg);
	} else if (ctxt->d & MemAbs)
3476
		rc = decode_abs(ctxt, &memop);
3477 3478 3479
	if (rc != X86EMUL_CONTINUE)
		goto done;

3480 3481
	if (!ctxt->has_seg_override)
		set_seg_override(ctxt, VCPU_SREG_DS);
3482

3483
	memop.addr.mem.seg = seg_override(ctxt);
3484

3485
	if (memop.type == OP_MEM && ctxt->ad_bytes != 8)
3486
		memop.addr.mem.ea = (u32)memop.addr.mem.ea;
3487 3488 3489 3490 3491

	/*
	 * Decode and fetch the source operand: register, memory
	 * or immediate.
	 */
3492
	switch (ctxt->d & SrcMask) {
3493 3494 3495
	case SrcNone:
		break;
	case SrcReg:
3496
		decode_register_operand(ctxt, &ctxt->src, 0);
3497 3498
		break;
	case SrcMem16:
3499
		memop.bytes = 2;
3500 3501
		goto srcmem_common;
	case SrcMem32:
3502
		memop.bytes = 4;
3503 3504
		goto srcmem_common;
	case SrcMem:
3505 3506
		memop.bytes = (ctxt->d & ByteOp) ? 1 :
							   ctxt->op_bytes;
3507
	srcmem_common:
3508 3509
		ctxt->src = memop;
		memopp = &ctxt->src;
3510
		break;
3511
	case SrcImmU16:
3512
		rc = decode_imm(ctxt, &ctxt->src, 2, false);
3513
		break;
3514
	case SrcImm:
3515
		rc = decode_imm(ctxt, &ctxt->src, imm_size(ctxt), true);
3516
		break;
3517
	case SrcImmU:
3518
		rc = decode_imm(ctxt, &ctxt->src, imm_size(ctxt), false);
3519 3520
		break;
	case SrcImmByte:
3521
		rc = decode_imm(ctxt, &ctxt->src, 1, true);
3522
		break;
3523
	case SrcImmUByte:
3524
		rc = decode_imm(ctxt, &ctxt->src, 1, false);
3525 3526
		break;
	case SrcAcc:
3527 3528 3529 3530
		ctxt->src.type = OP_REG;
		ctxt->src.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		ctxt->src.addr.reg = &ctxt->regs[VCPU_REGS_RAX];
		fetch_register_operand(&ctxt->src);
3531 3532
		break;
	case SrcOne:
3533 3534
		ctxt->src.bytes = 1;
		ctxt->src.val = 1;
3535 3536
		break;
	case SrcSI:
3537 3538 3539 3540 3541 3542
		ctxt->src.type = OP_MEM;
		ctxt->src.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		ctxt->src.addr.mem.ea =
			register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
		ctxt->src.addr.mem.seg = seg_override(ctxt);
		ctxt->src.val = 0;
3543 3544
		break;
	case SrcImmFAddr:
3545 3546 3547
		ctxt->src.type = OP_IMM;
		ctxt->src.addr.mem.ea = ctxt->_eip;
		ctxt->src.bytes = ctxt->op_bytes + 2;
3548
		insn_fetch_arr(ctxt->src.valptr, ctxt->src.bytes, ctxt);
3549 3550
		break;
	case SrcMemFAddr:
3551
		memop.bytes = ctxt->op_bytes + 2;
3552
		goto srcmem_common;
3553
		break;
3554
	case SrcDX:
3555 3556 3557 3558
		ctxt->src.type = OP_REG;
		ctxt->src.bytes = 2;
		ctxt->src.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
		fetch_register_operand(&ctxt->src);
3559
		break;
3560 3561
	}

3562 3563 3564
	if (rc != X86EMUL_CONTINUE)
		goto done;

3565 3566 3567 3568
	/*
	 * Decode and fetch the second source operand: register, memory
	 * or immediate.
	 */
3569
	switch (ctxt->d & Src2Mask) {
3570 3571 3572
	case Src2None:
		break;
	case Src2CL:
3573
		ctxt->src2.bytes = 1;
3574
		ctxt->src2.val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
3575 3576
		break;
	case Src2ImmByte:
3577
		rc = decode_imm(ctxt, &ctxt->src2, 1, true);
3578 3579
		break;
	case Src2One:
3580 3581
		ctxt->src2.bytes = 1;
		ctxt->src2.val = 1;
3582
		break;
3583
	case Src2Imm:
3584
		rc = decode_imm(ctxt, &ctxt->src2, imm_size(ctxt), true);
3585
		break;
3586 3587
	}

3588 3589 3590
	if (rc != X86EMUL_CONTINUE)
		goto done;

3591
	/* Decode and fetch the destination operand: register or memory. */
3592
	switch (ctxt->d & DstMask) {
3593
	case DstReg:
3594 3595
		decode_register_operand(ctxt, &ctxt->dst,
			 ctxt->twobyte && (ctxt->b == 0xb6 || ctxt->b == 0xb7));
3596
		break;
3597
	case DstImmUByte:
3598 3599 3600
		ctxt->dst.type = OP_IMM;
		ctxt->dst.addr.mem.ea = ctxt->_eip;
		ctxt->dst.bytes = 1;
3601
		ctxt->dst.val = insn_fetch(u8, ctxt);
3602
		break;
3603 3604
	case DstMem:
	case DstMem64:
3605 3606 3607 3608
		ctxt->dst = memop;
		memopp = &ctxt->dst;
		if ((ctxt->d & DstMask) == DstMem64)
			ctxt->dst.bytes = 8;
3609
		else
3610 3611 3612 3613
			ctxt->dst.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		if (ctxt->d & BitOp)
			fetch_bit_operand(ctxt);
		ctxt->dst.orig_val = ctxt->dst.val;
3614 3615
		break;
	case DstAcc:
3616 3617 3618 3619 3620
		ctxt->dst.type = OP_REG;
		ctxt->dst.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RAX];
		fetch_register_operand(&ctxt->dst);
		ctxt->dst.orig_val = ctxt->dst.val;
3621 3622
		break;
	case DstDI:
3623 3624 3625 3626 3627 3628
		ctxt->dst.type = OP_MEM;
		ctxt->dst.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		ctxt->dst.addr.mem.ea =
			register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
		ctxt->dst.addr.mem.seg = VCPU_SREG_ES;
		ctxt->dst.val = 0;
3629
		break;
3630
	case DstDX:
3631 3632 3633 3634
		ctxt->dst.type = OP_REG;
		ctxt->dst.bytes = 2;
		ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
		fetch_register_operand(&ctxt->dst);
3635
		break;
3636 3637 3638
	case ImplicitOps:
		/* Special instructions do their own operand decoding. */
	default:
3639
		ctxt->dst.type = OP_NONE; /* Disable writeback. */
3640
		break;
3641 3642 3643
	}

done:
3644 3645
	if (memopp && memopp->type == OP_MEM && ctxt->rip_relative)
		memopp->addr.mem.ea += ctxt->_eip;
3646

3647
	return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
3648 3649
}

3650 3651 3652 3653 3654 3655 3656 3657 3658
static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
{
	/* The second termination condition only applies for REPE
	 * and REPNE. Test if the repeat string operation prefix is
	 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
	 * corresponding termination condition according to:
	 * 	- if REPE/REPZ and ZF = 0 then done
	 * 	- if REPNE/REPNZ and ZF = 1 then done
	 */
3659 3660 3661
	if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
	     (ctxt->b == 0xae) || (ctxt->b == 0xaf))
	    && (((ctxt->rep_prefix == REPE_PREFIX) &&
3662
		 ((ctxt->eflags & EFLG_ZF) == 0))
3663
		|| ((ctxt->rep_prefix == REPNE_PREFIX) &&
3664 3665 3666 3667 3668 3669
		    ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
		return true;

	return false;
}

3670
int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
3671
{
3672
	struct x86_emulate_ops *ops = ctxt->ops;
3673
	u64 msr_data;
3674
	int rc = X86EMUL_CONTINUE;
3675
	int saved_dst_type = ctxt->dst.type;
3676

3677
	ctxt->mem_read.pos = 0;
3678

3679
	if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
3680
		rc = emulate_ud(ctxt);
3681 3682 3683
		goto done;
	}

3684
	/* LOCK prefix is allowed only with some instructions */
3685
	if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
3686
		rc = emulate_ud(ctxt);
3687 3688 3689
		goto done;
	}

3690
	if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
3691
		rc = emulate_ud(ctxt);
3692 3693 3694
		goto done;
	}

3695
	if ((ctxt->d & Sse)
3696 3697
	    && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
		|| !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
A
Avi Kivity 已提交
3698 3699 3700 3701
		rc = emulate_ud(ctxt);
		goto done;
	}

3702
	if ((ctxt->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
A
Avi Kivity 已提交
3703 3704 3705 3706
		rc = emulate_nm(ctxt);
		goto done;
	}

3707 3708
	if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
		rc = emulator_check_intercept(ctxt, ctxt->intercept,
3709
					      X86_ICPT_PRE_EXCEPT);
3710 3711 3712 3713
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3714
	/* Privileged instruction can be executed only in CPL=0 */
3715
	if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
3716
		rc = emulate_gp(ctxt, 0);
3717 3718 3719
		goto done;
	}

3720
	/* Instruction can only be executed in protected mode */
3721
	if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
3722 3723 3724 3725
		rc = emulate_ud(ctxt);
		goto done;
	}

3726
	/* Do instruction specific permission checks */
3727 3728
	if (ctxt->check_perm) {
		rc = ctxt->check_perm(ctxt);
3729 3730 3731 3732
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3733 3734
	if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
		rc = emulator_check_intercept(ctxt, ctxt->intercept,
3735
					      X86_ICPT_POST_EXCEPT);
3736 3737 3738 3739
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3740
	if (ctxt->rep_prefix && (ctxt->d & String)) {
3741
		/* All REP prefixes have the same first termination condition */
3742 3743
		if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
			ctxt->eip = ctxt->_eip;
3744 3745 3746 3747
			goto done;
		}
	}

3748 3749 3750
	if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
		rc = segmented_read(ctxt, ctxt->src.addr.mem,
				    ctxt->src.valptr, ctxt->src.bytes);
3751
		if (rc != X86EMUL_CONTINUE)
3752
			goto done;
3753
		ctxt->src.orig_val64 = ctxt->src.val64;
3754 3755
	}

3756 3757 3758
	if (ctxt->src2.type == OP_MEM) {
		rc = segmented_read(ctxt, ctxt->src2.addr.mem,
				    &ctxt->src2.val, ctxt->src2.bytes);
3759 3760 3761 3762
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3763
	if ((ctxt->d & DstMask) == ImplicitOps)
3764 3765 3766
		goto special_insn;


3767
	if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
3768
		/* optimisation - avoid slow emulated read if Mov */
3769 3770
		rc = segmented_read(ctxt, ctxt->dst.addr.mem,
				   &ctxt->dst.val, ctxt->dst.bytes);
3771 3772
		if (rc != X86EMUL_CONTINUE)
			goto done;
3773
	}
3774
	ctxt->dst.orig_val = ctxt->dst.val;
3775

3776 3777
special_insn:

3778 3779
	if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
		rc = emulator_check_intercept(ctxt, ctxt->intercept,
3780
					      X86_ICPT_POST_MEMACCESS);
3781 3782 3783 3784
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3785 3786
	if (ctxt->execute) {
		rc = ctxt->execute(ctxt);
3787 3788 3789 3790 3791
		if (rc != X86EMUL_CONTINUE)
			goto done;
		goto writeback;
	}

3792
	if (ctxt->twobyte)
A
Avi Kivity 已提交
3793 3794
		goto twobyte_insn;

3795
	switch (ctxt->b) {
3796
	case 0x06:		/* push es */
3797
		rc = emulate_push_sreg(ctxt, VCPU_SREG_ES);
3798 3799
		break;
	case 0x07:		/* pop es */
3800
		rc = emulate_pop_sreg(ctxt, VCPU_SREG_ES);
3801 3802
		break;
	case 0x0e:		/* push cs */
3803
		rc = emulate_push_sreg(ctxt, VCPU_SREG_CS);
3804 3805
		break;
	case 0x16:		/* push ss */
3806
		rc = emulate_push_sreg(ctxt, VCPU_SREG_SS);
3807 3808
		break;
	case 0x17:		/* pop ss */
3809
		rc = emulate_pop_sreg(ctxt, VCPU_SREG_SS);
3810 3811
		break;
	case 0x1e:		/* push ds */
3812
		rc = emulate_push_sreg(ctxt, VCPU_SREG_DS);
3813 3814
		break;
	case 0x1f:		/* pop ds */
3815
		rc = emulate_pop_sreg(ctxt, VCPU_SREG_DS);
3816
		break;
3817
	case 0x40 ... 0x47: /* inc r16/r32 */
3818
		emulate_1op(ctxt, "inc");
3819 3820
		break;
	case 0x48 ... 0x4f: /* dec r16/r32 */
3821
		emulate_1op(ctxt, "dec");
3822
		break;
A
Avi Kivity 已提交
3823
	case 0x63:		/* movsxd */
3824
		if (ctxt->mode != X86EMUL_MODE_PROT64)
A
Avi Kivity 已提交
3825
			goto cannot_emulate;
3826
		ctxt->dst.val = (s32) ctxt->src.val;
A
Avi Kivity 已提交
3827
		break;
3828 3829
	case 0x6c:		/* insb */
	case 0x6d:		/* insw/insd */
3830
		ctxt->src.val = ctxt->regs[VCPU_REGS_RDX];
3831
		goto do_io_in;
3832 3833
	case 0x6e:		/* outsb */
	case 0x6f:		/* outsw/outsd */
3834
		ctxt->dst.val = ctxt->regs[VCPU_REGS_RDX];
3835
		goto do_io_out;
3836
		break;
3837
	case 0x70 ... 0x7f: /* jcc (short) */
3838 3839
		if (test_cc(ctxt->b, ctxt->eflags))
			jmp_rel(ctxt, ctxt->src.val);
3840
		break;
N
Nitin A Kamble 已提交
3841
	case 0x8d: /* lea r16/r32, m */
3842
		ctxt->dst.val = ctxt->src.addr.mem.ea;
N
Nitin A Kamble 已提交
3843
		break;
A
Avi Kivity 已提交
3844
	case 0x8f:		/* pop (sole member of Grp1a) */
3845
		rc = em_grp1a(ctxt);
A
Avi Kivity 已提交
3846
		break;
3847
	case 0x90 ... 0x97: /* nop / xchg reg, rax */
3848
		if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
3849
			break;
3850 3851
		rc = em_xchg(ctxt);
		break;
3852
	case 0x98: /* cbw/cwde/cdqe */
3853 3854 3855 3856
		switch (ctxt->op_bytes) {
		case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
		case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
		case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
3857 3858
		}
		break;
3859
	case 0xc0 ... 0xc1:
3860
		rc = em_grp2(ctxt);
3861
		break;
3862
	case 0xc4:		/* les */
3863
		rc = emulate_load_segment(ctxt, VCPU_SREG_ES);
3864 3865
		break;
	case 0xc5:		/* lds */
3866
		rc = emulate_load_segment(ctxt, VCPU_SREG_DS);
3867
		break;
3868
	case 0xcc:		/* int3 */
3869 3870
		rc = emulate_int(ctxt, 3);
		break;
3871
	case 0xcd:		/* int n */
3872
		rc = emulate_int(ctxt, ctxt->src.val);
3873 3874
		break;
	case 0xce:		/* into */
3875 3876
		if (ctxt->eflags & EFLG_OF)
			rc = emulate_int(ctxt, 4);
3877
		break;
3878
	case 0xd0 ... 0xd1:	/* Grp2 */
3879
		rc = em_grp2(ctxt);
3880 3881
		break;
	case 0xd2 ... 0xd3:	/* Grp2 */
3882
		ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
3883
		rc = em_grp2(ctxt);
3884
		break;
3885 3886
	case 0xe4: 	/* inb */
	case 0xe5: 	/* in */
3887
		goto do_io_in;
3888 3889
	case 0xe6: /* outb */
	case 0xe7: /* out */
3890
		goto do_io_out;
3891
	case 0xe8: /* call (near) */ {
3892 3893 3894
		long int rel = ctxt->src.val;
		ctxt->src.val = (unsigned long) ctxt->_eip;
		jmp_rel(ctxt, rel);
3895
		rc = em_push(ctxt);
3896
		break;
3897 3898
	}
	case 0xe9: /* jmp rel */
3899
	case 0xeb: /* jmp rel short */
3900 3901
		jmp_rel(ctxt, ctxt->src.val);
		ctxt->dst.type = OP_NONE; /* Disable writeback. */
3902
		break;
3903 3904
	case 0xec: /* in al,dx */
	case 0xed: /* in (e/r)ax,dx */
3905
	do_io_in:
3906 3907
		if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
				     &ctxt->dst.val))
3908 3909
			goto done; /* IO is needed */
		break;
3910 3911
	case 0xee: /* out dx,al */
	case 0xef: /* out dx,(e/r)ax */
3912
	do_io_out:
3913 3914 3915
		ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
				      &ctxt->src.val, 1);
		ctxt->dst.type = OP_NONE;	/* Disable writeback. */
3916
		break;
3917
	case 0xf4:              /* hlt */
3918
		ctxt->ops->halt(ctxt);
3919
		break;
3920 3921 3922 3923
	case 0xf5:	/* cmc */
		/* complement carry flag from eflags reg */
		ctxt->eflags ^= EFLG_CF;
		break;
3924
	case 0xf6 ... 0xf7:	/* Grp3 */
3925
		rc = em_grp3(ctxt);
3926
		break;
3927 3928 3929
	case 0xf8: /* clc */
		ctxt->eflags &= ~EFLG_CF;
		break;
3930 3931 3932
	case 0xf9: /* stc */
		ctxt->eflags |= EFLG_CF;
		break;
3933 3934 3935 3936 3937 3938
	case 0xfc: /* cld */
		ctxt->eflags &= ~EFLG_DF;
		break;
	case 0xfd: /* std */
		ctxt->eflags |= EFLG_DF;
		break;
3939
	case 0xfe: /* Grp4 */
3940
		rc = em_grp45(ctxt);
3941
		break;
3942
	case 0xff: /* Grp5 */
3943 3944
		rc = em_grp45(ctxt);
		break;
3945 3946
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
3947
	}
3948

3949 3950 3951
	if (rc != X86EMUL_CONTINUE)
		goto done;

3952
writeback:
3953
	rc = writeback(ctxt);
3954
	if (rc != X86EMUL_CONTINUE)
3955 3956
		goto done;

3957 3958 3959 3960
	/*
	 * restore dst type in case the decoding will be reused
	 * (happens for string instruction )
	 */
3961
	ctxt->dst.type = saved_dst_type;
3962

3963 3964 3965
	if ((ctxt->d & SrcMask) == SrcSI)
		string_addr_inc(ctxt, seg_override(ctxt),
				VCPU_REGS_RSI, &ctxt->src);
3966

3967
	if ((ctxt->d & DstMask) == DstDI)
3968
		string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
3969
				&ctxt->dst);
3970

3971 3972 3973
	if (ctxt->rep_prefix && (ctxt->d & String)) {
		struct read_cache *r = &ctxt->io_read;
		register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3974

3975 3976 3977 3978 3979
		if (!string_insn_completed(ctxt)) {
			/*
			 * Re-enter guest when pio read ahead buffer is empty
			 * or, if it is not used, after each 1024 iteration.
			 */
3980
			if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
3981 3982 3983 3984 3985 3986
			    (r->end == 0 || r->end != r->pos)) {
				/*
				 * Reset read cache. Usually happens before
				 * decode, but since instruction is restarted
				 * we have to do it here.
				 */
3987
				ctxt->mem_read.end = 0;
3988 3989 3990
				return EMULATION_RESTART;
			}
			goto done; /* skip rip writeback */
3991
		}
3992
	}
3993

3994
	ctxt->eip = ctxt->_eip;
3995 3996

done:
3997 3998
	if (rc == X86EMUL_PROPAGATE_FAULT)
		ctxt->have_exception = true;
3999 4000 4001
	if (rc == X86EMUL_INTERCEPTED)
		return EMULATION_INTERCEPTED;

4002
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
A
Avi Kivity 已提交
4003 4004

twobyte_insn:
4005
	switch (ctxt->b) {
4006
	case 0x09:		/* wbinvd */
4007
		(ctxt->ops->wbinvd)(ctxt);
4008 4009
		break;
	case 0x08:		/* invd */
4010 4011 4012 4013
	case 0x0d:		/* GrpP (prefetch) */
	case 0x18:		/* Grp16 (prefetch/nop) */
		break;
	case 0x20: /* mov cr, reg */
4014
		ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
4015
		break;
A
Avi Kivity 已提交
4016
	case 0x21: /* mov from dr to reg */
4017
		ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
A
Avi Kivity 已提交
4018
		break;
4019
	case 0x22: /* mov reg, cr */
4020
		if (ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) {
4021
			emulate_gp(ctxt, 0);
4022
			rc = X86EMUL_PROPAGATE_FAULT;
4023 4024
			goto done;
		}
4025
		ctxt->dst.type = OP_NONE;
4026
		break;
A
Avi Kivity 已提交
4027
	case 0x23: /* mov from reg to dr */
4028
		if (ops->set_dr(ctxt, ctxt->modrm_reg, ctxt->src.val &
4029
				((ctxt->mode == X86EMUL_MODE_PROT64) ?
4030
				 ~0ULL : ~0U)) < 0) {
4031
			/* #UD condition is already handled by the code above */
4032
			emulate_gp(ctxt, 0);
4033
			rc = X86EMUL_PROPAGATE_FAULT;
4034 4035 4036
			goto done;
		}

4037
		ctxt->dst.type = OP_NONE;	/* no writeback */
A
Avi Kivity 已提交
4038
		break;
4039 4040
	case 0x30:
		/* wrmsr */
4041 4042 4043
		msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
			| ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
		if (ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data)) {
4044
			emulate_gp(ctxt, 0);
4045
			rc = X86EMUL_PROPAGATE_FAULT;
4046
			goto done;
4047 4048 4049 4050 4051
		}
		rc = X86EMUL_CONTINUE;
		break;
	case 0x32:
		/* rdmsr */
4052
		if (ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data)) {
4053
			emulate_gp(ctxt, 0);
4054
			rc = X86EMUL_PROPAGATE_FAULT;
4055
			goto done;
4056
		} else {
4057 4058
			ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
			ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
4059 4060 4061
		}
		rc = X86EMUL_CONTINUE;
		break;
A
Avi Kivity 已提交
4062
	case 0x40 ... 0x4f:	/* cmov */
4063 4064 4065
		ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
		if (!test_cc(ctxt->b, ctxt->eflags))
			ctxt->dst.type = OP_NONE; /* no writeback */
A
Avi Kivity 已提交
4066
		break;
4067
	case 0x80 ... 0x8f: /* jnz rel, etc*/
4068 4069
		if (test_cc(ctxt->b, ctxt->eflags))
			jmp_rel(ctxt, ctxt->src.val);
4070
		break;
4071
	case 0x90 ... 0x9f:     /* setcc r/m8 */
4072
		ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
4073
		break;
4074
	case 0xa0:	  /* push fs */
4075
		rc = emulate_push_sreg(ctxt, VCPU_SREG_FS);
4076 4077
		break;
	case 0xa1:	 /* pop fs */
4078
		rc = emulate_pop_sreg(ctxt, VCPU_SREG_FS);
4079
		break;
4080 4081
	case 0xa3:
	      bt:		/* bt */
4082
		ctxt->dst.type = OP_NONE;
4083
		/* only subword offset */
4084
		ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
4085
		emulate_2op_SrcV_nobyte(ctxt, "bt");
4086
		break;
4087 4088
	case 0xa4: /* shld imm8, r, r/m */
	case 0xa5: /* shld cl, r, r/m */
4089
		emulate_2op_cl(ctxt, "shld");
4090
		break;
4091
	case 0xa8:	/* push gs */
4092
		rc = emulate_push_sreg(ctxt, VCPU_SREG_GS);
4093 4094
		break;
	case 0xa9:	/* pop gs */
4095
		rc = emulate_pop_sreg(ctxt, VCPU_SREG_GS);
4096
		break;
4097 4098
	case 0xab:
	      bts:		/* bts */
4099
		emulate_2op_SrcV_nobyte(ctxt, "bts");
4100
		break;
4101 4102
	case 0xac: /* shrd imm8, r, r/m */
	case 0xad: /* shrd cl, r, r/m */
4103
		emulate_2op_cl(ctxt, "shrd");
4104
		break;
4105 4106
	case 0xae:              /* clflush */
		break;
A
Avi Kivity 已提交
4107 4108 4109 4110 4111
	case 0xb0 ... 0xb1:	/* cmpxchg */
		/*
		 * Save real source value, then compare EAX against
		 * destination.
		 */
4112 4113
		ctxt->src.orig_val = ctxt->src.val;
		ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
4114
		emulate_2op_SrcV(ctxt, "cmp");
4115
		if (ctxt->eflags & EFLG_ZF) {
A
Avi Kivity 已提交
4116
			/* Success: write back to memory. */
4117
			ctxt->dst.val = ctxt->src.orig_val;
A
Avi Kivity 已提交
4118 4119
		} else {
			/* Failure: write the value we saw to EAX. */
4120 4121
			ctxt->dst.type = OP_REG;
			ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
A
Avi Kivity 已提交
4122 4123
		}
		break;
4124
	case 0xb2:		/* lss */
4125
		rc = emulate_load_segment(ctxt, VCPU_SREG_SS);
4126
		break;
A
Avi Kivity 已提交
4127 4128
	case 0xb3:
	      btr:		/* btr */
4129
		emulate_2op_SrcV_nobyte(ctxt, "btr");
A
Avi Kivity 已提交
4130
		break;
4131
	case 0xb4:		/* lfs */
4132
		rc = emulate_load_segment(ctxt, VCPU_SREG_FS);
4133 4134
		break;
	case 0xb5:		/* lgs */
4135
		rc = emulate_load_segment(ctxt, VCPU_SREG_GS);
4136
		break;
A
Avi Kivity 已提交
4137
	case 0xb6 ... 0xb7:	/* movzx */
4138 4139 4140
		ctxt->dst.bytes = ctxt->op_bytes;
		ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
						       : (u16) ctxt->src.val;
A
Avi Kivity 已提交
4141 4142
		break;
	case 0xba:		/* Grp8 */
4143
		switch (ctxt->modrm_reg & 3) {
A
Avi Kivity 已提交
4144 4145 4146 4147 4148 4149 4150 4151 4152 4153
		case 0:
			goto bt;
		case 1:
			goto bts;
		case 2:
			goto btr;
		case 3:
			goto btc;
		}
		break;
4154 4155
	case 0xbb:
	      btc:		/* btc */
4156
		emulate_2op_SrcV_nobyte(ctxt, "btc");
4157
		break;
4158 4159 4160
	case 0xbc: {		/* bsf */
		u8 zf;
		__asm__ ("bsf %2, %0; setz %1"
4161 4162
			 : "=r"(ctxt->dst.val), "=q"(zf)
			 : "r"(ctxt->src.val));
4163 4164 4165
		ctxt->eflags &= ~X86_EFLAGS_ZF;
		if (zf) {
			ctxt->eflags |= X86_EFLAGS_ZF;
4166
			ctxt->dst.type = OP_NONE;	/* Disable writeback. */
4167 4168 4169 4170 4171 4172
		}
		break;
	}
	case 0xbd: {		/* bsr */
		u8 zf;
		__asm__ ("bsr %2, %0; setz %1"
4173 4174
			 : "=r"(ctxt->dst.val), "=q"(zf)
			 : "r"(ctxt->src.val));
4175 4176 4177
		ctxt->eflags &= ~X86_EFLAGS_ZF;
		if (zf) {
			ctxt->eflags |= X86_EFLAGS_ZF;
4178
			ctxt->dst.type = OP_NONE;	/* Disable writeback. */
4179 4180 4181
		}
		break;
	}
A
Avi Kivity 已提交
4182
	case 0xbe ... 0xbf:	/* movsx */
4183 4184 4185
		ctxt->dst.bytes = ctxt->op_bytes;
		ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val :
							(s16) ctxt->src.val;
A
Avi Kivity 已提交
4186
		break;
4187
	case 0xc0 ... 0xc1:	/* xadd */
4188
		emulate_2op_SrcV(ctxt, "add");
4189
		/* Write back the register source. */
4190 4191
		ctxt->src.val = ctxt->dst.orig_val;
		write_register_operand(&ctxt->src);
4192
		break;
4193
	case 0xc3:		/* movnti */
4194 4195 4196
		ctxt->dst.bytes = ctxt->op_bytes;
		ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
							(u64) ctxt->src.val;
4197
		break;
A
Avi Kivity 已提交
4198
	case 0xc7:		/* Grp9 (cmpxchg8b) */
4199
		rc = em_grp9(ctxt);
4200
		break;
4201 4202
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
4203
	}
4204 4205 4206 4207

	if (rc != X86EMUL_CONTINUE)
		goto done;

A
Avi Kivity 已提交
4208 4209 4210
	goto writeback;

cannot_emulate:
4211
	return EMULATION_FAILED;
A
Avi Kivity 已提交
4212
}