intel_drv.h 65.5 KB
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/*
 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
 * Copyright (c) 2007-2008 Intel Corporation
 *   Jesse Barnes <jesse.barnes@intel.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */
#ifndef __INTEL_DRV_H__
#define __INTEL_DRV_H__

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#include <linux/async.h>
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#include <linux/i2c.h>
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#include <linux/hdmi.h>
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#include <linux/sched/clock.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
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#include <drm/drm_encoder.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_dp_dual_mode_helper.h>
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#include <drm/drm_dp_mst_helper.h>
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#include <drm/drm_rect.h>
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#include <drm/drm_atomic.h>
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/**
 * _wait_for - magic (register) wait macro
 *
 * Does the right thing for modeset paths when run under kdgb or similar atomic
 * contexts. Note that it's important that we check the condition again after
 * having timed out, since the timeout could be due to preemption or similar and
 * we've never had a chance to check the condition before the timeout.
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 *
 * TODO: When modesetting has fully transitioned to atomic, the below
 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
 * added.
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 */
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#define _wait_for(COND, US, W) ({ \
	unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;	\
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	int ret__;							\
	for (;;) {							\
		bool expired__ = time_after(jiffies, timeout__);	\
		if (COND) {						\
			ret__ = 0;					\
			break;						\
		}							\
		if (expired__) {					\
			ret__ = -ETIMEDOUT;				\
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			break;						\
		}							\
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		if ((W) && drm_can_sleep()) {				\
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			usleep_range((W), (W)*2);			\
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		} else {						\
			cpu_relax();					\
		}							\
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	}								\
	ret__;								\
})

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#define wait_for(COND, MS)	  	_wait_for((COND), (MS) * 1000, 1000)

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/* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
#if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
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# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
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#else
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# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
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#endif

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#define _wait_for_atomic(COND, US, ATOMIC) \
({ \
	int cpu, ret, timeout = (US) * 1000; \
	u64 base; \
	_WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
	if (!(ATOMIC)) { \
		preempt_disable(); \
		cpu = smp_processor_id(); \
	} \
	base = local_clock(); \
	for (;;) { \
		u64 now = local_clock(); \
		if (!(ATOMIC)) \
			preempt_enable(); \
		if (COND) { \
			ret = 0; \
			break; \
		} \
		if (now - base >= timeout) { \
			ret = -ETIMEDOUT; \
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			break; \
		} \
		cpu_relax(); \
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		if (!(ATOMIC)) { \
			preempt_disable(); \
			if (unlikely(cpu != smp_processor_id())) { \
				timeout -= now - base; \
				cpu = smp_processor_id(); \
				base = local_clock(); \
			} \
		} \
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	} \
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	ret; \
})

#define wait_for_us(COND, US) \
({ \
	int ret__; \
	BUILD_BUG_ON(!__builtin_constant_p(US)); \
	if ((US) > 10) \
		ret__ = _wait_for((COND), (US), 10); \
	else \
		ret__ = _wait_for_atomic((COND), (US), 0); \
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	ret__; \
})

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#define wait_for_atomic_us(COND, US) \
({ \
	BUILD_BUG_ON(!__builtin_constant_p(US)); \
	BUILD_BUG_ON((US) > 50000); \
	_wait_for_atomic((COND), (US), 1); \
})

#define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
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#define KHz(x) (1000 * (x))
#define MHz(x) KHz(1000 * (x))
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/*
 * Display related stuff
 */

/* store information about an Ixxx DVO */
/* The i830->i865 use multiple DVOs with multiple i2cs */
/* the i915, i945 have a single sDVO i2c bus - which is different */
#define MAX_OUTPUTS 6
/* maximum connectors per crtcs in the mode set */

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/* Maximum cursor sizes */
#define GEN2_CURSOR_WIDTH 64
#define GEN2_CURSOR_HEIGHT 64
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#define MAX_CURSOR_WIDTH 256
#define MAX_CURSOR_HEIGHT 256
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#define INTEL_I2C_BUS_DVO 1
#define INTEL_I2C_BUS_SDVO 2

/* these are outputs from the chip - integrated only
   external chips are via DVO or SDVO output */
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enum intel_output_type {
	INTEL_OUTPUT_UNUSED = 0,
	INTEL_OUTPUT_ANALOG = 1,
	INTEL_OUTPUT_DVO = 2,
	INTEL_OUTPUT_SDVO = 3,
	INTEL_OUTPUT_LVDS = 4,
	INTEL_OUTPUT_TVOUT = 5,
	INTEL_OUTPUT_HDMI = 6,
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	INTEL_OUTPUT_DP = 7,
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	INTEL_OUTPUT_EDP = 8,
	INTEL_OUTPUT_DSI = 9,
	INTEL_OUTPUT_UNKNOWN = 10,
	INTEL_OUTPUT_DP_MST = 11,
};
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#define INTEL_DVO_CHIP_NONE 0
#define INTEL_DVO_CHIP_LVDS 1
#define INTEL_DVO_CHIP_TMDS 2
#define INTEL_DVO_CHIP_TVOUT 4

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#define INTEL_DSI_VIDEO_MODE	0
#define INTEL_DSI_COMMAND_MODE	1
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struct intel_framebuffer {
	struct drm_framebuffer base;
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	struct drm_i915_gem_object *obj;
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	struct intel_rotation_info rot_info;
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	/* for each plane in the normal GTT view */
	struct {
		unsigned int x, y;
	} normal[2];
	/* for each plane in the rotated GTT view */
	struct {
		unsigned int x, y;
		unsigned int pitch; /* pixels */
	} rotated[2];
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};

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struct intel_fbdev {
	struct drm_fb_helper helper;
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	struct intel_framebuffer *fb;
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	struct i915_vma *vma;
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	async_cookie_t cookie;
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	int preferred_bpp;
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};
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struct intel_encoder {
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	struct drm_encoder base;
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	enum intel_output_type type;
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	enum port port;
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	unsigned int cloneable;
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	void (*hot_plug)(struct intel_encoder *);
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	bool (*compute_config)(struct intel_encoder *,
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			       struct intel_crtc_state *,
			       struct drm_connector_state *);
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	void (*pre_pll_enable)(struct intel_encoder *,
			       struct intel_crtc_state *,
			       struct drm_connector_state *);
	void (*pre_enable)(struct intel_encoder *,
			   struct intel_crtc_state *,
			   struct drm_connector_state *);
	void (*enable)(struct intel_encoder *,
		       struct intel_crtc_state *,
		       struct drm_connector_state *);
	void (*disable)(struct intel_encoder *,
			struct intel_crtc_state *,
			struct drm_connector_state *);
	void (*post_disable)(struct intel_encoder *,
			     struct intel_crtc_state *,
			     struct drm_connector_state *);
	void (*post_pll_disable)(struct intel_encoder *,
				 struct intel_crtc_state *,
				 struct drm_connector_state *);
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	/* Read out the current hw state of this connector, returning true if
	 * the encoder is active. If the encoder is enabled it also set the pipe
	 * it is connected to in the pipe parameter. */
	bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
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	/* Reconstructs the equivalent mode flags for the current hardware
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	 * state. This must be called _after_ display->get_pipe_config has
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	 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
	 * be set correctly before calling this function. */
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	void (*get_config)(struct intel_encoder *,
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			   struct intel_crtc_state *pipe_config);
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	/* Returns a mask of power domains that need to be referenced as part
	 * of the hardware state readout code. */
	u64 (*get_power_domains)(struct intel_encoder *encoder);
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	/*
	 * Called during system suspend after all pending requests for the
	 * encoder are flushed (for example for DP AUX transactions) and
	 * device interrupts are disabled.
	 */
	void (*suspend)(struct intel_encoder *);
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	int crtc_mask;
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	enum hpd_pin hpd_pin;
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	enum intel_display_power_domain power_domain;
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	/* for communication with audio component; protected by av_mutex */
	const struct drm_connector *audio_connector;
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};

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struct intel_panel {
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	struct drm_display_mode *fixed_mode;
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	struct drm_display_mode *downclock_mode;
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	/* backlight */
	struct {
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		bool present;
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		u32 level;
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		u32 min;
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		u32 max;
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		bool enabled;
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		bool combination_mode;	/* gen 2/4 only */
		bool active_low_pwm;
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		bool alternate_pwm_increment;	/* lpt+ */
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		/* PWM chip */
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		bool util_pin_active_low;	/* bxt+ */
		u8 controller;		/* bxt+ only */
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		struct pwm_device *pwm;

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		struct backlight_device *device;
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		/* Connector and platform specific backlight functions */
		int (*setup)(struct intel_connector *connector, enum pipe pipe);
		uint32_t (*get)(struct intel_connector *connector);
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		void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
		void (*disable)(const struct drm_connector_state *conn_state);
		void (*enable)(const struct intel_crtc_state *crtc_state,
			       const struct drm_connector_state *conn_state);
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		uint32_t (*hz_to_pwm)(struct intel_connector *connector,
				      uint32_t hz);
		void (*power)(struct intel_connector *, bool enable);
	} backlight;
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};

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struct intel_connector {
	struct drm_connector base;
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	/*
	 * The fixed encoder this connector is connected to.
	 */
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	struct intel_encoder *encoder;
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	/* ACPI device id for ACPI and driver cooperation */
	u32 acpi_device_id;

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	/* Reads out the current hw, returning true if the connector is enabled
	 * and active (i.e. dpms ON state). */
	bool (*get_hw_state)(struct intel_connector *);
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	/* Panel info for eDP and LVDS */
	struct intel_panel panel;
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	/* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
	struct edid *edid;
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	struct edid *detect_edid;
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	/* since POLL and HPD connectors may use the same HPD line keep the native
	   state of connector->polled in case hotplug storm detection changes it */
	u8 polled;
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	void *port; /* store this opaque as its illegal to dereference it */

	struct intel_dp *mst_port;
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	/* Work struct to schedule a uevent on link train failure */
	struct work_struct modeset_retry_work;
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};

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struct intel_digital_connector_state {
	struct drm_connector_state base;

	enum hdmi_force_audio force_audio;
	int broadcast_rgb;
};

#define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)

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struct dpll {
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	/* given values */
	int n;
	int m1, m2;
	int p1, p2;
	/* derived values */
	int	dot;
	int	vco;
	int	m;
	int	p;
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};
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struct intel_atomic_state {
	struct drm_atomic_state base;

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	struct {
		/*
		 * Logical state of cdclk (used for all scaling, watermark,
		 * etc. calculations and checks). This is computed as if all
		 * enabled crtcs were active.
		 */
		struct intel_cdclk_state logical;

		/*
		 * Actual state of cdclk, can be different from the logical
		 * state only when all crtc's are DPMS off.
		 */
		struct intel_cdclk_state actual;
	} cdclk;
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	bool dpll_set, modeset;

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	/*
	 * Does this transaction change the pipes that are active?  This mask
	 * tracks which CRTC's have changed their active state at the end of
	 * the transaction (not counting the temporary disable during modesets).
	 * This mask should only be non-zero when intel_state->modeset is true,
	 * but the converse is not necessarily true; simply changing a mode may
	 * not flip the final active status of any CRTC's
	 */
	unsigned int active_pipe_changes;

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	unsigned int active_crtcs;
	unsigned int min_pixclk[I915_MAX_PIPES];

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	struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
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	/*
	 * Current watermarks can't be trusted during hardware readout, so
	 * don't bother calculating intermediate watermarks.
	 */
	bool skip_intermediate_wm;
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	/* Gen9+ only */
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	struct skl_wm_values wm_results;
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	struct i915_sw_fence commit_ready;
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	struct llist_node freed;
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};

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struct intel_plane_state {
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	struct drm_plane_state base;
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	struct drm_rect clip;
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	struct i915_vma *vma;
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	struct {
		u32 offset;
		int x, y;
	} main;
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	struct {
		u32 offset;
		int x, y;
	} aux;
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	/* plane control register */
	u32 ctl;

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	/*
	 * scaler_id
	 *    = -1 : not using a scaler
	 *    >=  0 : using a scalers
	 *
	 * plane requiring a scaler:
	 *   - During check_plane, its bit is set in
	 *     crtc_state->scaler_state.scaler_users by calling helper function
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	 *     update_scaler_plane.
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	 *   - scaler_id indicates the scaler it got assigned.
	 *
	 * plane doesn't require a scaler:
	 *   - this can happen when scaling is no more required or plane simply
	 *     got disabled.
	 *   - During check_plane, corresponding bit is reset in
	 *     crtc_state->scaler_state.scaler_users by calling helper function
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	 *     update_scaler_plane.
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	 */
	int scaler_id;
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	struct drm_intel_sprite_colorkey ckey;
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};

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struct intel_initial_plane_config {
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	struct intel_framebuffer *fb;
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	unsigned int tiling;
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	int size;
	u32 base;
};

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#define SKL_MIN_SRC_W 8
#define SKL_MAX_SRC_W 4096
#define SKL_MIN_SRC_H 8
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#define SKL_MAX_SRC_H 4096
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#define SKL_MIN_DST_W 8
#define SKL_MAX_DST_W 4096
#define SKL_MIN_DST_H 8
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#define SKL_MAX_DST_H 4096
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struct intel_scaler {
	int in_use;
	uint32_t mode;
};

struct intel_crtc_scaler_state {
#define SKL_NUM_SCALERS 2
	struct intel_scaler scalers[SKL_NUM_SCALERS];

	/*
	 * scaler_users: keeps track of users requesting scalers on this crtc.
	 *
	 *     If a bit is set, a user is using a scaler.
	 *     Here user can be a plane or crtc as defined below:
	 *       bits 0-30 - plane (bit position is index from drm_plane_index)
	 *       bit 31    - crtc
	 *
	 * Instead of creating a new index to cover planes and crtc, using
	 * existing drm_plane_index for planes which is well less than 31
	 * planes and bit 31 for crtc. This should be fine to cover all
	 * our platforms.
	 *
	 * intel_atomic_setup_scalers will setup available scalers to users
	 * requesting scalers. It will gracefully fail if request exceeds
	 * avilability.
	 */
#define SKL_CRTC_INDEX 31
	unsigned scaler_users;

	/* scaler used by crtc for panel fitting purpose */
	int scaler_id;
};

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/* drm_mode->private_flags */
#define I915_MODE_FLAG_INHERITED 1

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struct intel_pipe_wm {
	struct intel_wm_level wm[5];
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	struct intel_wm_level raw_wm[5];
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	uint32_t linetime;
	bool fbc_wm_enabled;
	bool pipe_enabled;
	bool sprites_enabled;
	bool sprites_scaled;
};

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struct skl_plane_wm {
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	struct skl_wm_level wm[8];
	struct skl_wm_level trans_wm;
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};

struct skl_pipe_wm {
	struct skl_plane_wm planes[I915_MAX_PLANES];
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	uint32_t linetime;
};

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enum vlv_wm_level {
	VLV_WM_LEVEL_PM2,
	VLV_WM_LEVEL_PM5,
	VLV_WM_LEVEL_DDR_DVFS,
	NUM_VLV_WM_LEVELS,
};

struct vlv_wm_state {
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	struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
	struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
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	uint8_t num_levels;
	bool cxsr;
};

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struct vlv_fifo_state {
	u16 plane[I915_MAX_PLANES];
};

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enum g4x_wm_level {
	G4X_WM_LEVEL_NORMAL,
	G4X_WM_LEVEL_SR,
	G4X_WM_LEVEL_HPLL,
	NUM_G4X_WM_LEVELS,
};

struct g4x_wm_state {
	struct g4x_pipe_wm wm;
	struct g4x_sr_wm sr;
	struct g4x_sr_wm hpll;
	bool cxsr;
	bool hpll_en;
	bool fbc_en;
};

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struct intel_crtc_wm_state {
	union {
		struct {
			/*
			 * Intermediate watermarks; these can be
			 * programmed immediately since they satisfy
			 * both the current configuration we're
			 * switching away from and the new
			 * configuration we're switching to.
			 */
			struct intel_pipe_wm intermediate;

			/*
			 * Optimal watermarks, programmed post-vblank
			 * when this state is committed.
			 */
			struct intel_pipe_wm optimal;
		} ilk;

		struct {
			/* gen9+ only needs 1-step wm programming */
			struct skl_pipe_wm optimal;
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			struct skl_ddb_entry ddb;
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		} skl;
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		struct {
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			/* "raw" watermarks (not inverted) */
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			struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
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			/* intermediate watermarks (inverted) */
			struct vlv_wm_state intermediate;
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			/* optimal watermarks (inverted) */
			struct vlv_wm_state optimal;
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			/* display FIFO split */
			struct vlv_fifo_state fifo_state;
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		} vlv;
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		struct {
			/* "raw" watermarks */
			struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
			/* intermediate watermarks */
			struct g4x_wm_state intermediate;
			/* optimal watermarks */
			struct g4x_wm_state optimal;
		} g4x;
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	};

	/*
	 * Platforms with two-step watermark programming will need to
	 * update watermark programming post-vblank to switch from the
	 * safe intermediate watermarks to the optimal final
	 * watermarks.
	 */
	bool need_postvbl_update;
};

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struct intel_crtc_state {
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	struct drm_crtc_state base;

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	/**
	 * quirks - bitfield with hw state readout quirks
	 *
	 * For various reasons the hw state readout code might not be able to
	 * completely faithfully read out the current state. These cases are
	 * tracked with quirk flags so that fastboot and state checker can act
	 * accordingly.
	 */
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#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS	(1<<0) /* unreliable sync mode.flags */
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	unsigned long quirks;

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	unsigned fb_bits; /* framebuffers to flip */
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	bool update_pipe; /* can a fast modeset be performed? */
	bool disable_cxsr;
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	bool update_wm_pre, update_wm_post; /* watermarks are updated */
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	bool fb_changed; /* fb on any of the planes is changed */
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	bool fifo_changed; /* FIFO split is changed */
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	/* Pipe source size (ie. panel fitter input size)
	 * All planes will be positioned inside this space,
	 * and get clipped at the edges. */
	int pipe_src_w, pipe_src_h;

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	/*
	 * Pipe pixel rate, adjusted for
	 * panel fitter/pipe scaler downscaling.
	 */
	unsigned int pixel_rate;

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	/* Whether to set up the PCH/FDI. Note that we never allow sharing
	 * between pch encoders and cpu encoders. */
	bool has_pch_encoder;
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	/* Are we sending infoframes on the attached port */
	bool has_infoframe;

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	/* CPU Transcoder for the pipe. Currently this can only differ from the
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	 * pipe on Haswell and later (where we have a special eDP transcoder)
	 * and Broxton (where we have special DSI transcoders). */
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	enum transcoder cpu_transcoder;

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	/*
	 * Use reduced/limited/broadcast rbg range, compressing from the full
	 * range fed into the crtcs.
	 */
	bool limited_color_range;

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	/* Bitmask of encoder types (enum intel_output_type)
	 * driven by the pipe.
	 */
	unsigned int output_types;

660 661 662
	/* Whether we should send NULL infoframes. Required for audio. */
	bool has_hdmi_sink;

663 664 665 666
	/* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
	 * has_dp_encoder is set. */
	bool has_audio;

667 668 669 670
	/*
	 * Enable dithering, used when the selected pipe bpp doesn't match the
	 * plane bpp.
	 */
671
	bool dither;
672

673 674 675 676 677 678 679 680
	/*
	 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
	 * compliance video pattern tests.
	 * Disable dither only if it is a compliance test request for
	 * 18bpp.
	 */
	bool dither_force_disable;

681 682 683
	/* Controls for the clock computation, to override various stages. */
	bool clock_set;

684 685 686 687
	/* SDVO TV has a bunch of special case. To make multifunction encoders
	 * work correctly, we need to track this at runtime.*/
	bool sdvo_tv_clock;

688 689 690 691 692 693 694
	/*
	 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
	 * required. This is set in the 2nd loop of calling encoder's
	 * ->compute_config if the first pick doesn't work out.
	 */
	bool bw_constrained;

695 696
	/* Settings for the intel dpll used on pretty much everything but
	 * haswell. */
697
	struct dpll dpll;
698

699 700
	/* Selected dpll when shared or NULL. */
	struct intel_shared_dpll *shared_dpll;
701

702 703 704
	/* Actual register state of the dpll, for shared dpll cross-checking. */
	struct intel_dpll_hw_state dpll_hw_state;

705 706 707 708 709
	/* DSI PLL registers */
	struct {
		u32 ctrl, div;
	} dsi_pll;

710
	int pipe_bpp;
711
	struct intel_link_m_n dp_m_n;
712

713 714
	/* m2_n2 for eDP downclock */
	struct intel_link_m_n dp_m2_n2;
715
	bool has_drrs;
716

717 718
	/*
	 * Frequence the dpll for the port should run at. Differs from the
719 720
	 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
	 * already multiplied by pixel_multiplier.
721
	 */
722 723
	int port_clock;

724 725
	/* Used by SDVO (and if we ever fix it, HDMI). */
	unsigned pixel_multiplier;
726

727 728
	uint8_t lane_count;

729 730 731 732 733 734
	/*
	 * Used by platforms having DP/HDMI PHY with programmable lane
	 * latency optimization.
	 */
	uint8_t lane_lat_optim_mask;

735
	/* Panel fitter controls for gen2-gen4 + VLV */
736 737 738
	struct {
		u32 control;
		u32 pgm_ratios;
739
		u32 lvds_border_bits;
740 741 742 743 744 745
	} gmch_pfit;

	/* Panel fitter placement and size for Ironlake+ */
	struct {
		u32 pos;
		u32 size;
746
		bool enabled;
747
		bool force_thru;
748
	} pch_pfit;
749

750
	/* FDI configuration, only valid if has_pch_encoder is set. */
751
	int fdi_lanes;
752
	struct intel_link_m_n fdi_m_n;
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Paulo Zanoni 已提交
753 754

	bool ips_enabled;
755

756 757
	bool enable_fbc;

758
	bool double_wide;
759 760

	int pbn;
761 762

	struct intel_crtc_scaler_state scaler_state;
763 764 765

	/* w/a for waiting 2 vblanks during crtc enable */
	enum pipe hsw_workaround_pipe;
766 767 768

	/* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
	bool disable_lp_wm;
769

770
	struct intel_crtc_wm_state wm;
771 772 773

	/* Gamma mode programmed on the pipe */
	uint32_t gamma_mode;
774 775 776

	/* bitmask of visible planes (enum plane_id) */
	u8 active_planes;
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777 778 779 780 781 782

	/* HDMI scrambling status */
	bool hdmi_scrambling;

	/* HDMI High TMDS char rate ratio */
	bool hdmi_high_tmds_clock_ratio;
783 784
};

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785 786
struct intel_crtc {
	struct drm_crtc base;
787 788
	enum pipe pipe;
	enum plane plane;
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789
	u8 lut_r[256], lut_g[256], lut_b[256];
790 791 792 793 794 795
	/*
	 * Whether the crtc and the connected output pipeline is active. Implies
	 * that crtc->enabled is set, i.e. the current mode configuration has
	 * some outputs connected to this crtc.
	 */
	bool active;
796
	bool lowfreq_avail;
797
	u8 plane_ids_mask;
798
	unsigned long long enabled_power_domains;
799
	struct intel_overlay *overlay;
800
	struct intel_flip_work *flip_work;
801

802 803
	atomic_t unpin_work_count;

804 805 806
	/* Display surface base address adjustement for pageflips. Note that on
	 * gen4+ this only adjusts up to a tile, offsets within a tile are
	 * handled in the hw itself (with the TILEOFF register). */
807
	u32 dspaddr_offset;
808 809
	int adjusted_x;
	int adjusted_y;
810

811
	struct intel_crtc_state *config;
812

813 814
	/* global reset count when the last flip was submitted */
	unsigned int reset_count;
815

816 817 818
	/* Access to these should be protected by dev_priv->irq_lock. */
	bool cpu_fifo_underrun_disabled;
	bool pch_fifo_underrun_disabled;
819 820 821 822

	/* per-pipe watermark state */
	struct {
		/* watermarks currently being used  */
823 824
		union {
			struct intel_pipe_wm ilk;
825
			struct vlv_wm_state vlv;
826
			struct g4x_wm_state g4x;
827
		} active;
828
	} wm;
829

830
	int scanline_offset;
831

832 833 834 835 836 837
	struct {
		unsigned start_vbl_count;
		ktime_t start_vbl_time;
		int min_vbl, max_vbl;
		int scanline_start;
	} debug;
838

839 840
	/* scalers available on this crtc */
	int num_scalers;
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Jesse Barnes 已提交
841 842
};

843 844
struct intel_plane {
	struct drm_plane base;
845 846
	u8 plane;
	enum plane_id id;
847
	enum pipe pipe;
848
	bool can_scale;
849
	int max_downscale;
850
	uint32_t frontbuffer_bit;
851

852 853 854 855
	struct {
		u32 base, cntl, size;
	} cursor;

856 857 858
	/*
	 * NOTE: Do not place new plane state fields here (e.g., when adding
	 * new plane properties).  New runtime state should now be placed in
859
	 * the intel_plane_state structure and accessed via plane_state.
860 861
	 */

862
	void (*update_plane)(struct intel_plane *plane,
863 864
			     const struct intel_crtc_state *crtc_state,
			     const struct intel_plane_state *plane_state);
865 866 867
	void (*disable_plane)(struct intel_plane *plane,
			      struct intel_crtc *crtc);
	int (*check_plane)(struct intel_plane *plane,
868
			   struct intel_crtc_state *crtc_state,
869
			   struct intel_plane_state *state);
870 871
};

872
struct intel_watermark_params {
873 874 875 876 877
	u16 fifo_size;
	u16 max_wm;
	u8 default_wm;
	u8 guard_size;
	u8 cacheline_size;
878 879 880
};

struct cxsr_latency {
881 882
	bool is_desktop : 1;
	bool is_ddr3 : 1;
883 884 885 886 887 888
	u16 fsb_freq;
	u16 mem_freq;
	u16 display_sr;
	u16 display_hpll_disable;
	u16 cursor_sr;
	u16 cursor_hpll_disable;
889 890
};

891
#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
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892
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
893
#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
894
#define to_intel_connector(x) container_of(x, struct intel_connector, base)
895
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
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896
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
897
#define to_intel_plane(x) container_of(x, struct intel_plane, base)
898
#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
899
#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
J
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900

901
struct intel_hdmi {
902
	i915_reg_t hdmi_reg;
903
	int ddc_bus;
904 905 906 907
	struct {
		enum drm_dp_dual_mode_type type;
		int max_tmds_clock;
	} dp_dual_mode;
908 909
	bool has_hdmi_sink;
	bool has_audio;
910
	bool rgb_quant_range_selectable;
911
	struct intel_connector *attached_connector;
912
	void (*write_infoframe)(struct drm_encoder *encoder,
913
				const struct intel_crtc_state *crtc_state,
914
				enum hdmi_infoframe_type type,
915
				const void *frame, ssize_t len);
916
	void (*set_infoframes)(struct drm_encoder *encoder,
917
			       bool enable,
918 919
			       const struct intel_crtc_state *crtc_state,
			       const struct drm_connector_state *conn_state);
920 921
	bool (*infoframe_enabled)(struct drm_encoder *encoder,
				  const struct intel_crtc_state *pipe_config);
922 923
};

924
struct intel_dp_mst_encoder;
925
#define DP_MAX_DOWNSTREAM_PORTS		0x10
926

927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946
/*
 * enum link_m_n_set:
 *	When platform provides two set of M_N registers for dp, we can
 *	program them and switch between them incase of DRRS.
 *	But When only one such register is provided, we have to program the
 *	required divider value on that registers itself based on the DRRS state.
 *
 * M1_N1	: Program dp_m_n on M1_N1 registers
 *			  dp_m2_n2 on M2_N2 registers (If supported)
 *
 * M2_N2	: Program dp_m2_n2 on M1_N1 registers
 *			  M2_N2 registers are not supported
 */

enum link_m_n_set {
	/* Sets the m1_n1 and m2_n2 */
	M1_N1 = 0,
	M2_N2
};

947 948 949 950 951 952 953 954
struct intel_dp_desc {
	u8 oui[3];
	u8 device_id[6];
	u8 hw_rev;
	u8 sw_major_rev;
	u8 sw_minor_rev;
} __packed;

955 956
struct intel_dp_compliance_data {
	unsigned long edid;
957 958 959
	uint8_t video_pattern;
	uint16_t hdisplay, vdisplay;
	uint8_t bpc;
960 961 962 963 964 965
};

struct intel_dp_compliance {
	unsigned long test_type;
	struct intel_dp_compliance_data test_data;
	bool test_active;
966 967
	int test_link_rate;
	u8 test_lane_count;
968 969
};

970
struct intel_dp {
971 972 973
	i915_reg_t output_reg;
	i915_reg_t aux_ch_ctl_reg;
	i915_reg_t aux_ch_data_reg[5];
974
	uint32_t DP;
975 976
	int link_rate;
	uint8_t lane_count;
977
	uint8_t sink_count;
978
	bool link_mst;
979
	bool has_audio;
980
	bool detect_done;
981
	bool channel_eq_status;
982
	bool reset_link_params;
983
	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
984
	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
985
	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
986
	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
987 988 989
	/* source rates */
	int num_source_rates;
	const int *source_rates;
990 991
	/* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
	int num_sink_rates;
992
	int sink_rates[DP_MAX_SUPPORTED_RATES];
993
	bool use_rate_select;
994 995 996
	/* intersection of source and sink rates */
	int num_common_rates;
	int common_rates[DP_MAX_SUPPORTED_RATES];
997 998 999 1000
	/* Max lane count for the current link */
	int max_link_lane_count;
	/* Max rate for the current link */
	int max_link_rate;
1001 1002
	/* sink or branch descriptor */
	struct intel_dp_desc desc;
1003
	struct drm_dp_aux aux;
1004
	enum intel_display_power_domain aux_power_domain;
1005 1006 1007 1008 1009 1010 1011 1012
	uint8_t train_set[4];
	int panel_power_up_delay;
	int panel_power_down_delay;
	int panel_power_cycle_delay;
	int backlight_on_delay;
	int backlight_off_delay;
	struct delayed_work panel_vdd_work;
	bool want_panel_vdd;
1013 1014
	unsigned long last_power_on;
	unsigned long last_backlight_off;
1015
	ktime_t panel_power_off_time;
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Dave Airlie 已提交
1016

1017 1018
	struct notifier_block edp_notifier;

1019 1020 1021 1022 1023
	/*
	 * Pipe whose power sequencer is currently locked into
	 * this port. Only relevant on VLV/CHV.
	 */
	enum pipe pps_pipe;
1024 1025 1026 1027 1028 1029
	/*
	 * Pipe currently driving the port. Used for preventing
	 * the use of the PPS for any pipe currentrly driving
	 * external DP as that will mess things up on VLV.
	 */
	enum pipe active_pipe;
1030 1031 1032 1033 1034
	/*
	 * Set if the sequencer may be reset due to a power transition,
	 * requiring a reinitialization. Only relevant on BXT.
	 */
	bool pps_reset;
1035
	struct edp_power_seq pps_delays;
1036

1037 1038
	bool can_mst; /* this port supports mst */
	bool is_mst;
1039
	int active_mst_links;
1040
	/* connector directly attached - won't be use for modeset in mst world */
1041
	struct intel_connector *attached_connector;
1042

1043 1044 1045 1046
	/* mst connector list */
	struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
	struct drm_dp_mst_topology_mgr mst_mgr;

1047
	uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1048 1049 1050 1051 1052 1053 1054 1055
	/*
	 * This function returns the value we have to program the AUX_CTL
	 * register with to kick off an AUX transaction.
	 */
	uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
				     bool has_aux_irq,
				     int send_bytes,
				     uint32_t aux_clock_divider);
1056 1057 1058 1059

	/* This is called before a link training is starterd */
	void (*prepare_link_retrain)(struct intel_dp *intel_dp);

1060
	/* Displayport compliance testing */
1061
	struct intel_dp_compliance compliance;
1062 1063
};

1064 1065 1066 1067 1068
struct intel_lspcon {
	bool active;
	enum drm_lspcon_mode mode;
};

1069 1070
struct intel_digital_port {
	struct intel_encoder base;
1071
	enum port port;
1072
	u32 saved_port_bits;
1073 1074
	struct intel_dp dp;
	struct intel_hdmi hdmi;
1075
	struct intel_lspcon lspcon;
1076
	enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1077
	bool release_cl2_override;
1078
	uint8_t max_lanes;
1079
	enum intel_display_power_domain ddi_io_power_domain;
1080 1081
};

1082 1083 1084 1085
struct intel_dp_mst_encoder {
	struct intel_encoder base;
	enum pipe pipe;
	struct intel_digital_port *primary;
1086
	struct intel_connector *connector;
1087 1088
};

1089
static inline enum dpio_channel
1090 1091 1092 1093
vlv_dport_to_channel(struct intel_digital_port *dport)
{
	switch (dport->port) {
	case PORT_B:
1094
	case PORT_D:
1095
		return DPIO_CH0;
1096
	case PORT_C:
1097
		return DPIO_CH1;
1098 1099 1100 1101 1102
	default:
		BUG();
	}
}

1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117
static inline enum dpio_phy
vlv_dport_to_phy(struct intel_digital_port *dport)
{
	switch (dport->port) {
	case PORT_B:
	case PORT_C:
		return DPIO_PHY0;
	case PORT_D:
		return DPIO_PHY1;
	default:
		BUG();
	}
}

static inline enum dpio_channel
1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130
vlv_pipe_to_channel(enum pipe pipe)
{
	switch (pipe) {
	case PIPE_A:
	case PIPE_C:
		return DPIO_CH0;
	case PIPE_B:
		return DPIO_CH1;
	default:
		BUG();
	}
}

1131
static inline struct intel_crtc *
1132
intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1133 1134 1135 1136
{
	return dev_priv->pipe_to_crtc_mapping[pipe];
}

1137
static inline struct intel_crtc *
1138
intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1139 1140 1141 1142
{
	return dev_priv->plane_to_crtc_mapping[plane];
}

1143 1144 1145 1146
struct intel_flip_work {
	struct work_struct unpin_work;
	struct work_struct mmio_work;

1147
	struct drm_crtc *crtc;
1148
	struct i915_vma *old_vma;
1149 1150
	struct drm_framebuffer *old_fb;
	struct drm_i915_gem_object *pending_flip_obj;
1151
	struct drm_pending_vblank_event *event;
1152
	atomic_t pending;
1153 1154 1155
	u32 flip_count;
	u32 gtt_offset;
	struct drm_i915_gem_request *flip_queued_req;
1156
	u32 flip_queued_vblank;
1157 1158
	u32 flip_ready_vblank;
	unsigned int rotation;
1159 1160
};

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Paulo Zanoni 已提交
1161
struct intel_load_detect_pipe {
1162
	struct drm_atomic_state *restore_state;
P
Paulo Zanoni 已提交
1163
};
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1164

P
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1165 1166
static inline struct intel_encoder *
intel_attached_encoder(struct drm_connector *connector)
1167 1168 1169 1170
{
	return to_intel_connector(connector)->encoder;
}

1171 1172 1173
static inline struct intel_digital_port *
enc_to_dig_port(struct drm_encoder *encoder)
{
1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186
	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);

	switch (intel_encoder->type) {
	case INTEL_OUTPUT_UNKNOWN:
		WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
	case INTEL_OUTPUT_DP:
	case INTEL_OUTPUT_EDP:
	case INTEL_OUTPUT_HDMI:
		return container_of(encoder, struct intel_digital_port,
				    base.base);
	default:
		return NULL;
	}
1187 1188
}

1189 1190 1191 1192 1193 1194
static inline struct intel_dp_mst_encoder *
enc_to_mst(struct drm_encoder *encoder)
{
	return container_of(encoder, struct intel_dp_mst_encoder, base.base);
}

1195 1196 1197
static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
{
	return &enc_to_dig_port(encoder)->dp;
1198 1199 1200 1201 1202 1203 1204 1205
}

static inline struct intel_digital_port *
dp_to_dig_port(struct intel_dp *intel_dp)
{
	return container_of(intel_dp, struct intel_digital_port, dp);
}

1206 1207 1208 1209 1210 1211
static inline struct intel_lspcon *
dp_to_lspcon(struct intel_dp *intel_dp)
{
	return &dp_to_dig_port(intel_dp)->lspcon;
}

1212 1213 1214 1215
static inline struct intel_digital_port *
hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
{
	return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1216 1217
}

1218
/* intel_fifo_underrun.c */
1219
bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1220
					   enum pipe pipe, bool enable);
1221
bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1222 1223
					   enum transcoder pch_transcoder,
					   bool enable);
1224 1225 1226 1227
void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
					 enum pipe pipe);
void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
					 enum transcoder pch_transcoder);
1228 1229
void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1230 1231

/* i915_irq.c */
1232 1233
void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1234 1235 1236
void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1237 1238
void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1239
void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1240 1241
void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1242 1243 1244 1245 1246 1247 1248

static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
					    u32 mask)
{
	return mask & ~i915->rps.pm_intrmsk_mbz;
}

1249 1250
void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1251 1252 1253 1254 1255 1256
static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
{
	/*
	 * We only use drm_irq_uninstall() at unload and VT switch, so
	 * this is the only thing we need to check.
	 */
1257
	return dev_priv->pm.irqs_enabled;
1258 1259
}

1260
int intel_get_crtc_scanline(struct intel_crtc *crtc);
1261 1262
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
				     unsigned int pipe_mask);
1263 1264
void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
				     unsigned int pipe_mask);
1265 1266 1267
void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
P
Paulo Zanoni 已提交
1268 1269

/* intel_crt.c */
1270
void intel_crt_init(struct drm_i915_private *dev_priv);
1271
void intel_crt_reset(struct drm_encoder *encoder);
P
Paulo Zanoni 已提交
1272 1273

/* intel_ddi.c */
1274 1275 1276
void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
				struct intel_crtc_state *old_crtc_state,
				struct drm_connector_state *old_conn_state);
1277 1278
void hsw_fdi_link_train(struct intel_crtc *crtc,
			const struct intel_crtc_state *crtc_state);
1279
void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1280 1281
enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1282
void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1283 1284
void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
				       enum transcoder cpu_transcoder);
1285 1286
void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1287 1288
struct intel_encoder *
intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1289
void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1290
void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1291
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1292 1293
bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
				 struct intel_crtc *intel_crtc);
1294
void intel_ddi_get_config(struct intel_encoder *encoder,
1295
			  struct intel_crtc_state *pipe_config);
P
Paulo Zanoni 已提交
1296

1297
void intel_ddi_clock_get(struct intel_encoder *encoder,
1298
			 struct intel_crtc_state *pipe_config);
1299 1300
void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
				    bool state);
1301
uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1302 1303
u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);

1304 1305
unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
				   int plane, unsigned int height);
1306

1307
/* intel_audio.c */
1308
void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1309 1310 1311
void intel_audio_codec_enable(struct intel_encoder *encoder,
			      const struct intel_crtc_state *crtc_state,
			      const struct drm_connector_state *conn_state);
1312
void intel_audio_codec_disable(struct intel_encoder *encoder);
I
Imre Deak 已提交
1313 1314
void i915_audio_component_init(struct drm_i915_private *dev_priv);
void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1315 1316
void intel_audio_init(struct drm_i915_private *dev_priv);
void intel_audio_deinit(struct drm_i915_private *dev_priv);
1317

1318
/* intel_cdclk.c */
1319 1320
void skl_init_cdclk(struct drm_i915_private *dev_priv);
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1321 1322
void cnl_init_cdclk(struct drm_i915_private *dev_priv);
void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1323 1324
void bxt_init_cdclk(struct drm_i915_private *dev_priv);
void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1325 1326 1327 1328
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
void intel_update_cdclk(struct drm_i915_private *dev_priv);
void intel_update_rawclk(struct drm_i915_private *dev_priv);
1329 1330
bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
			       const struct intel_cdclk_state *b);
1331 1332
void intel_set_cdclk(struct drm_i915_private *dev_priv,
		     const struct intel_cdclk_state *cdclk_state);
1333

1334
/* intel_display.c */
1335 1336
void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1337
enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1338
void intel_update_rawclk(struct drm_i915_private *dev_priv);
1339
int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1340 1341
int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
		      const char *name, u32 reg, int ref_freq);
1342 1343
int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
			   const char *name, u32 reg);
1344 1345
void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1346
extern const struct drm_plane_funcs intel_plane_funcs;
1347
void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1348
unsigned int intel_fb_xy_to_linear(int x, int y,
1349 1350
				   const struct intel_plane_state *state,
				   int plane);
1351
void intel_add_fb_offsets(int *x, int *y,
1352
			  const struct intel_plane_state *state, int plane);
1353
unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1354
bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1355 1356
void intel_mark_busy(struct drm_i915_private *dev_priv);
void intel_mark_idle(struct drm_i915_private *dev_priv);
1357
int intel_display_suspend(struct drm_device *dev);
1358
void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1359
void intel_encoder_destroy(struct drm_encoder *encoder);
1360 1361
int intel_connector_init(struct intel_connector *);
struct intel_connector *intel_connector_alloc(void);
1362 1363 1364 1365 1366
bool intel_connector_get_hw_state(struct intel_connector *connector);
void intel_connector_attach_encoder(struct intel_connector *connector,
				    struct intel_encoder *encoder);
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
					     struct drm_crtc *crtc);
1367
enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1368 1369
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
1370 1371
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
					     enum pipe pipe);
1372 1373 1374 1375 1376 1377
static inline bool
intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
		    enum intel_output_type type)
{
	return crtc_state->output_types & (1 << type);
}
1378 1379 1380 1381
static inline bool
intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
{
	return crtc_state->output_types &
1382
		((1 << INTEL_OUTPUT_DP) |
1383 1384 1385
		 (1 << INTEL_OUTPUT_DP_MST) |
		 (1 << INTEL_OUTPUT_EDP));
}
1386
static inline void
1387
intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1388
{
1389
	drm_wait_one_vblank(&dev_priv->drm, pipe);
1390
}
1391
static inline void
1392
intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1393
{
1394
	const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1395 1396

	if (crtc->active)
1397
		intel_wait_for_vblank(dev_priv, pipe);
1398
}
1399 1400 1401

u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);

1402
int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1403
void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1404 1405
			 struct intel_digital_port *dport,
			 unsigned int expected_mask);
1406 1407 1408 1409
int intel_get_load_detect_pipe(struct drm_connector *connector,
			       struct drm_display_mode *mode,
			       struct intel_load_detect_pipe *old,
			       struct drm_modeset_acquire_ctx *ctx);
1410
void intel_release_load_detect_pipe(struct drm_connector *connector,
1411 1412
				    struct intel_load_detect_pipe *old,
				    struct drm_modeset_acquire_ctx *ctx);
C
Chris Wilson 已提交
1413 1414
struct i915_vma *
intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1415
void intel_unpin_fb_vma(struct i915_vma *vma);
1416
struct drm_framebuffer *
1417 1418
intel_framebuffer_create(struct drm_i915_gem_object *obj,
			 struct drm_mode_fb_cmd2 *mode_cmd);
1419
void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1420
void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1421
void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1422
int intel_prepare_plane_fb(struct drm_plane *plane,
1423
			   struct drm_plane_state *new_state);
1424
void intel_cleanup_plane_fb(struct drm_plane *plane,
1425
			    struct drm_plane_state *old_state);
1426 1427 1428 1429 1430 1431 1432 1433
int intel_plane_atomic_get_property(struct drm_plane *plane,
				    const struct drm_plane_state *state,
				    struct drm_property *property,
				    uint64_t *val);
int intel_plane_atomic_set_property(struct drm_plane *plane,
				    struct drm_plane_state *state,
				    struct drm_property *property,
				    uint64_t val);
1434 1435
int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
				    struct drm_plane_state *plane_state);
1436

1437 1438 1439
void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
				    enum pipe pipe);

1440
int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1441
		     const struct dpll *dpll);
1442
void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1443
int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1444

1445
/* modesetting asserts */
1446 1447
void assert_panel_unlocked(struct drm_i915_private *dev_priv,
			   enum pipe pipe);
1448 1449 1450 1451
void assert_pll(struct drm_i915_private *dev_priv,
		enum pipe pipe, bool state);
#define assert_pll_enabled(d, p) assert_pll(d, p, true)
#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1452 1453 1454
void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1455 1456 1457 1458
void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
		       enum pipe pipe, bool state);
#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1459
void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1460 1461
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1462
u32 intel_compute_tile_offset(int *x, int *y,
1463
			      const struct intel_plane_state *state, int plane);
1464 1465
void intel_prepare_reset(struct drm_i915_private *dev_priv);
void intel_finish_reset(struct drm_i915_private *dev_priv);
1466 1467
void hsw_enable_pc8(struct drm_i915_private *dev_priv);
void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1468
void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1469 1470
void bxt_enable_dc9(struct drm_i915_private *dev_priv);
void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1471
void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1472
unsigned int skl_cdclk_get_vco(unsigned int freq);
1473 1474
void skl_enable_dc6(struct drm_i915_private *dev_priv);
void skl_disable_dc6(struct drm_i915_private *dev_priv);
1475
void intel_dp_get_m_n(struct intel_crtc *crtc,
1476
		      struct intel_crtc_state *pipe_config);
1477
void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1478
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
I
Imre Deak 已提交
1479
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1480 1481
			struct dpll *best_clock);
int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1482

1483
bool intel_crtc_active(struct intel_crtc *crtc);
1484 1485
void hsw_enable_ips(struct intel_crtc *crtc);
void hsw_disable_ips(struct intel_crtc *crtc);
1486
enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1487
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1488
				 struct intel_crtc_state *pipe_config);
1489

1490
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1491
int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1492

1493 1494 1495 1496
static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
{
	return i915_ggtt_offset(state->vma);
}
1497

1498 1499
u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
		  const struct intel_plane_state *plane_state);
1500 1501
u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
		     unsigned int rotation);
1502
int skl_check_plane_surface(struct intel_plane_state *plane_state);
1503
int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1504

1505
/* intel_csr.c */
1506
void intel_csr_ucode_init(struct drm_i915_private *);
1507
void intel_csr_load_program(struct drm_i915_private *);
1508
void intel_csr_ucode_fini(struct drm_i915_private *);
1509 1510
void intel_csr_ucode_suspend(struct drm_i915_private *);
void intel_csr_ucode_resume(struct drm_i915_private *);
1511

P
Paulo Zanoni 已提交
1512
/* intel_dp.c */
1513 1514
bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
		   enum port port);
1515 1516
bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			     struct intel_connector *intel_connector);
1517
void intel_dp_set_link_params(struct intel_dp *intel_dp,
1518 1519
			      int link_rate, uint8_t lane_count,
			      bool link_mst);
1520 1521
int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
					    int link_rate, uint8_t lane_count);
1522 1523 1524
void intel_dp_start_link_train(struct intel_dp *intel_dp);
void intel_dp_stop_link_train(struct intel_dp *intel_dp);
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1525 1526
void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1527
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1528
int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1529
bool intel_dp_compute_config(struct intel_encoder *encoder,
1530 1531
			     struct intel_crtc_state *pipe_config,
			     struct drm_connector_state *conn_state);
1532
bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
1533 1534
enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
				  bool long_hpd);
1535 1536 1537
void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
			    const struct drm_connector_state *conn_state);
void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1538
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1539 1540
void intel_edp_panel_on(struct intel_dp *intel_dp);
void intel_edp_panel_off(struct intel_dp *intel_dp);
1541 1542
void intel_dp_mst_suspend(struct drm_device *dev);
void intel_dp_mst_resume(struct drm_device *dev);
1543
int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1544
int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1545
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1546
void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1547
void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
R
Rodrigo Vivi 已提交
1548
uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1549
void intel_plane_destroy(struct drm_plane *plane);
1550 1551 1552 1553
void intel_edp_drrs_enable(struct intel_dp *intel_dp,
			   struct intel_crtc_state *crtc_state);
void intel_edp_drrs_disable(struct intel_dp *intel_dp,
			   struct intel_crtc_state *crtc_state);
1554 1555 1556 1557
void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
			       unsigned int frontbuffer_bits);
void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
			  unsigned int frontbuffer_bits);
R
Rodrigo Vivi 已提交
1558

1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570
void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
				       uint8_t dp_train_pat);
void
intel_dp_set_signal_levels(struct intel_dp *intel_dp);
void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
uint8_t
intel_dp_voltage_max(struct intel_dp *intel_dp);
uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
			   uint8_t *link_bw, uint8_t *rate_select);
1571
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1572 1573 1574
bool
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);

1575 1576 1577 1578 1579
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
	return ~((1 << lane_count) - 1) & 0xf;
}

1580
bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1581 1582
bool __intel_dp_read_desc(struct intel_dp *intel_dp,
			  struct intel_dp_desc *desc);
1583
bool intel_dp_read_desc(struct intel_dp *intel_dp);
1584 1585
int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1586 1587
bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
				  struct intel_digital_port *port);
1588

1589 1590 1591
/* intel_dp_aux_backlight.c */
int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);

1592 1593 1594
/* intel_dp_mst.c */
int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
P
Paulo Zanoni 已提交
1595
/* intel_dsi.c */
1596
void intel_dsi_init(struct drm_i915_private *dev_priv);
P
Paulo Zanoni 已提交
1597

1598 1599
/* intel_dsi_dcs_backlight.c */
int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
P
Paulo Zanoni 已提交
1600 1601

/* intel_dvo.c */
1602
void intel_dvo_init(struct drm_i915_private *dev_priv);
1603 1604
/* intel_hotplug.c */
void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
P
Paulo Zanoni 已提交
1605 1606


1607
/* legacy fbdev emulation in intel_fbdev.c */
1608
#ifdef CONFIG_DRM_FBDEV_EMULATION
1609
extern int intel_fbdev_init(struct drm_device *dev);
1610
extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1611
extern void intel_fbdev_fini(struct drm_device *dev);
1612
extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1613 1614
extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
extern void intel_fbdev_restore_mode(struct drm_device *dev);
1615 1616 1617 1618 1619
#else
static inline int intel_fbdev_init(struct drm_device *dev)
{
	return 0;
}
P
Paulo Zanoni 已提交
1620

1621
static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1622 1623 1624 1625 1626 1627 1628
{
}

static inline void intel_fbdev_fini(struct drm_device *dev)
{
}

1629
static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1630 1631 1632
{
}

1633 1634 1635 1636
static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
{
}

1637
static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1638 1639 1640
{
}
#endif
P
Paulo Zanoni 已提交
1641

1642
/* intel_fbc.c */
1643 1644
void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
			   struct drm_atomic_state *state);
1645
bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1646 1647 1648
void intel_fbc_pre_update(struct intel_crtc *crtc,
			  struct intel_crtc_state *crtc_state,
			  struct intel_plane_state *plane_state);
1649
void intel_fbc_post_update(struct intel_crtc *crtc);
1650
void intel_fbc_init(struct drm_i915_private *dev_priv);
1651
void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1652 1653 1654
void intel_fbc_enable(struct intel_crtc *crtc,
		      struct intel_crtc_state *crtc_state,
		      struct intel_plane_state *plane_state);
1655 1656
void intel_fbc_disable(struct intel_crtc *crtc);
void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1657 1658 1659 1660
void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
			  unsigned int frontbuffer_bits,
			  enum fb_op_origin origin);
void intel_fbc_flush(struct drm_i915_private *dev_priv,
1661
		     unsigned int frontbuffer_bits, enum fb_op_origin origin);
1662
void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1663
void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1664

P
Paulo Zanoni 已提交
1665
/* intel_hdmi.c */
1666 1667
void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
		     enum port port);
1668 1669 1670 1671
void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
			       struct intel_connector *intel_connector);
struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1672 1673
			       struct intel_crtc_state *pipe_config,
			       struct drm_connector_state *conn_state);
S
Shashank Sharma 已提交
1674 1675 1676 1677
void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
				       struct drm_connector *connector,
				       bool high_tmds_clock_ratio,
				       bool scrambling);
1678
void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
P
Paulo Zanoni 已提交
1679 1680 1681


/* intel_lvds.c */
1682
void intel_lvds_init(struct drm_i915_private *dev_priv);
1683
struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1684
bool intel_is_dual_link_lvds(struct drm_device *dev);
P
Paulo Zanoni 已提交
1685 1686 1687 1688


/* intel_modes.c */
int intel_connector_update_modes(struct drm_connector *connector,
1689
				 struct edid *edid);
P
Paulo Zanoni 已提交
1690
int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1691 1692
void intel_attach_force_audio_property(struct drm_connector *connector);
void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1693
void intel_attach_aspect_ratio_property(struct drm_connector *connector);
P
Paulo Zanoni 已提交
1694 1695 1696


/* intel_overlay.c */
1697 1698
void intel_setup_overlay(struct drm_i915_private *dev_priv);
void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1699
int intel_overlay_switch_off(struct intel_overlay *overlay);
1700 1701 1702 1703
int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file_priv);
int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
1704
void intel_overlay_reset(struct drm_i915_private *dev_priv);
P
Paulo Zanoni 已提交
1705 1706 1707


/* intel_panel.c */
1708
int intel_panel_init(struct intel_panel *panel,
1709 1710
		     struct drm_display_mode *fixed_mode,
		     struct drm_display_mode *downclock_mode);
1711 1712 1713 1714
void intel_panel_fini(struct intel_panel *panel);
void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
			    struct drm_display_mode *adjusted_mode);
void intel_pch_panel_fitting(struct intel_crtc *crtc,
1715
			     struct intel_crtc_state *pipe_config,
1716 1717
			     int fitting_mode);
void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1718
			      struct intel_crtc_state *pipe_config,
1719
			      int fitting_mode);
1720
void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1721
				    u32 level, u32 max);
1722 1723
int intel_panel_setup_backlight(struct drm_connector *connector,
				enum pipe pipe);
1724 1725 1726
void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
				  const struct drm_connector_state *conn_state);
void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1727
void intel_panel_destroy_backlight(struct drm_connector *connector);
1728
enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1729
extern struct drm_display_mode *intel_find_panel_downclock(
1730
				struct drm_i915_private *dev_priv,
1731 1732
				struct drm_display_mode *fixed_mode,
				struct drm_connector *connector);
1733 1734

#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1735
int intel_backlight_device_register(struct intel_connector *connector);
1736 1737
void intel_backlight_device_unregister(struct intel_connector *connector);
#else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1738 1739 1740 1741
static int intel_backlight_device_register(struct intel_connector *connector)
{
	return 0;
}
1742 1743 1744 1745
static inline void intel_backlight_device_unregister(struct intel_connector *connector)
{
}
#endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1746

P
Paulo Zanoni 已提交
1747

R
Rodrigo Vivi 已提交
1748 1749 1750
/* intel_psr.c */
void intel_psr_enable(struct intel_dp *intel_dp);
void intel_psr_disable(struct intel_dp *intel_dp);
1751
void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1752
			  unsigned frontbuffer_bits);
1753
void intel_psr_flush(struct drm_i915_private *dev_priv,
1754 1755
		     unsigned frontbuffer_bits,
		     enum fb_op_origin origin);
1756
void intel_psr_init(struct drm_i915_private *dev_priv);
1757
void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1758
				   unsigned frontbuffer_bits);
R
Rodrigo Vivi 已提交
1759

1760 1761
/* intel_runtime_pm.c */
int intel_power_domains_init(struct drm_i915_private *);
1762
void intel_power_domains_fini(struct drm_i915_private *);
1763 1764
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1765
void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1766 1767
void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1768
void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1769 1770
const char *
intel_display_power_domain_str(enum intel_display_power_domain domain);
1771

1772 1773 1774 1775
bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
				    enum intel_display_power_domain domain);
bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
				      enum intel_display_power_domain domain);
1776 1777
void intel_display_power_get(struct drm_i915_private *dev_priv,
			     enum intel_display_power_domain domain);
1778 1779
bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
					enum intel_display_power_domain domain);
1780 1781
void intel_display_power_put(struct drm_i915_private *dev_priv,
			     enum intel_display_power_domain domain);
1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793

static inline void
assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
{
	WARN_ONCE(dev_priv->pm.suspended,
		  "Device suspended during HW access\n");
}

static inline void
assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
{
	assert_rpm_device_not_suspended(dev_priv);
1794 1795
	WARN_ONCE(!atomic_read(&dev_priv->pm.wakeref_count),
		  "RPM wakelock ref not held during HW access");
1796 1797
}

1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838
/**
 * disable_rpm_wakeref_asserts - disable the RPM assert checks
 * @dev_priv: i915 device instance
 *
 * This function disable asserts that check if we hold an RPM wakelock
 * reference, while keeping the device-not-suspended checks still enabled.
 * It's meant to be used only in special circumstances where our rule about
 * the wakelock refcount wrt. the device power state doesn't hold. According
 * to this rule at any point where we access the HW or want to keep the HW in
 * an active state we must hold an RPM wakelock reference acquired via one of
 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
 * forcewake release timer, and the GPU RPS and hangcheck works. All other
 * users should avoid using this function.
 *
 * Any calls to this function must have a symmetric call to
 * enable_rpm_wakeref_asserts().
 */
static inline void
disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
{
	atomic_inc(&dev_priv->pm.wakeref_count);
}

/**
 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
 * @dev_priv: i915 device instance
 *
 * This function re-enables the RPM assert checks after disabling them with
 * disable_rpm_wakeref_asserts. It's meant to be used only in special
 * circumstances otherwise its use should be avoided.
 *
 * Any calls to this function must have a symmetric call to
 * disable_rpm_wakeref_asserts().
 */
static inline void
enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
{
	atomic_dec(&dev_priv->pm.wakeref_count);
}

1839
void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1840
bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1841 1842 1843
void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
void intel_runtime_pm_put(struct drm_i915_private *dev_priv);

1844 1845
void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);

1846 1847
void chv_phy_powergate_lanes(struct intel_encoder *encoder,
			     bool override, unsigned int mask);
1848 1849
bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
			  enum dpio_channel ch, bool override);
1850 1851


P
Paulo Zanoni 已提交
1852
/* intel_pm.c */
1853
void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1854
void intel_suspend_hw(struct drm_i915_private *dev_priv);
1855
int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1856
void intel_update_watermarks(struct intel_crtc *crtc);
1857
void intel_init_pm(struct drm_i915_private *dev_priv);
1858
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1859
void intel_pm_setup(struct drm_i915_private *dev_priv);
1860 1861
void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
void intel_gpu_ips_teardown(void);
1862
void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1863 1864
void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1865
void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1866
void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1867
void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1868
void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1869 1870
void gen6_rps_busy(struct drm_i915_private *dev_priv);
void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
D
Daniel Vetter 已提交
1871
void gen6_rps_idle(struct drm_i915_private *dev_priv);
1872
void gen6_rps_boost(struct drm_i915_private *dev_priv,
1873 1874
		    struct intel_rps_client *rps,
		    unsigned long submitted);
1875
void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1876
void g4x_wm_get_hw_state(struct drm_device *dev);
1877
void vlv_wm_get_hw_state(struct drm_device *dev);
1878
void ilk_wm_get_hw_state(struct drm_device *dev);
1879
void skl_wm_get_hw_state(struct drm_device *dev);
1880 1881
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
			  struct skl_ddb_allocation *ddb /* out */);
1882 1883
void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
			      struct skl_pipe_wm *out);
1884
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
1885
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
1886 1887 1888
bool intel_can_enable_sagv(struct drm_atomic_state *state);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
1889 1890
bool skl_wm_level_equals(const struct skl_wm_level *l1,
			 const struct skl_wm_level *l2);
1891 1892 1893
bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
				 const struct skl_ddb_entry *ddb,
				 int ignore);
1894
bool ilk_disable_lp_wm(struct drm_device *dev);
1895
int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1896 1897
int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
				  struct intel_crtc_state *cstate);
1898 1899 1900 1901
static inline int intel_enable_rc6(void)
{
	return i915.enable_rc6;
}
1902

P
Paulo Zanoni 已提交
1903
/* intel_sdvo.c */
1904
bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1905
		     i915_reg_t reg, enum port port);
1906

R
Rodrigo Vivi 已提交
1907

P
Paulo Zanoni 已提交
1908
/* intel_sprite.c */
1909 1910
int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
			     int usecs);
1911
struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1912
					      enum pipe pipe, int plane);
1913 1914
int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
1915
void intel_pipe_update_start(struct intel_crtc *crtc);
1916
void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
P
Paulo Zanoni 已提交
1917 1918

/* intel_tv.c */
1919
void intel_tv_init(struct drm_i915_private *dev_priv);
1920

1921
/* intel_atomic.c */
1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934
int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
						const struct drm_connector_state *state,
						struct drm_property *property,
						uint64_t *val);
int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
						struct drm_connector_state *state,
						struct drm_property *property,
						uint64_t val);
int intel_digital_connector_atomic_check(struct drm_connector *conn,
					 struct drm_connector_state *new_state);
struct drm_connector_state *
intel_digital_connector_duplicate_state(struct drm_connector *connector);

1935 1936 1937
struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
void intel_crtc_destroy_state(struct drm_crtc *crtc,
			       struct drm_crtc_state *state);
1938 1939 1940
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
void intel_atomic_state_clear(struct drm_atomic_state *);

1941 1942 1943 1944 1945 1946 1947
static inline struct intel_crtc_state *
intel_atomic_get_crtc_state(struct drm_atomic_state *state,
			    struct intel_crtc *crtc)
{
	struct drm_crtc_state *crtc_state;
	crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
	if (IS_ERR(crtc_state))
1948
		return ERR_CAST(crtc_state);
1949 1950 1951

	return to_intel_crtc_state(crtc_state);
}
1952

1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966
static inline struct intel_crtc_state *
intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
				     struct intel_crtc *crtc)
{
	struct drm_crtc_state *crtc_state;

	crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);

	if (crtc_state)
		return to_intel_crtc_state(crtc_state);
	else
		return NULL;
}

1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977
static inline struct intel_plane_state *
intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
				      struct intel_plane *plane)
{
	struct drm_plane_state *plane_state;

	plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);

	return to_intel_plane_state(plane_state);
}

1978 1979 1980
int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
			       struct intel_crtc *intel_crtc,
			       struct intel_crtc_state *crtc_state);
1981 1982

/* intel_atomic_plane.c */
1983
struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1984 1985 1986 1987
struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
void intel_plane_destroy_state(struct drm_plane *plane,
			       struct drm_plane_state *state);
extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1988 1989
int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
					struct intel_plane_state *intel_state);
1990

1991 1992
/* intel_color.c */
void intel_color_init(struct drm_crtc *crtc);
1993
int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1994 1995
void intel_color_set_csc(struct drm_crtc_state *crtc_state);
void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1996

1997 1998
/* intel_lspcon.c */
bool lspcon_init(struct intel_digital_port *intel_dig_port);
1999
void lspcon_resume(struct intel_lspcon *lspcon);
2000
void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2001 2002 2003

/* intel_pipe_crc.c */
int intel_pipe_crc_create(struct drm_minor *minor);
T
Tomeu Vizoso 已提交
2004 2005 2006 2007 2008 2009
#ifdef CONFIG_DEBUG_FS
int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
			      size_t *values_cnt);
#else
#define intel_crtc_set_crc_source NULL
#endif
2010
extern const struct file_operations i915_display_crc_ctl_fops;
J
Jesse Barnes 已提交
2011
#endif /* __INTEL_DRV_H__ */