intel-iommu.c 136.8 KB
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/*
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 * Copyright © 2006-2014 Intel Corporation.
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 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
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 * Authors: David Woodhouse <dwmw2@infradead.org>,
 *          Ashok Raj <ashok.raj@intel.com>,
 *          Shaohua Li <shaohua.li@intel.com>,
 *          Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>,
 *          Fenghua Yu <fenghua.yu@intel.com>
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 *          Joerg Roedel <jroedel@suse.de>
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 */

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#define pr_fmt(fmt)     "DMAR: " fmt

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#include <linux/init.h>
#include <linux/bitmap.h>
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#include <linux/debugfs.h>
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#include <linux/export.h>
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#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/pci.h>
#include <linux/dmar.h>
#include <linux/dma-mapping.h>
#include <linux/mempool.h>
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#include <linux/memory.h>
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#include <linux/cpu.h>
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#include <linux/timer.h>
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#include <linux/io.h>
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#include <linux/iova.h>
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#include <linux/iommu.h>
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#include <linux/intel-iommu.h>
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#include <linux/syscore_ops.h>
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#include <linux/tboot.h>
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#include <linux/dmi.h>
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#include <linux/pci-ats.h>
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#include <linux/memblock.h>
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#include <linux/dma-contiguous.h>
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#include <linux/crash_dump.h>
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#include <asm/irq_remapping.h>
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#include <asm/cacheflush.h>
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#include <asm/iommu.h>
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#include "irq_remapping.h"

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#define ROOT_SIZE		VTD_PAGE_SIZE
#define CONTEXT_SIZE		VTD_PAGE_SIZE

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#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
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#define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB)
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#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
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#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
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#define IOAPIC_RANGE_START	(0xfee00000)
#define IOAPIC_RANGE_END	(0xfeefffff)
#define IOVA_START_ADDR		(0x1000)

#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48

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#define MAX_AGAW_WIDTH 64
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#define MAX_AGAW_PFN_WIDTH	(MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)
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#define __DOMAIN_MAX_PFN(gaw)  ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)

/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
   to match. That way, we can use 'unsigned long' for PFNs with impunity. */
#define DOMAIN_MAX_PFN(gaw)	((unsigned long) min_t(uint64_t, \
				__DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
#define DOMAIN_MAX_ADDR(gaw)	(((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
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/* IO virtual address start page frame number */
#define IOVA_START_PFN		(1)

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#define IOVA_PFN(addr)		((addr) >> PAGE_SHIFT)
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#define DMA_32BIT_PFN		IOVA_PFN(DMA_BIT_MASK(32))
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#define DMA_64BIT_PFN		IOVA_PFN(DMA_BIT_MASK(64))
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/* page table handling */
#define LEVEL_STRIDE		(9)
#define LEVEL_MASK		(((u64)1 << LEVEL_STRIDE) - 1)

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/*
 * This bitmap is used to advertise the page sizes our hardware support
 * to the IOMMU core, which will then use this information to split
 * physically contiguous memory regions it is mapping into page sizes
 * that we support.
 *
 * Traditionally the IOMMU core just handed us the mappings directly,
 * after making sure the size is an order of a 4KiB page and that the
 * mapping has natural alignment.
 *
 * To retain this behavior, we currently advertise that we support
 * all page sizes that are an order of 4KiB.
 *
 * If at some point we'd like to utilize the IOMMU core's new behavior,
 * we could change this to advertise the real page sizes we support.
 */
#define INTEL_IOMMU_PGSIZES	(~0xFFFUL)

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static inline int agaw_to_level(int agaw)
{
	return agaw + 2;
}

static inline int agaw_to_width(int agaw)
{
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	return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH);
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}

static inline int width_to_agaw(int width)
{
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	return DIV_ROUND_UP(width - 30, LEVEL_STRIDE);
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}

static inline unsigned int level_to_offset_bits(int level)
{
	return (level - 1) * LEVEL_STRIDE;
}

static inline int pfn_level_offset(unsigned long pfn, int level)
{
	return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
}

static inline unsigned long level_mask(int level)
{
	return -1UL << level_to_offset_bits(level);
}

static inline unsigned long level_size(int level)
{
	return 1UL << level_to_offset_bits(level);
}

static inline unsigned long align_to_level(unsigned long pfn, int level)
{
	return (pfn + level_size(level) - 1) & level_mask(level);
}
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static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
{
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	return  1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
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}

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/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
   are never going to work. */
static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
{
	return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
}

static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
{
	return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
}
static inline unsigned long page_to_dma_pfn(struct page *pg)
{
	return mm_to_dma_pfn(page_to_pfn(pg));
}
static inline unsigned long virt_to_dma_pfn(void *p)
{
	return page_to_dma_pfn(virt_to_page(p));
}

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/* global iommu list, set NULL for ignored DMAR units */
static struct intel_iommu **g_iommus;

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static void __init check_tylersburg_isoch(void);
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static int rwbf_quirk;

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/*
 * set to 1 to panic kernel if can't successfully enable VT-d
 * (used when kernel is launched w/ TXT)
 */
static int force_on = 0;
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int intel_iommu_tboot_noforce;
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/*
 * 0: Present
 * 1-11: Reserved
 * 12-63: Context Ptr (12 - (haw-1))
 * 64-127: Reserved
 */
struct root_entry {
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	u64	lo;
	u64	hi;
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};
#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))

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/*
 * Take a root_entry and return the Lower Context Table Pointer (LCTP)
 * if marked present.
 */
static phys_addr_t root_entry_lctp(struct root_entry *re)
{
	if (!(re->lo & 1))
		return 0;

	return re->lo & VTD_PAGE_MASK;
}

/*
 * Take a root_entry and return the Upper Context Table Pointer (UCTP)
 * if marked present.
 */
static phys_addr_t root_entry_uctp(struct root_entry *re)
{
	if (!(re->hi & 1))
		return 0;
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	return re->hi & VTD_PAGE_MASK;
}
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/*
 * low 64 bits:
 * 0: present
 * 1: fault processing disable
 * 2-3: translation type
 * 12-63: address space root
 * high 64 bits:
 * 0-2: address width
 * 3-6: aval
 * 8-23: domain id
 */
struct context_entry {
	u64 lo;
	u64 hi;
};
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static inline void context_clear_pasid_enable(struct context_entry *context)
{
	context->lo &= ~(1ULL << 11);
}

static inline bool context_pasid_enabled(struct context_entry *context)
{
	return !!(context->lo & (1ULL << 11));
}

static inline void context_set_copied(struct context_entry *context)
{
	context->hi |= (1ull << 3);
}

static inline bool context_copied(struct context_entry *context)
{
	return !!(context->hi & (1ULL << 3));
}

static inline bool __context_present(struct context_entry *context)
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{
	return (context->lo & 1);
}
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static inline bool context_present(struct context_entry *context)
{
	return context_pasid_enabled(context) ?
	     __context_present(context) :
	     __context_present(context) && !context_copied(context);
}

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static inline void context_set_present(struct context_entry *context)
{
	context->lo |= 1;
}

static inline void context_set_fault_enable(struct context_entry *context)
{
	context->lo &= (((u64)-1) << 2) | 1;
}

static inline void context_set_translation_type(struct context_entry *context,
						unsigned long value)
{
	context->lo &= (((u64)-1) << 4) | 3;
	context->lo |= (value & 3) << 2;
}

static inline void context_set_address_root(struct context_entry *context,
					    unsigned long value)
{
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	context->lo &= ~VTD_PAGE_MASK;
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	context->lo |= value & VTD_PAGE_MASK;
}

static inline void context_set_address_width(struct context_entry *context,
					     unsigned long value)
{
	context->hi |= value & 7;
}

static inline void context_set_domain_id(struct context_entry *context,
					 unsigned long value)
{
	context->hi |= (value & ((1 << 16) - 1)) << 8;
}

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static inline int context_domain_id(struct context_entry *c)
{
	return((c->hi >> 8) & 0xffff);
}

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static inline void context_clear_entry(struct context_entry *context)
{
	context->lo = 0;
	context->hi = 0;
}
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/*
 * 0: readable
 * 1: writable
 * 2-6: reserved
 * 7: super page
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 * 8-10: available
 * 11: snoop behavior
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 * 12-63: Host physcial address
 */
struct dma_pte {
	u64 val;
};

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static inline void dma_clear_pte(struct dma_pte *pte)
{
	pte->val = 0;
}

static inline u64 dma_pte_addr(struct dma_pte *pte)
{
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#ifdef CONFIG_64BIT
	return pte->val & VTD_PAGE_MASK;
#else
	/* Must have a full atomic 64-bit read */
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	return  __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
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#endif
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}

static inline bool dma_pte_present(struct dma_pte *pte)
{
	return (pte->val & 3) != 0;
}
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static inline bool dma_pte_superpage(struct dma_pte *pte)
{
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	return (pte->val & DMA_PTE_LARGE_PAGE);
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}

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static inline int first_pte_in_page(struct dma_pte *pte)
{
	return !((unsigned long)pte & ~VTD_PAGE_MASK);
}

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/*
 * This domain is a statically identity mapping domain.
 *	1. This domain creats a static 1:1 mapping to all usable memory.
 * 	2. It maps to each iommu if successful.
 *	3. Each iommu mapps to this domain if successful.
 */
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static struct dmar_domain *si_domain;
static int hw_pass_through = 1;
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/*
 * Domain represents a virtual machine, more than one devices
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 * across iommus may be owned in one domain, e.g. kvm guest.
 */
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#define DOMAIN_FLAG_VIRTUAL_MACHINE	(1 << 0)
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/* si_domain contains mulitple devices */
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#define DOMAIN_FLAG_STATIC_IDENTITY	(1 << 1)
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#define for_each_domain_iommu(idx, domain)			\
	for (idx = 0; idx < g_num_of_iommus; idx++)		\
		if (domain->iommu_refcnt[idx])

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struct dmar_domain {
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	int	nid;			/* node id */
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	unsigned	iommu_refcnt[DMAR_UNITS_SUPPORTED];
					/* Refcount of devices per iommu */

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	u16		iommu_did[DMAR_UNITS_SUPPORTED];
					/* Domain ids per IOMMU. Use u16 since
					 * domain ids are 16 bit wide according
					 * to VT-d spec, section 9.3 */
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	bool has_iotlb_device;
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	struct list_head devices;	/* all devices' list */
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	struct iova_domain iovad;	/* iova's that belong to this domain */

	struct dma_pte	*pgd;		/* virtual address */
	int		gaw;		/* max guest address width */

	/* adjusted guest address width, 0 is level 2 30-bit */
	int		agaw;

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	int		flags;		/* flags to find out type of domain */
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	int		iommu_coherency;/* indicate coherency of iommu access */
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	int		iommu_snooping; /* indicate snooping control feature*/
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	int		iommu_count;	/* reference count of iommu */
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	int		iommu_superpage;/* Level of superpages supported:
					   0 == 4KiB (no superpages), 1 == 2MiB,
					   2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
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	u64		max_addr;	/* maximum mapped address */
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	struct iommu_domain domain;	/* generic domain data structure for
					   iommu core */
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};

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/* PCI domain-device relationship */
struct device_domain_info {
	struct list_head link;	/* link to domain siblings */
	struct list_head global; /* link to global list */
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	u8 bus;			/* PCI bus number */
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	u8 devfn;		/* PCI devfn number */
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	u8 pasid_supported:3;
	u8 pasid_enabled:1;
	u8 pri_supported:1;
	u8 pri_enabled:1;
	u8 ats_supported:1;
	u8 ats_enabled:1;
	u8 ats_qdep;
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	struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
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	struct intel_iommu *iommu; /* IOMMU used by this device */
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	struct dmar_domain *domain; /* pointer to domain */
};

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struct dmar_rmrr_unit {
	struct list_head list;		/* list of rmrr units	*/
	struct acpi_dmar_header *hdr;	/* ACPI header		*/
	u64	base_address;		/* reserved base address*/
	u64	end_address;		/* reserved end address */
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	struct dmar_dev_scope *devices;	/* target devices */
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	int	devices_cnt;		/* target device count */
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	struct iommu_resv_region *resv; /* reserved region handle */
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};

struct dmar_atsr_unit {
	struct list_head list;		/* list of ATSR units */
	struct acpi_dmar_header *hdr;	/* ACPI header */
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	struct dmar_dev_scope *devices;	/* target devices */
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	int devices_cnt;		/* target device count */
	u8 include_all:1;		/* include all ports */
};

static LIST_HEAD(dmar_atsr_units);
static LIST_HEAD(dmar_rmrr_units);

#define for_each_rmrr_units(rmrr) \
	list_for_each_entry(rmrr, &dmar_rmrr_units, list)

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/* bitmap for indexing intel_iommus */
static int g_num_of_iommus;

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static void domain_exit(struct dmar_domain *domain);
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static void domain_remove_dev_info(struct dmar_domain *domain);
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static void dmar_remove_one_dev_info(struct dmar_domain *domain,
				     struct device *dev);
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static void __dmar_remove_one_dev_info(struct device_domain_info *info);
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static void domain_context_clear(struct intel_iommu *iommu,
				 struct device *dev);
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static int domain_detach_iommu(struct dmar_domain *domain,
			       struct intel_iommu *iommu);
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#ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
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int dmar_disabled = 0;
#else
int dmar_disabled = 1;
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#endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
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int intel_iommu_enabled = 0;
EXPORT_SYMBOL_GPL(intel_iommu_enabled);

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static int dmar_map_gfx = 1;
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static int dmar_forcedac;
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static int intel_iommu_strict;
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static int intel_iommu_superpage = 1;
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static int intel_iommu_ecs = 1;
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static int intel_iommu_pasid28;
static int iommu_identity_mapping;
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#define IDENTMAP_ALL		1
#define IDENTMAP_GFX		2
#define IDENTMAP_AZALIA		4
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/* Broadwell and Skylake have broken ECS support — normal so-called "second
 * level" translation of DMA requests-without-PASID doesn't actually happen
 * unless you also set the NESTE bit in an extended context-entry. Which of
 * course means that SVM doesn't work because it's trying to do nested
 * translation of the physical addresses it finds in the process page tables,
 * through the IOVA->phys mapping found in the "second level" page tables.
 *
 * The VT-d specification was retroactively changed to change the definition
 * of the capability bits and pretend that Broadwell/Skylake never happened...
 * but unfortunately the wrong bit was changed. It's ECS which is broken, but
 * for some reason it was the PASID capability bit which was redefined (from
 * bit 28 on BDW/SKL to bit 40 in future).
 *
 * So our test for ECS needs to eschew those implementations which set the old
 * PASID capabiity bit 28, since those are the ones on which ECS is broken.
 * Unless we are working around the 'pasid28' limitations, that is, by putting
 * the device into passthrough mode for normal DMA and thus masking the bug.
 */
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#define ecs_enabled(iommu) (intel_iommu_ecs && ecap_ecs(iommu->ecap) && \
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			    (intel_iommu_pasid28 || !ecap_broken_pasid(iommu->ecap)))
/* PASID support is thus enabled if ECS is enabled and *either* of the old
 * or new capability bits are set. */
#define pasid_enabled(iommu) (ecs_enabled(iommu) &&			\
			      (ecap_pasid(iommu->ecap) || ecap_broken_pasid(iommu->ecap)))
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int intel_iommu_gfx_mapped;
EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);

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#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
static DEFINE_SPINLOCK(device_domain_lock);
static LIST_HEAD(device_domain_list);

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const struct iommu_ops intel_iommu_ops;
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static bool translation_pre_enabled(struct intel_iommu *iommu)
{
	return (iommu->flags & VTD_FLAG_TRANS_PRE_ENABLED);
}

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static void clear_translation_pre_enabled(struct intel_iommu *iommu)
{
	iommu->flags &= ~VTD_FLAG_TRANS_PRE_ENABLED;
}

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static void init_translation_status(struct intel_iommu *iommu)
{
	u32 gsts;

	gsts = readl(iommu->reg + DMAR_GSTS_REG);
	if (gsts & DMA_GSTS_TES)
		iommu->flags |= VTD_FLAG_TRANS_PRE_ENABLED;
}

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/* Convert generic 'struct iommu_domain to private struct dmar_domain */
static struct dmar_domain *to_dmar_domain(struct iommu_domain *dom)
{
	return container_of(dom, struct dmar_domain, domain);
}

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static int __init intel_iommu_setup(char *str)
{
	if (!str)
		return -EINVAL;
	while (*str) {
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		if (!strncmp(str, "on", 2)) {
			dmar_disabled = 0;
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			pr_info("IOMMU enabled\n");
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		} else if (!strncmp(str, "off", 3)) {
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			dmar_disabled = 1;
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			pr_info("IOMMU disabled\n");
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		} else if (!strncmp(str, "igfx_off", 8)) {
			dmar_map_gfx = 0;
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			pr_info("Disable GFX device mapping\n");
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		} else if (!strncmp(str, "forcedac", 8)) {
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			pr_info("Forcing DAC for PCI devices\n");
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			dmar_forcedac = 1;
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		} else if (!strncmp(str, "strict", 6)) {
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			pr_info("Disable batched IOTLB flush\n");
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			intel_iommu_strict = 1;
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		} else if (!strncmp(str, "sp_off", 6)) {
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			pr_info("Disable supported super page\n");
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			intel_iommu_superpage = 0;
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		} else if (!strncmp(str, "ecs_off", 7)) {
			printk(KERN_INFO
				"Intel-IOMMU: disable extended context table support\n");
			intel_iommu_ecs = 0;
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		} else if (!strncmp(str, "pasid28", 7)) {
			printk(KERN_INFO
				"Intel-IOMMU: enable pre-production PASID support\n");
			intel_iommu_pasid28 = 1;
			iommu_identity_mapping |= IDENTMAP_GFX;
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		} else if (!strncmp(str, "tboot_noforce", 13)) {
			printk(KERN_INFO
				"Intel-IOMMU: not forcing on after tboot. This could expose security risk for tboot\n");
			intel_iommu_tboot_noforce = 1;
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		}

		str += strcspn(str, ",");
		while (*str == ',')
			str++;
	}
	return 0;
}
__setup("intel_iommu=", intel_iommu_setup);

static struct kmem_cache *iommu_domain_cache;
static struct kmem_cache *iommu_devinfo_cache;

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static struct dmar_domain* get_iommu_domain(struct intel_iommu *iommu, u16 did)
{
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	struct dmar_domain **domains;
	int idx = did >> 8;

	domains = iommu->domains[idx];
	if (!domains)
		return NULL;

	return domains[did & 0xff];
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}

static void set_iommu_domain(struct intel_iommu *iommu, u16 did,
			     struct dmar_domain *domain)
{
618 619 620 621 622 623 624 625 626 627 628 629 630
	struct dmar_domain **domains;
	int idx = did >> 8;

	if (!iommu->domains[idx]) {
		size_t size = 256 * sizeof(struct dmar_domain *);
		iommu->domains[idx] = kzalloc(size, GFP_ATOMIC);
	}

	domains = iommu->domains[idx];
	if (WARN_ON(!domains))
		return;
	else
		domains[did & 0xff] = domain;
631 632
}

633
static inline void *alloc_pgtable_page(int node)
634
{
635 636
	struct page *page;
	void *vaddr = NULL;
637

638 639 640
	page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
	if (page)
		vaddr = page_address(page);
641
	return vaddr;
642 643 644 645 646 647 648 649 650
}

static inline void free_pgtable_page(void *vaddr)
{
	free_page((unsigned long)vaddr);
}

static inline void *alloc_domain_mem(void)
{
651
	return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
652 653
}

K
Kay, Allen M 已提交
654
static void free_domain_mem(void *vaddr)
655 656 657 658 659 660
{
	kmem_cache_free(iommu_domain_cache, vaddr);
}

static inline void * alloc_devinfo_mem(void)
{
661
	return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
662 663 664 665 666 667 668
}

static inline void free_devinfo_mem(void *vaddr)
{
	kmem_cache_free(iommu_devinfo_cache, vaddr);
}

669 670 671 672 673
static inline int domain_type_is_vm(struct dmar_domain *domain)
{
	return domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE;
}

674 675 676 677 678
static inline int domain_type_is_si(struct dmar_domain *domain)
{
	return domain->flags & DOMAIN_FLAG_STATIC_IDENTITY;
}

679 680 681 682 683
static inline int domain_type_is_vm_or_si(struct dmar_domain *domain)
{
	return domain->flags & (DOMAIN_FLAG_VIRTUAL_MACHINE |
				DOMAIN_FLAG_STATIC_IDENTITY);
}
W
Weidong Han 已提交
684

685 686 687 688 689 690 691 692
static inline int domain_pfn_supported(struct dmar_domain *domain,
				       unsigned long pfn)
{
	int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;

	return !(addr_width < BITS_PER_LONG && pfn >> addr_width);
}

F
Fenghua Yu 已提交
693
static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
W
Weidong Han 已提交
694 695 696 697 698
{
	unsigned long sagaw;
	int agaw = -1;

	sagaw = cap_sagaw(iommu->cap);
F
Fenghua Yu 已提交
699
	for (agaw = width_to_agaw(max_gaw);
W
Weidong Han 已提交
700 701 702 703 704 705 706 707
	     agaw >= 0; agaw--) {
		if (test_bit(agaw, &sagaw))
			break;
	}

	return agaw;
}

F
Fenghua Yu 已提交
708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725
/*
 * Calculate max SAGAW for each iommu.
 */
int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
{
	return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
}

/*
 * calculate agaw for each iommu.
 * "SAGAW" may be different across iommus, use a default agaw, and
 * get a supported less agaw for iommus that don't support the default agaw.
 */
int iommu_calculate_agaw(struct intel_iommu *iommu)
{
	return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
}

726
/* This functionin only returns single iommu in a domain */
727 728 729 730
static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
{
	int iommu_id;

731
	/* si_domain and vm domain should not get here. */
732
	BUG_ON(domain_type_is_vm_or_si(domain));
733 734 735
	for_each_domain_iommu(iommu_id, domain)
		break;

736 737 738 739 740 741
	if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
		return NULL;

	return g_iommus[iommu_id];
}

W
Weidong Han 已提交
742 743
static void domain_update_iommu_coherency(struct dmar_domain *domain)
{
744 745
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;
746 747
	bool found = false;
	int i;
748

749
	domain->iommu_coherency = 1;
W
Weidong Han 已提交
750

751
	for_each_domain_iommu(i, domain) {
752
		found = true;
W
Weidong Han 已提交
753 754 755 756 757
		if (!ecap_coherent(g_iommus[i]->ecap)) {
			domain->iommu_coherency = 0;
			break;
		}
	}
758 759 760 761 762 763 764 765 766 767 768 769
	if (found)
		return;

	/* No hardware attached; use lowest common denominator */
	rcu_read_lock();
	for_each_active_iommu(iommu, drhd) {
		if (!ecap_coherent(iommu->ecap)) {
			domain->iommu_coherency = 0;
			break;
		}
	}
	rcu_read_unlock();
W
Weidong Han 已提交
770 771
}

772
static int domain_update_iommu_snooping(struct intel_iommu *skip)
773
{
774 775 776
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;
	int ret = 1;
777

778 779 780 781 782 783 784
	rcu_read_lock();
	for_each_active_iommu(iommu, drhd) {
		if (iommu != skip) {
			if (!ecap_sc_support(iommu->ecap)) {
				ret = 0;
				break;
			}
785 786
		}
	}
787 788 789
	rcu_read_unlock();

	return ret;
790 791
}

792
static int domain_update_iommu_superpage(struct intel_iommu *skip)
793
{
794
	struct dmar_drhd_unit *drhd;
795
	struct intel_iommu *iommu;
796
	int mask = 0xf;
797 798

	if (!intel_iommu_superpage) {
799
		return 0;
800 801
	}

802
	/* set iommu_superpage to the smallest common denominator */
803
	rcu_read_lock();
804
	for_each_active_iommu(iommu, drhd) {
805 806 807 808
		if (iommu != skip) {
			mask &= cap_super_page_val(iommu->cap);
			if (!mask)
				break;
809 810
		}
	}
811 812
	rcu_read_unlock();

813
	return fls(mask);
814 815
}

816 817 818 819
/* Some capabilities may be different across iommus */
static void domain_update_iommu_cap(struct dmar_domain *domain)
{
	domain_update_iommu_coherency(domain);
820 821
	domain->iommu_snooping = domain_update_iommu_snooping(NULL);
	domain->iommu_superpage = domain_update_iommu_superpage(NULL);
822 823
}

824 825 826 827 828 829 830
static inline struct context_entry *iommu_context_addr(struct intel_iommu *iommu,
						       u8 bus, u8 devfn, int alloc)
{
	struct root_entry *root = &iommu->root_entry[bus];
	struct context_entry *context;
	u64 *entry;

831
	entry = &root->lo;
832
	if (ecs_enabled(iommu)) {
833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857
		if (devfn >= 0x80) {
			devfn -= 0x80;
			entry = &root->hi;
		}
		devfn *= 2;
	}
	if (*entry & 1)
		context = phys_to_virt(*entry & VTD_PAGE_MASK);
	else {
		unsigned long phy_addr;
		if (!alloc)
			return NULL;

		context = alloc_pgtable_page(iommu->node);
		if (!context)
			return NULL;

		__iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
		phy_addr = virt_to_phys((void *)context);
		*entry = phy_addr | 1;
		__iommu_flush_cache(iommu, entry, sizeof(*entry));
	}
	return &context[devfn];
}

858 859 860 861 862
static int iommu_dummy(struct device *dev)
{
	return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
}

863
static struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn)
864 865
{
	struct dmar_drhd_unit *drhd = NULL;
866
	struct intel_iommu *iommu;
867 868
	struct device *tmp;
	struct pci_dev *ptmp, *pdev = NULL;
869
	u16 segment = 0;
870 871
	int i;

872 873 874
	if (iommu_dummy(dev))
		return NULL;

875
	if (dev_is_pci(dev)) {
876 877
		struct pci_dev *pf_pdev;

878
		pdev = to_pci_dev(dev);
879 880 881 882 883 884 885

#ifdef CONFIG_X86
		/* VMD child devices currently cannot be handled individually */
		if (is_vmd(pdev->bus))
			return NULL;
#endif

886 887 888 889
		/* VFs aren't listed in scope tables; we need to look up
		 * the PF instead to find the IOMMU. */
		pf_pdev = pci_physfn(pdev);
		dev = &pf_pdev->dev;
890
		segment = pci_domain_nr(pdev->bus);
891
	} else if (has_acpi_companion(dev))
892 893
		dev = &ACPI_COMPANION(dev)->dev;

894
	rcu_read_lock();
895
	for_each_active_iommu(iommu, drhd) {
896
		if (pdev && segment != drhd->segment)
897
			continue;
898

899
		for_each_active_dev_scope(drhd->devices,
900 901
					  drhd->devices_cnt, i, tmp) {
			if (tmp == dev) {
902 903 904 905
				/* For a VF use its original BDF# not that of the PF
				 * which we used for the IOMMU lookup. Strictly speaking
				 * we could do this for all PCI devices; we only need to
				 * get the BDF# from the scope table for ACPI matches. */
906
				if (pdev && pdev->is_virtfn)
907 908
					goto got_pdev;

909 910
				*bus = drhd->devices[i].bus;
				*devfn = drhd->devices[i].devfn;
911
				goto out;
912 913 914 915 916 917 918 919 920 921
			}

			if (!pdev || !dev_is_pci(tmp))
				continue;

			ptmp = to_pci_dev(tmp);
			if (ptmp->subordinate &&
			    ptmp->subordinate->number <= pdev->bus->number &&
			    ptmp->subordinate->busn_res.end >= pdev->bus->number)
				goto got_pdev;
922
		}
923

924 925 926 927
		if (pdev && drhd->include_all) {
		got_pdev:
			*bus = pdev->bus->number;
			*devfn = pdev->devfn;
928
			goto out;
929
		}
930
	}
931
	iommu = NULL;
932
 out:
933
	rcu_read_unlock();
934

935
	return iommu;
936 937
}

W
Weidong Han 已提交
938 939 940 941 942 943 944
static void domain_flush_cache(struct dmar_domain *domain,
			       void *addr, int size)
{
	if (!domain->iommu_coherency)
		clflush_cache_range(addr, size);
}

945 946 947
static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
{
	struct context_entry *context;
948
	int ret = 0;
949 950 951
	unsigned long flags;

	spin_lock_irqsave(&iommu->lock, flags);
952 953 954
	context = iommu_context_addr(iommu, bus, devfn, 0);
	if (context)
		ret = context_present(context);
955 956 957 958 959 960 961 962 963 964 965 966 967 968 969
	spin_unlock_irqrestore(&iommu->lock, flags);
	return ret;
}

static void free_context_table(struct intel_iommu *iommu)
{
	int i;
	unsigned long flags;
	struct context_entry *context;

	spin_lock_irqsave(&iommu->lock, flags);
	if (!iommu->root_entry) {
		goto out;
	}
	for (i = 0; i < ROOT_ENTRY_NR; i++) {
970
		context = iommu_context_addr(iommu, i, 0, 0);
971 972
		if (context)
			free_pgtable_page(context);
973

974
		if (!ecs_enabled(iommu))
975 976 977 978 979 980
			continue;

		context = iommu_context_addr(iommu, i, 0x80, 0);
		if (context)
			free_pgtable_page(context);

981 982 983 984 985 986 987
	}
	free_pgtable_page(iommu->root_entry);
	iommu->root_entry = NULL;
out:
	spin_unlock_irqrestore(&iommu->lock, flags);
}

988
static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
989
				      unsigned long pfn, int *target_level)
990 991 992
{
	struct dma_pte *parent, *pte = NULL;
	int level = agaw_to_level(domain->agaw);
993
	int offset;
994 995

	BUG_ON(!domain->pgd);
996

997
	if (!domain_pfn_supported(domain, pfn))
998 999 1000
		/* Address beyond IOMMU's addressing capabilities. */
		return NULL;

1001 1002
	parent = domain->pgd;

1003
	while (1) {
1004 1005
		void *tmp_page;

1006
		offset = pfn_level_offset(pfn, level);
1007
		pte = &parent[offset];
1008
		if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
1009
			break;
1010
		if (level == *target_level)
1011 1012
			break;

1013
		if (!dma_pte_present(pte)) {
1014 1015
			uint64_t pteval;

1016
			tmp_page = alloc_pgtable_page(domain->nid);
1017

1018
			if (!tmp_page)
1019
				return NULL;
1020

1021
			domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
1022
			pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
1023
			if (cmpxchg64(&pte->val, 0ULL, pteval))
1024 1025
				/* Someone else set it while we were thinking; use theirs. */
				free_pgtable_page(tmp_page);
1026
			else
1027
				domain_flush_cache(domain, pte, sizeof(*pte));
1028
		}
1029 1030 1031
		if (level == 1)
			break;

1032
		parent = phys_to_virt(dma_pte_addr(pte));
1033 1034 1035
		level--;
	}

1036 1037 1038
	if (!*target_level)
		*target_level = level;

1039 1040 1041
	return pte;
}

1042

1043
/* return address's pte at specific level */
1044 1045
static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
					 unsigned long pfn,
1046
					 int level, int *large_page)
1047 1048 1049 1050 1051 1052 1053
{
	struct dma_pte *parent, *pte = NULL;
	int total = agaw_to_level(domain->agaw);
	int offset;

	parent = domain->pgd;
	while (level <= total) {
1054
		offset = pfn_level_offset(pfn, total);
1055 1056 1057 1058
		pte = &parent[offset];
		if (level == total)
			return pte;

1059 1060
		if (!dma_pte_present(pte)) {
			*large_page = total;
1061
			break;
1062 1063
		}

1064
		if (dma_pte_superpage(pte)) {
1065 1066 1067 1068
			*large_page = total;
			return pte;
		}

1069
		parent = phys_to_virt(dma_pte_addr(pte));
1070 1071 1072 1073 1074 1075
		total--;
	}
	return NULL;
}

/* clear last level pte, a tlb flush should be followed */
1076
static void dma_pte_clear_range(struct dmar_domain *domain,
1077 1078
				unsigned long start_pfn,
				unsigned long last_pfn)
1079
{
1080
	unsigned int large_page = 1;
1081
	struct dma_pte *first_pte, *pte;
1082

1083 1084
	BUG_ON(!domain_pfn_supported(domain, start_pfn));
	BUG_ON(!domain_pfn_supported(domain, last_pfn));
1085
	BUG_ON(start_pfn > last_pfn);
1086

1087
	/* we don't need lock here; nobody else touches the iova range */
1088
	do {
1089 1090
		large_page = 1;
		first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
1091
		if (!pte) {
1092
			start_pfn = align_to_level(start_pfn + 1, large_page + 1);
1093 1094
			continue;
		}
1095
		do {
1096
			dma_clear_pte(pte);
1097
			start_pfn += lvl_to_nr_pages(large_page);
1098
			pte++;
1099 1100
		} while (start_pfn <= last_pfn && !first_pte_in_page(pte));

1101 1102
		domain_flush_cache(domain, first_pte,
				   (void *)pte - (void *)first_pte);
1103 1104

	} while (start_pfn && start_pfn <= last_pfn);
1105 1106
}

1107
static void dma_pte_free_level(struct dmar_domain *domain, int level,
1108 1109 1110
			       int retain_level, struct dma_pte *pte,
			       unsigned long pfn, unsigned long start_pfn,
			       unsigned long last_pfn)
1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121
{
	pfn = max(start_pfn, pfn);
	pte = &pte[pfn_level_offset(pfn, level)];

	do {
		unsigned long level_pfn;
		struct dma_pte *level_pte;

		if (!dma_pte_present(pte) || dma_pte_superpage(pte))
			goto next;

1122
		level_pfn = pfn & level_mask(level);
1123 1124
		level_pte = phys_to_virt(dma_pte_addr(pte));

1125 1126 1127 1128 1129
		if (level > 2) {
			dma_pte_free_level(domain, level - 1, retain_level,
					   level_pte, level_pfn, start_pfn,
					   last_pfn);
		}
1130

1131 1132 1133 1134 1135
		/*
		 * Free the page table if we're below the level we want to
		 * retain and the range covers the entire table.
		 */
		if (level < retain_level && !(start_pfn > level_pfn ||
1136
		      last_pfn < level_pfn + level_size(level) - 1)) {
1137 1138 1139 1140 1141 1142 1143 1144 1145
			dma_clear_pte(pte);
			domain_flush_cache(domain, pte, sizeof(*pte));
			free_pgtable_page(level_pte);
		}
next:
		pfn += level_size(level);
	} while (!first_pte_in_page(++pte) && pfn <= last_pfn);
}

1146 1147 1148 1149
/*
 * clear last level (leaf) ptes and free page table pages below the
 * level we wish to keep intact.
 */
1150
static void dma_pte_free_pagetable(struct dmar_domain *domain,
1151
				   unsigned long start_pfn,
1152 1153
				   unsigned long last_pfn,
				   int retain_level)
1154
{
1155 1156
	BUG_ON(!domain_pfn_supported(domain, start_pfn));
	BUG_ON(!domain_pfn_supported(domain, last_pfn));
1157
	BUG_ON(start_pfn > last_pfn);
1158

1159 1160
	dma_pte_clear_range(domain, start_pfn, last_pfn);

1161
	/* We don't need lock here; nobody else touches the iova range */
1162
	dma_pte_free_level(domain, agaw_to_level(domain->agaw), retain_level,
1163
			   domain->pgd, 0, start_pfn, last_pfn);
1164

1165
	/* free pgd */
1166
	if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
1167 1168 1169 1170 1171
		free_pgtable_page(domain->pgd);
		domain->pgd = NULL;
	}
}

1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190
/* When a page at a given level is being unlinked from its parent, we don't
   need to *modify* it at all. All we need to do is make a list of all the
   pages which can be freed just as soon as we've flushed the IOTLB and we
   know the hardware page-walk will no longer touch them.
   The 'pte' argument is the *parent* PTE, pointing to the page that is to
   be freed. */
static struct page *dma_pte_list_pagetables(struct dmar_domain *domain,
					    int level, struct dma_pte *pte,
					    struct page *freelist)
{
	struct page *pg;

	pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT);
	pg->freelist = freelist;
	freelist = pg;

	if (level == 1)
		return freelist;

1191 1192
	pte = page_address(pg);
	do {
1193 1194 1195
		if (dma_pte_present(pte) && !dma_pte_superpage(pte))
			freelist = dma_pte_list_pagetables(domain, level - 1,
							   pte, freelist);
1196 1197
		pte++;
	} while (!first_pte_in_page(pte));
1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253

	return freelist;
}

static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level,
					struct dma_pte *pte, unsigned long pfn,
					unsigned long start_pfn,
					unsigned long last_pfn,
					struct page *freelist)
{
	struct dma_pte *first_pte = NULL, *last_pte = NULL;

	pfn = max(start_pfn, pfn);
	pte = &pte[pfn_level_offset(pfn, level)];

	do {
		unsigned long level_pfn;

		if (!dma_pte_present(pte))
			goto next;

		level_pfn = pfn & level_mask(level);

		/* If range covers entire pagetable, free it */
		if (start_pfn <= level_pfn &&
		    last_pfn >= level_pfn + level_size(level) - 1) {
			/* These suborbinate page tables are going away entirely. Don't
			   bother to clear them; we're just going to *free* them. */
			if (level > 1 && !dma_pte_superpage(pte))
				freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist);

			dma_clear_pte(pte);
			if (!first_pte)
				first_pte = pte;
			last_pte = pte;
		} else if (level > 1) {
			/* Recurse down into a level that isn't *entirely* obsolete */
			freelist = dma_pte_clear_level(domain, level - 1,
						       phys_to_virt(dma_pte_addr(pte)),
						       level_pfn, start_pfn, last_pfn,
						       freelist);
		}
next:
		pfn += level_size(level);
	} while (!first_pte_in_page(++pte) && pfn <= last_pfn);

	if (first_pte)
		domain_flush_cache(domain, first_pte,
				   (void *)++last_pte - (void *)first_pte);

	return freelist;
}

/* We can't just free the pages because the IOMMU may still be walking
   the page tables, and may have cached the intermediate levels. The
   pages can only be freed after the IOTLB flush has been done. */
1254 1255 1256
static struct page *domain_unmap(struct dmar_domain *domain,
				 unsigned long start_pfn,
				 unsigned long last_pfn)
1257 1258 1259
{
	struct page *freelist = NULL;

1260 1261
	BUG_ON(!domain_pfn_supported(domain, start_pfn));
	BUG_ON(!domain_pfn_supported(domain, last_pfn));
1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279
	BUG_ON(start_pfn > last_pfn);

	/* we don't need lock here; nobody else touches the iova range */
	freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw),
				       domain->pgd, 0, start_pfn, last_pfn, NULL);

	/* free pgd */
	if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
		struct page *pgd_page = virt_to_page(domain->pgd);
		pgd_page->freelist = freelist;
		freelist = pgd_page;

		domain->pgd = NULL;
	}

	return freelist;
}

1280
static void dma_free_pagelist(struct page *freelist)
1281 1282 1283 1284 1285 1286 1287 1288 1289
{
	struct page *pg;

	while ((pg = freelist)) {
		freelist = pg->freelist;
		free_pgtable_page(page_address(pg));
	}
}

1290 1291 1292 1293 1294 1295 1296
static void iova_entry_free(unsigned long data)
{
	struct page *freelist = (struct page *)data;

	dma_free_pagelist(freelist);
}

1297 1298 1299 1300 1301 1302
/* iommu handling */
static int iommu_alloc_root_entry(struct intel_iommu *iommu)
{
	struct root_entry *root;
	unsigned long flags;

1303
	root = (struct root_entry *)alloc_pgtable_page(iommu->node);
1304
	if (!root) {
J
Joerg Roedel 已提交
1305
		pr_err("Allocating root entry for %s failed\n",
1306
			iommu->name);
1307
		return -ENOMEM;
1308
	}
1309

F
Fenghua Yu 已提交
1310
	__iommu_flush_cache(iommu, root, ROOT_SIZE);
1311 1312 1313 1314 1315 1316 1317 1318 1319 1320

	spin_lock_irqsave(&iommu->lock, flags);
	iommu->root_entry = root;
	spin_unlock_irqrestore(&iommu->lock, flags);

	return 0;
}

static void iommu_set_root_entry(struct intel_iommu *iommu)
{
1321
	u64 addr;
1322
	u32 sts;
1323 1324
	unsigned long flag;

1325
	addr = virt_to_phys(iommu->root_entry);
1326
	if (ecs_enabled(iommu))
1327
		addr |= DMA_RTADDR_RTT;
1328

1329
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
1330
	dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr);
1331

1332
	writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
1333 1334 1335

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1336
		      readl, (sts & DMA_GSTS_RTPS), sts);
1337

1338
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1339 1340 1341 1342 1343 1344 1345
}

static void iommu_flush_write_buffer(struct intel_iommu *iommu)
{
	u32 val;
	unsigned long flag;

1346
	if (!rwbf_quirk && !cap_rwbf(iommu->cap))
1347 1348
		return;

1349
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
1350
	writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
1351 1352 1353

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1354
		      readl, (!(val & DMA_GSTS_WBFS)), val);
1355

1356
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1357 1358 1359
}

/* return value determine if we need a write buffer flush */
1360 1361 1362
static void __iommu_flush_context(struct intel_iommu *iommu,
				  u16 did, u16 source_id, u8 function_mask,
				  u64 type)
1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382
{
	u64 val = 0;
	unsigned long flag;

	switch (type) {
	case DMA_CCMD_GLOBAL_INVL:
		val = DMA_CCMD_GLOBAL_INVL;
		break;
	case DMA_CCMD_DOMAIN_INVL:
		val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
		break;
	case DMA_CCMD_DEVICE_INVL:
		val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
			| DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
		break;
	default:
		BUG();
	}
	val |= DMA_CCMD_ICC;

1383
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
1384 1385 1386 1387 1388 1389
	dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
		dmar_readq, (!(val & DMA_CCMD_ICC)), val);

1390
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1391 1392 1393
}

/* return value determine if we need a write buffer flush */
1394 1395
static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
				u64 addr, unsigned int size_order, u64 type)
1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410
{
	int tlb_offset = ecap_iotlb_offset(iommu->ecap);
	u64 val = 0, val_iva = 0;
	unsigned long flag;

	switch (type) {
	case DMA_TLB_GLOBAL_FLUSH:
		/* global flush doesn't need set IVA_REG */
		val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
		break;
	case DMA_TLB_DSI_FLUSH:
		val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
		break;
	case DMA_TLB_PSI_FLUSH:
		val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1411
		/* IH bit is passed in as part of address */
1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428
		val_iva = size_order | addr;
		break;
	default:
		BUG();
	}
	/* Note: set drain read/write */
#if 0
	/*
	 * This is probably to be super secure.. Looks like we can
	 * ignore it without any impact.
	 */
	if (cap_read_drain(iommu->cap))
		val |= DMA_TLB_READ_DRAIN;
#endif
	if (cap_write_drain(iommu->cap))
		val |= DMA_TLB_WRITE_DRAIN;

1429
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
1430 1431 1432 1433 1434 1435 1436 1437 1438
	/* Note: Only uses first TLB reg currently */
	if (val_iva)
		dmar_writeq(iommu->reg + tlb_offset, val_iva);
	dmar_writeq(iommu->reg + tlb_offset + 8, val);

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, tlb_offset + 8,
		dmar_readq, (!(val & DMA_TLB_IVT)), val);

1439
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1440 1441 1442

	/* check IOTLB invalidation granularity */
	if (DMA_TLB_IAIG(val) == 0)
J
Joerg Roedel 已提交
1443
		pr_err("Flush IOTLB failed\n");
1444
	if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
J
Joerg Roedel 已提交
1445
		pr_debug("TLB flush request %Lx, actual %Lx\n",
F
Fenghua Yu 已提交
1446 1447
			(unsigned long long)DMA_TLB_IIRG(type),
			(unsigned long long)DMA_TLB_IAIG(val));
1448 1449
}

1450 1451 1452
static struct device_domain_info *
iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu,
			 u8 bus, u8 devfn)
Y
Yu Zhao 已提交
1453 1454 1455
{
	struct device_domain_info *info;

1456 1457
	assert_spin_locked(&device_domain_lock);

Y
Yu Zhao 已提交
1458 1459 1460 1461
	if (!iommu->qi)
		return NULL;

	list_for_each_entry(info, &domain->devices, link)
1462 1463
		if (info->iommu == iommu && info->bus == bus &&
		    info->devfn == devfn) {
1464 1465
			if (info->ats_supported && info->dev)
				return info;
Y
Yu Zhao 已提交
1466 1467 1468
			break;
		}

1469
	return NULL;
Y
Yu Zhao 已提交
1470 1471
}

1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494
static void domain_update_iotlb(struct dmar_domain *domain)
{
	struct device_domain_info *info;
	bool has_iotlb_device = false;

	assert_spin_locked(&device_domain_lock);

	list_for_each_entry(info, &domain->devices, link) {
		struct pci_dev *pdev;

		if (!info->dev || !dev_is_pci(info->dev))
			continue;

		pdev = to_pci_dev(info->dev);
		if (pdev->ats_enabled) {
			has_iotlb_device = true;
			break;
		}
	}

	domain->has_iotlb_device = has_iotlb_device;
}

Y
Yu Zhao 已提交
1495
static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1496
{
1497 1498
	struct pci_dev *pdev;

1499 1500
	assert_spin_locked(&device_domain_lock);

1501
	if (!info || !dev_is_pci(info->dev))
Y
Yu Zhao 已提交
1502 1503
		return;

1504 1505
	pdev = to_pci_dev(info->dev);

1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519
#ifdef CONFIG_INTEL_IOMMU_SVM
	/* The PCIe spec, in its wisdom, declares that the behaviour of
	   the device if you enable PASID support after ATS support is
	   undefined. So always enable PASID support on devices which
	   have it, even if we can't yet know if we're ever going to
	   use it. */
	if (info->pasid_supported && !pci_enable_pasid(pdev, info->pasid_supported & ~1))
		info->pasid_enabled = 1;

	if (info->pri_supported && !pci_reset_pri(pdev) && !pci_enable_pri(pdev, 32))
		info->pri_enabled = 1;
#endif
	if (info->ats_supported && !pci_enable_ats(pdev, VTD_PAGE_SHIFT)) {
		info->ats_enabled = 1;
1520
		domain_update_iotlb(info->domain);
1521 1522
		info->ats_qdep = pci_ats_queue_depth(pdev);
	}
Y
Yu Zhao 已提交
1523 1524 1525 1526
}

static void iommu_disable_dev_iotlb(struct device_domain_info *info)
{
1527 1528
	struct pci_dev *pdev;

1529 1530
	assert_spin_locked(&device_domain_lock);

1531
	if (!dev_is_pci(info->dev))
Y
Yu Zhao 已提交
1532 1533
		return;

1534 1535 1536 1537 1538
	pdev = to_pci_dev(info->dev);

	if (info->ats_enabled) {
		pci_disable_ats(pdev);
		info->ats_enabled = 0;
1539
		domain_update_iotlb(info->domain);
1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550
	}
#ifdef CONFIG_INTEL_IOMMU_SVM
	if (info->pri_enabled) {
		pci_disable_pri(pdev);
		info->pri_enabled = 0;
	}
	if (info->pasid_enabled) {
		pci_disable_pasid(pdev);
		info->pasid_enabled = 0;
	}
#endif
Y
Yu Zhao 已提交
1551 1552 1553 1554 1555 1556 1557 1558 1559
}

static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
				  u64 addr, unsigned mask)
{
	u16 sid, qdep;
	unsigned long flags;
	struct device_domain_info *info;

1560 1561 1562
	if (!domain->has_iotlb_device)
		return;

Y
Yu Zhao 已提交
1563 1564
	spin_lock_irqsave(&device_domain_lock, flags);
	list_for_each_entry(info, &domain->devices, link) {
1565
		if (!info->ats_enabled)
Y
Yu Zhao 已提交
1566 1567 1568
			continue;

		sid = info->bus << 8 | info->devfn;
1569
		qdep = info->ats_qdep;
Y
Yu Zhao 已提交
1570 1571 1572 1573 1574
		qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
	}
	spin_unlock_irqrestore(&device_domain_lock, flags);
}

1575 1576 1577 1578
static void iommu_flush_iotlb_psi(struct intel_iommu *iommu,
				  struct dmar_domain *domain,
				  unsigned long pfn, unsigned int pages,
				  int ih, int map)
1579
{
1580
	unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1581
	uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1582
	u16 did = domain->iommu_did[iommu->seq_id];
1583 1584 1585

	BUG_ON(pages == 0);

1586 1587
	if (ih)
		ih = 1 << 6;
1588
	/*
1589 1590
	 * Fallback to domain selective flush if no PSI support or the size is
	 * too big.
1591 1592 1593
	 * PSI requires page size to be 2 ^ x, and the base address is naturally
	 * aligned to the size
	 */
1594 1595
	if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
		iommu->flush.flush_iotlb(iommu, did, 0, 0,
1596
						DMA_TLB_DSI_FLUSH);
1597
	else
1598
		iommu->flush.flush_iotlb(iommu, did, addr | ih, mask,
1599
						DMA_TLB_PSI_FLUSH);
1600 1601

	/*
1602 1603
	 * In caching mode, changes of pages from non-present to present require
	 * flush. However, device IOTLB doesn't need to be flushed in this case.
1604
	 */
1605
	if (!cap_caching_mode(iommu->cap) || !map)
1606 1607
		iommu_flush_dev_iotlb(get_iommu_domain(iommu, did),
				      addr, mask);
1608 1609
}

1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628
static void iommu_flush_iova(struct iova_domain *iovad)
{
	struct dmar_domain *domain;
	int idx;

	domain = container_of(iovad, struct dmar_domain, iovad);

	for_each_domain_iommu(idx, domain) {
		struct intel_iommu *iommu = g_iommus[idx];
		u16 did = domain->iommu_did[iommu->seq_id];

		iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH);

		if (!cap_caching_mode(iommu->cap))
			iommu_flush_dev_iotlb(get_iommu_domain(iommu, did),
					      0, MAX_AGAW_PFN_WIDTH);
	}
}

M
mark gross 已提交
1629 1630 1631 1632 1633
static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
{
	u32 pmen;
	unsigned long flags;

1634
	raw_spin_lock_irqsave(&iommu->register_lock, flags);
M
mark gross 已提交
1635 1636 1637 1638 1639 1640 1641 1642
	pmen = readl(iommu->reg + DMAR_PMEN_REG);
	pmen &= ~DMA_PMEN_EPM;
	writel(pmen, iommu->reg + DMAR_PMEN_REG);

	/* wait for the protected region status bit to clear */
	IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
		readl, !(pmen & DMA_PMEN_PRS), pmen);

1643
	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
M
mark gross 已提交
1644 1645
}

1646
static void iommu_enable_translation(struct intel_iommu *iommu)
1647 1648 1649 1650
{
	u32 sts;
	unsigned long flags;

1651
	raw_spin_lock_irqsave(&iommu->register_lock, flags);
1652 1653
	iommu->gcmd |= DMA_GCMD_TE;
	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1654 1655 1656

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1657
		      readl, (sts & DMA_GSTS_TES), sts);
1658

1659
	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1660 1661
}

1662
static void iommu_disable_translation(struct intel_iommu *iommu)
1663 1664 1665 1666
{
	u32 sts;
	unsigned long flag;

1667
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
1668 1669 1670 1671 1672
	iommu->gcmd &= ~DMA_GCMD_TE;
	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1673
		      readl, (!(sts & DMA_GSTS_TES)), sts);
1674

1675
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1676 1677
}

1678

1679 1680
static int iommu_init_domains(struct intel_iommu *iommu)
{
1681 1682
	u32 ndomains, nlongs;
	size_t size;
1683 1684

	ndomains = cap_ndoms(iommu->cap);
1685
	pr_debug("%s: Number of Domains supported <%d>\n",
J
Joerg Roedel 已提交
1686
		 iommu->name, ndomains);
1687 1688
	nlongs = BITS_TO_LONGS(ndomains);

1689 1690
	spin_lock_init(&iommu->lock);

1691 1692
	iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
	if (!iommu->domain_ids) {
J
Joerg Roedel 已提交
1693 1694
		pr_err("%s: Allocating domain id array failed\n",
		       iommu->name);
1695 1696
		return -ENOMEM;
	}
1697

1698
	size = (ALIGN(ndomains, 256) >> 8) * sizeof(struct dmar_domain **);
1699 1700 1701 1702 1703 1704 1705 1706
	iommu->domains = kzalloc(size, GFP_KERNEL);

	if (iommu->domains) {
		size = 256 * sizeof(struct dmar_domain *);
		iommu->domains[0] = kzalloc(size, GFP_KERNEL);
	}

	if (!iommu->domains || !iommu->domains[0]) {
J
Joerg Roedel 已提交
1707 1708
		pr_err("%s: Allocating domain array failed\n",
		       iommu->name);
1709
		kfree(iommu->domain_ids);
1710
		kfree(iommu->domains);
1711
		iommu->domain_ids = NULL;
1712
		iommu->domains    = NULL;
1713 1714 1715
		return -ENOMEM;
	}

1716 1717


1718
	/*
1719 1720 1721 1722
	 * If Caching mode is set, then invalid translations are tagged
	 * with domain-id 0, hence we need to pre-allocate it. We also
	 * use domain-id 0 as a marker for non-allocated domain-id, so
	 * make sure it is not used for a real domain.
1723
	 */
1724 1725
	set_bit(0, iommu->domain_ids);

1726 1727 1728
	return 0;
}

1729
static void disable_dmar_iommu(struct intel_iommu *iommu)
1730
{
1731
	struct device_domain_info *info, *tmp;
1732
	unsigned long flags;
1733

1734 1735
	if (!iommu->domains || !iommu->domain_ids)
		return;
1736

1737
again:
1738
	spin_lock_irqsave(&device_domain_lock, flags);
1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749
	list_for_each_entry_safe(info, tmp, &device_domain_list, global) {
		struct dmar_domain *domain;

		if (info->iommu != iommu)
			continue;

		if (!info->dev || !info->domain)
			continue;

		domain = info->domain;

1750
		__dmar_remove_one_dev_info(info);
1751

1752 1753 1754 1755 1756 1757 1758 1759
		if (!domain_type_is_vm_or_si(domain)) {
			/*
			 * The domain_exit() function  can't be called under
			 * device_domain_lock, as it takes this lock itself.
			 * So release the lock here and re-run the loop
			 * afterwards.
			 */
			spin_unlock_irqrestore(&device_domain_lock, flags);
1760
			domain_exit(domain);
1761 1762
			goto again;
		}
1763
	}
1764
	spin_unlock_irqrestore(&device_domain_lock, flags);
1765 1766 1767

	if (iommu->gcmd & DMA_GCMD_TE)
		iommu_disable_translation(iommu);
1768
}
1769

1770 1771 1772
static void free_dmar_iommu(struct intel_iommu *iommu)
{
	if ((iommu->domains) && (iommu->domain_ids)) {
1773
		int elems = ALIGN(cap_ndoms(iommu->cap), 256) >> 8;
1774 1775 1776 1777
		int i;

		for (i = 0; i < elems; i++)
			kfree(iommu->domains[i]);
1778 1779 1780 1781 1782
		kfree(iommu->domains);
		kfree(iommu->domain_ids);
		iommu->domains = NULL;
		iommu->domain_ids = NULL;
	}
1783

W
Weidong Han 已提交
1784 1785
	g_iommus[iommu->seq_id] = NULL;

1786 1787
	/* free context mapping */
	free_context_table(iommu);
1788 1789

#ifdef CONFIG_INTEL_IOMMU_SVM
1790 1791 1792
	if (pasid_enabled(iommu)) {
		if (ecap_prs(iommu->ecap))
			intel_svm_finish_prq(iommu);
1793
		intel_svm_free_pasid_tables(iommu);
1794
	}
1795
#endif
1796 1797
}

1798
static struct dmar_domain *alloc_domain(int flags)
1799 1800 1801 1802 1803 1804 1805
{
	struct dmar_domain *domain;

	domain = alloc_domain_mem();
	if (!domain)
		return NULL;

1806
	memset(domain, 0, sizeof(*domain));
1807
	domain->nid = -1;
1808
	domain->flags = flags;
1809
	domain->has_iotlb_device = false;
1810
	INIT_LIST_HEAD(&domain->devices);
1811 1812 1813 1814

	return domain;
}

1815 1816
/* Must be called with iommu->lock */
static int domain_attach_iommu(struct dmar_domain *domain,
1817 1818
			       struct intel_iommu *iommu)
{
1819
	unsigned long ndomains;
1820
	int num;
1821

1822
	assert_spin_locked(&device_domain_lock);
1823
	assert_spin_locked(&iommu->lock);
1824

1825 1826 1827
	domain->iommu_refcnt[iommu->seq_id] += 1;
	domain->iommu_count += 1;
	if (domain->iommu_refcnt[iommu->seq_id] == 1) {
1828
		ndomains = cap_ndoms(iommu->cap);
1829 1830 1831 1832 1833 1834
		num      = find_first_zero_bit(iommu->domain_ids, ndomains);

		if (num >= ndomains) {
			pr_err("%s: No free domain ids\n", iommu->name);
			domain->iommu_refcnt[iommu->seq_id] -= 1;
			domain->iommu_count -= 1;
1835
			return -ENOSPC;
1836
		}
1837

1838 1839 1840 1841 1842
		set_bit(num, iommu->domain_ids);
		set_iommu_domain(iommu, num, domain);

		domain->iommu_did[iommu->seq_id] = num;
		domain->nid			 = iommu->node;
1843 1844 1845

		domain_update_iommu_cap(domain);
	}
1846

1847
	return 0;
1848 1849 1850 1851 1852
}

static int domain_detach_iommu(struct dmar_domain *domain,
			       struct intel_iommu *iommu)
{
1853 1854
	int num, count = INT_MAX;

1855
	assert_spin_locked(&device_domain_lock);
1856
	assert_spin_locked(&iommu->lock);
1857

1858 1859 1860
	domain->iommu_refcnt[iommu->seq_id] -= 1;
	count = --domain->iommu_count;
	if (domain->iommu_refcnt[iommu->seq_id] == 0) {
1861 1862 1863
		num = domain->iommu_did[iommu->seq_id];
		clear_bit(num, iommu->domain_ids);
		set_iommu_domain(iommu, num, NULL);
1864 1865

		domain_update_iommu_cap(domain);
1866
		domain->iommu_did[iommu->seq_id] = 0;
1867 1868 1869 1870 1871
	}

	return count;
}

1872
static struct iova_domain reserved_iova_list;
M
Mark Gross 已提交
1873
static struct lock_class_key reserved_rbtree_key;
1874

1875
static int dmar_init_reserved_ranges(void)
1876 1877 1878 1879 1880
{
	struct pci_dev *pdev = NULL;
	struct iova *iova;
	int i;

1881 1882
	init_iova_domain(&reserved_iova_list, VTD_PAGE_SIZE, IOVA_START_PFN,
			DMA_32BIT_PFN);
1883

M
Mark Gross 已提交
1884 1885 1886
	lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
		&reserved_rbtree_key);

1887 1888 1889
	/* IOAPIC ranges shouldn't be accessed by DMA */
	iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
		IOVA_PFN(IOAPIC_RANGE_END));
1890
	if (!iova) {
J
Joerg Roedel 已提交
1891
		pr_err("Reserve IOAPIC range failed\n");
1892 1893
		return -ENODEV;
	}
1894 1895 1896 1897 1898 1899 1900 1901 1902

	/* Reserve all PCI MMIO to avoid peer-to-peer access */
	for_each_pci_dev(pdev) {
		struct resource *r;

		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			r = &pdev->resource[i];
			if (!r->flags || !(r->flags & IORESOURCE_MEM))
				continue;
1903 1904 1905
			iova = reserve_iova(&reserved_iova_list,
					    IOVA_PFN(r->start),
					    IOVA_PFN(r->end));
1906
			if (!iova) {
J
Joerg Roedel 已提交
1907
				pr_err("Reserve iova failed\n");
1908 1909
				return -ENODEV;
			}
1910 1911
		}
	}
1912
	return 0;
1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933
}

static void domain_reserve_special_ranges(struct dmar_domain *domain)
{
	copy_reserved_iova(&reserved_iova_list, &domain->iovad);
}

static inline int guestwidth_to_adjustwidth(int gaw)
{
	int agaw;
	int r = (gaw - 12) % 9;

	if (r == 0)
		agaw = gaw;
	else
		agaw = gaw + 9 - r;
	if (agaw > 64)
		agaw = 64;
	return agaw;
}

1934 1935
static int domain_init(struct dmar_domain *domain, struct intel_iommu *iommu,
		       int guest_width)
1936 1937 1938
{
	int adjust_width, agaw;
	unsigned long sagaw;
1939
	int err;
1940

1941 1942
	init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN,
			DMA_32BIT_PFN);
1943 1944 1945 1946 1947 1948

	err = init_iova_flush_queue(&domain->iovad,
				    iommu_flush_iova, iova_entry_free);
	if (err)
		return err;

1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959
	domain_reserve_special_ranges(domain);

	/* calculate AGAW */
	if (guest_width > cap_mgaw(iommu->cap))
		guest_width = cap_mgaw(iommu->cap);
	domain->gaw = guest_width;
	adjust_width = guestwidth_to_adjustwidth(guest_width);
	agaw = width_to_agaw(adjust_width);
	sagaw = cap_sagaw(iommu->cap);
	if (!test_bit(agaw, &sagaw)) {
		/* hardware doesn't support it, choose a bigger one */
J
Joerg Roedel 已提交
1960
		pr_debug("Hardware doesn't support agaw %d\n", agaw);
1961 1962 1963 1964 1965 1966
		agaw = find_next_bit(&sagaw, 5, agaw);
		if (agaw >= 5)
			return -ENODEV;
	}
	domain->agaw = agaw;

W
Weidong Han 已提交
1967 1968 1969 1970 1971
	if (ecap_coherent(iommu->ecap))
		domain->iommu_coherency = 1;
	else
		domain->iommu_coherency = 0;

1972 1973 1974 1975 1976
	if (ecap_sc_support(iommu->ecap))
		domain->iommu_snooping = 1;
	else
		domain->iommu_snooping = 0;

1977 1978 1979 1980 1981
	if (intel_iommu_superpage)
		domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
	else
		domain->iommu_superpage = 0;

1982
	domain->nid = iommu->node;
1983

1984
	/* always allocate the top pgd */
1985
	domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
1986 1987
	if (!domain->pgd)
		return -ENOMEM;
F
Fenghua Yu 已提交
1988
	__iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1989 1990 1991 1992 1993
	return 0;
}

static void domain_exit(struct dmar_domain *domain)
{
1994
	struct page *freelist = NULL;
1995 1996 1997 1998 1999

	/* Domain 0 is reserved, so dont process it */
	if (!domain)
		return;

2000 2001
	/* Remove associated devices and clear attached or cached domains */
	rcu_read_lock();
2002
	domain_remove_dev_info(domain);
2003
	rcu_read_unlock();
2004

2005 2006 2007
	/* destroy iovas */
	put_iova_domain(&domain->iovad);

2008
	freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
2009

2010 2011
	dma_free_pagelist(freelist);

2012 2013 2014
	free_domain_mem(domain);
}

2015 2016
static int domain_context_mapping_one(struct dmar_domain *domain,
				      struct intel_iommu *iommu,
2017
				      u8 bus, u8 devfn)
2018
{
2019
	u16 did = domain->iommu_did[iommu->seq_id];
2020 2021
	int translation = CONTEXT_TT_MULTI_LEVEL;
	struct device_domain_info *info = NULL;
2022 2023
	struct context_entry *context;
	unsigned long flags;
2024
	struct dma_pte *pgd;
2025
	int ret, agaw;
2026

2027 2028
	WARN_ON(did == 0);

2029 2030
	if (hw_pass_through && domain_type_is_si(domain))
		translation = CONTEXT_TT_PASS_THROUGH;
2031 2032 2033

	pr_debug("Set context mapping for %02x:%02x.%d\n",
		bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
F
Fenghua Yu 已提交
2034

2035
	BUG_ON(!domain->pgd);
W
Weidong Han 已提交
2036

2037 2038 2039 2040
	spin_lock_irqsave(&device_domain_lock, flags);
	spin_lock(&iommu->lock);

	ret = -ENOMEM;
2041
	context = iommu_context_addr(iommu, bus, devfn, 1);
2042
	if (!context)
2043
		goto out_unlock;
2044

2045 2046 2047
	ret = 0;
	if (context_present(context))
		goto out_unlock;
2048

2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060
	/*
	 * For kdump cases, old valid entries may be cached due to the
	 * in-flight DMA and copied pgtable, but there is no unmapping
	 * behaviour for them, thus we need an explicit cache flush for
	 * the newly-mapped device. For kdump, at this point, the device
	 * is supposed to finish reset at its driver probe stage, so no
	 * in-flight DMA will exist, and we don't need to worry anymore
	 * hereafter.
	 */
	if (context_copied(context)) {
		u16 did_old = context_domain_id(context);

2061
		if (did_old >= 0 && did_old < cap_ndoms(iommu->cap)) {
2062 2063 2064 2065
			iommu->flush.flush_context(iommu, did_old,
						   (((u16)bus) << 8) | devfn,
						   DMA_CCMD_MASK_NOBIT,
						   DMA_CCMD_DEVICE_INVL);
2066 2067 2068
			iommu->flush.flush_iotlb(iommu, did_old, 0, 0,
						 DMA_TLB_DSI_FLUSH);
		}
2069 2070
	}

2071 2072
	pgd = domain->pgd;

2073
	context_clear_entry(context);
2074
	context_set_domain_id(context, did);
2075

2076 2077 2078 2079
	/*
	 * Skip top levels of page tables for iommu which has less agaw
	 * than default.  Unnecessary for PT mode.
	 */
Y
Yu Zhao 已提交
2080
	if (translation != CONTEXT_TT_PASS_THROUGH) {
2081
		for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
2082
			ret = -ENOMEM;
2083
			pgd = phys_to_virt(dma_pte_addr(pgd));
2084 2085
			if (!dma_pte_present(pgd))
				goto out_unlock;
2086
		}
F
Fenghua Yu 已提交
2087

2088
		info = iommu_support_dev_iotlb(domain, iommu, bus, devfn);
2089 2090 2091 2092
		if (info && info->ats_supported)
			translation = CONTEXT_TT_DEV_IOTLB;
		else
			translation = CONTEXT_TT_MULTI_LEVEL;
2093

Y
Yu Zhao 已提交
2094 2095
		context_set_address_root(context, virt_to_phys(pgd));
		context_set_address_width(context, iommu->agaw);
2096 2097 2098 2099 2100 2101 2102
	} else {
		/*
		 * In pass through mode, AW must be programmed to
		 * indicate the largest AGAW value supported by
		 * hardware. And ASR is ignored by hardware.
		 */
		context_set_address_width(context, iommu->msagaw);
Y
Yu Zhao 已提交
2103
	}
F
Fenghua Yu 已提交
2104 2105

	context_set_translation_type(context, translation);
2106 2107
	context_set_fault_enable(context);
	context_set_present(context);
W
Weidong Han 已提交
2108
	domain_flush_cache(domain, context, sizeof(*context));
2109

2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120
	/*
	 * It's a non-present to present mapping. If hardware doesn't cache
	 * non-present entry we only need to flush the write-buffer. If the
	 * _does_ cache non-present entries, then it does so in the special
	 * domain #0, which we have to flush:
	 */
	if (cap_caching_mode(iommu->cap)) {
		iommu->flush.flush_context(iommu, 0,
					   (((u16)bus) << 8) | devfn,
					   DMA_CCMD_MASK_NOBIT,
					   DMA_CCMD_DEVICE_INVL);
2121
		iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH);
2122
	} else {
2123
		iommu_flush_write_buffer(iommu);
2124
	}
Y
Yu Zhao 已提交
2125
	iommu_enable_dev_iotlb(info);
2126

2127 2128 2129 2130 2131
	ret = 0;

out_unlock:
	spin_unlock(&iommu->lock);
	spin_unlock_irqrestore(&device_domain_lock, flags);
2132

2133
	return ret;
2134 2135
}

2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146
struct domain_context_mapping_data {
	struct dmar_domain *domain;
	struct intel_iommu *iommu;
};

static int domain_context_mapping_cb(struct pci_dev *pdev,
				     u16 alias, void *opaque)
{
	struct domain_context_mapping_data *data = opaque;

	return domain_context_mapping_one(data->domain, data->iommu,
2147
					  PCI_BUS_NUM(alias), alias & 0xff);
2148 2149
}

2150
static int
2151
domain_context_mapping(struct dmar_domain *domain, struct device *dev)
2152
{
2153
	struct intel_iommu *iommu;
2154
	u8 bus, devfn;
2155
	struct domain_context_mapping_data data;
2156

2157
	iommu = device_to_iommu(dev, &bus, &devfn);
2158 2159
	if (!iommu)
		return -ENODEV;
2160

2161
	if (!dev_is_pci(dev))
2162
		return domain_context_mapping_one(domain, iommu, bus, devfn);
2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176

	data.domain = domain;
	data.iommu = iommu;

	return pci_for_each_dma_alias(to_pci_dev(dev),
				      &domain_context_mapping_cb, &data);
}

static int domain_context_mapped_cb(struct pci_dev *pdev,
				    u16 alias, void *opaque)
{
	struct intel_iommu *iommu = opaque;

	return !device_context_mapped(iommu, PCI_BUS_NUM(alias), alias & 0xff);
2177 2178
}

2179
static int domain_context_mapped(struct device *dev)
2180
{
W
Weidong Han 已提交
2181
	struct intel_iommu *iommu;
2182
	u8 bus, devfn;
W
Weidong Han 已提交
2183

2184
	iommu = device_to_iommu(dev, &bus, &devfn);
W
Weidong Han 已提交
2185 2186
	if (!iommu)
		return -ENODEV;
2187

2188 2189
	if (!dev_is_pci(dev))
		return device_context_mapped(iommu, bus, devfn);
2190

2191 2192
	return !pci_for_each_dma_alias(to_pci_dev(dev),
				       domain_context_mapped_cb, iommu);
2193 2194
}

2195 2196 2197 2198 2199 2200 2201 2202
/* Returns a number of VTD pages, but aligned to MM page size */
static inline unsigned long aligned_nrpages(unsigned long host_addr,
					    size_t size)
{
	host_addr &= ~PAGE_MASK;
	return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
}

2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230
/* Return largest possible superpage level for a given mapping */
static inline int hardware_largepage_caps(struct dmar_domain *domain,
					  unsigned long iov_pfn,
					  unsigned long phy_pfn,
					  unsigned long pages)
{
	int support, level = 1;
	unsigned long pfnmerge;

	support = domain->iommu_superpage;

	/* To use a large page, the virtual *and* physical addresses
	   must be aligned to 2MiB/1GiB/etc. Lower bits set in either
	   of them will mean we have to use smaller pages. So just
	   merge them and check both at once. */
	pfnmerge = iov_pfn | phy_pfn;

	while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
		pages >>= VTD_STRIDE_SHIFT;
		if (!pages)
			break;
		pfnmerge >>= VTD_STRIDE_SHIFT;
		level++;
		support--;
	}
	return level;
}

2231 2232 2233
static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
			    struct scatterlist *sg, unsigned long phys_pfn,
			    unsigned long nr_pages, int prot)
2234 2235
{
	struct dma_pte *first_pte = NULL, *pte = NULL;
2236
	phys_addr_t uninitialized_var(pteval);
2237
	unsigned long sg_res = 0;
2238 2239
	unsigned int largepage_lvl = 0;
	unsigned long lvl_pages = 0;
2240

2241
	BUG_ON(!domain_pfn_supported(domain, iov_pfn + nr_pages - 1));
2242 2243 2244 2245 2246 2247

	if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
		return -EINVAL;

	prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;

2248 2249
	if (!sg) {
		sg_res = nr_pages;
2250 2251 2252
		pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
	}

2253
	while (nr_pages > 0) {
2254 2255
		uint64_t tmp;

2256
		if (!sg_res) {
2257
			sg_res = aligned_nrpages(sg->offset, sg->length);
2258 2259
			sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
			sg->dma_length = sg->length;
D
Dan Williams 已提交
2260
			pteval = page_to_phys(sg_page(sg)) | prot;
2261
			phys_pfn = pteval >> VTD_PAGE_SHIFT;
2262
		}
2263

2264
		if (!pte) {
2265 2266
			largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);

2267
			first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl);
2268 2269
			if (!pte)
				return -ENOMEM;
2270
			/* It is large page*/
2271
			if (largepage_lvl > 1) {
2272 2273
				unsigned long nr_superpages, end_pfn;

2274
				pteval |= DMA_PTE_LARGE_PAGE;
2275
				lvl_pages = lvl_to_nr_pages(largepage_lvl);
2276 2277 2278 2279

				nr_superpages = sg_res / lvl_pages;
				end_pfn = iov_pfn + nr_superpages * lvl_pages - 1;

2280 2281
				/*
				 * Ensure that old small page tables are
2282
				 * removed to make room for superpage(s).
2283 2284
				 * We're adding new large pages, so make sure
				 * we don't remove their parent tables.
2285
				 */
2286 2287
				dma_pte_free_pagetable(domain, iov_pfn, end_pfn,
						       largepage_lvl + 1);
2288
			} else {
2289
				pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;
2290
			}
2291

2292 2293 2294 2295
		}
		/* We don't need lock here, nobody else
		 * touches the iova range
		 */
2296
		tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
2297
		if (tmp) {
2298
			static int dumps = 5;
J
Joerg Roedel 已提交
2299 2300
			pr_crit("ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
				iov_pfn, tmp, (unsigned long long)pteval);
2301 2302 2303 2304 2305 2306
			if (dumps) {
				dumps--;
				debug_dma_dump_mappings(NULL);
			}
			WARN_ON(1);
		}
2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329

		lvl_pages = lvl_to_nr_pages(largepage_lvl);

		BUG_ON(nr_pages < lvl_pages);
		BUG_ON(sg_res < lvl_pages);

		nr_pages -= lvl_pages;
		iov_pfn += lvl_pages;
		phys_pfn += lvl_pages;
		pteval += lvl_pages * VTD_PAGE_SIZE;
		sg_res -= lvl_pages;

		/* If the next PTE would be the first in a new page, then we
		   need to flush the cache on the entries we've just written.
		   And then we'll need to recalculate 'pte', so clear it and
		   let it get set again in the if (!pte) block above.

		   If we're done (!nr_pages) we need to flush the cache too.

		   Also if we've been setting superpages, we may need to
		   recalculate 'pte' and switch back to smaller pages for the
		   end of the mapping, if the trailing size is not enough to
		   use another superpage (i.e. sg_res < lvl_pages). */
2330
		pte++;
2331 2332
		if (!nr_pages || first_pte_in_page(pte) ||
		    (largepage_lvl > 1 && sg_res < lvl_pages)) {
2333 2334 2335 2336
			domain_flush_cache(domain, first_pte,
					   (void *)pte - (void *)first_pte);
			pte = NULL;
		}
2337 2338

		if (!sg_res && nr_pages)
2339 2340 2341 2342 2343
			sg = sg_next(sg);
	}
	return 0;
}

2344 2345 2346
static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
				    struct scatterlist *sg, unsigned long nr_pages,
				    int prot)
2347
{
2348 2349
	return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
}
2350

2351 2352 2353 2354 2355
static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
				     unsigned long phys_pfn, unsigned long nr_pages,
				     int prot)
{
	return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
2356 2357
}

2358
static void domain_context_clear_one(struct intel_iommu *iommu, u8 bus, u8 devfn)
2359
{
2360 2361 2362 2363
	unsigned long flags;
	struct context_entry *context;
	u16 did_old;

2364 2365
	if (!iommu)
		return;
2366

2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386
	spin_lock_irqsave(&iommu->lock, flags);
	context = iommu_context_addr(iommu, bus, devfn, 0);
	if (!context) {
		spin_unlock_irqrestore(&iommu->lock, flags);
		return;
	}
	did_old = context_domain_id(context);
	context_clear_entry(context);
	__iommu_flush_cache(iommu, context, sizeof(*context));
	spin_unlock_irqrestore(&iommu->lock, flags);
	iommu->flush.flush_context(iommu,
				   did_old,
				   (((u16)bus) << 8) | devfn,
				   DMA_CCMD_MASK_NOBIT,
				   DMA_CCMD_DEVICE_INVL);
	iommu->flush.flush_iotlb(iommu,
				 did_old,
				 0,
				 0,
				 DMA_TLB_DSI_FLUSH);
2387 2388
}

2389 2390 2391 2392 2393 2394
static inline void unlink_domain_info(struct device_domain_info *info)
{
	assert_spin_locked(&device_domain_lock);
	list_del(&info->link);
	list_del(&info->global);
	if (info->dev)
2395
		info->dev->archdata.iommu = NULL;
2396 2397
}

2398 2399
static void domain_remove_dev_info(struct dmar_domain *domain)
{
2400
	struct device_domain_info *info, *tmp;
2401
	unsigned long flags;
2402 2403

	spin_lock_irqsave(&device_domain_lock, flags);
2404
	list_for_each_entry_safe(info, tmp, &domain->devices, link)
2405
		__dmar_remove_one_dev_info(info);
2406 2407 2408 2409 2410
	spin_unlock_irqrestore(&device_domain_lock, flags);
}

/*
 * find_domain
2411
 * Note: we use struct device->archdata.iommu stores the info
2412
 */
2413
static struct dmar_domain *find_domain(struct device *dev)
2414 2415 2416 2417
{
	struct device_domain_info *info;

	/* No lock here, assumes no domain exit in normal case */
2418
	info = dev->archdata.iommu;
2419
	if (likely(info))
2420 2421 2422 2423
		return info->domain;
	return NULL;
}

2424
static inline struct device_domain_info *
2425 2426 2427 2428 2429
dmar_search_domain_by_dev_info(int segment, int bus, int devfn)
{
	struct device_domain_info *info;

	list_for_each_entry(info, &device_domain_list, global)
2430
		if (info->iommu->segment == segment && info->bus == bus &&
2431
		    info->devfn == devfn)
2432
			return info;
2433 2434 2435 2436

	return NULL;
}

2437 2438 2439 2440
static struct dmar_domain *dmar_insert_one_dev_info(struct intel_iommu *iommu,
						    int bus, int devfn,
						    struct device *dev,
						    struct dmar_domain *domain)
2441
{
2442
	struct dmar_domain *found = NULL;
2443 2444
	struct device_domain_info *info;
	unsigned long flags;
2445
	int ret;
2446 2447 2448

	info = alloc_devinfo_mem();
	if (!info)
2449
		return NULL;
2450 2451 2452

	info->bus = bus;
	info->devfn = devfn;
2453 2454 2455
	info->ats_supported = info->pasid_supported = info->pri_supported = 0;
	info->ats_enabled = info->pasid_enabled = info->pri_enabled = 0;
	info->ats_qdep = 0;
2456 2457
	info->dev = dev;
	info->domain = domain;
2458
	info->iommu = iommu;
2459

2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480
	if (dev && dev_is_pci(dev)) {
		struct pci_dev *pdev = to_pci_dev(info->dev);

		if (ecap_dev_iotlb_support(iommu->ecap) &&
		    pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS) &&
		    dmar_find_matched_atsr_unit(pdev))
			info->ats_supported = 1;

		if (ecs_enabled(iommu)) {
			if (pasid_enabled(iommu)) {
				int features = pci_pasid_features(pdev);
				if (features >= 0)
					info->pasid_supported = features | 1;
			}

			if (info->ats_supported && ecap_prs(iommu->ecap) &&
			    pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI))
				info->pri_supported = 1;
		}
	}

2481 2482
	spin_lock_irqsave(&device_domain_lock, flags);
	if (dev)
2483
		found = find_domain(dev);
2484 2485

	if (!found) {
2486
		struct device_domain_info *info2;
2487
		info2 = dmar_search_domain_by_dev_info(iommu->segment, bus, devfn);
2488 2489 2490 2491
		if (info2) {
			found      = info2->domain;
			info2->dev = dev;
		}
2492
	}
2493

2494 2495 2496
	if (found) {
		spin_unlock_irqrestore(&device_domain_lock, flags);
		free_devinfo_mem(info);
2497 2498
		/* Caller must free the original domain */
		return found;
2499 2500
	}

2501 2502 2503 2504 2505
	spin_lock(&iommu->lock);
	ret = domain_attach_iommu(domain, iommu);
	spin_unlock(&iommu->lock);

	if (ret) {
2506
		spin_unlock_irqrestore(&device_domain_lock, flags);
2507
		free_devinfo_mem(info);
2508 2509 2510
		return NULL;
	}

2511 2512 2513 2514 2515 2516
	list_add(&info->link, &domain->devices);
	list_add(&info->global, &device_domain_list);
	if (dev)
		dev->archdata.iommu = info;
	spin_unlock_irqrestore(&device_domain_lock, flags);

2517 2518
	if (dev && domain_context_mapping(domain, dev)) {
		pr_err("Domain context map for %s failed\n", dev_name(dev));
2519
		dmar_remove_one_dev_info(domain, dev);
2520 2521 2522
		return NULL;
	}

2523
	return domain;
2524 2525
}

2526 2527 2528 2529 2530 2531
static int get_last_alias(struct pci_dev *pdev, u16 alias, void *opaque)
{
	*(u16 *)opaque = alias;
	return 0;
}

2532
static struct dmar_domain *find_or_alloc_domain(struct device *dev, int gaw)
2533
{
2534
	struct device_domain_info *info = NULL;
2535
	struct dmar_domain *domain = NULL;
2536
	struct intel_iommu *iommu;
2537
	u16 req_id, dma_alias;
2538
	unsigned long flags;
2539
	u8 bus, devfn;
2540

2541 2542 2543 2544
	iommu = device_to_iommu(dev, &bus, &devfn);
	if (!iommu)
		return NULL;

2545 2546
	req_id = ((u16)bus << 8) | devfn;

2547 2548
	if (dev_is_pci(dev)) {
		struct pci_dev *pdev = to_pci_dev(dev);
2549

2550 2551 2552 2553 2554 2555 2556 2557 2558
		pci_for_each_dma_alias(pdev, get_last_alias, &dma_alias);

		spin_lock_irqsave(&device_domain_lock, flags);
		info = dmar_search_domain_by_dev_info(pci_domain_nr(pdev->bus),
						      PCI_BUS_NUM(dma_alias),
						      dma_alias & 0xff);
		if (info) {
			iommu = info->iommu;
			domain = info->domain;
2559
		}
2560
		spin_unlock_irqrestore(&device_domain_lock, flags);
2561

2562
		/* DMA alias already has a domain, use it */
2563
		if (info)
2564
			goto out;
2565
	}
2566

2567
	/* Allocate and initialize new domain for the device */
2568
	domain = alloc_domain(0);
2569
	if (!domain)
2570
		return NULL;
2571
	if (domain_init(domain, iommu, gaw)) {
2572 2573
		domain_exit(domain);
		return NULL;
2574
	}
2575

2576
out:
2577

2578 2579
	return domain;
}
2580

2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607
static struct dmar_domain *set_domain_for_dev(struct device *dev,
					      struct dmar_domain *domain)
{
	struct intel_iommu *iommu;
	struct dmar_domain *tmp;
	u16 req_id, dma_alias;
	u8 bus, devfn;

	iommu = device_to_iommu(dev, &bus, &devfn);
	if (!iommu)
		return NULL;

	req_id = ((u16)bus << 8) | devfn;

	if (dev_is_pci(dev)) {
		struct pci_dev *pdev = to_pci_dev(dev);

		pci_for_each_dma_alias(pdev, get_last_alias, &dma_alias);

		/* register PCI DMA alias device */
		if (req_id != dma_alias) {
			tmp = dmar_insert_one_dev_info(iommu, PCI_BUS_NUM(dma_alias),
					dma_alias & 0xff, NULL, domain);

			if (!tmp || tmp != domain)
				return tmp;
		}
2608 2609
	}

2610
	tmp = dmar_insert_one_dev_info(iommu, bus, devfn, dev, domain);
2611 2612 2613 2614 2615
	if (!tmp || tmp != domain)
		return tmp;

	return domain;
}
2616

2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630
static struct dmar_domain *get_domain_for_dev(struct device *dev, int gaw)
{
	struct dmar_domain *domain, *tmp;

	domain = find_domain(dev);
	if (domain)
		goto out;

	domain = find_or_alloc_domain(dev, gaw);
	if (!domain)
		goto out;

	tmp = set_domain_for_dev(dev, domain);
	if (!tmp || domain != tmp) {
2631 2632 2633
		domain_exit(domain);
		domain = tmp;
	}
2634

2635 2636
out:

2637
	return domain;
2638 2639
}

2640 2641 2642
static int iommu_domain_identity_map(struct dmar_domain *domain,
				     unsigned long long start,
				     unsigned long long end)
2643
{
2644 2645 2646 2647 2648
	unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
	unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;

	if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
			  dma_to_mm_pfn(last_vpfn))) {
J
Joerg Roedel 已提交
2649
		pr_err("Reserving iova failed\n");
2650
		return -ENOMEM;
2651 2652
	}

J
Joerg Roedel 已提交
2653
	pr_debug("Mapping reserved region %llx-%llx\n", start, end);
2654 2655 2656 2657
	/*
	 * RMRR range might have overlap with physical memory range,
	 * clear it first
	 */
2658
	dma_pte_clear_range(domain, first_vpfn, last_vpfn);
2659

2660 2661
	return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
				  last_vpfn - first_vpfn + 1,
2662
				  DMA_PTE_READ|DMA_PTE_WRITE);
2663 2664
}

2665 2666 2667 2668
static int domain_prepare_identity_map(struct device *dev,
				       struct dmar_domain *domain,
				       unsigned long long start,
				       unsigned long long end)
2669
{
2670 2671 2672 2673 2674
	/* For _hardware_ passthrough, don't bother. But for software
	   passthrough, we do it anyway -- it may indicate a memory
	   range which is reserved in E820, so which didn't get set
	   up to start with in si_domain */
	if (domain == si_domain && hw_pass_through) {
J
Joerg Roedel 已提交
2675 2676
		pr_warn("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
			dev_name(dev), start, end);
2677 2678 2679
		return 0;
	}

J
Joerg Roedel 已提交
2680 2681 2682
	pr_info("Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
		dev_name(dev), start, end);

2683 2684 2685 2686 2687 2688
	if (end < start) {
		WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
			"BIOS vendor: %s; Ver: %s; Product Version: %s\n",
			dmi_get_system_info(DMI_BIOS_VENDOR),
			dmi_get_system_info(DMI_BIOS_VERSION),
		     dmi_get_system_info(DMI_PRODUCT_VERSION));
2689
		return -EIO;
2690 2691
	}

2692 2693 2694 2695 2696 2697 2698
	if (end >> agaw_to_width(domain->agaw)) {
		WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
		     "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
		     agaw_to_width(domain->agaw),
		     dmi_get_system_info(DMI_BIOS_VENDOR),
		     dmi_get_system_info(DMI_BIOS_VERSION),
		     dmi_get_system_info(DMI_PRODUCT_VERSION));
2699
		return -EIO;
2700
	}
2701

2702 2703
	return iommu_domain_identity_map(domain, start, end);
}
2704

2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718
static int iommu_prepare_identity_map(struct device *dev,
				      unsigned long long start,
				      unsigned long long end)
{
	struct dmar_domain *domain;
	int ret;

	domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
	if (!domain)
		return -ENOMEM;

	ret = domain_prepare_identity_map(dev, domain, start, end);
	if (ret)
		domain_exit(domain);
2719

2720 2721 2722 2723
	return ret;
}

static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
2724
					 struct device *dev)
2725
{
2726
	if (dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2727
		return 0;
2728 2729
	return iommu_prepare_identity_map(dev, rmrr->base_address,
					  rmrr->end_address);
2730 2731
}

2732
#ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
2733 2734 2735 2736 2737 2738 2739 2740 2741
static inline void iommu_prepare_isa(void)
{
	struct pci_dev *pdev;
	int ret;

	pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
	if (!pdev)
		return;

J
Joerg Roedel 已提交
2742
	pr_info("Prepare 0-16MiB unity mapping for LPC\n");
2743
	ret = iommu_prepare_identity_map(&pdev->dev, 0, 16*1024*1024 - 1);
2744 2745

	if (ret)
J
Joerg Roedel 已提交
2746
		pr_err("Failed to create 0-16MiB identity map - floppy might not work\n");
2747

2748
	pci_dev_put(pdev);
2749 2750 2751 2752 2753 2754
}
#else
static inline void iommu_prepare_isa(void)
{
	return;
}
2755
#endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */
2756

2757
static int md_domain_init(struct dmar_domain *domain, int guest_width);
2758

2759
static int __init si_domain_init(int hw)
2760
{
2761
	int nid, ret = 0;
2762

2763
	si_domain = alloc_domain(DOMAIN_FLAG_STATIC_IDENTITY);
2764 2765 2766 2767 2768 2769 2770 2771
	if (!si_domain)
		return -EFAULT;

	if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
		domain_exit(si_domain);
		return -EFAULT;
	}

2772
	pr_debug("Identity mapping domain allocated\n");
2773

2774 2775 2776
	if (hw)
		return 0;

2777
	for_each_online_node(nid) {
2778 2779 2780 2781 2782 2783 2784 2785 2786
		unsigned long start_pfn, end_pfn;
		int i;

		for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) {
			ret = iommu_domain_identity_map(si_domain,
					PFN_PHYS(start_pfn), PFN_PHYS(end_pfn));
			if (ret)
				return ret;
		}
2787 2788
	}

2789 2790 2791
	return 0;
}

2792
static int identity_mapping(struct device *dev)
2793 2794 2795 2796 2797 2798
{
	struct device_domain_info *info;

	if (likely(!iommu_identity_mapping))
		return 0;

2799
	info = dev->archdata.iommu;
2800 2801
	if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
		return (info->domain == si_domain);
2802 2803 2804 2805

	return 0;
}

2806
static int domain_add_dev_info(struct dmar_domain *domain, struct device *dev)
2807
{
2808
	struct dmar_domain *ndomain;
2809
	struct intel_iommu *iommu;
2810
	u8 bus, devfn;
2811

2812
	iommu = device_to_iommu(dev, &bus, &devfn);
2813 2814 2815
	if (!iommu)
		return -ENODEV;

2816
	ndomain = dmar_insert_one_dev_info(iommu, bus, devfn, dev, domain);
2817 2818
	if (ndomain != domain)
		return -EBUSY;
2819 2820 2821 2822

	return 0;
}

2823
static bool device_has_rmrr(struct device *dev)
2824 2825
{
	struct dmar_rmrr_unit *rmrr;
2826
	struct device *tmp;
2827 2828
	int i;

2829
	rcu_read_lock();
2830
	for_each_rmrr_units(rmrr) {
2831 2832 2833 2834 2835 2836
		/*
		 * Return TRUE if this RMRR contains the device that
		 * is passed in.
		 */
		for_each_active_dev_scope(rmrr->devices,
					  rmrr->devices_cnt, i, tmp)
2837
			if (tmp == dev) {
2838
				rcu_read_unlock();
2839
				return true;
2840
			}
2841
	}
2842
	rcu_read_unlock();
2843 2844 2845
	return false;
}

2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862
/*
 * There are a couple cases where we need to restrict the functionality of
 * devices associated with RMRRs.  The first is when evaluating a device for
 * identity mapping because problems exist when devices are moved in and out
 * of domains and their respective RMRR information is lost.  This means that
 * a device with associated RMRRs will never be in a "passthrough" domain.
 * The second is use of the device through the IOMMU API.  This interface
 * expects to have full control of the IOVA space for the device.  We cannot
 * satisfy both the requirement that RMRR access is maintained and have an
 * unencumbered IOVA space.  We also have no ability to quiesce the device's
 * use of the RMRR space or even inform the IOMMU API user of the restriction.
 * We therefore prevent devices associated with an RMRR from participating in
 * the IOMMU API, which eliminates them from device assignment.
 *
 * In both cases we assume that PCI USB devices with RMRRs have them largely
 * for historical reasons and that the RMRR space is not actively used post
 * boot.  This exclusion may change if vendors begin to abuse it.
2863 2864 2865 2866
 *
 * The same exception is made for graphics devices, with the requirement that
 * any use of the RMRR regions will be torn down before assigning the device
 * to a guest.
2867 2868 2869 2870 2871 2872 2873 2874 2875
 */
static bool device_is_rmrr_locked(struct device *dev)
{
	if (!device_has_rmrr(dev))
		return false;

	if (dev_is_pci(dev)) {
		struct pci_dev *pdev = to_pci_dev(dev);

2876
		if (IS_USB_DEVICE(pdev) || IS_GFX_DEVICE(pdev))
2877 2878 2879 2880 2881 2882
			return false;
	}

	return true;
}

2883
static int iommu_should_identity_map(struct device *dev, int startup)
2884
{
2885

2886 2887
	if (dev_is_pci(dev)) {
		struct pci_dev *pdev = to_pci_dev(dev);
2888

2889
		if (device_is_rmrr_locked(dev))
2890
			return 0;
2891

2892 2893
		if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev))
			return 1;
2894

2895 2896
		if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
			return 1;
2897

2898
		if (!(iommu_identity_mapping & IDENTMAP_ALL))
2899
			return 0;
2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923

		/*
		 * We want to start off with all devices in the 1:1 domain, and
		 * take them out later if we find they can't access all of memory.
		 *
		 * However, we can't do this for PCI devices behind bridges,
		 * because all PCI devices behind the same bridge will end up
		 * with the same source-id on their transactions.
		 *
		 * Practically speaking, we can't change things around for these
		 * devices at run-time, because we can't be sure there'll be no
		 * DMA transactions in flight for any of their siblings.
		 *
		 * So PCI devices (unless they're on the root bus) as well as
		 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
		 * the 1:1 domain, just in _case_ one of their siblings turns out
		 * not to be able to map all of memory.
		 */
		if (!pci_is_pcie(pdev)) {
			if (!pci_is_root_bus(pdev->bus))
				return 0;
			if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
				return 0;
		} else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE)
2924
			return 0;
2925 2926 2927 2928
	} else {
		if (device_has_rmrr(dev))
			return 0;
	}
2929

2930
	/*
2931
	 * At boot time, we don't yet know if devices will be 64-bit capable.
2932
	 * Assume that they will — if they turn out not to be, then we can
2933 2934
	 * take them out of the 1:1 domain later.
	 */
2935 2936 2937 2938 2939
	if (!startup) {
		/*
		 * If the device's dma_mask is less than the system's memory
		 * size then this is not a candidate for identity mapping.
		 */
2940
		u64 dma_mask = *dev->dma_mask;
2941

2942 2943 2944
		if (dev->coherent_dma_mask &&
		    dev->coherent_dma_mask < dma_mask)
			dma_mask = dev->coherent_dma_mask;
2945

2946
		return dma_mask >= dma_get_required_mask(dev);
2947
	}
2948 2949 2950 2951

	return 1;
}

2952 2953 2954 2955 2956 2957 2958
static int __init dev_prepare_static_identity_mapping(struct device *dev, int hw)
{
	int ret;

	if (!iommu_should_identity_map(dev, 1))
		return 0;

2959
	ret = domain_add_dev_info(si_domain, dev);
2960
	if (!ret)
J
Joerg Roedel 已提交
2961 2962
		pr_info("%s identity mapping for device %s\n",
			hw ? "Hardware" : "Software", dev_name(dev));
2963 2964 2965 2966 2967 2968 2969 2970
	else if (ret == -ENODEV)
		/* device not associated with an iommu */
		ret = 0;

	return ret;
}


2971
static int __init iommu_prepare_static_identity_mapping(int hw)
2972 2973
{
	struct pci_dev *pdev = NULL;
2974 2975 2976 2977 2978
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;
	struct device *dev;
	int i;
	int ret = 0;
2979 2980

	for_each_pci_dev(pdev) {
2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992
		ret = dev_prepare_static_identity_mapping(&pdev->dev, hw);
		if (ret)
			return ret;
	}

	for_each_active_iommu(iommu, drhd)
		for_each_active_dev_scope(drhd->devices, drhd->devices_cnt, i, dev) {
			struct acpi_device_physical_node *pn;
			struct acpi_device *adev;

			if (dev->bus != &acpi_bus_type)
				continue;
2993

2994 2995 2996 2997 2998 2999
			adev= to_acpi_device(dev);
			mutex_lock(&adev->physical_node_lock);
			list_for_each_entry(pn, &adev->physical_node_list, node) {
				ret = dev_prepare_static_identity_mapping(pn->dev, hw);
				if (ret)
					break;
3000
			}
3001 3002 3003
			mutex_unlock(&adev->physical_node_lock);
			if (ret)
				return ret;
3004
		}
3005 3006 3007 3008

	return 0;
}

3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034
static void intel_iommu_init_qi(struct intel_iommu *iommu)
{
	/*
	 * Start from the sane iommu hardware state.
	 * If the queued invalidation is already initialized by us
	 * (for example, while enabling interrupt-remapping) then
	 * we got the things already rolling from a sane state.
	 */
	if (!iommu->qi) {
		/*
		 * Clear any previous faults.
		 */
		dmar_fault(-1, iommu);
		/*
		 * Disable queued invalidation if supported and already enabled
		 * before OS handover.
		 */
		dmar_disable_qi(iommu);
	}

	if (dmar_enable_qi(iommu)) {
		/*
		 * Queued Invalidate not enabled, use Register Based Invalidate
		 */
		iommu->flush.flush_context = __iommu_flush_context;
		iommu->flush.flush_iotlb = __iommu_flush_iotlb;
J
Joerg Roedel 已提交
3035
		pr_info("%s: Using Register based invalidation\n",
3036 3037 3038 3039
			iommu->name);
	} else {
		iommu->flush.flush_context = qi_flush_context;
		iommu->flush.flush_iotlb = qi_flush_iotlb;
J
Joerg Roedel 已提交
3040
		pr_info("%s: Using Queued invalidation\n", iommu->name);
3041 3042 3043
	}
}

3044
static int copy_context_table(struct intel_iommu *iommu,
3045
			      struct root_entry *old_re,
3046 3047 3048
			      struct context_entry **tbl,
			      int bus, bool ext)
{
3049
	int tbl_idx, pos = 0, idx, devfn, ret = 0, did;
3050
	struct context_entry *new_ce = NULL, ce;
3051
	struct context_entry *old_ce = NULL;
3052
	struct root_entry re;
3053 3054 3055
	phys_addr_t old_ce_phys;

	tbl_idx = ext ? bus * 2 : bus;
3056
	memcpy(&re, old_re, sizeof(re));
3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075

	for (devfn = 0; devfn < 256; devfn++) {
		/* First calculate the correct index */
		idx = (ext ? devfn * 2 : devfn) % 256;

		if (idx == 0) {
			/* First save what we may have and clean up */
			if (new_ce) {
				tbl[tbl_idx] = new_ce;
				__iommu_flush_cache(iommu, new_ce,
						    VTD_PAGE_SIZE);
				pos = 1;
			}

			if (old_ce)
				iounmap(old_ce);

			ret = 0;
			if (devfn < 0x80)
3076
				old_ce_phys = root_entry_lctp(&re);
3077
			else
3078
				old_ce_phys = root_entry_uctp(&re);
3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090

			if (!old_ce_phys) {
				if (ext && devfn == 0) {
					/* No LCTP, try UCTP */
					devfn = 0x7f;
					continue;
				} else {
					goto out;
				}
			}

			ret = -ENOMEM;
3091 3092
			old_ce = memremap(old_ce_phys, PAGE_SIZE,
					MEMREMAP_WB);
3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103
			if (!old_ce)
				goto out;

			new_ce = alloc_pgtable_page(iommu->node);
			if (!new_ce)
				goto out_unmap;

			ret = 0;
		}

		/* Now copy the context entry */
3104
		memcpy(&ce, old_ce + idx, sizeof(ce));
3105

3106
		if (!__context_present(&ce))
3107 3108
			continue;

3109 3110 3111 3112
		did = context_domain_id(&ce);
		if (did >= 0 && did < cap_ndoms(iommu->cap))
			set_bit(did, iommu->domain_ids);

3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131
		/*
		 * We need a marker for copied context entries. This
		 * marker needs to work for the old format as well as
		 * for extended context entries.
		 *
		 * Bit 67 of the context entry is used. In the old
		 * format this bit is available to software, in the
		 * extended format it is the PGE bit, but PGE is ignored
		 * by HW if PASIDs are disabled (and thus still
		 * available).
		 *
		 * So disable PASIDs first and then mark the entry
		 * copied. This means that we don't copy PASID
		 * translations from the old kernel, but this is fine as
		 * faults there are not fatal.
		 */
		context_clear_pasid_enable(&ce);
		context_set_copied(&ce);

3132 3133 3134 3135 3136 3137 3138 3139
		new_ce[idx] = ce;
	}

	tbl[tbl_idx + pos] = new_ce;

	__iommu_flush_cache(iommu, new_ce, VTD_PAGE_SIZE);

out_unmap:
3140
	memunmap(old_ce);
3141 3142 3143 3144 3145 3146 3147 3148

out:
	return ret;
}

static int copy_translation_tables(struct intel_iommu *iommu)
{
	struct context_entry **ctxt_tbls;
3149
	struct root_entry *old_rt;
3150 3151 3152 3153 3154
	phys_addr_t old_rt_phys;
	int ctxt_table_entries;
	unsigned long flags;
	u64 rtaddr_reg;
	int bus, ret;
3155
	bool new_ext, ext;
3156 3157 3158

	rtaddr_reg = dmar_readq(iommu->reg + DMAR_RTADDR_REG);
	ext        = !!(rtaddr_reg & DMA_RTADDR_RTT);
3159 3160 3161 3162 3163 3164 3165 3166 3167 3168
	new_ext    = !!ecap_ecs(iommu->ecap);

	/*
	 * The RTT bit can only be changed when translation is disabled,
	 * but disabling translation means to open a window for data
	 * corruption. So bail out and don't copy anything if we would
	 * have to change the bit.
	 */
	if (new_ext != ext)
		return -EINVAL;
3169 3170 3171 3172 3173

	old_rt_phys = rtaddr_reg & VTD_PAGE_MASK;
	if (!old_rt_phys)
		return -EINVAL;

3174
	old_rt = memremap(old_rt_phys, PAGE_SIZE, MEMREMAP_WB);
3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222
	if (!old_rt)
		return -ENOMEM;

	/* This is too big for the stack - allocate it from slab */
	ctxt_table_entries = ext ? 512 : 256;
	ret = -ENOMEM;
	ctxt_tbls = kzalloc(ctxt_table_entries * sizeof(void *), GFP_KERNEL);
	if (!ctxt_tbls)
		goto out_unmap;

	for (bus = 0; bus < 256; bus++) {
		ret = copy_context_table(iommu, &old_rt[bus],
					 ctxt_tbls, bus, ext);
		if (ret) {
			pr_err("%s: Failed to copy context table for bus %d\n",
				iommu->name, bus);
			continue;
		}
	}

	spin_lock_irqsave(&iommu->lock, flags);

	/* Context tables are copied, now write them to the root_entry table */
	for (bus = 0; bus < 256; bus++) {
		int idx = ext ? bus * 2 : bus;
		u64 val;

		if (ctxt_tbls[idx]) {
			val = virt_to_phys(ctxt_tbls[idx]) | 1;
			iommu->root_entry[bus].lo = val;
		}

		if (!ext || !ctxt_tbls[idx + 1])
			continue;

		val = virt_to_phys(ctxt_tbls[idx + 1]) | 1;
		iommu->root_entry[bus].hi = val;
	}

	spin_unlock_irqrestore(&iommu->lock, flags);

	kfree(ctxt_tbls);

	__iommu_flush_cache(iommu, iommu->root_entry, PAGE_SIZE);

	ret = 0;

out_unmap:
3223
	memunmap(old_rt);
3224 3225 3226 3227

	return ret;
}

3228
static int __init init_dmars(void)
3229 3230 3231
{
	struct dmar_drhd_unit *drhd;
	struct dmar_rmrr_unit *rmrr;
3232
	bool copied_tables = false;
3233
	struct device *dev;
3234
	struct intel_iommu *iommu;
3235
	int i, ret;
3236

3237 3238 3239 3240 3241 3242 3243
	/*
	 * for each drhd
	 *    allocate root
	 *    initialize and program root entry to not present
	 * endfor
	 */
	for_each_drhd_unit(drhd) {
M
mark gross 已提交
3244 3245 3246 3247 3248
		/*
		 * lock not needed as this is only incremented in the single
		 * threaded kernel __init code path all other access are read
		 * only
		 */
3249
		if (g_num_of_iommus < DMAR_UNITS_SUPPORTED) {
3250 3251 3252
			g_num_of_iommus++;
			continue;
		}
J
Joerg Roedel 已提交
3253
		pr_err_once("Exceeded %d IOMMUs\n", DMAR_UNITS_SUPPORTED);
M
mark gross 已提交
3254 3255
	}

3256 3257 3258 3259
	/* Preallocate enough resources for IOMMU hot-addition */
	if (g_num_of_iommus < DMAR_UNITS_SUPPORTED)
		g_num_of_iommus = DMAR_UNITS_SUPPORTED;

W
Weidong Han 已提交
3260 3261 3262
	g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
			GFP_KERNEL);
	if (!g_iommus) {
J
Joerg Roedel 已提交
3263
		pr_err("Allocating global iommu array failed\n");
W
Weidong Han 已提交
3264 3265 3266 3267
		ret = -ENOMEM;
		goto error;
	}

3268
	for_each_active_iommu(iommu, drhd) {
W
Weidong Han 已提交
3269
		g_iommus[iommu->seq_id] = iommu;
3270

3271 3272
		intel_iommu_init_qi(iommu);

3273 3274
		ret = iommu_init_domains(iommu);
		if (ret)
3275
			goto free_iommu;
3276

3277 3278
		init_translation_status(iommu);

3279 3280 3281 3282 3283 3284
		if (translation_pre_enabled(iommu) && !is_kdump_kernel()) {
			iommu_disable_translation(iommu);
			clear_translation_pre_enabled(iommu);
			pr_warn("Translation was enabled for %s but we are not in kdump mode\n",
				iommu->name);
		}
3285

3286 3287 3288
		/*
		 * TBD:
		 * we could share the same root & context tables
L
Lucas De Marchi 已提交
3289
		 * among all IOMMU's. Need to Split it later.
3290 3291
		 */
		ret = iommu_alloc_root_entry(iommu);
3292
		if (ret)
3293
			goto free_iommu;
3294

3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315
		if (translation_pre_enabled(iommu)) {
			pr_info("Translation already enabled - trying to copy translation structures\n");

			ret = copy_translation_tables(iommu);
			if (ret) {
				/*
				 * We found the IOMMU with translation
				 * enabled - but failed to copy over the
				 * old root-entry table. Try to proceed
				 * by disabling translation now and
				 * allocating a clean root-entry table.
				 * This might cause DMAR faults, but
				 * probably the dump will still succeed.
				 */
				pr_err("Failed to copy translation tables from previous kernel for %s\n",
				       iommu->name);
				iommu_disable_translation(iommu);
				clear_translation_pre_enabled(iommu);
			} else {
				pr_info("Copied translation tables from previous kernel for %s\n",
					iommu->name);
3316
				copied_tables = true;
3317 3318 3319
			}
		}

F
Fenghua Yu 已提交
3320
		if (!ecap_pass_through(iommu->ecap))
3321
			hw_pass_through = 0;
3322 3323 3324 3325
#ifdef CONFIG_INTEL_IOMMU_SVM
		if (pasid_enabled(iommu))
			intel_svm_alloc_pasid_tables(iommu);
#endif
3326 3327
	}

3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339
	/*
	 * Now that qi is enabled on all iommus, set the root entry and flush
	 * caches. This is required on some Intel X58 chipsets, otherwise the
	 * flush_context function will loop forever and the boot hangs.
	 */
	for_each_active_iommu(iommu, drhd) {
		iommu_flush_write_buffer(iommu);
		iommu_set_root_entry(iommu);
		iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
		iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
	}

3340
	if (iommu_pass_through)
3341 3342
		iommu_identity_mapping |= IDENTMAP_ALL;

3343
#ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
3344
	iommu_identity_mapping |= IDENTMAP_GFX;
3345
#endif
3346

3347 3348
	check_tylersburg_isoch();

3349 3350 3351 3352 3353 3354
	if (iommu_identity_mapping) {
		ret = si_domain_init(hw_pass_through);
		if (ret)
			goto free_iommu;
	}

3355

3356 3357 3358 3359 3360 3361 3362 3363 3364
	/*
	 * If we copied translations from a previous kernel in the kdump
	 * case, we can not assign the devices to domains now, as that
	 * would eliminate the old mappings. So skip this part and defer
	 * the assignment to device driver initialization time.
	 */
	if (copied_tables)
		goto domains_done;

3365
	/*
3366 3367 3368
	 * If pass through is not set or not enabled, setup context entries for
	 * identity mappings for rmrr, gfx, and isa and may fall back to static
	 * identity mapping if iommu_identity_mapping is set.
3369
	 */
3370 3371
	if (iommu_identity_mapping) {
		ret = iommu_prepare_static_identity_mapping(hw_pass_through);
F
Fenghua Yu 已提交
3372
		if (ret) {
J
Joerg Roedel 已提交
3373
			pr_crit("Failed to setup IOMMU pass-through\n");
3374
			goto free_iommu;
3375 3376 3377
		}
	}
	/*
3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389
	 * For each rmrr
	 *   for each dev attached to rmrr
	 *   do
	 *     locate drhd for dev, alloc domain for dev
	 *     allocate free domain
	 *     allocate page table entries for rmrr
	 *     if context not allocated for bus
	 *           allocate and init context
	 *           set present in root table for this bus
	 *     init context with domain, translation etc
	 *    endfor
	 * endfor
3390
	 */
J
Joerg Roedel 已提交
3391
	pr_info("Setting RMRR:\n");
3392
	for_each_rmrr_units(rmrr) {
3393 3394
		/* some BIOS lists non-exist devices in DMAR table. */
		for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt,
3395
					  i, dev) {
3396
			ret = iommu_prepare_rmrr_dev(rmrr, dev);
3397
			if (ret)
J
Joerg Roedel 已提交
3398
				pr_err("Mapping reserved region failed\n");
3399
		}
F
Fenghua Yu 已提交
3400
	}
3401

3402 3403
	iommu_prepare_isa();

3404 3405
domains_done:

3406 3407 3408 3409 3410 3411 3412
	/*
	 * for each drhd
	 *   enable fault log
	 *   global invalidate context cache
	 *   global invalidate iotlb
	 *   enable translation
	 */
3413
	for_each_iommu(iommu, drhd) {
3414 3415 3416 3417 3418 3419
		if (drhd->ignored) {
			/*
			 * we always have to disable PMRs or DMA may fail on
			 * this device
			 */
			if (force_on)
3420
				iommu_disable_protect_mem_regions(iommu);
3421
			continue;
3422
		}
3423 3424 3425

		iommu_flush_write_buffer(iommu);

3426 3427 3428 3429 3430 3431 3432
#ifdef CONFIG_INTEL_IOMMU_SVM
		if (pasid_enabled(iommu) && ecap_prs(iommu->ecap)) {
			ret = intel_svm_enable_prq(iommu);
			if (ret)
				goto free_iommu;
		}
#endif
3433 3434
		ret = dmar_set_interrupt(iommu);
		if (ret)
3435
			goto free_iommu;
3436

3437 3438 3439
		if (!translation_pre_enabled(iommu))
			iommu_enable_translation(iommu);

3440
		iommu_disable_protect_mem_regions(iommu);
3441 3442 3443
	}

	return 0;
3444 3445

free_iommu:
3446 3447
	for_each_active_iommu(iommu, drhd) {
		disable_dmar_iommu(iommu);
3448
		free_dmar_iommu(iommu);
3449
	}
3450

W
Weidong Han 已提交
3451
	kfree(g_iommus);
3452

3453
error:
3454 3455 3456
	return ret;
}

3457
/* This takes a number of _MM_ pages, not VTD pages */
3458
static unsigned long intel_alloc_iova(struct device *dev,
3459 3460
				     struct dmar_domain *domain,
				     unsigned long nrpages, uint64_t dma_mask)
3461
{
3462
	unsigned long iova_pfn = 0;
3463

3464 3465
	/* Restrict dma_mask to the width that the iommu can handle */
	dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
3466 3467
	/* Ensure we reserve the whole size-aligned region */
	nrpages = __roundup_pow_of_two(nrpages);
3468 3469

	if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
3470 3471
		/*
		 * First try to allocate an io virtual address in
3472
		 * DMA_BIT_MASK(32) and if that fails then try allocating
J
Joe Perches 已提交
3473
		 * from higher range
3474
		 */
3475 3476 3477 3478
		iova_pfn = alloc_iova_fast(&domain->iovad, nrpages,
					   IOVA_PFN(DMA_BIT_MASK(32)));
		if (iova_pfn)
			return iova_pfn;
3479
	}
3480 3481
	iova_pfn = alloc_iova_fast(&domain->iovad, nrpages, IOVA_PFN(dma_mask));
	if (unlikely(!iova_pfn)) {
J
Joerg Roedel 已提交
3482
		pr_err("Allocating %ld-page iova for %s failed",
3483
		       nrpages, dev_name(dev));
3484
		return 0;
3485 3486
	}

3487
	return iova_pfn;
3488 3489
}

3490
static struct dmar_domain *get_valid_domain_for_dev(struct device *dev)
3491
{
3492
	struct dmar_domain *domain, *tmp;
3493 3494 3495
	struct dmar_rmrr_unit *rmrr;
	struct device *i_dev;
	int i, ret;
3496

3497 3498 3499 3500 3501 3502 3503
	domain = find_domain(dev);
	if (domain)
		goto out;

	domain = find_or_alloc_domain(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
	if (!domain)
		goto out;
3504

3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521
	/* We have a new domain - setup possible RMRRs for the device */
	rcu_read_lock();
	for_each_rmrr_units(rmrr) {
		for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt,
					  i, i_dev) {
			if (i_dev != dev)
				continue;

			ret = domain_prepare_identity_map(dev, domain,
							  rmrr->base_address,
							  rmrr->end_address);
			if (ret)
				dev_err(dev, "Mapping reserved region failed\n");
		}
	}
	rcu_read_unlock();

3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533
	tmp = set_domain_for_dev(dev, domain);
	if (!tmp || domain != tmp) {
		domain_exit(domain);
		domain = tmp;
	}

out:

	if (!domain)
		pr_err("Allocating domain for %s failed\n", dev_name(dev));


3534 3535 3536
	return domain;
}

3537
/* Check if the dev needs to go through non-identity map and unmap process.*/
3538
static int iommu_no_mapping(struct device *dev)
3539 3540 3541
{
	int found;

3542
	if (iommu_dummy(dev))
3543 3544
		return 1;

3545
	if (!iommu_identity_mapping)
3546
		return 0;
3547

3548
	found = identity_mapping(dev);
3549
	if (found) {
3550
		if (iommu_should_identity_map(dev, 0))
3551 3552 3553 3554 3555 3556
			return 1;
		else {
			/*
			 * 32 bit DMA is removed from si_domain and fall back
			 * to non-identity mapping.
			 */
3557
			dmar_remove_one_dev_info(si_domain, dev);
J
Joerg Roedel 已提交
3558 3559
			pr_info("32bit %s uses non-identity mapping\n",
				dev_name(dev));
3560 3561 3562 3563 3564 3565 3566
			return 0;
		}
	} else {
		/*
		 * In case of a detached 64 bit DMA device from vm, the device
		 * is put into si_domain for identity mapping.
		 */
3567
		if (iommu_should_identity_map(dev, 0)) {
3568
			int ret;
3569
			ret = domain_add_dev_info(si_domain, dev);
3570
			if (!ret) {
J
Joerg Roedel 已提交
3571 3572
				pr_info("64bit %s uses identity mapping\n",
					dev_name(dev));
3573 3574 3575 3576 3577
				return 1;
			}
		}
	}

3578
	return 0;
3579 3580
}

3581
static dma_addr_t __intel_map_single(struct device *dev, phys_addr_t paddr,
3582
				     size_t size, int dir, u64 dma_mask)
3583 3584
{
	struct dmar_domain *domain;
F
Fenghua Yu 已提交
3585
	phys_addr_t start_paddr;
3586
	unsigned long iova_pfn;
3587
	int prot = 0;
I
Ingo Molnar 已提交
3588
	int ret;
3589
	struct intel_iommu *iommu;
3590
	unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
3591 3592

	BUG_ON(dir == DMA_NONE);
3593

3594
	if (iommu_no_mapping(dev))
I
Ingo Molnar 已提交
3595
		return paddr;
3596

3597
	domain = get_valid_domain_for_dev(dev);
3598 3599 3600
	if (!domain)
		return 0;

3601
	iommu = domain_get_iommu(domain);
3602
	size = aligned_nrpages(paddr, size);
3603

3604 3605
	iova_pfn = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), dma_mask);
	if (!iova_pfn)
3606 3607
		goto error;

3608 3609 3610 3611 3612
	/*
	 * Check if DMAR supports zero-length reads on write only
	 * mappings..
	 */
	if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
3613
			!cap_zlr(iommu->cap))
3614 3615 3616 3617
		prot |= DMA_PTE_READ;
	if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
		prot |= DMA_PTE_WRITE;
	/*
I
Ingo Molnar 已提交
3618
	 * paddr - (paddr + size) might be partial page, we should map the whole
3619
	 * page.  Note: if two part of one page are separately mapped, we
I
Ingo Molnar 已提交
3620
	 * might have two guest_addr mapping to the same host paddr, but this
3621 3622
	 * is not a big problem
	 */
3623
	ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova_pfn),
3624
				 mm_to_dma_pfn(paddr_pfn), size, prot);
3625 3626 3627
	if (ret)
		goto error;

3628 3629
	/* it's a non-present to present mapping. Only flush if caching mode */
	if (cap_caching_mode(iommu->cap))
3630
		iommu_flush_iotlb_psi(iommu, domain,
3631
				      mm_to_dma_pfn(iova_pfn),
3632
				      size, 0, 1);
3633
	else
3634
		iommu_flush_write_buffer(iommu);
3635

3636
	start_paddr = (phys_addr_t)iova_pfn << PAGE_SHIFT;
3637 3638
	start_paddr += paddr & ~PAGE_MASK;
	return start_paddr;
3639 3640

error:
3641
	if (iova_pfn)
3642
		free_iova_fast(&domain->iovad, iova_pfn, dma_to_mm_pfn(size));
J
Joerg Roedel 已提交
3643
	pr_err("Device %s request: %zx@%llx dir %d --- failed\n",
3644
		dev_name(dev), size, (unsigned long long)paddr, dir);
3645 3646 3647
	return 0;
}

3648 3649 3650
static dma_addr_t intel_map_page(struct device *dev, struct page *page,
				 unsigned long offset, size_t size,
				 enum dma_data_direction dir,
3651
				 unsigned long attrs)
3652
{
3653
	return __intel_map_single(dev, page_to_phys(page) + offset, size,
3654
				  dir, *dev->dma_mask);
3655 3656
}

3657
static void intel_unmap(struct device *dev, dma_addr_t dev_addr, size_t size)
3658
{
3659
	struct dmar_domain *domain;
3660
	unsigned long start_pfn, last_pfn;
3661
	unsigned long nrpages;
3662
	unsigned long iova_pfn;
3663
	struct intel_iommu *iommu;
3664
	struct page *freelist;
3665

3666
	if (iommu_no_mapping(dev))
3667
		return;
3668

3669
	domain = find_domain(dev);
3670 3671
	BUG_ON(!domain);

3672 3673
	iommu = domain_get_iommu(domain);

3674
	iova_pfn = IOVA_PFN(dev_addr);
3675

3676
	nrpages = aligned_nrpages(dev_addr, size);
3677
	start_pfn = mm_to_dma_pfn(iova_pfn);
3678
	last_pfn = start_pfn + nrpages - 1;
3679

3680
	pr_debug("Device %s unmapping: pfn %lx-%lx\n",
3681
		 dev_name(dev), start_pfn, last_pfn);
3682

3683
	freelist = domain_unmap(domain, start_pfn, last_pfn);
3684

M
mark gross 已提交
3685
	if (intel_iommu_strict) {
3686
		iommu_flush_iotlb_psi(iommu, domain, start_pfn,
3687
				      nrpages, !freelist, 0);
M
mark gross 已提交
3688
		/* free iova */
3689
		free_iova_fast(&domain->iovad, iova_pfn, dma_to_mm_pfn(nrpages));
3690
		dma_free_pagelist(freelist);
M
mark gross 已提交
3691
	} else {
3692 3693
		queue_iova(&domain->iovad, iova_pfn, nrpages,
			   (unsigned long)freelist);
M
mark gross 已提交
3694 3695 3696 3697 3698
		/*
		 * queue up the release of the unmap to save the 1/6th of the
		 * cpu used up by the iotlb flush operation...
		 */
	}
3699 3700
}

3701 3702
static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
			     size_t size, enum dma_data_direction dir,
3703
			     unsigned long attrs)
3704
{
3705
	intel_unmap(dev, dev_addr, size);
3706 3707
}

3708
static void *intel_alloc_coherent(struct device *dev, size_t size,
3709
				  dma_addr_t *dma_handle, gfp_t flags,
3710
				  unsigned long attrs)
3711
{
A
Akinobu Mita 已提交
3712
	struct page *page = NULL;
3713 3714
	int order;

F
Fenghua Yu 已提交
3715
	size = PAGE_ALIGN(size);
3716
	order = get_order(size);
3717

3718
	if (!iommu_no_mapping(dev))
3719
		flags &= ~(GFP_DMA | GFP_DMA32);
3720 3721
	else if (dev->coherent_dma_mask < dma_get_required_mask(dev)) {
		if (dev->coherent_dma_mask < DMA_BIT_MASK(32))
3722 3723 3724 3725
			flags |= GFP_DMA;
		else
			flags |= GFP_DMA32;
	}
3726

3727
	if (gfpflags_allow_blocking(flags)) {
A
Akinobu Mita 已提交
3728 3729
		unsigned int count = size >> PAGE_SHIFT;

3730
		page = dma_alloc_from_contiguous(dev, count, order, flags);
A
Akinobu Mita 已提交
3731 3732 3733 3734 3735 3736 3737 3738 3739 3740
		if (page && iommu_no_mapping(dev) &&
		    page_to_phys(page) + size > dev->coherent_dma_mask) {
			dma_release_from_contiguous(dev, page, count);
			page = NULL;
		}
	}

	if (!page)
		page = alloc_pages(flags, order);
	if (!page)
3741
		return NULL;
A
Akinobu Mita 已提交
3742
	memset(page_address(page), 0, size);
3743

A
Akinobu Mita 已提交
3744
	*dma_handle = __intel_map_single(dev, page_to_phys(page), size,
3745
					 DMA_BIDIRECTIONAL,
3746
					 dev->coherent_dma_mask);
3747
	if (*dma_handle)
A
Akinobu Mita 已提交
3748 3749 3750 3751
		return page_address(page);
	if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
		__free_pages(page, order);

3752 3753 3754
	return NULL;
}

3755
static void intel_free_coherent(struct device *dev, size_t size, void *vaddr,
3756
				dma_addr_t dma_handle, unsigned long attrs)
3757 3758
{
	int order;
A
Akinobu Mita 已提交
3759
	struct page *page = virt_to_page(vaddr);
3760

F
Fenghua Yu 已提交
3761
	size = PAGE_ALIGN(size);
3762 3763
	order = get_order(size);

3764
	intel_unmap(dev, dma_handle, size);
A
Akinobu Mita 已提交
3765 3766
	if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
		__free_pages(page, order);
3767 3768
}

3769
static void intel_unmap_sg(struct device *dev, struct scatterlist *sglist,
3770
			   int nelems, enum dma_data_direction dir,
3771
			   unsigned long attrs)
3772
{
3773 3774 3775 3776 3777 3778 3779 3780 3781 3782
	dma_addr_t startaddr = sg_dma_address(sglist) & PAGE_MASK;
	unsigned long nrpages = 0;
	struct scatterlist *sg;
	int i;

	for_each_sg(sglist, sg, nelems, i) {
		nrpages += aligned_nrpages(sg_dma_address(sg), sg_dma_len(sg));
	}

	intel_unmap(dev, startaddr, nrpages << VTD_PAGE_SHIFT);
3783 3784 3785
}

static int intel_nontranslate_map_sg(struct device *hddev,
F
FUJITA Tomonori 已提交
3786
	struct scatterlist *sglist, int nelems, int dir)
3787 3788
{
	int i;
F
FUJITA Tomonori 已提交
3789
	struct scatterlist *sg;
3790

F
FUJITA Tomonori 已提交
3791
	for_each_sg(sglist, sg, nelems, i) {
F
FUJITA Tomonori 已提交
3792
		BUG_ON(!sg_page(sg));
D
Dan Williams 已提交
3793
		sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
F
FUJITA Tomonori 已提交
3794
		sg->dma_length = sg->length;
3795 3796 3797 3798
	}
	return nelems;
}

3799
static int intel_map_sg(struct device *dev, struct scatterlist *sglist, int nelems,
3800
			enum dma_data_direction dir, unsigned long attrs)
3801 3802 3803
{
	int i;
	struct dmar_domain *domain;
3804 3805
	size_t size = 0;
	int prot = 0;
3806
	unsigned long iova_pfn;
3807
	int ret;
F
FUJITA Tomonori 已提交
3808
	struct scatterlist *sg;
3809
	unsigned long start_vpfn;
3810
	struct intel_iommu *iommu;
3811 3812

	BUG_ON(dir == DMA_NONE);
3813 3814
	if (iommu_no_mapping(dev))
		return intel_nontranslate_map_sg(dev, sglist, nelems, dir);
3815

3816
	domain = get_valid_domain_for_dev(dev);
3817 3818 3819
	if (!domain)
		return 0;

3820 3821
	iommu = domain_get_iommu(domain);

3822
	for_each_sg(sglist, sg, nelems, i)
3823
		size += aligned_nrpages(sg->offset, sg->length);
3824

3825
	iova_pfn = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size),
3826
				*dev->dma_mask);
3827
	if (!iova_pfn) {
F
FUJITA Tomonori 已提交
3828
		sglist->dma_length = 0;
3829 3830 3831 3832 3833 3834 3835 3836
		return 0;
	}

	/*
	 * Check if DMAR supports zero-length reads on write only
	 * mappings..
	 */
	if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
3837
			!cap_zlr(iommu->cap))
3838 3839 3840 3841
		prot |= DMA_PTE_READ;
	if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
		prot |= DMA_PTE_WRITE;

3842
	start_vpfn = mm_to_dma_pfn(iova_pfn);
3843

3844
	ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
3845 3846
	if (unlikely(ret)) {
		dma_pte_free_pagetable(domain, start_vpfn,
3847 3848
				       start_vpfn + size - 1,
				       agaw_to_level(domain->agaw) + 1);
3849
		free_iova_fast(&domain->iovad, iova_pfn, dma_to_mm_pfn(size));
3850
		return 0;
3851 3852
	}

3853 3854
	/* it's a non-present to present mapping. Only flush if caching mode */
	if (cap_caching_mode(iommu->cap))
3855
		iommu_flush_iotlb_psi(iommu, domain, start_vpfn, size, 0, 1);
3856
	else
3857
		iommu_flush_write_buffer(iommu);
3858

3859 3860 3861
	return nelems;
}

3862 3863 3864 3865 3866
static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
{
	return !dma_addr;
}

3867
const struct dma_map_ops intel_dma_ops = {
3868 3869
	.alloc = intel_alloc_coherent,
	.free = intel_free_coherent,
3870 3871
	.map_sg = intel_map_sg,
	.unmap_sg = intel_unmap_sg,
3872 3873
	.map_page = intel_map_page,
	.unmap_page = intel_unmap_page,
3874
	.mapping_error = intel_mapping_error,
3875 3876 3877
#ifdef CONFIG_X86
	.dma_supported = x86_dma_supported,
#endif
3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890
};

static inline int iommu_domain_cache_init(void)
{
	int ret = 0;

	iommu_domain_cache = kmem_cache_create("iommu_domain",
					 sizeof(struct dmar_domain),
					 0,
					 SLAB_HWCACHE_ALIGN,

					 NULL);
	if (!iommu_domain_cache) {
J
Joerg Roedel 已提交
3891
		pr_err("Couldn't create iommu_domain cache\n");
3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907
		ret = -ENOMEM;
	}

	return ret;
}

static inline int iommu_devinfo_cache_init(void)
{
	int ret = 0;

	iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
					 sizeof(struct device_domain_info),
					 0,
					 SLAB_HWCACHE_ALIGN,
					 NULL);
	if (!iommu_devinfo_cache) {
J
Joerg Roedel 已提交
3908
		pr_err("Couldn't create devinfo cache\n");
3909 3910 3911 3912 3913 3914 3915 3916 3917
		ret = -ENOMEM;
	}

	return ret;
}

static int __init iommu_init_mempool(void)
{
	int ret;
3918
	ret = iova_cache_get();
3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931
	if (ret)
		return ret;

	ret = iommu_domain_cache_init();
	if (ret)
		goto domain_error;

	ret = iommu_devinfo_cache_init();
	if (!ret)
		return ret;

	kmem_cache_destroy(iommu_domain_cache);
domain_error:
3932
	iova_cache_put();
3933 3934 3935 3936 3937 3938 3939 3940

	return -ENOMEM;
}

static void __init iommu_exit_mempool(void)
{
	kmem_cache_destroy(iommu_devinfo_cache);
	kmem_cache_destroy(iommu_domain_cache);
3941
	iova_cache_put();
3942 3943
}

3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971
static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
{
	struct dmar_drhd_unit *drhd;
	u32 vtbar;
	int rc;

	/* We know that this device on this chipset has its own IOMMU.
	 * If we find it under a different IOMMU, then the BIOS is lying
	 * to us. Hope that the IOMMU for this device is actually
	 * disabled, and it needs no translation...
	 */
	rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
	if (rc) {
		/* "can't" happen */
		dev_info(&pdev->dev, "failed to run vt-d quirk\n");
		return;
	}
	vtbar &= 0xffff0000;

	/* we know that the this iommu should be at offset 0xa000 from vtbar */
	drhd = dmar_find_matched_drhd_unit(pdev);
	if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
			    TAINT_FIRMWARE_WORKAROUND,
			    "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
		pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
}
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);

3972 3973 3974
static void __init init_no_remapping_devices(void)
{
	struct dmar_drhd_unit *drhd;
3975
	struct device *dev;
3976
	int i;
3977 3978 3979

	for_each_drhd_unit(drhd) {
		if (!drhd->include_all) {
3980 3981 3982
			for_each_active_dev_scope(drhd->devices,
						  drhd->devices_cnt, i, dev)
				break;
3983
			/* ignore DMAR unit if no devices exist */
3984 3985 3986 3987 3988
			if (i == drhd->devices_cnt)
				drhd->ignored = 1;
		}
	}

3989 3990
	for_each_active_drhd_unit(drhd) {
		if (drhd->include_all)
3991 3992
			continue;

3993 3994
		for_each_active_dev_scope(drhd->devices,
					  drhd->devices_cnt, i, dev)
3995
			if (!dev_is_pci(dev) || !IS_GFX_DEVICE(to_pci_dev(dev)))
3996 3997 3998 3999
				break;
		if (i < drhd->devices_cnt)
			continue;

4000 4001 4002 4003 4004 4005
		/* This IOMMU has *only* gfx devices. Either bypass it or
		   set the gfx_mapped flag, as appropriate */
		if (dmar_map_gfx) {
			intel_iommu_gfx_mapped = 1;
		} else {
			drhd->ignored = 1;
4006 4007
			for_each_active_dev_scope(drhd->devices,
						  drhd->devices_cnt, i, dev)
4008
				dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
4009 4010 4011 4012
		}
	}
}

4013 4014 4015 4016 4017 4018 4019 4020 4021 4022
#ifdef CONFIG_SUSPEND
static int init_iommu_hw(void)
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu = NULL;

	for_each_active_iommu(iommu, drhd)
		if (iommu->qi)
			dmar_reenable_qi(iommu);

4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033
	for_each_iommu(iommu, drhd) {
		if (drhd->ignored) {
			/*
			 * we always have to disable PMRs or DMA may fail on
			 * this device
			 */
			if (force_on)
				iommu_disable_protect_mem_regions(iommu);
			continue;
		}
	
4034 4035 4036 4037 4038
		iommu_flush_write_buffer(iommu);

		iommu_set_root_entry(iommu);

		iommu->flush.flush_context(iommu, 0, 0, 0,
4039
					   DMA_CCMD_GLOBAL_INVL);
4040 4041
		iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
		iommu_enable_translation(iommu);
4042
		iommu_disable_protect_mem_regions(iommu);
4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054
	}

	return 0;
}

static void iommu_flush_all(void)
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;

	for_each_active_iommu(iommu, drhd) {
		iommu->flush.flush_context(iommu, 0, 0, 0,
4055
					   DMA_CCMD_GLOBAL_INVL);
4056
		iommu->flush.flush_iotlb(iommu, 0, 0, 0,
4057
					 DMA_TLB_GLOBAL_FLUSH);
4058 4059 4060
	}
}

4061
static int iommu_suspend(void)
4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu = NULL;
	unsigned long flag;

	for_each_active_iommu(iommu, drhd) {
		iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
						 GFP_ATOMIC);
		if (!iommu->iommu_state)
			goto nomem;
	}

	iommu_flush_all();

	for_each_active_iommu(iommu, drhd) {
		iommu_disable_translation(iommu);

4079
		raw_spin_lock_irqsave(&iommu->register_lock, flag);
4080 4081 4082 4083 4084 4085 4086 4087 4088 4089

		iommu->iommu_state[SR_DMAR_FECTL_REG] =
			readl(iommu->reg + DMAR_FECTL_REG);
		iommu->iommu_state[SR_DMAR_FEDATA_REG] =
			readl(iommu->reg + DMAR_FEDATA_REG);
		iommu->iommu_state[SR_DMAR_FEADDR_REG] =
			readl(iommu->reg + DMAR_FEADDR_REG);
		iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
			readl(iommu->reg + DMAR_FEUADDR_REG);

4090
		raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
4091 4092 4093 4094 4095 4096 4097 4098 4099 4100
	}
	return 0;

nomem:
	for_each_active_iommu(iommu, drhd)
		kfree(iommu->iommu_state);

	return -ENOMEM;
}

4101
static void iommu_resume(void)
4102 4103 4104 4105 4106 4107
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu = NULL;
	unsigned long flag;

	if (init_iommu_hw()) {
4108 4109 4110 4111
		if (force_on)
			panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
		else
			WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
4112
		return;
4113 4114 4115 4116
	}

	for_each_active_iommu(iommu, drhd) {

4117
		raw_spin_lock_irqsave(&iommu->register_lock, flag);
4118 4119 4120 4121 4122 4123 4124 4125 4126 4127

		writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
			iommu->reg + DMAR_FECTL_REG);
		writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
			iommu->reg + DMAR_FEDATA_REG);
		writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
			iommu->reg + DMAR_FEADDR_REG);
		writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
			iommu->reg + DMAR_FEUADDR_REG);

4128
		raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
4129 4130 4131 4132 4133 4134
	}

	for_each_active_iommu(iommu, drhd)
		kfree(iommu->iommu_state);
}

4135
static struct syscore_ops iommu_syscore_ops = {
4136 4137 4138 4139
	.resume		= iommu_resume,
	.suspend	= iommu_suspend,
};

4140
static void __init init_iommu_pm_ops(void)
4141
{
4142
	register_syscore_ops(&iommu_syscore_ops);
4143 4144 4145
}

#else
4146
static inline void init_iommu_pm_ops(void) {}
4147 4148
#endif	/* CONFIG_PM */

4149

4150
int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg)
4151 4152
{
	struct acpi_dmar_reserved_memory *rmrr;
4153
	int prot = DMA_PTE_READ|DMA_PTE_WRITE;
4154
	struct dmar_rmrr_unit *rmrru;
4155
	size_t length;
4156 4157 4158

	rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
	if (!rmrru)
4159
		goto out;
4160 4161 4162 4163 4164

	rmrru->hdr = header;
	rmrr = (struct acpi_dmar_reserved_memory *)header;
	rmrru->base_address = rmrr->base_address;
	rmrru->end_address = rmrr->end_address;
4165 4166 4167 4168 4169 4170 4171

	length = rmrr->end_address - rmrr->base_address + 1;
	rmrru->resv = iommu_alloc_resv_region(rmrr->base_address, length, prot,
					      IOMMU_RESV_DIRECT);
	if (!rmrru->resv)
		goto free_rmrru;

4172 4173 4174
	rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1),
				((void *)rmrr) + rmrr->header.length,
				&rmrru->devices_cnt);
4175 4176
	if (rmrru->devices_cnt && rmrru->devices == NULL)
		goto free_all;
4177

4178
	list_add(&rmrru->list, &dmar_rmrr_units);
4179

4180
	return 0;
4181 4182 4183 4184 4185 4186
free_all:
	kfree(rmrru->resv);
free_rmrru:
	kfree(rmrru);
out:
	return -ENOMEM;
4187 4188
}

4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207
static struct dmar_atsr_unit *dmar_find_atsr(struct acpi_dmar_atsr *atsr)
{
	struct dmar_atsr_unit *atsru;
	struct acpi_dmar_atsr *tmp;

	list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
		tmp = (struct acpi_dmar_atsr *)atsru->hdr;
		if (atsr->segment != tmp->segment)
			continue;
		if (atsr->header.length != tmp->header.length)
			continue;
		if (memcmp(atsr, tmp, atsr->header.length) == 0)
			return atsru;
	}

	return NULL;
}

int dmar_parse_one_atsr(struct acpi_dmar_header *hdr, void *arg)
4208 4209 4210 4211
{
	struct acpi_dmar_atsr *atsr;
	struct dmar_atsr_unit *atsru;

4212
	if (system_state >= SYSTEM_RUNNING && !intel_iommu_enabled)
4213 4214
		return 0;

4215
	atsr = container_of(hdr, struct acpi_dmar_atsr, header);
4216 4217 4218 4219 4220
	atsru = dmar_find_atsr(atsr);
	if (atsru)
		return 0;

	atsru = kzalloc(sizeof(*atsru) + hdr->length, GFP_KERNEL);
4221 4222 4223
	if (!atsru)
		return -ENOMEM;

4224 4225 4226 4227 4228 4229 4230
	/*
	 * If memory is allocated from slab by ACPI _DSM method, we need to
	 * copy the memory content because the memory buffer will be freed
	 * on return.
	 */
	atsru->hdr = (void *)(atsru + 1);
	memcpy(atsru->hdr, hdr, hdr->length);
4231
	atsru->include_all = atsr->flags & 0x1;
4232 4233 4234 4235 4236 4237 4238 4239 4240
	if (!atsru->include_all) {
		atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1),
				(void *)atsr + atsr->header.length,
				&atsru->devices_cnt);
		if (atsru->devices_cnt && atsru->devices == NULL) {
			kfree(atsru);
			return -ENOMEM;
		}
	}
4241

4242
	list_add_rcu(&atsru->list, &dmar_atsr_units);
4243 4244 4245 4246

	return 0;
}

4247 4248 4249 4250 4251 4252
static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru)
{
	dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt);
	kfree(atsru);
}

4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280
int dmar_release_one_atsr(struct acpi_dmar_header *hdr, void *arg)
{
	struct acpi_dmar_atsr *atsr;
	struct dmar_atsr_unit *atsru;

	atsr = container_of(hdr, struct acpi_dmar_atsr, header);
	atsru = dmar_find_atsr(atsr);
	if (atsru) {
		list_del_rcu(&atsru->list);
		synchronize_rcu();
		intel_iommu_free_atsr(atsru);
	}

	return 0;
}

int dmar_check_one_atsr(struct acpi_dmar_header *hdr, void *arg)
{
	int i;
	struct device *dev;
	struct acpi_dmar_atsr *atsr;
	struct dmar_atsr_unit *atsru;

	atsr = container_of(hdr, struct acpi_dmar_atsr, header);
	atsru = dmar_find_atsr(atsr);
	if (!atsru)
		return 0;

4281
	if (!atsru->include_all && atsru->devices && atsru->devices_cnt) {
4282 4283 4284
		for_each_active_dev_scope(atsru->devices, atsru->devices_cnt,
					  i, dev)
			return -EBUSY;
4285
	}
4286 4287 4288 4289

	return 0;
}

4290 4291 4292 4293 4294 4295 4296 4297 4298
static int intel_iommu_add(struct dmar_drhd_unit *dmaru)
{
	int sp, ret = 0;
	struct intel_iommu *iommu = dmaru->iommu;

	if (g_iommus[iommu->seq_id])
		return 0;

	if (hw_pass_through && !ecap_pass_through(iommu->ecap)) {
J
Joerg Roedel 已提交
4299
		pr_warn("%s: Doesn't support hardware pass through.\n",
4300 4301 4302 4303 4304
			iommu->name);
		return -ENXIO;
	}
	if (!ecap_sc_support(iommu->ecap) &&
	    domain_update_iommu_snooping(iommu)) {
J
Joerg Roedel 已提交
4305
		pr_warn("%s: Doesn't support snooping.\n",
4306 4307 4308 4309 4310
			iommu->name);
		return -ENXIO;
	}
	sp = domain_update_iommu_superpage(iommu) - 1;
	if (sp >= 0 && !(cap_super_page_val(iommu->cap) & (1 << sp))) {
J
Joerg Roedel 已提交
4311
		pr_warn("%s: Doesn't support large page.\n",
4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328
			iommu->name);
		return -ENXIO;
	}

	/*
	 * Disable translation if already enabled prior to OS handover.
	 */
	if (iommu->gcmd & DMA_GCMD_TE)
		iommu_disable_translation(iommu);

	g_iommus[iommu->seq_id] = iommu;
	ret = iommu_init_domains(iommu);
	if (ret == 0)
		ret = iommu_alloc_root_entry(iommu);
	if (ret)
		goto out;

4329 4330 4331 4332 4333
#ifdef CONFIG_INTEL_IOMMU_SVM
	if (pasid_enabled(iommu))
		intel_svm_alloc_pasid_tables(iommu);
#endif

4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344
	if (dmaru->ignored) {
		/*
		 * we always have to disable PMRs or DMA may fail on this device
		 */
		if (force_on)
			iommu_disable_protect_mem_regions(iommu);
		return 0;
	}

	intel_iommu_init_qi(iommu);
	iommu_flush_write_buffer(iommu);
4345 4346 4347 4348 4349 4350 4351 4352

#ifdef CONFIG_INTEL_IOMMU_SVM
	if (pasid_enabled(iommu) && ecap_prs(iommu->ecap)) {
		ret = intel_svm_enable_prq(iommu);
		if (ret)
			goto disable_iommu;
	}
#endif
4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365 4366 4367 4368 4369 4370 4371
	ret = dmar_set_interrupt(iommu);
	if (ret)
		goto disable_iommu;

	iommu_set_root_entry(iommu);
	iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
	iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
	iommu_enable_translation(iommu);

	iommu_disable_protect_mem_regions(iommu);
	return 0;

disable_iommu:
	disable_dmar_iommu(iommu);
out:
	free_dmar_iommu(iommu);
	return ret;
}

4372 4373
int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
{
4374 4375 4376 4377 4378 4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389
	int ret = 0;
	struct intel_iommu *iommu = dmaru->iommu;

	if (!intel_iommu_enabled)
		return 0;
	if (iommu == NULL)
		return -EINVAL;

	if (insert) {
		ret = intel_iommu_add(dmaru);
	} else {
		disable_dmar_iommu(iommu);
		free_dmar_iommu(iommu);
	}

	return ret;
4390 4391
}

4392 4393 4394 4395 4396 4397 4398 4399
static void intel_iommu_free_dmars(void)
{
	struct dmar_rmrr_unit *rmrru, *rmrr_n;
	struct dmar_atsr_unit *atsru, *atsr_n;

	list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) {
		list_del(&rmrru->list);
		dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt);
4400
		kfree(rmrru->resv);
4401
		kfree(rmrru);
4402 4403
	}

4404 4405 4406 4407
	list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) {
		list_del(&atsru->list);
		intel_iommu_free_atsr(atsru);
	}
4408 4409 4410 4411
}

int dmar_find_matched_atsr_unit(struct pci_dev *dev)
{
4412
	int i, ret = 1;
4413
	struct pci_bus *bus;
4414 4415
	struct pci_dev *bridge = NULL;
	struct device *tmp;
4416 4417 4418 4419 4420
	struct acpi_dmar_atsr *atsr;
	struct dmar_atsr_unit *atsru;

	dev = pci_physfn(dev);
	for (bus = dev->bus; bus; bus = bus->parent) {
4421
		bridge = bus->self;
4422 4423 4424 4425 4426
		/* If it's an integrated device, allow ATS */
		if (!bridge)
			return 1;
		/* Connected via non-PCIe: no ATS */
		if (!pci_is_pcie(bridge) ||
4427
		    pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
4428
			return 0;
4429
		/* If we found the root port, look it up in the ATSR */
4430
		if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT)
4431 4432 4433
			break;
	}

4434
	rcu_read_lock();
4435 4436 4437 4438 4439
	list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
		atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
		if (atsr->segment != pci_domain_nr(dev->bus))
			continue;

4440
		for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp)
4441
			if (tmp == &bridge->dev)
4442
				goto out;
4443 4444

		if (atsru->include_all)
4445
			goto out;
4446
	}
4447 4448
	ret = 0;
out:
4449
	rcu_read_unlock();
4450

4451
	return ret;
4452 4453
}

4454 4455 4456 4457 4458 4459 4460 4461
int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
{
	int ret = 0;
	struct dmar_rmrr_unit *rmrru;
	struct dmar_atsr_unit *atsru;
	struct acpi_dmar_atsr *atsr;
	struct acpi_dmar_reserved_memory *rmrr;

4462
	if (!intel_iommu_enabled && system_state >= SYSTEM_RUNNING)
4463 4464 4465 4466 4467 4468 4469 4470 4471 4472
		return 0;

	list_for_each_entry(rmrru, &dmar_rmrr_units, list) {
		rmrr = container_of(rmrru->hdr,
				    struct acpi_dmar_reserved_memory, header);
		if (info->event == BUS_NOTIFY_ADD_DEVICE) {
			ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1),
				((void *)rmrr) + rmrr->header.length,
				rmrr->segment, rmrru->devices,
				rmrru->devices_cnt);
4473
			if(ret < 0)
4474
				return ret;
4475
		} else if (info->event == BUS_NOTIFY_REMOVED_DEVICE) {
4476 4477
			dmar_remove_dev_scope(info, rmrr->segment,
				rmrru->devices, rmrru->devices_cnt);
4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494
		}
	}

	list_for_each_entry(atsru, &dmar_atsr_units, list) {
		if (atsru->include_all)
			continue;

		atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
		if (info->event == BUS_NOTIFY_ADD_DEVICE) {
			ret = dmar_insert_dev_scope(info, (void *)(atsr + 1),
					(void *)atsr + atsr->header.length,
					atsr->segment, atsru->devices,
					atsru->devices_cnt);
			if (ret > 0)
				break;
			else if(ret < 0)
				return ret;
4495
		} else if (info->event == BUS_NOTIFY_REMOVED_DEVICE) {
4496 4497 4498 4499 4500 4501 4502 4503 4504
			if (dmar_remove_dev_scope(info, atsr->segment,
					atsru->devices, atsru->devices_cnt))
				break;
		}
	}

	return 0;
}

F
Fenghua Yu 已提交
4505 4506 4507 4508 4509 4510 4511 4512 4513 4514 4515 4516
/*
 * Here we only respond to action of unbound device from driver.
 *
 * Added device is not attached to its DMAR domain here yet. That will happen
 * when mapping the device to iova.
 */
static int device_notifier(struct notifier_block *nb,
				  unsigned long action, void *data)
{
	struct device *dev = data;
	struct dmar_domain *domain;

4517
	if (iommu_dummy(dev))
4518 4519
		return 0;

4520
	if (action != BUS_NOTIFY_REMOVED_DEVICE)
4521 4522
		return 0;

4523
	domain = find_domain(dev);
F
Fenghua Yu 已提交
4524 4525 4526
	if (!domain)
		return 0;

4527
	dmar_remove_one_dev_info(domain, dev);
4528
	if (!domain_type_is_vm_or_si(domain) && list_empty(&domain->devices))
4529
		domain_exit(domain);
4530

F
Fenghua Yu 已提交
4531 4532 4533 4534 4535 4536 4537
	return 0;
}

static struct notifier_block device_nb = {
	.notifier_call = device_notifier,
};

4538 4539 4540 4541 4542 4543 4544 4545 4546 4547 4548 4549
static int intel_iommu_memory_notifier(struct notifier_block *nb,
				       unsigned long val, void *v)
{
	struct memory_notify *mhp = v;
	unsigned long long start, end;
	unsigned long start_vpfn, last_vpfn;

	switch (val) {
	case MEM_GOING_ONLINE:
		start = mhp->start_pfn << PAGE_SHIFT;
		end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1;
		if (iommu_domain_identity_map(si_domain, start, end)) {
J
Joerg Roedel 已提交
4550
			pr_warn("Failed to build identity map for [%llx-%llx]\n",
4551 4552 4553 4554 4555 4556 4557 4558 4559 4560 4561 4562 4563
				start, end);
			return NOTIFY_BAD;
		}
		break;

	case MEM_OFFLINE:
	case MEM_CANCEL_ONLINE:
		start_vpfn = mm_to_dma_pfn(mhp->start_pfn);
		last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1);
		while (start_vpfn <= last_vpfn) {
			struct iova *iova;
			struct dmar_drhd_unit *drhd;
			struct intel_iommu *iommu;
4564
			struct page *freelist;
4565 4566 4567

			iova = find_iova(&si_domain->iovad, start_vpfn);
			if (iova == NULL) {
J
Joerg Roedel 已提交
4568
				pr_debug("Failed get IOVA for PFN %lx\n",
4569 4570 4571 4572 4573 4574 4575
					 start_vpfn);
				break;
			}

			iova = split_and_remove_iova(&si_domain->iovad, iova,
						     start_vpfn, last_vpfn);
			if (iova == NULL) {
J
Joerg Roedel 已提交
4576
				pr_warn("Failed to split IOVA PFN [%lx-%lx]\n",
4577 4578 4579 4580
					start_vpfn, last_vpfn);
				return NOTIFY_BAD;
			}

4581 4582 4583
			freelist = domain_unmap(si_domain, iova->pfn_lo,
					       iova->pfn_hi);

4584 4585
			rcu_read_lock();
			for_each_active_iommu(iommu, drhd)
4586
				iommu_flush_iotlb_psi(iommu, si_domain,
4587
					iova->pfn_lo, iova_size(iova),
4588
					!freelist, 0);
4589
			rcu_read_unlock();
4590
			dma_free_pagelist(freelist);
4591 4592 4593 4594 4595 4596 4597 4598 4599 4600 4601 4602 4603 4604 4605

			start_vpfn = iova->pfn_hi + 1;
			free_iova_mem(iova);
		}
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block intel_iommu_memory_nb = {
	.notifier_call = intel_iommu_memory_notifier,
	.priority = 0
};

4606 4607 4608 4609 4610 4611 4612
static void free_all_cpu_cached_iovas(unsigned int cpu)
{
	int i;

	for (i = 0; i < g_num_of_iommus; i++) {
		struct intel_iommu *iommu = g_iommus[i];
		struct dmar_domain *domain;
4613
		int did;
4614 4615 4616 4617

		if (!iommu)
			continue;

4618
		for (did = 0; did < cap_ndoms(iommu->cap); did++) {
4619
			domain = get_iommu_domain(iommu, (u16)did);
4620 4621 4622 4623 4624 4625 4626 4627

			if (!domain)
				continue;
			free_cpu_cached_iovas(cpu, &domain->iovad);
		}
	}
}

4628
static int intel_iommu_cpu_dead(unsigned int cpu)
4629
{
4630 4631
	free_all_cpu_cached_iovas(cpu);
	return 0;
4632 4633
}

4634 4635 4636 4637 4638 4639 4640 4641 4642
static void intel_disable_iommus(void)
{
	struct intel_iommu *iommu = NULL;
	struct dmar_drhd_unit *drhd;

	for_each_iommu(iommu, drhd)
		iommu_disable_translation(iommu);
}

4643 4644
static inline struct intel_iommu *dev_to_intel_iommu(struct device *dev)
{
4645 4646 4647
	struct iommu_device *iommu_dev = dev_to_iommu_device(dev);

	return container_of(iommu_dev, struct intel_iommu, iommu);
4648 4649
}

4650 4651 4652 4653
static ssize_t intel_iommu_show_version(struct device *dev,
					struct device_attribute *attr,
					char *buf)
{
4654
	struct intel_iommu *iommu = dev_to_intel_iommu(dev);
4655 4656 4657 4658 4659 4660 4661 4662 4663 4664
	u32 ver = readl(iommu->reg + DMAR_VER_REG);
	return sprintf(buf, "%d:%d\n",
		       DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver));
}
static DEVICE_ATTR(version, S_IRUGO, intel_iommu_show_version, NULL);

static ssize_t intel_iommu_show_address(struct device *dev,
					struct device_attribute *attr,
					char *buf)
{
4665
	struct intel_iommu *iommu = dev_to_intel_iommu(dev);
4666 4667 4668 4669 4670 4671 4672 4673
	return sprintf(buf, "%llx\n", iommu->reg_phys);
}
static DEVICE_ATTR(address, S_IRUGO, intel_iommu_show_address, NULL);

static ssize_t intel_iommu_show_cap(struct device *dev,
				    struct device_attribute *attr,
				    char *buf)
{
4674
	struct intel_iommu *iommu = dev_to_intel_iommu(dev);
4675 4676 4677 4678 4679 4680 4681 4682
	return sprintf(buf, "%llx\n", iommu->cap);
}
static DEVICE_ATTR(cap, S_IRUGO, intel_iommu_show_cap, NULL);

static ssize_t intel_iommu_show_ecap(struct device *dev,
				    struct device_attribute *attr,
				    char *buf)
{
4683
	struct intel_iommu *iommu = dev_to_intel_iommu(dev);
4684 4685 4686 4687
	return sprintf(buf, "%llx\n", iommu->ecap);
}
static DEVICE_ATTR(ecap, S_IRUGO, intel_iommu_show_ecap, NULL);

4688 4689 4690 4691
static ssize_t intel_iommu_show_ndoms(struct device *dev,
				      struct device_attribute *attr,
				      char *buf)
{
4692
	struct intel_iommu *iommu = dev_to_intel_iommu(dev);
4693 4694 4695 4696 4697 4698 4699 4700
	return sprintf(buf, "%ld\n", cap_ndoms(iommu->cap));
}
static DEVICE_ATTR(domains_supported, S_IRUGO, intel_iommu_show_ndoms, NULL);

static ssize_t intel_iommu_show_ndoms_used(struct device *dev,
					   struct device_attribute *attr,
					   char *buf)
{
4701
	struct intel_iommu *iommu = dev_to_intel_iommu(dev);
4702 4703 4704 4705 4706
	return sprintf(buf, "%d\n", bitmap_weight(iommu->domain_ids,
						  cap_ndoms(iommu->cap)));
}
static DEVICE_ATTR(domains_used, S_IRUGO, intel_iommu_show_ndoms_used, NULL);

4707 4708 4709 4710 4711
static struct attribute *intel_iommu_attrs[] = {
	&dev_attr_version.attr,
	&dev_attr_address.attr,
	&dev_attr_cap.attr,
	&dev_attr_ecap.attr,
4712 4713
	&dev_attr_domains_supported.attr,
	&dev_attr_domains_used.attr,
4714 4715 4716 4717 4718 4719 4720 4721 4722 4723 4724 4725 4726
	NULL,
};

static struct attribute_group intel_iommu_group = {
	.name = "intel-iommu",
	.attrs = intel_iommu_attrs,
};

const struct attribute_group *intel_iommu_groups[] = {
	&intel_iommu_group,
	NULL,
};

4727 4728
int __init intel_iommu_init(void)
{
4729
	int ret = -ENODEV;
4730
	struct dmar_drhd_unit *drhd;
4731
	struct intel_iommu *iommu;
4732

4733 4734 4735
	/* VT-d is required for a TXT/tboot launch, so enforce that */
	force_on = tboot_force_iommu();

4736 4737 4738 4739 4740 4741 4742
	if (iommu_init_mempool()) {
		if (force_on)
			panic("tboot: Failed to initialize iommu memory\n");
		return -ENOMEM;
	}

	down_write(&dmar_global_lock);
4743 4744 4745
	if (dmar_table_init()) {
		if (force_on)
			panic("tboot: Failed to initialize DMAR table\n");
4746
		goto out_free_dmar;
4747
	}
4748

4749
	if (dmar_dev_scope_init() < 0) {
4750 4751
		if (force_on)
			panic("tboot: Failed to initialize DMAR device scope\n");
4752
		goto out_free_dmar;
4753
	}
4754

4755
	if (no_iommu || dmar_disabled) {
4756 4757 4758 4759 4760 4761 4762 4763 4764 4765 4766 4767 4768
		/*
		 * We exit the function here to ensure IOMMU's remapping and
		 * mempool aren't setup, which means that the IOMMU's PMRs
		 * won't be disabled via the call to init_dmars(). So disable
		 * it explicitly here. The PMRs were setup by tboot prior to
		 * calling SENTER, but the kernel is expected to reset/tear
		 * down the PMRs.
		 */
		if (intel_iommu_tboot_noforce) {
			for_each_iommu(iommu, drhd)
				iommu_disable_protect_mem_regions(iommu);
		}

4769 4770 4771 4772 4773 4774
		/*
		 * Make sure the IOMMUs are switched off, even when we
		 * boot into a kexec kernel and the previous kernel left
		 * them enabled
		 */
		intel_disable_iommus();
4775
		goto out_free_dmar;
4776
	}
4777

4778
	if (list_empty(&dmar_rmrr_units))
J
Joerg Roedel 已提交
4779
		pr_info("No RMRR found\n");
4780 4781

	if (list_empty(&dmar_atsr_units))
J
Joerg Roedel 已提交
4782
		pr_info("No ATSR found\n");
4783

4784 4785 4786
	if (dmar_init_reserved_ranges()) {
		if (force_on)
			panic("tboot: Failed to reserve iommu ranges\n");
4787
		goto out_free_reserved_range;
4788
	}
4789 4790 4791

	init_no_remapping_devices();

4792
	ret = init_dmars();
4793
	if (ret) {
4794 4795
		if (force_on)
			panic("tboot: Failed to initialize DMARs\n");
J
Joerg Roedel 已提交
4796
		pr_err("Initialization failed\n");
4797
		goto out_free_reserved_range;
4798
	}
4799
	up_write(&dmar_global_lock);
J
Joerg Roedel 已提交
4800
	pr_info("Intel(R) Virtualization Technology for Directed I/O\n");
4801

4802 4803 4804
#ifdef CONFIG_SWIOTLB
	swiotlb = 0;
#endif
4805
	dma_ops = &intel_dma_ops;
F
Fenghua Yu 已提交
4806

4807
	init_iommu_pm_ops();
4808

4809 4810 4811 4812 4813 4814 4815
	for_each_active_iommu(iommu, drhd) {
		iommu_device_sysfs_add(&iommu->iommu, NULL,
				       intel_iommu_groups,
				       "%s", iommu->name);
		iommu_device_set_ops(&iommu->iommu, &intel_iommu_ops);
		iommu_device_register(&iommu->iommu);
	}
4816

4817
	bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
F
Fenghua Yu 已提交
4818
	bus_register_notifier(&pci_bus_type, &device_nb);
4819 4820
	if (si_domain && !hw_pass_through)
		register_memory_notifier(&intel_iommu_memory_nb);
4821 4822
	cpuhp_setup_state(CPUHP_IOMMU_INTEL_DEAD, "iommu/intel:dead", NULL,
			  intel_iommu_cpu_dead);
4823 4824
	intel_iommu_enabled = 1;

4825
	return 0;
4826 4827 4828 4829 4830

out_free_reserved_range:
	put_iova_domain(&reserved_iova_list);
out_free_dmar:
	intel_iommu_free_dmars();
4831 4832
	up_write(&dmar_global_lock);
	iommu_exit_mempool();
4833
	return ret;
4834
}
4835

4836
static int domain_context_clear_one_cb(struct pci_dev *pdev, u16 alias, void *opaque)
4837 4838 4839
{
	struct intel_iommu *iommu = opaque;

4840
	domain_context_clear_one(iommu, PCI_BUS_NUM(alias), alias & 0xff);
4841 4842 4843 4844 4845 4846 4847 4848 4849
	return 0;
}

/*
 * NB - intel-iommu lacks any sort of reference counting for the users of
 * dependent devices.  If multiple endpoints have intersecting dependent
 * devices, unbinding the driver from any one of them will possibly leave
 * the others unable to operate.
 */
4850
static void domain_context_clear(struct intel_iommu *iommu, struct device *dev)
4851
{
4852
	if (!iommu || !dev || !dev_is_pci(dev))
4853 4854
		return;

4855
	pci_for_each_dma_alias(to_pci_dev(dev), &domain_context_clear_one_cb, iommu);
4856 4857
}

4858
static void __dmar_remove_one_dev_info(struct device_domain_info *info)
4859 4860 4861 4862
{
	struct intel_iommu *iommu;
	unsigned long flags;

4863 4864
	assert_spin_locked(&device_domain_lock);

4865
	if (WARN_ON(!info))
4866 4867
		return;

4868
	iommu = info->iommu;
4869

4870 4871 4872 4873
	if (info->dev) {
		iommu_disable_dev_iotlb(info);
		domain_context_clear(iommu, info->dev);
	}
4874

4875
	unlink_domain_info(info);
4876

4877
	spin_lock_irqsave(&iommu->lock, flags);
4878
	domain_detach_iommu(info->domain, iommu);
4879
	spin_unlock_irqrestore(&iommu->lock, flags);
4880

4881
	free_devinfo_mem(info);
4882 4883
}

4884 4885 4886
static void dmar_remove_one_dev_info(struct dmar_domain *domain,
				     struct device *dev)
{
4887
	struct device_domain_info *info;
4888
	unsigned long flags;
4889

4890
	spin_lock_irqsave(&device_domain_lock, flags);
4891 4892
	info = dev->archdata.iommu;
	__dmar_remove_one_dev_info(info);
4893
	spin_unlock_irqrestore(&device_domain_lock, flags);
4894 4895
}

4896
static int md_domain_init(struct dmar_domain *domain, int guest_width)
4897 4898 4899
{
	int adjust_width;

4900 4901
	init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN,
			DMA_32BIT_PFN);
4902 4903 4904 4905 4906 4907 4908 4909
	domain_reserve_special_ranges(domain);

	/* calculate AGAW */
	domain->gaw = guest_width;
	adjust_width = guestwidth_to_adjustwidth(guest_width);
	domain->agaw = width_to_agaw(adjust_width);

	domain->iommu_coherency = 0;
4910
	domain->iommu_snooping = 0;
4911
	domain->iommu_superpage = 0;
4912
	domain->max_addr = 0;
4913 4914

	/* always allocate the top pgd */
4915
	domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
4916 4917 4918 4919 4920 4921
	if (!domain->pgd)
		return -ENOMEM;
	domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
	return 0;
}

4922
static struct iommu_domain *intel_iommu_domain_alloc(unsigned type)
K
Kay, Allen M 已提交
4923
{
4924
	struct dmar_domain *dmar_domain;
4925 4926 4927 4928
	struct iommu_domain *domain;

	if (type != IOMMU_DOMAIN_UNMANAGED)
		return NULL;
K
Kay, Allen M 已提交
4929

4930
	dmar_domain = alloc_domain(DOMAIN_FLAG_VIRTUAL_MACHINE);
4931
	if (!dmar_domain) {
J
Joerg Roedel 已提交
4932
		pr_err("Can't allocate dmar_domain\n");
4933
		return NULL;
K
Kay, Allen M 已提交
4934
	}
4935
	if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
J
Joerg Roedel 已提交
4936
		pr_err("Domain initialization failed\n");
4937
		domain_exit(dmar_domain);
4938
		return NULL;
K
Kay, Allen M 已提交
4939
	}
4940
	domain_update_iommu_cap(dmar_domain);
4941

4942
	domain = &dmar_domain->domain;
4943 4944 4945 4946
	domain->geometry.aperture_start = 0;
	domain->geometry.aperture_end   = __DOMAIN_MAX_ADDR(dmar_domain->gaw);
	domain->geometry.force_aperture = true;

4947
	return domain;
K
Kay, Allen M 已提交
4948 4949
}

4950
static void intel_iommu_domain_free(struct iommu_domain *domain)
K
Kay, Allen M 已提交
4951
{
4952
	domain_exit(to_dmar_domain(domain));
K
Kay, Allen M 已提交
4953 4954
}

4955 4956
static int intel_iommu_attach_device(struct iommu_domain *domain,
				     struct device *dev)
K
Kay, Allen M 已提交
4957
{
4958
	struct dmar_domain *dmar_domain = to_dmar_domain(domain);
4959 4960
	struct intel_iommu *iommu;
	int addr_width;
4961
	u8 bus, devfn;
4962

4963 4964 4965 4966 4967
	if (device_is_rmrr_locked(dev)) {
		dev_warn(dev, "Device is ineligible for IOMMU domain attach due to platform RMRR requirement.  Contact your platform vendor.\n");
		return -EPERM;
	}

4968 4969
	/* normally dev is not mapped */
	if (unlikely(domain_context_mapped(dev))) {
4970 4971
		struct dmar_domain *old_domain;

4972
		old_domain = find_domain(dev);
4973
		if (old_domain) {
4974
			rcu_read_lock();
4975
			dmar_remove_one_dev_info(old_domain, dev);
4976
			rcu_read_unlock();
4977 4978 4979 4980

			if (!domain_type_is_vm_or_si(old_domain) &&
			     list_empty(&old_domain->devices))
				domain_exit(old_domain);
4981 4982 4983
		}
	}

4984
	iommu = device_to_iommu(dev, &bus, &devfn);
4985 4986 4987 4988 4989
	if (!iommu)
		return -ENODEV;

	/* check if this iommu agaw is sufficient for max mapped address */
	addr_width = agaw_to_width(iommu->agaw);
4990 4991 4992 4993
	if (addr_width > cap_mgaw(iommu->cap))
		addr_width = cap_mgaw(iommu->cap);

	if (dmar_domain->max_addr > (1LL << addr_width)) {
J
Joerg Roedel 已提交
4994
		pr_err("%s: iommu width (%d) is not "
4995
		       "sufficient for the mapped address (%llx)\n",
4996
		       __func__, addr_width, dmar_domain->max_addr);
4997 4998
		return -EFAULT;
	}
4999 5000 5001 5002 5003 5004 5005 5006 5007 5008
	dmar_domain->gaw = addr_width;

	/*
	 * Knock out extra levels of page tables if necessary
	 */
	while (iommu->agaw < dmar_domain->agaw) {
		struct dma_pte *pte;

		pte = dmar_domain->pgd;
		if (dma_pte_present(pte)) {
5009 5010
			dmar_domain->pgd = (struct dma_pte *)
				phys_to_virt(dma_pte_addr(pte));
5011
			free_pgtable_page(pte);
5012 5013 5014
		}
		dmar_domain->agaw--;
	}
5015

5016
	return domain_add_dev_info(dmar_domain, dev);
K
Kay, Allen M 已提交
5017 5018
}

5019 5020
static void intel_iommu_detach_device(struct iommu_domain *domain,
				      struct device *dev)
K
Kay, Allen M 已提交
5021
{
5022
	dmar_remove_one_dev_info(to_dmar_domain(domain), dev);
5023
}
5024

5025 5026
static int intel_iommu_map(struct iommu_domain *domain,
			   unsigned long iova, phys_addr_t hpa,
5027
			   size_t size, int iommu_prot)
5028
{
5029
	struct dmar_domain *dmar_domain = to_dmar_domain(domain);
5030
	u64 max_addr;
5031
	int prot = 0;
5032
	int ret;
5033

5034 5035 5036 5037
	if (iommu_prot & IOMMU_READ)
		prot |= DMA_PTE_READ;
	if (iommu_prot & IOMMU_WRITE)
		prot |= DMA_PTE_WRITE;
5038 5039
	if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
		prot |= DMA_PTE_SNP;
5040

5041
	max_addr = iova + size;
5042
	if (dmar_domain->max_addr < max_addr) {
5043 5044 5045
		u64 end;

		/* check if minimum agaw is sufficient for mapped address */
5046
		end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
5047
		if (end < max_addr) {
J
Joerg Roedel 已提交
5048
			pr_err("%s: iommu width (%d) is not "
5049
			       "sufficient for the mapped address (%llx)\n",
5050
			       __func__, dmar_domain->gaw, max_addr);
5051 5052
			return -EFAULT;
		}
5053
		dmar_domain->max_addr = max_addr;
5054
	}
5055 5056
	/* Round up size to next multiple of PAGE_SIZE, if it and
	   the low bits of hpa would take us onto the next page */
5057
	size = aligned_nrpages(hpa, size);
5058 5059
	ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
				 hpa >> VTD_PAGE_SHIFT, size, prot);
5060
	return ret;
K
Kay, Allen M 已提交
5061 5062
}

5063
static size_t intel_iommu_unmap(struct iommu_domain *domain,
5064
				unsigned long iova, size_t size)
K
Kay, Allen M 已提交
5065
{
5066
	struct dmar_domain *dmar_domain = to_dmar_domain(domain);
5067 5068 5069 5070
	struct page *freelist = NULL;
	struct intel_iommu *iommu;
	unsigned long start_pfn, last_pfn;
	unsigned int npages;
5071
	int iommu_id, level = 0;
5072 5073 5074

	/* Cope with horrid API which requires us to unmap more than the
	   size argument if it happens to be a large-page mapping. */
5075
	BUG_ON(!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level));
5076 5077 5078

	if (size < VTD_PAGE_SIZE << level_to_offset_bits(level))
		size = VTD_PAGE_SIZE << level_to_offset_bits(level);
5079

5080 5081 5082 5083 5084 5085 5086
	start_pfn = iova >> VTD_PAGE_SHIFT;
	last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT;

	freelist = domain_unmap(dmar_domain, start_pfn, last_pfn);

	npages = last_pfn - start_pfn + 1;

5087
	for_each_domain_iommu(iommu_id, dmar_domain) {
5088
		iommu = g_iommus[iommu_id];
5089

5090 5091
		iommu_flush_iotlb_psi(g_iommus[iommu_id], dmar_domain,
				      start_pfn, npages, !freelist, 0);
5092 5093 5094
	}

	dma_free_pagelist(freelist);
5095

5096 5097
	if (dmar_domain->max_addr == iova + size)
		dmar_domain->max_addr = iova;
5098

5099
	return size;
K
Kay, Allen M 已提交
5100 5101
}

5102
static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
5103
					    dma_addr_t iova)
K
Kay, Allen M 已提交
5104
{
5105
	struct dmar_domain *dmar_domain = to_dmar_domain(domain);
K
Kay, Allen M 已提交
5106
	struct dma_pte *pte;
5107
	int level = 0;
5108
	u64 phys = 0;
K
Kay, Allen M 已提交
5109

5110
	pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level);
K
Kay, Allen M 已提交
5111
	if (pte)
5112
		phys = dma_pte_addr(pte);
K
Kay, Allen M 已提交
5113

5114
	return phys;
K
Kay, Allen M 已提交
5115
}
5116

5117
static bool intel_iommu_capable(enum iommu_cap cap)
S
Sheng Yang 已提交
5118 5119
{
	if (cap == IOMMU_CAP_CACHE_COHERENCY)
5120
		return domain_update_iommu_snooping(NULL) == 1;
5121
	if (cap == IOMMU_CAP_INTR_REMAP)
5122
		return irq_remapping_enabled == 1;
S
Sheng Yang 已提交
5123

5124
	return false;
S
Sheng Yang 已提交
5125 5126
}

5127 5128
static int intel_iommu_add_device(struct device *dev)
{
5129
	struct intel_iommu *iommu;
5130
	struct iommu_group *group;
5131
	u8 bus, devfn;
5132

5133 5134
	iommu = device_to_iommu(dev, &bus, &devfn);
	if (!iommu)
5135 5136
		return -ENODEV;

5137
	iommu_device_link(&iommu->iommu, dev);
5138

5139
	group = iommu_group_get_for_dev(dev);
5140

5141 5142
	if (IS_ERR(group))
		return PTR_ERR(group);
5143

5144
	iommu_group_put(group);
5145
	return 0;
5146
}
5147

5148 5149
static void intel_iommu_remove_device(struct device *dev)
{
5150 5151 5152 5153 5154 5155 5156
	struct intel_iommu *iommu;
	u8 bus, devfn;

	iommu = device_to_iommu(dev, &bus, &devfn);
	if (!iommu)
		return;

5157
	iommu_group_remove_device(dev);
5158

5159
	iommu_device_unlink(&iommu->iommu, dev);
5160 5161
}

5162 5163 5164 5165 5166 5167 5168 5169 5170 5171 5172 5173 5174 5175 5176 5177 5178 5179 5180 5181 5182 5183
static void intel_iommu_get_resv_regions(struct device *device,
					 struct list_head *head)
{
	struct iommu_resv_region *reg;
	struct dmar_rmrr_unit *rmrr;
	struct device *i_dev;
	int i;

	rcu_read_lock();
	for_each_rmrr_units(rmrr) {
		for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt,
					  i, i_dev) {
			if (i_dev != device)
				continue;

			list_add_tail(&rmrr->resv->list, head);
		}
	}
	rcu_read_unlock();

	reg = iommu_alloc_resv_region(IOAPIC_RANGE_START,
				      IOAPIC_RANGE_END - IOAPIC_RANGE_START + 1,
5184
				      0, IOMMU_RESV_MSI);
5185 5186 5187 5188 5189 5190 5191 5192 5193 5194 5195 5196 5197 5198
	if (!reg)
		return;
	list_add_tail(&reg->list, head);
}

static void intel_iommu_put_resv_regions(struct device *dev,
					 struct list_head *head)
{
	struct iommu_resv_region *entry, *next;

	list_for_each_entry_safe(entry, next, head, list) {
		if (entry->type == IOMMU_RESV_RESERVED)
			kfree(entry);
	}
5199 5200
}

5201
#ifdef CONFIG_INTEL_IOMMU_SVM
5202 5203 5204 5205 5206 5207 5208 5209 5210 5211 5212 5213 5214 5215 5216 5217 5218 5219 5220
#define MAX_NR_PASID_BITS (20)
static inline unsigned long intel_iommu_get_pts(struct intel_iommu *iommu)
{
	/*
	 * Convert ecap_pss to extend context entry pts encoding, also
	 * respect the soft pasid_max value set by the iommu.
	 * - number of PASID bits = ecap_pss + 1
	 * - number of PASID table entries = 2^(pts + 5)
	 * Therefore, pts = ecap_pss - 4
	 * e.g. KBL ecap_pss = 0x13, PASID has 20 bits, pts = 15
	 */
	if (ecap_pss(iommu->ecap) < 5)
		return 0;

	/* pasid_max is encoded as actual number of entries not the bits */
	return find_first_bit((unsigned long *)&iommu->pasid_max,
			MAX_NR_PASID_BITS) - 5;
}

5221 5222 5223 5224 5225 5226 5227 5228 5229 5230 5231 5232 5233 5234 5235 5236 5237 5238 5239 5240 5241 5242 5243 5244 5245 5246 5247 5248 5249 5250 5251
int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sdev)
{
	struct device_domain_info *info;
	struct context_entry *context;
	struct dmar_domain *domain;
	unsigned long flags;
	u64 ctx_lo;
	int ret;

	domain = get_valid_domain_for_dev(sdev->dev);
	if (!domain)
		return -EINVAL;

	spin_lock_irqsave(&device_domain_lock, flags);
	spin_lock(&iommu->lock);

	ret = -EINVAL;
	info = sdev->dev->archdata.iommu;
	if (!info || !info->pasid_supported)
		goto out;

	context = iommu_context_addr(iommu, info->bus, info->devfn, 0);
	if (WARN_ON(!context))
		goto out;

	ctx_lo = context[0].lo;

	sdev->did = domain->iommu_did[iommu->seq_id];
	sdev->sid = PCI_DEVID(info->bus, info->devfn);

	if (!(ctx_lo & CONTEXT_PASIDE)) {
5252 5253
		if (iommu->pasid_state_table)
			context[1].hi = (u64)virt_to_phys(iommu->pasid_state_table);
5254 5255 5256
		context[1].lo = (u64)virt_to_phys(iommu->pasid_table) |
			intel_iommu_get_pts(iommu);

5257 5258 5259 5260 5261 5262 5263 5264 5265 5266 5267 5268 5269 5270 5271 5272 5273 5274
		wmb();
		/* CONTEXT_TT_MULTI_LEVEL and CONTEXT_TT_DEV_IOTLB are both
		 * extended to permit requests-with-PASID if the PASIDE bit
		 * is set. which makes sense. For CONTEXT_TT_PASS_THROUGH,
		 * however, the PASIDE bit is ignored and requests-with-PASID
		 * are unconditionally blocked. Which makes less sense.
		 * So convert from CONTEXT_TT_PASS_THROUGH to one of the new
		 * "guest mode" translation types depending on whether ATS
		 * is available or not. Annoyingly, we can't use the new
		 * modes *unless* PASIDE is set. */
		if ((ctx_lo & CONTEXT_TT_MASK) == (CONTEXT_TT_PASS_THROUGH << 2)) {
			ctx_lo &= ~CONTEXT_TT_MASK;
			if (info->ats_supported)
				ctx_lo |= CONTEXT_TT_PT_PASID_DEV_IOTLB << 2;
			else
				ctx_lo |= CONTEXT_TT_PT_PASID << 2;
		}
		ctx_lo |= CONTEXT_PASIDE;
5275 5276
		if (iommu->pasid_state_table)
			ctx_lo |= CONTEXT_DINVE;
5277 5278
		if (info->pri_supported)
			ctx_lo |= CONTEXT_PRS;
5279 5280 5281 5282 5283 5284 5285 5286 5287 5288 5289 5290 5291 5292 5293 5294 5295 5296 5297 5298 5299 5300 5301 5302 5303 5304 5305 5306 5307 5308 5309 5310 5311 5312 5313 5314 5315 5316 5317
		context[0].lo = ctx_lo;
		wmb();
		iommu->flush.flush_context(iommu, sdev->did, sdev->sid,
					   DMA_CCMD_MASK_NOBIT,
					   DMA_CCMD_DEVICE_INVL);
	}

	/* Enable PASID support in the device, if it wasn't already */
	if (!info->pasid_enabled)
		iommu_enable_dev_iotlb(info);

	if (info->ats_enabled) {
		sdev->dev_iotlb = 1;
		sdev->qdep = info->ats_qdep;
		if (sdev->qdep >= QI_DEV_EIOTLB_MAX_INVS)
			sdev->qdep = 0;
	}
	ret = 0;

 out:
	spin_unlock(&iommu->lock);
	spin_unlock_irqrestore(&device_domain_lock, flags);

	return ret;
}

struct intel_iommu *intel_svm_device_to_iommu(struct device *dev)
{
	struct intel_iommu *iommu;
	u8 bus, devfn;

	if (iommu_dummy(dev)) {
		dev_warn(dev,
			 "No IOMMU translation for device; cannot enable SVM\n");
		return NULL;
	}

	iommu = device_to_iommu(dev, &bus, &devfn);
	if ((!iommu)) {
5318
		dev_err(dev, "No IOMMU for device; cannot enable SVM\n");
5319 5320 5321 5322
		return NULL;
	}

	if (!iommu->pasid_table) {
5323
		dev_err(dev, "PASID not enabled on IOMMU; cannot enable SVM\n");
5324 5325 5326 5327 5328 5329 5330
		return NULL;
	}

	return iommu;
}
#endif /* CONFIG_INTEL_IOMMU_SVM */

5331
const struct iommu_ops intel_iommu_ops = {
5332 5333 5334 5335 5336 5337 5338 5339 5340 5341 5342 5343 5344 5345 5346
	.capable		= intel_iommu_capable,
	.domain_alloc		= intel_iommu_domain_alloc,
	.domain_free		= intel_iommu_domain_free,
	.attach_dev		= intel_iommu_attach_device,
	.detach_dev		= intel_iommu_detach_device,
	.map			= intel_iommu_map,
	.unmap			= intel_iommu_unmap,
	.map_sg			= default_iommu_map_sg,
	.iova_to_phys		= intel_iommu_iova_to_phys,
	.add_device		= intel_iommu_add_device,
	.remove_device		= intel_iommu_remove_device,
	.get_resv_regions	= intel_iommu_get_resv_regions,
	.put_resv_regions	= intel_iommu_put_resv_regions,
	.device_group		= pci_device_group,
	.pgsize_bitmap		= INTEL_IOMMU_PGSIZES,
5347
};
5348

5349 5350 5351
static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
{
	/* G4x/GM45 integrated gfx dmar support is totally busted. */
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Joerg Roedel 已提交
5352
	pr_info("Disabling IOMMU for graphics on this chipset\n");
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	dmar_map_gfx = 0;
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx);

5364
static void quirk_iommu_rwbf(struct pci_dev *dev)
5365 5366 5367
{
	/*
	 * Mobile 4 Series Chipset neglects to set RWBF capability,
5368
	 * but needs it. Same seems to hold for the desktop versions.
5369
	 */
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Joerg Roedel 已提交
5370
	pr_info("Forcing write-buffer flush capability\n");
5371 5372 5373 5374
	rwbf_quirk = 1;
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
5375 5376 5377 5378 5379 5380
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
5381

5382 5383 5384 5385 5386 5387 5388 5389 5390 5391
#define GGC 0x52
#define GGC_MEMORY_SIZE_MASK	(0xf << 8)
#define GGC_MEMORY_SIZE_NONE	(0x0 << 8)
#define GGC_MEMORY_SIZE_1M	(0x1 << 8)
#define GGC_MEMORY_SIZE_2M	(0x3 << 8)
#define GGC_MEMORY_VT_ENABLED	(0x8 << 8)
#define GGC_MEMORY_SIZE_2M_VT	(0x9 << 8)
#define GGC_MEMORY_SIZE_3M_VT	(0xa << 8)
#define GGC_MEMORY_SIZE_4M_VT	(0xb << 8)

5392
static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
5393 5394 5395
{
	unsigned short ggc;

5396
	if (pci_read_config_word(dev, GGC, &ggc))
5397 5398
		return;

5399
	if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
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Joerg Roedel 已提交
5400
		pr_info("BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
5401
		dmar_map_gfx = 0;
5402 5403
	} else if (dmar_map_gfx) {
		/* we have to ensure the gfx device is idle before we flush */
J
Joerg Roedel 已提交
5404
		pr_info("Disabling batched IOTLB flush on Ironlake\n");
5405 5406
		intel_iommu_strict = 1;
       }
5407 5408 5409 5410 5411 5412
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);

5413 5414 5415 5416 5417 5418 5419 5420 5421 5422 5423 5424 5425 5426 5427 5428 5429 5430 5431 5432 5433 5434 5435 5436 5437 5438 5439 5440 5441 5442 5443 5444 5445 5446 5447 5448 5449 5450 5451 5452 5453 5454 5455 5456 5457 5458 5459 5460 5461 5462 5463 5464 5465
/* On Tylersburg chipsets, some BIOSes have been known to enable the
   ISOCH DMAR unit for the Azalia sound device, but not give it any
   TLB entries, which causes it to deadlock. Check for that.  We do
   this in a function called from init_dmars(), instead of in a PCI
   quirk, because we don't want to print the obnoxious "BIOS broken"
   message if VT-d is actually disabled.
*/
static void __init check_tylersburg_isoch(void)
{
	struct pci_dev *pdev;
	uint32_t vtisochctrl;

	/* If there's no Azalia in the system anyway, forget it. */
	pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL);
	if (!pdev)
		return;
	pci_dev_put(pdev);

	/* System Management Registers. Might be hidden, in which case
	   we can't do the sanity check. But that's OK, because the
	   known-broken BIOSes _don't_ actually hide it, so far. */
	pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL);
	if (!pdev)
		return;

	if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) {
		pci_dev_put(pdev);
		return;
	}

	pci_dev_put(pdev);

	/* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
	if (vtisochctrl & 1)
		return;

	/* Drop all bits other than the number of TLB entries */
	vtisochctrl &= 0x1c;

	/* If we have the recommended number of TLB entries (16), fine. */
	if (vtisochctrl == 0x10)
		return;

	/* Zero TLB entries? You get to ride the short bus to school. */
	if (!vtisochctrl) {
		WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
		     "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
		     dmi_get_system_info(DMI_BIOS_VENDOR),
		     dmi_get_system_info(DMI_BIOS_VERSION),
		     dmi_get_system_info(DMI_PRODUCT_VERSION));
		iommu_identity_mapping |= IDENTMAP_AZALIA;
		return;
	}
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Joerg Roedel 已提交
5466 5467

	pr_warn("Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
5468 5469
	       vtisochctrl);
}