i915_gpu_error.c 41.8 KB
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/*
 * Copyright (c) 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *    Keith Packard <keithp@keithp.com>
 *    Mika Kuoppala <mika.kuoppala@intel.com>
 *
 */

#include <generated/utsrelease.h>
#include "i915_drv.h"

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static const char *engine_str(int engine)
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{
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	switch (engine) {
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	case RCS: return "render";
	case VCS: return "bsd";
	case BCS: return "blt";
	case VECS: return "vebox";
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	case VCS2: return "bsd2";
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	default: return "";
	}
}

static const char *tiling_flag(int tiling)
{
	switch (tiling) {
	default:
	case I915_TILING_NONE: return "";
	case I915_TILING_X: return " X";
	case I915_TILING_Y: return " Y";
	}
}

static const char *dirty_flag(int dirty)
{
	return dirty ? " dirty" : "";
}

static const char *purgeable_flag(int purgeable)
{
	return purgeable ? " purgeable" : "";
}

static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
{

	if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
		e->err = -ENOSPC;
		return false;
	}

	if (e->bytes == e->size - 1 || e->err)
		return false;

	return true;
}

static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
			      unsigned len)
{
	if (e->pos + len <= e->start) {
		e->pos += len;
		return false;
	}

	/* First vsnprintf needs to fit in its entirety for memmove */
	if (len >= e->size) {
		e->err = -EIO;
		return false;
	}

	return true;
}

static void __i915_error_advance(struct drm_i915_error_state_buf *e,
				 unsigned len)
{
	/* If this is first printf in this window, adjust it so that
	 * start position matches start of the buffer
	 */

	if (e->pos < e->start) {
		const size_t off = e->start - e->pos;

		/* Should not happen but be paranoid */
		if (off > len || e->bytes) {
			e->err = -EIO;
			return;
		}

		memmove(e->buf, e->buf + off, len - off);
		e->bytes = len - off;
		e->pos = e->start;
		return;
	}

	e->bytes += len;
	e->pos += len;
}

static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
			       const char *f, va_list args)
{
	unsigned len;

	if (!__i915_error_ok(e))
		return;

	/* Seek the first printf which is hits start position */
	if (e->pos < e->start) {
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		va_list tmp;

		va_copy(tmp, args);
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		len = vsnprintf(NULL, 0, f, tmp);
		va_end(tmp);

		if (!__i915_error_seek(e, len))
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			return;
	}

	len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
	if (len >= e->size - e->bytes)
		len = e->size - e->bytes - 1;

	__i915_error_advance(e, len);
}

static void i915_error_puts(struct drm_i915_error_state_buf *e,
			    const char *str)
{
	unsigned len;

	if (!__i915_error_ok(e))
		return;

	len = strlen(str);

	/* Seek the first printf which is hits start position */
	if (e->pos < e->start) {
		if (!__i915_error_seek(e, len))
			return;
	}

	if (len >= e->size - e->bytes)
		len = e->size - e->bytes - 1;
	memcpy(e->buf + e->bytes, str, len);

	__i915_error_advance(e, len);
}

#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
#define err_puts(e, s) i915_error_puts(e, s)

static void print_error_buffers(struct drm_i915_error_state_buf *m,
				const char *name,
				struct drm_i915_error_buffer *err,
				int count)
{
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	int i;

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	err_printf(m, "%s [%d]:\n", name, count);
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	while (count--) {
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		err_printf(m, "    %08x_%08x %8u %02x %02x [ ",
			   upper_32_bits(err->gtt_offset),
			   lower_32_bits(err->gtt_offset),
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			   err->size,
			   err->read_domains,
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			   err->write_domain);
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		for (i = 0; i < I915_NUM_ENGINES; i++)
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			err_printf(m, "%02x ", err->rseqno[i]);

		err_printf(m, "] %02x", err->wseqno);
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		err_puts(m, tiling_flag(err->tiling));
		err_puts(m, dirty_flag(err->dirty));
		err_puts(m, purgeable_flag(err->purgeable));
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		err_puts(m, err->userptr ? " userptr" : "");
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		err_puts(m, err->engine != -1 ? " " : "");
		err_puts(m, engine_str(err->engine));
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		err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
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		if (err->name)
			err_printf(m, " (name: %d)", err->name);
		if (err->fence_reg != I915_FENCE_REG_NONE)
			err_printf(m, " (fence: %d)", err->fence_reg);

		err_puts(m, "\n");
		err++;
	}
}

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static const char *hangcheck_action_to_str(enum intel_engine_hangcheck_action a)
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{
	switch (a) {
	case HANGCHECK_IDLE:
		return "idle";
	case HANGCHECK_WAIT:
		return "wait";
	case HANGCHECK_ACTIVE:
		return "active";
	case HANGCHECK_KICK:
		return "kick";
	case HANGCHECK_HUNG:
		return "hung";
	}

	return "unknown";
}

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static void error_print_instdone(struct drm_i915_error_state_buf *m,
				 struct drm_i915_error_engine *ee)
{
	err_printf(m, "  INSTDONE: 0x%08x\n",
		   ee->instdone.instdone);

	if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
		return;

	err_printf(m, "  SC_INSTDONE: 0x%08x\n",
		   ee->instdone.slice_common);

	if (INTEL_GEN(m->i915) <= 6)
		return;

	err_printf(m, "  SAMPLER_INSTDONE: 0x%08x\n",
		   ee->instdone.sampler);
	err_printf(m, "  ROW_INSTDONE: 0x%08x\n",
		   ee->instdone.row);
}

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static void error_print_engine(struct drm_i915_error_state_buf *m,
			       struct drm_i915_error_engine *ee)
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{
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	err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
	err_printf(m, "  START: 0x%08x\n", ee->start);
	err_printf(m, "  HEAD:  0x%08x\n", ee->head);
	err_printf(m, "  TAIL:  0x%08x\n", ee->tail);
	err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
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	err_printf(m, "  MODE:  0x%08x\n", ee->mode);
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	err_printf(m, "  HWS:   0x%08x\n", ee->hws);
	err_printf(m, "  ACTHD: 0x%08x %08x\n",
		   (u32)(ee->acthd>>32), (u32)ee->acthd);
	err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
	err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
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	error_print_instdone(m, ee);

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	if (ee->batchbuffer) {
		u64 start = ee->batchbuffer->gtt_offset;
		u64 end = start + ee->batchbuffer->gtt_size;

		err_printf(m, "  batch: [0x%08x_%08x, 0x%08x_%08x]\n",
			   upper_32_bits(start), lower_32_bits(start),
			   upper_32_bits(end), lower_32_bits(end));
	}
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	if (INTEL_GEN(m->i915) >= 4) {
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		err_printf(m, "  BBADDR: 0x%08x_%08x\n",
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			   (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
		err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
		err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
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	}
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	err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
	err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
		   lower_32_bits(ee->faddr));
	if (INTEL_GEN(m->i915) >= 6) {
		err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
		err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
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		err_printf(m, "  SYNC_0: 0x%08x [last synced 0x%08x]\n",
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			   ee->semaphore_mboxes[0],
			   ee->semaphore_seqno[0]);
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		err_printf(m, "  SYNC_1: 0x%08x [last synced 0x%08x]\n",
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			   ee->semaphore_mboxes[1],
			   ee->semaphore_seqno[1]);
		if (HAS_VEBOX(m->i915)) {
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			err_printf(m, "  SYNC_2: 0x%08x [last synced 0x%08x]\n",
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				   ee->semaphore_mboxes[2],
				   ee->semaphore_seqno[2]);
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		}
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	}
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	if (USES_PPGTT(m->i915)) {
		err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
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		if (INTEL_GEN(m->i915) >= 8) {
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			int i;
			for (i = 0; i < 4; i++)
				err_printf(m, "  PDP%d: 0x%016llx\n",
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					   i, ee->vm_info.pdp[i]);
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		} else {
			err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
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				   ee->vm_info.pp_dir_base);
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		}
	}
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	err_printf(m, "  seqno: 0x%08x\n", ee->seqno);
	err_printf(m, "  last_seqno: 0x%08x\n", ee->last_seqno);
	err_printf(m, "  waiting: %s\n", yesno(ee->waiting));
	err_printf(m, "  ring->head: 0x%08x\n", ee->cpu_ring_head);
	err_printf(m, "  ring->tail: 0x%08x\n", ee->cpu_ring_tail);
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	err_printf(m, "  hangcheck: %s [%d]\n",
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		   hangcheck_action_to_str(ee->hangcheck_action),
		   ee->hangcheck_score);
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}

void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
{
	va_list args;

	va_start(args, f);
	i915_error_vprintf(e, f, args);
	va_end(args);
}

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static void print_error_obj(struct drm_i915_error_state_buf *m,
			    struct drm_i915_error_object *obj)
{
	int page, offset, elt;

	for (page = offset = 0; page < obj->page_count; page++) {
		for (elt = 0; elt < PAGE_SIZE/4; elt++) {
			err_printf(m, "%08x :  %08x\n", offset,
				   obj->pages[page][elt]);
			offset += 4;
		}
	}
}

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static void err_print_capabilities(struct drm_i915_error_state_buf *m,
				   const struct intel_device_info *info)
{
#define PRINT_FLAG(x)  err_printf(m, #x ": %s\n", yesno(info->x))
#define SEP_SEMICOLON ;
	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
#undef PRINT_FLAG
#undef SEP_SEMICOLON
}

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int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
			    const struct i915_error_state_file_priv *error_priv)
{
	struct drm_device *dev = error_priv->dev;
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	struct drm_i915_private *dev_priv = to_i915(dev);
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	struct pci_dev *pdev = dev_priv->drm.pdev;
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	struct drm_i915_error_state *error = error_priv->error;
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	struct drm_i915_error_object *obj;
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	int i, j, offset, elt;
	int max_hangcheck_score;
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	if (!error) {
		err_printf(m, "no error state collected\n");
		goto out;
	}

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	err_printf(m, "%s\n", error->error_msg);
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	err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
		   error->time.tv_usec);
	err_printf(m, "Kernel: " UTS_RELEASE "\n");
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	err_print_capabilities(m, &error->device_info);
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	max_hangcheck_score = 0;
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	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		if (error->engine[i].hangcheck_score > max_hangcheck_score)
			max_hangcheck_score = error->engine[i].hangcheck_score;
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	}
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	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		if (error->engine[i].hangcheck_score == max_hangcheck_score &&
		    error->engine[i].pid != -1) {
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			err_printf(m, "Active process (on ring %s): %s [%d]\n",
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				   engine_str(i),
				   error->engine[i].comm,
				   error->engine[i].pid);
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		}
	}
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	err_printf(m, "Reset count: %u\n", error->reset_count);
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	err_printf(m, "Suspend count: %u\n", error->suspend_count);
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	err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
	err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
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	err_printf(m, "PCI Subsystem: %04x:%04x\n",
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		   pdev->subsystem_vendor,
		   pdev->subsystem_device);
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	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
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	if (HAS_CSR(dev)) {
		struct intel_csr *csr = &dev_priv->csr;

		err_printf(m, "DMC loaded: %s\n",
			   yesno(csr->dmc_payload != NULL));
		err_printf(m, "DMC fw version: %d.%d\n",
			   CSR_VERSION_MAJOR(csr->version),
			   CSR_VERSION_MINOR(csr->version));
	}

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	err_printf(m, "EIR: 0x%08x\n", error->eir);
	err_printf(m, "IER: 0x%08x\n", error->ier);
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	if (INTEL_INFO(dev)->gen >= 8) {
		for (i = 0; i < 4; i++)
			err_printf(m, "GTIER gt %d: 0x%08x\n", i,
				   error->gtier[i]);
	} else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
		err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
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	err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
	err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
	err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
	err_printf(m, "CCID: 0x%08x\n", error->ccid);
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	err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
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	for (i = 0; i < dev_priv->num_fence_regs; i++)
		err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);

	if (INTEL_INFO(dev)->gen >= 6) {
		err_printf(m, "ERROR: 0x%08x\n", error->error);
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		if (INTEL_INFO(dev)->gen >= 8)
			err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
				   error->fault_data1, error->fault_data0);

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		err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
	}

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	if (IS_GEN7(dev))
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		err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);

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	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		if (error->engine[i].engine_id != -1)
			error_print_engine(m, &error->engine[i]);
	}
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	for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {
		char buf[128];
		int len, first = 1;
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		if (!error->active_vm[i])
			break;

		len = scnprintf(buf, sizeof(buf), "Active (");
		for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
			if (error->engine[j].vm != error->active_vm[i])
				continue;

			len += scnprintf(buf + len, sizeof(buf), "%s%s",
					 first ? "" : ", ",
					 dev_priv->engine[j].name);
			first = 0;
		}
		scnprintf(buf + len, sizeof(buf), ")");
		print_error_buffers(m, buf,
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				    error->active_bo[i],
				    error->active_bo_count[i]);
	}
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	print_error_buffers(m, "Pinned (global)",
			    error->pinned_bo,
			    error->pinned_bo_count);

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	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		struct drm_i915_error_engine *ee = &error->engine[i];

		obj = ee->batchbuffer;
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		if (obj) {
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			err_puts(m, dev_priv->engine[i].name);
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			if (ee->pid != -1)
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				err_printf(m, " (submitted by %s [%d])",
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					   ee->comm,
					   ee->pid);
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			err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
				   upper_32_bits(obj->gtt_offset),
				   lower_32_bits(obj->gtt_offset));
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			print_error_obj(m, obj);
		}

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		obj = ee->wa_batchbuffer;
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		if (obj) {
			err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
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				   dev_priv->engine[i].name,
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				   lower_32_bits(obj->gtt_offset));
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			print_error_obj(m, obj);
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		}

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		if (ee->num_requests) {
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			err_printf(m, "%s --- %d requests\n",
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				   dev_priv->engine[i].name,
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				   ee->num_requests);
			for (j = 0; j < ee->num_requests; j++) {
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				err_printf(m, "  pid %d, seqno 0x%08x, emitted %ld, head 0x%08x, tail 0x%08x\n",
					   ee->requests[j].pid,
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					   ee->requests[j].seqno,
					   ee->requests[j].jiffies,
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					   ee->requests[j].head,
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					   ee->requests[j].tail);
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			}
		}

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		if (IS_ERR(ee->waiters)) {
			err_printf(m, "%s --- ? waiters [unable to acquire spinlock]\n",
				   dev_priv->engine[i].name);
		} else if (ee->num_waiters) {
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			err_printf(m, "%s --- %d waiters\n",
				   dev_priv->engine[i].name,
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				   ee->num_waiters);
			for (j = 0; j < ee->num_waiters; j++) {
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				err_printf(m, " seqno 0x%08x for %s [%d]\n",
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					   ee->waiters[j].seqno,
					   ee->waiters[j].comm,
					   ee->waiters[j].pid);
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			}
		}

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		if ((obj = ee->ringbuffer)) {
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			err_printf(m, "%s --- ringbuffer = 0x%08x\n",
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				   dev_priv->engine[i].name,
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				   lower_32_bits(obj->gtt_offset));
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			print_error_obj(m, obj);
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		}

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		if ((obj = ee->hws_page)) {
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			u64 hws_offset = obj->gtt_offset;
			u32 *hws_page = &obj->pages[0][0];

			if (i915.enable_execlists) {
				hws_offset += LRC_PPHWSP_PN * PAGE_SIZE;
				hws_page = &obj->pages[LRC_PPHWSP_PN][0];
			}
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			err_printf(m, "%s --- HW Status = 0x%08llx\n",
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				   dev_priv->engine[i].name, hws_offset);
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			offset = 0;
			for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
				err_printf(m, "[%04x] %08x %08x %08x %08x\n",
					   offset,
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					   hws_page[elt],
					   hws_page[elt+1],
					   hws_page[elt+2],
					   hws_page[elt+3]);
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				offset += 16;
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			}
		}

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		obj = ee->wa_ctx;
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		if (obj) {
			u64 wa_ctx_offset = obj->gtt_offset;
			u32 *wa_ctx_page = &obj->pages[0][0];
559
			struct intel_engine_cs *engine = &dev_priv->engine[RCS];
560 561
			u32 wa_ctx_size = (engine->wa_ctx.indirect_ctx.size +
					   engine->wa_ctx.per_ctx.size);
562 563

			err_printf(m, "%s --- WA ctx batch buffer = 0x%08llx\n",
564
				   dev_priv->engine[i].name, wa_ctx_offset);
565 566 567 568 569 570 571 572 573 574 575 576
			offset = 0;
			for (elt = 0; elt < wa_ctx_size; elt += 4) {
				err_printf(m, "[%04x] %08x %08x %08x %08x\n",
					   offset,
					   wa_ctx_page[elt + 0],
					   wa_ctx_page[elt + 1],
					   wa_ctx_page[elt + 2],
					   wa_ctx_page[elt + 3]);
				offset += 16;
			}
		}

577
		if ((obj = ee->ctx)) {
578
			err_printf(m, "%s --- HW Context = 0x%08x\n",
579
				   dev_priv->engine[i].name,
580
				   lower_32_bits(obj->gtt_offset));
581
			print_error_obj(m, obj);
582 583 584
		}
	}

585
	if ((obj = error->semaphore)) {
586 587
		err_printf(m, "Semaphore page = 0x%08x\n",
			   lower_32_bits(obj->gtt_offset));
588 589 590 591 592 593 594 595 596 597
		for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
			err_printf(m, "[%04x] %08x %08x %08x %08x\n",
				   elt * 4,
				   obj->pages[0][elt],
				   obj->pages[0][elt+1],
				   obj->pages[0][elt+2],
				   obj->pages[0][elt+3]);
		}
	}

598 599 600 601 602 603 604 605 606 607 608 609 610 611
	if (error->overlay)
		intel_overlay_print_error_state(m, error->overlay);

	if (error->display)
		intel_display_print_error_state(m, dev, error->display);

out:
	if (m->bytes == 0 && m->err)
		return m->err;

	return 0;
}

int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
612
			      struct drm_i915_private *i915,
613 614 615
			      size_t count, loff_t pos)
{
	memset(ebuf, 0, sizeof(*ebuf));
616
	ebuf->i915 = i915;
617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661

	/* We need to have enough room to store any i915_error_state printf
	 * so that we can move it to start position.
	 */
	ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
	ebuf->buf = kmalloc(ebuf->size,
				GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);

	if (ebuf->buf == NULL) {
		ebuf->size = PAGE_SIZE;
		ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
	}

	if (ebuf->buf == NULL) {
		ebuf->size = 128;
		ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
	}

	if (ebuf->buf == NULL)
		return -ENOMEM;

	ebuf->start = pos;

	return 0;
}

static void i915_error_object_free(struct drm_i915_error_object *obj)
{
	int page;

	if (obj == NULL)
		return;

	for (page = 0; page < obj->page_count; page++)
		kfree(obj->pages[page]);

	kfree(obj);
}

static void i915_error_state_free(struct kref *error_ref)
{
	struct drm_i915_error_state *error = container_of(error_ref,
							  typeof(*error), ref);
	int i;

662 663 664 665 666 667 668 669 670 671 672
	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		struct drm_i915_error_engine *ee = &error->engine[i];

		i915_error_object_free(ee->batchbuffer);
		i915_error_object_free(ee->wa_batchbuffer);
		i915_error_object_free(ee->ringbuffer);
		i915_error_object_free(ee->hws_page);
		i915_error_object_free(ee->ctx);
		i915_error_object_free(ee->wa_ctx);

		kfree(ee->requests);
673 674
		if (!IS_ERR_OR_NULL(ee->waiters))
			kfree(ee->waiters);
675 676
	}

677
	i915_error_object_free(error->semaphore);
678

679
	for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
680 681
		kfree(error->active_bo[i]);
	kfree(error->pinned_bo);
682

683 684 685 686 687 688
	kfree(error->overlay);
	kfree(error->display);
	kfree(error);
}

static struct drm_i915_error_object *
689
i915_error_object_create(struct drm_i915_private *dev_priv,
C
Chris Wilson 已提交
690
			 struct i915_vma *vma)
691
{
692
	struct i915_ggtt *ggtt = &dev_priv->ggtt;
C
Chris Wilson 已提交
693
	struct drm_i915_gem_object *src;
694
	struct drm_i915_error_object *dst;
695
	int num_pages;
696 697
	bool use_ggtt;
	int i = 0;
698
	u64 reloc_offset;
699

C
Chris Wilson 已提交
700 701 702 703 704
	if (!vma)
		return NULL;

	src = vma->obj;
	if (!src->pages)
705 706
		return NULL;

707 708
	num_pages = src->base.size >> PAGE_SHIFT;

709
	dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
C
Chris Wilson 已提交
710
	if (!dst)
711 712
		return NULL;

713 714 715 716
	dst->gtt_offset = vma->node.start;
	dst->gtt_size = vma->node.size;

	reloc_offset = dst->gtt_offset;
717
	use_ggtt = (src->cache_level == I915_CACHE_NONE &&
C
Chris Wilson 已提交
718
		   (vma->flags & I915_VMA_GLOBAL_BIND) &&
719
		   reloc_offset + num_pages * PAGE_SIZE <= ggtt->mappable_end);
720 721 722 723 724

	/* Cannot access stolen address directly, try to use the aperture */
	if (src->stolen) {
		use_ggtt = true;

C
Chris Wilson 已提交
725
		if (!(vma->flags & I915_VMA_GLOBAL_BIND))
726 727
			goto unwind;

C
Chris Wilson 已提交
728
		reloc_offset = vma->node.start;
729
		if (reloc_offset + num_pages * PAGE_SIZE > ggtt->mappable_end)
730 731 732 733
			goto unwind;
	}

	/* Cannot access snooped pages through the aperture */
734 735
	if (use_ggtt && src->cache_level != I915_CACHE_NONE &&
	    !HAS_LLC(dev_priv))
736 737 738 739
		goto unwind;

	dst->page_count = num_pages;
	while (num_pages--) {
740 741 742 743 744 745 746 747
		unsigned long flags;
		void *d;

		d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
		if (d == NULL)
			goto unwind;

		local_irq_save(flags);
748
		if (use_ggtt) {
749 750 751 752 753 754 755
			void __iomem *s;

			/* Simply ignore tiling or any overlapping fence.
			 * It's part of the error state, and this hopefully
			 * captures what the GPU read.
			 */

756
			s = io_mapping_map_atomic_wc(&ggtt->mappable,
757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775
						     reloc_offset);
			memcpy_fromio(d, s, PAGE_SIZE);
			io_mapping_unmap_atomic(s);
		} else {
			struct page *page;
			void *s;

			page = i915_gem_object_get_page(src, i);

			drm_clflush_pages(&page, 1);

			s = kmap_atomic(page);
			memcpy(d, s, PAGE_SIZE);
			kunmap_atomic(s);

			drm_clflush_pages(&page, 1);
		}
		local_irq_restore(flags);

776
		dst->pages[i++] = d;
777 778 779 780 781 782 783 784 785 786 787 788
		reloc_offset += PAGE_SIZE;
	}

	return dst;

unwind:
	while (i--)
		kfree(dst->pages[i]);
	kfree(dst);
	return NULL;
}

789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806
/* The error capture is special as tries to run underneath the normal
 * locking rules - so we use the raw version of the i915_gem_active lookup.
 */
static inline uint32_t
__active_get_seqno(struct i915_gem_active *active)
{
	return i915_gem_request_get_seqno(__i915_gem_active_peek(active));
}

static inline int
__active_get_engine_id(struct i915_gem_active *active)
{
	struct intel_engine_cs *engine;

	engine = i915_gem_request_get_engine(__i915_gem_active_peek(active));
	return engine ? engine->id : -1;
}

807
static void capture_bo(struct drm_i915_error_buffer *err,
808
		       struct i915_vma *vma)
809
{
810
	struct drm_i915_gem_object *obj = vma->obj;
811
	int i;
812

813 814
	err->size = obj->base.size;
	err->name = obj->base.name;
815

816
	for (i = 0; i < I915_NUM_ENGINES; i++)
817 818 819 820
		err->rseqno[i] = __active_get_seqno(&obj->last_read[i]);
	err->wseqno = __active_get_seqno(&obj->last_write);
	err->engine = __active_get_engine_id(&obj->last_write);

821
	err->gtt_offset = vma->node.start;
822 823
	err->read_domains = obj->base.read_domains;
	err->write_domain = obj->base.write_domain;
824
	err->fence_reg = vma->fence ? vma->fence->id : -1;
825
	err->tiling = i915_gem_object_get_tiling(obj);
826 827
	err->dirty = obj->dirty;
	err->purgeable = obj->madv != I915_MADV_WILLNEED;
828
	err->userptr = obj->userptr.mm != NULL;
829 830 831
	err->cache_level = obj->cache_level;
}

832 833 834
static u32 capture_error_bo(struct drm_i915_error_buffer *err,
			    int count, struct list_head *head,
			    bool pinned_only)
835
{
B
Ben Widawsky 已提交
836
	struct i915_vma *vma;
837 838
	int i = 0;

839
	list_for_each_entry(vma, head, vm_link) {
840 841 842
		if (pinned_only && !i915_vma_is_pinned(vma))
			continue;

843
		capture_bo(err++, vma);
844 845 846 847 848 849 850
		if (++i == count)
			break;
	}

	return i;
}

851 852 853 854 855 856 857 858 859 860
/* Generate a semi-unique error code. The code is not meant to have meaning, The
 * code's only purpose is to try to prevent false duplicated bug reports by
 * grossly estimating a GPU error state.
 *
 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
 * the hang if we could strip the GTT offset information from it.
 *
 * It's only a small step better than a random number in its current form.
 */
static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
861
					 struct drm_i915_error_state *error,
862
					 int *engine_id)
863 864 865 866 867 868 869 870 871
{
	uint32_t error_code = 0;
	int i;

	/* IPEHR would be an ideal way to detect errors, as it's the gross
	 * measure of "the command that hung." However, has some very common
	 * synchronization commands which almost always appear in the case
	 * strictly a client bug. Use instdone to differentiate those some.
	 */
872
	for (i = 0; i < I915_NUM_ENGINES; i++) {
873 874 875
		if (error->engine[i].hangcheck_action == HANGCHECK_HUNG) {
			if (engine_id)
				*engine_id = i;
876

877 878
			return error->engine[i].ipehr ^
			       error->engine[i].instdone.instdone;
879 880
		}
	}
881 882 883 884

	return error_code;
}

885
static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
886 887 888 889
				   struct drm_i915_error_state *error)
{
	int i;

890
	if (IS_GEN3(dev_priv) || IS_GEN2(dev_priv)) {
891
		for (i = 0; i < dev_priv->num_fence_regs; i++)
892
			error->fence[i] = I915_READ(FENCE_REG(i));
893
	} else if (IS_GEN5(dev_priv) || IS_GEN4(dev_priv)) {
894 895
		for (i = 0; i < dev_priv->num_fence_regs; i++)
			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
896
	} else if (INTEL_GEN(dev_priv) >= 6) {
897 898 899
		for (i = 0; i < dev_priv->num_fence_regs; i++)
			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
	}
900 901
}

902

903
static void gen8_record_semaphore_state(struct drm_i915_error_state *error,
904
					struct intel_engine_cs *engine,
905
					struct drm_i915_error_engine *ee)
906
{
907
	struct drm_i915_private *dev_priv = engine->i915;
908
	struct intel_engine_cs *to;
909
	enum intel_engine_id id;
910

911
	if (!error->semaphore)
912
		return;
913

914
	for_each_engine_id(to, dev_priv, id) {
915 916 917
		int idx;
		u16 signal_offset;
		u32 *tmp;
918

919
		if (engine == to)
920 921
			continue;

922 923
		signal_offset =
			(GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1)) / 4;
924
		tmp = error->semaphore->pages[0];
925
		idx = intel_engine_sync_index(engine, to);
926

927 928
		ee->semaphore_mboxes[idx] = tmp[signal_offset];
		ee->semaphore_seqno[idx] = engine->semaphore.sync_seqno[idx];
929 930 931
	}
}

932 933
static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
					struct drm_i915_error_engine *ee)
934
{
935 936 937 938 939 940
	struct drm_i915_private *dev_priv = engine->i915;

	ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
	ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
	ee->semaphore_seqno[0] = engine->semaphore.sync_seqno[0];
	ee->semaphore_seqno[1] = engine->semaphore.sync_seqno[1];
941

942
	if (HAS_VEBOX(dev_priv)) {
943
		ee->semaphore_mboxes[2] =
944
			I915_READ(RING_SYNC_2(engine->mmio_base));
945
		ee->semaphore_seqno[2] = engine->semaphore.sync_seqno[2];
946 947 948
	}
}

949 950
static void error_record_engine_waiters(struct intel_engine_cs *engine,
					struct drm_i915_error_engine *ee)
951 952 953 954 955 956
{
	struct intel_breadcrumbs *b = &engine->breadcrumbs;
	struct drm_i915_error_waiter *waiter;
	struct rb_node *rb;
	int count;

957 958
	ee->num_waiters = 0;
	ee->waiters = NULL;
959

960 961 962 963 964 965 966 967
	if (RB_EMPTY_ROOT(&b->waiters))
		return;

	if (!spin_trylock(&b->lock)) {
		ee->waiters = ERR_PTR(-EDEADLK);
		return;
	}

968 969 970 971 972 973 974 975 976 977 978 979 980
	count = 0;
	for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb))
		count++;
	spin_unlock(&b->lock);

	waiter = NULL;
	if (count)
		waiter = kmalloc_array(count,
				       sizeof(struct drm_i915_error_waiter),
				       GFP_ATOMIC);
	if (!waiter)
		return;

981 982 983 984 985
	if (!spin_trylock(&b->lock)) {
		kfree(waiter);
		ee->waiters = ERR_PTR(-EDEADLK);
		return;
	}
986

987
	ee->waiters = waiter;
988 989 990 991 992 993 994 995
	for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
		struct intel_wait *w = container_of(rb, typeof(*w), node);

		strcpy(waiter->comm, w->tsk->comm);
		waiter->pid = w->tsk->pid;
		waiter->seqno = w->seqno;
		waiter++;

996
		if (++ee->num_waiters == count)
997 998 999 1000 1001
			break;
	}
	spin_unlock(&b->lock);
}

1002 1003 1004
static void error_record_engine_registers(struct drm_i915_error_state *error,
					  struct intel_engine_cs *engine,
					  struct drm_i915_error_engine *ee)
1005
{
1006 1007
	struct drm_i915_private *dev_priv = engine->i915;

1008
	if (INTEL_GEN(dev_priv) >= 6) {
1009 1010
		ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
		ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
1011
		if (INTEL_GEN(dev_priv) >= 8)
1012
			gen8_record_semaphore_state(error, engine, ee);
1013
		else
1014
			gen6_record_semaphore_state(engine, ee);
1015 1016
	}

1017
	if (INTEL_GEN(dev_priv) >= 4) {
1018 1019 1020 1021 1022
		ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
		ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
		ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
		ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
		ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
1023
		if (INTEL_GEN(dev_priv) >= 8) {
1024 1025
			ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
			ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
1026
		}
1027
		ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
1028
	} else {
1029 1030 1031
		ee->faddr = I915_READ(DMA_FADD_I8XX);
		ee->ipeir = I915_READ(IPEIR);
		ee->ipehr = I915_READ(IPEHR);
1032 1033
	}

1034 1035
	i915_get_engine_instdone(dev_priv, engine->id, &ee->instdone);

1036 1037
	ee->waiting = intel_engine_has_waiter(engine);
	ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
1038
	ee->acthd = intel_engine_get_active_head(engine);
1039 1040 1041 1042 1043 1044
	ee->seqno = intel_engine_get_seqno(engine);
	ee->last_seqno = engine->last_submitted_seqno;
	ee->start = I915_READ_START(engine);
	ee->head = I915_READ_HEAD(engine);
	ee->tail = I915_READ_TAIL(engine);
	ee->ctl = I915_READ_CTL(engine);
1045 1046
	if (INTEL_GEN(dev_priv) > 2)
		ee->mode = I915_READ_MODE(engine);
1047

1048
	if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
1049
		i915_reg_t mmio;
1050

1051
		if (IS_GEN7(dev_priv)) {
1052
			switch (engine->id) {
1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066
			default:
			case RCS:
				mmio = RENDER_HWS_PGA_GEN7;
				break;
			case BCS:
				mmio = BLT_HWS_PGA_GEN7;
				break;
			case VCS:
				mmio = BSD_HWS_PGA_GEN7;
				break;
			case VECS:
				mmio = VEBOX_HWS_PGA_GEN7;
				break;
			}
1067
		} else if (IS_GEN6(engine->i915)) {
1068
			mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1069 1070
		} else {
			/* XXX: gen8 returns to sanity */
1071
			mmio = RING_HWS_PGA(engine->mmio_base);
1072 1073
		}

1074
		ee->hws = I915_READ(mmio);
1075 1076
	}

1077 1078
	ee->hangcheck_score = engine->hangcheck.score;
	ee->hangcheck_action = engine->hangcheck.action;
1079

1080
	if (USES_PPGTT(dev_priv)) {
1081 1082
		int i;

1083
		ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
1084

1085
		if (IS_GEN6(dev_priv))
1086
			ee->vm_info.pp_dir_base =
1087
				I915_READ(RING_PP_DIR_BASE_READ(engine));
1088
		else if (IS_GEN7(dev_priv))
1089
			ee->vm_info.pp_dir_base =
1090
				I915_READ(RING_PP_DIR_BASE(engine));
1091
		else if (INTEL_GEN(dev_priv) >= 8)
1092
			for (i = 0; i < 4; i++) {
1093
				ee->vm_info.pdp[i] =
1094
					I915_READ(GEN8_RING_PDP_UDW(engine, i));
1095 1096
				ee->vm_info.pdp[i] <<= 32;
				ee->vm_info.pdp[i] |=
1097
					I915_READ(GEN8_RING_PDP_LDW(engine, i));
1098 1099
			}
	}
1100 1101
}

1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158
static void engine_record_requests(struct intel_engine_cs *engine,
				   struct drm_i915_gem_request *first,
				   struct drm_i915_error_engine *ee)
{
	struct drm_i915_gem_request *request;
	int count;

	count = 0;
	request = first;
	list_for_each_entry_from(request, &engine->request_list, link)
		count++;
	if (!count)
		return;

	ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
	if (!ee->requests)
		return;

	ee->num_requests = count;

	count = 0;
	request = first;
	list_for_each_entry_from(request, &engine->request_list, link) {
		struct drm_i915_error_request *erq;

		if (count >= ee->num_requests) {
			/*
			 * If the ring request list was changed in
			 * between the point where the error request
			 * list was created and dimensioned and this
			 * point then just exit early to avoid crashes.
			 *
			 * We don't need to communicate that the
			 * request list changed state during error
			 * state capture and that the error state is
			 * slightly incorrect as a consequence since we
			 * are typically only interested in the request
			 * list state at the point of error state
			 * capture, not in any changes happening during
			 * the capture.
			 */
			break;
		}

		erq = &ee->requests[count++];
		erq->seqno = request->fence.seqno;
		erq->jiffies = request->emitted_jiffies;
		erq->head = request->head;
		erq->tail = request->tail;

		rcu_read_lock();
		erq->pid = request->ctx->pid ? pid_nr(request->ctx->pid) : 0;
		rcu_read_unlock();
	}
	ee->num_requests = count;
}

1159
static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
1160 1161
				  struct drm_i915_error_state *error)
{
1162
	struct i915_ggtt *ggtt = &dev_priv->ggtt;
1163
	int i;
1164

1165
	error->semaphore =
C
Chris Wilson 已提交
1166
		i915_error_object_create(dev_priv, dev_priv->semaphore);
1167

1168
	for (i = 0; i < I915_NUM_ENGINES; i++) {
1169
		struct intel_engine_cs *engine = &dev_priv->engine[i];
1170
		struct drm_i915_error_engine *ee = &error->engine[i];
1171
		struct drm_i915_gem_request *request;
1172

1173 1174
		ee->pid = -1;
		ee->engine_id = -1;
1175

1176
		if (!intel_engine_initialized(engine))
1177 1178
			continue;

1179
		ee->engine_id = i;
1180

1181 1182
		error_record_engine_registers(error, engine, ee);
		error_record_engine_waiters(engine, ee);
1183

1184
		request = i915_gem_find_active_request(engine);
1185
		if (request) {
1186
			struct intel_ring *ring;
1187
			struct pid *pid;
1188

1189
			ee->vm = request->ctx->ppgtt ?
1190
				&request->ctx->ppgtt->base : &ggtt->base;
1191

1192 1193 1194 1195
			/* We need to copy these to an anonymous buffer
			 * as the simplest method to avoid being overwritten
			 * by userspace.
			 */
1196
			ee->batchbuffer =
1197
				i915_error_object_create(dev_priv,
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Chris Wilson 已提交
1198
							 request->batch);
1199

1200
			if (HAS_BROKEN_CS_TLB(dev_priv))
1201
				ee->wa_batchbuffer =
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Chris Wilson 已提交
1202 1203
					i915_error_object_create(dev_priv,
								 engine->scratch);
1204

C
Chris Wilson 已提交
1205 1206 1207
			ee->ctx =
				i915_error_object_create(dev_priv,
							 request->ctx->engine[i].state);
1208

1209 1210
			pid = request->ctx->pid;
			if (pid) {
1211 1212 1213
				struct task_struct *task;

				rcu_read_lock();
1214
				task = pid_task(pid, PIDTYPE_PID);
1215
				if (task) {
1216 1217
					strcpy(ee->comm, task->comm);
					ee->pid = task->pid;
1218 1219 1220
				}
				rcu_read_unlock();
			}
1221

1222 1223 1224
			error->simulated |=
				request->ctx->flags & CONTEXT_NO_ERROR_CAPTURE;

1225 1226 1227
			ring = request->ring;
			ee->cpu_ring_head = ring->head;
			ee->cpu_ring_tail = ring->tail;
1228
			ee->ringbuffer =
C
Chris Wilson 已提交
1229
				i915_error_object_create(dev_priv, ring->vma);
1230 1231

			engine_record_requests(engine, request, ee);
1232
		}
1233

1234
		ee->hws_page =
C
Chris Wilson 已提交
1235 1236
			i915_error_object_create(dev_priv,
						 engine->status_page.vma);
1237

C
Chris Wilson 已提交
1238 1239
		ee->wa_ctx =
			i915_error_object_create(dev_priv, engine->wa_ctx.vma);
1240 1241 1242
	}
}

1243 1244 1245
static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
				struct drm_i915_error_state *error,
				struct i915_address_space *vm,
1246
				int idx)
1247
{
1248
	struct drm_i915_error_buffer *active_bo;
1249
	struct i915_vma *vma;
1250
	int count;
1251

1252
	count = 0;
1253
	list_for_each_entry(vma, &vm->active_list, vm_link)
1254
		count++;
1255

1256 1257 1258
	active_bo = NULL;
	if (count)
		active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC);
1259
	if (active_bo)
1260 1261 1262 1263 1264 1265 1266
		count = capture_error_bo(active_bo, count, &vm->active_list, false);
	else
		count = 0;

	error->active_vm[idx] = vm;
	error->active_bo[idx] = active_bo;
	error->active_bo_count[idx] = count;
1267 1268
}

1269 1270
static void i915_capture_active_buffers(struct drm_i915_private *dev_priv,
					struct drm_i915_error_state *error)
1271
{
1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284
	int cnt = 0, i, j;

	BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
	BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));
	BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));

	/* Scan each engine looking for unique active contexts/vm */
	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		struct drm_i915_error_engine *ee = &error->engine[i];
		bool found;

		if (!ee->vm)
			continue;
1285

1286 1287 1288 1289 1290
		found = false;
		for (j = 0; j < i && !found; j++)
			found = error->engine[j].vm == ee->vm;
		if (!found)
			i915_gem_capture_vm(dev_priv, error, ee->vm, cnt++);
1291
	}
1292 1293
}

1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324
static void i915_capture_pinned_buffers(struct drm_i915_private *dev_priv,
					struct drm_i915_error_state *error)
{
	struct i915_address_space *vm = &dev_priv->ggtt.base;
	struct drm_i915_error_buffer *bo;
	struct i915_vma *vma;
	int count_inactive, count_active;

	count_inactive = 0;
	list_for_each_entry(vma, &vm->active_list, vm_link)
		count_inactive++;

	count_active = 0;
	list_for_each_entry(vma, &vm->inactive_list, vm_link)
		count_active++;

	bo = NULL;
	if (count_inactive + count_active)
		bo = kcalloc(count_inactive + count_active,
			     sizeof(*bo), GFP_ATOMIC);
	if (!bo)
		return;

	count_inactive = capture_error_bo(bo, count_inactive,
					  &vm->active_list, true);
	count_active = capture_error_bo(bo + count_inactive, count_active,
					&vm->inactive_list, true);
	error->pinned_bo_count = count_inactive + count_active;
	error->pinned_bo = bo;
}

1325 1326 1327
/* Capture all registers which don't fit into another category. */
static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
				   struct drm_i915_error_state *error)
1328
{
1329
	struct drm_device *dev = &dev_priv->drm;
1330
	int i;
1331

1332 1333 1334 1335 1336 1337 1338
	/* General organization
	 * 1. Registers specific to a single generation
	 * 2. Registers which belong to multiple generations
	 * 3. Feature specific registers.
	 * 4. Everything else
	 * Please try to follow the order.
	 */
1339

1340 1341
	/* 1: Registers specific to a single generation */
	if (IS_VALLEYVIEW(dev)) {
1342
		error->gtier[0] = I915_READ(GTIER);
1343
		error->ier = I915_READ(VLV_IER);
1344
		error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
1345
	}
1346

1347 1348
	if (IS_GEN7(dev))
		error->err_int = I915_READ(GEN7_ERR_INT);
1349

1350 1351 1352 1353 1354
	if (INTEL_INFO(dev)->gen >= 8) {
		error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
		error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
	}

1355
	if (IS_GEN6(dev)) {
1356
		error->forcewake = I915_READ_FW(FORCEWAKE);
1357 1358 1359
		error->gab_ctl = I915_READ(GAB_CTL);
		error->gfx_mode = I915_READ(GFX_MODE);
	}
1360

1361 1362
	/* 2: Registers which belong to multiple generations */
	if (INTEL_INFO(dev)->gen >= 7)
1363
		error->forcewake = I915_READ_FW(FORCEWAKE_MT);
1364 1365

	if (INTEL_INFO(dev)->gen >= 6) {
1366
		error->derrmr = I915_READ(DERRMR);
1367 1368 1369 1370
		error->error = I915_READ(ERROR_GEN6);
		error->done_reg = I915_READ(DONE_REG);
	}

1371
	/* 3: Feature specific registers */
1372 1373 1374 1375 1376 1377
	if (IS_GEN6(dev) || IS_GEN7(dev)) {
		error->gam_ecochk = I915_READ(GAM_ECOCHK);
		error->gac_eco = I915_READ(GAC_ECO_BITS);
	}

	/* 4: Everything else */
1378 1379 1380
	if (HAS_HW_CONTEXTS(dev))
		error->ccid = I915_READ(CCID);

1381 1382 1383 1384 1385
	if (INTEL_INFO(dev)->gen >= 8) {
		error->ier = I915_READ(GEN8_DE_MISC_IER);
		for (i = 0; i < 4; i++)
			error->gtier[i] = I915_READ(GEN8_GT_IER(i));
	} else if (HAS_PCH_SPLIT(dev)) {
1386
		error->ier = I915_READ(DEIER);
1387
		error->gtier[0] = I915_READ(GTIER);
1388 1389 1390 1391
	} else if (IS_GEN2(dev)) {
		error->ier = I915_READ16(IER);
	} else if (!IS_VALLEYVIEW(dev)) {
		error->ier = I915_READ(IER);
1392 1393 1394
	}
	error->eir = I915_READ(EIR);
	error->pgtbl_er = I915_READ(PGTBL_ER);
1395 1396
}

1397
static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
1398
				   struct drm_i915_error_state *error,
1399
				   u32 engine_mask,
1400
				   const char *error_msg)
1401 1402
{
	u32 ecode;
1403
	int engine_id = -1, len;
1404

1405
	ecode = i915_error_generate_code(dev_priv, error, &engine_id);
1406

1407
	len = scnprintf(error->error_msg, sizeof(error->error_msg),
1408
			"GPU HANG: ecode %d:%d:0x%08x",
1409
			INTEL_GEN(dev_priv), engine_id, ecode);
1410

1411
	if (engine_id != -1 && error->engine[engine_id].pid != -1)
1412 1413 1414
		len += scnprintf(error->error_msg + len,
				 sizeof(error->error_msg) - len,
				 ", in %s [%d]",
1415 1416
				 error->engine[engine_id].comm,
				 error->engine[engine_id].pid);
1417 1418 1419 1420

	scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
		  ", reason: %s, action: %s",
		  error_msg,
1421
		  engine_mask ? "reset" : "continue");
1422 1423
}

1424 1425 1426
static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
				   struct drm_i915_error_state *error)
{
1427 1428 1429 1430
	error->iommu = -1;
#ifdef CONFIG_INTEL_IOMMU
	error->iommu = intel_iommu_gfx_mapped;
#endif
1431
	error->reset_count = i915_reset_count(&dev_priv->gpu_error);
1432
	error->suspend_count = dev_priv->suspend_count;
1433 1434 1435 1436

	memcpy(&error->device_info,
	       INTEL_INFO(dev_priv),
	       sizeof(error->device_info));
1437 1438
}

1439 1440 1441 1442 1443 1444 1445 1446 1447
/**
 * i915_capture_error_state - capture an error record for later analysis
 * @dev: drm device
 *
 * Should be called when an error is detected (either a hang or an error
 * interrupt) to capture error state from the time of the error.  Fills
 * out a structure which becomes available in debugfs for user level tools
 * to pick up.
 */
1448 1449
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
1450
			      const char *error_msg)
1451
{
1452
	static bool warned;
1453 1454 1455
	struct drm_i915_error_state *error;
	unsigned long flags;

1456 1457 1458
	if (READ_ONCE(dev_priv->gpu_error.first_error))
		return;

1459 1460 1461 1462 1463 1464 1465
	/* Account for pipe specific data like PIPE*STAT */
	error = kzalloc(sizeof(*error), GFP_ATOMIC);
	if (!error) {
		DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
		return;
	}

1466 1467
	kref_init(&error->ref);

1468
	i915_capture_gen_state(dev_priv, error);
1469
	i915_capture_reg_state(dev_priv, error);
1470 1471
	i915_gem_record_fences(dev_priv, error);
	i915_gem_record_rings(dev_priv, error);
1472 1473
	i915_capture_active_buffers(dev_priv, error);
	i915_capture_pinned_buffers(dev_priv, error);
1474

1475 1476
	do_gettimeofday(&error->time);

1477 1478
	error->overlay = intel_overlay_capture_error_state(dev_priv);
	error->display = intel_display_capture_error_state(dev_priv);
1479

1480
	i915_error_capture_msg(dev_priv, error, engine_mask, error_msg);
1481 1482
	DRM_INFO("%s\n", error->error_msg);

1483 1484 1485 1486 1487 1488 1489
	if (!error->simulated) {
		spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
		if (!dev_priv->gpu_error.first_error) {
			dev_priv->gpu_error.first_error = error;
			error = NULL;
		}
		spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1490 1491
	}

1492
	if (error) {
1493
		i915_error_state_free(&error->ref);
1494 1495 1496 1497 1498 1499 1500 1501
		return;
	}

	if (!warned) {
		DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
		DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
		DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
		DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1502 1503
		DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
			 dev_priv->drm.primary->index);
1504 1505
		warned = true;
	}
1506 1507 1508 1509 1510
}

void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv)
{
1511
	struct drm_i915_private *dev_priv = to_i915(dev);
1512

1513
	spin_lock_irq(&dev_priv->gpu_error.lock);
1514 1515 1516
	error_priv->error = dev_priv->gpu_error.first_error;
	if (error_priv->error)
		kref_get(&error_priv->error->ref);
1517
	spin_unlock_irq(&dev_priv->gpu_error.lock);
1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528

}

void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
{
	if (error_priv->error)
		kref_put(&error_priv->error->ref, i915_error_state_free);
}

void i915_destroy_error_state(struct drm_device *dev)
{
1529
	struct drm_i915_private *dev_priv = to_i915(dev);
1530 1531
	struct drm_i915_error_state *error;

1532
	spin_lock_irq(&dev_priv->gpu_error.lock);
1533 1534
	error = dev_priv->gpu_error.first_error;
	dev_priv->gpu_error.first_error = NULL;
1535
	spin_unlock_irq(&dev_priv->gpu_error.lock);
1536 1537 1538 1539 1540

	if (error)
		kref_put(&error->ref, i915_error_state_free);
}

1541
const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
1542 1543 1544
{
	switch (type) {
	case I915_CACHE_NONE: return " uncached";
1545
	case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
1546
	case I915_CACHE_L3_LLC: return " L3+LLC";
1547
	case I915_CACHE_WT: return " WT";
1548 1549 1550 1551 1552
	default: return "";
	}
}

/* NB: please notice the memset */
1553 1554 1555
void i915_get_engine_instdone(struct drm_i915_private *dev_priv,
			      enum intel_engine_id engine_id,
			      struct intel_instdone *instdone)
1556
{
1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585
	u32 mmio_base = dev_priv->engine[engine_id].mmio_base;

	memset(instdone, 0, sizeof(*instdone));

	switch (INTEL_GEN(dev_priv)) {
	default:
		instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));

		if (engine_id != RCS)
			break;

		instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
		instdone->sampler = I915_READ(GEN7_SAMPLER_INSTDONE);
		instdone->row = I915_READ(GEN7_ROW_INSTDONE);

		break;
	case 6:
	case 5:
	case 4:
		instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));

		if (engine_id == RCS)
			/* HACK: Using the wrong struct member */
			instdone->slice_common = I915_READ(GEN4_INSTDONE1);
		break;
	case 3:
	case 2:
		instdone->instdone = I915_READ(GEN2_INSTDONE);
		break;
1586 1587
	}
}