i915_gpu_error.c 40.7 KB
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/*
 * Copyright (c) 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *    Keith Packard <keithp@keithp.com>
 *    Mika Kuoppala <mika.kuoppala@intel.com>
 *
 */

#include <generated/utsrelease.h>
#include "i915_drv.h"

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static const char *engine_str(int engine)
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{
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	switch (engine) {
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	case RCS: return "render";
	case VCS: return "bsd";
	case BCS: return "blt";
	case VECS: return "vebox";
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	case VCS2: return "bsd2";
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	default: return "";
	}
}

static const char *pin_flag(int pinned)
{
	if (pinned > 0)
		return " P";
	else if (pinned < 0)
		return " p";
	else
		return "";
}

static const char *tiling_flag(int tiling)
{
	switch (tiling) {
	default:
	case I915_TILING_NONE: return "";
	case I915_TILING_X: return " X";
	case I915_TILING_Y: return " Y";
	}
}

static const char *dirty_flag(int dirty)
{
	return dirty ? " dirty" : "";
}

static const char *purgeable_flag(int purgeable)
{
	return purgeable ? " purgeable" : "";
}

static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
{

	if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
		e->err = -ENOSPC;
		return false;
	}

	if (e->bytes == e->size - 1 || e->err)
		return false;

	return true;
}

static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
			      unsigned len)
{
	if (e->pos + len <= e->start) {
		e->pos += len;
		return false;
	}

	/* First vsnprintf needs to fit in its entirety for memmove */
	if (len >= e->size) {
		e->err = -EIO;
		return false;
	}

	return true;
}

static void __i915_error_advance(struct drm_i915_error_state_buf *e,
				 unsigned len)
{
	/* If this is first printf in this window, adjust it so that
	 * start position matches start of the buffer
	 */

	if (e->pos < e->start) {
		const size_t off = e->start - e->pos;

		/* Should not happen but be paranoid */
		if (off > len || e->bytes) {
			e->err = -EIO;
			return;
		}

		memmove(e->buf, e->buf + off, len - off);
		e->bytes = len - off;
		e->pos = e->start;
		return;
	}

	e->bytes += len;
	e->pos += len;
}

static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
			       const char *f, va_list args)
{
	unsigned len;

	if (!__i915_error_ok(e))
		return;

	/* Seek the first printf which is hits start position */
	if (e->pos < e->start) {
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		va_list tmp;

		va_copy(tmp, args);
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		len = vsnprintf(NULL, 0, f, tmp);
		va_end(tmp);

		if (!__i915_error_seek(e, len))
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			return;
	}

	len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
	if (len >= e->size - e->bytes)
		len = e->size - e->bytes - 1;

	__i915_error_advance(e, len);
}

static void i915_error_puts(struct drm_i915_error_state_buf *e,
			    const char *str)
{
	unsigned len;

	if (!__i915_error_ok(e))
		return;

	len = strlen(str);

	/* Seek the first printf which is hits start position */
	if (e->pos < e->start) {
		if (!__i915_error_seek(e, len))
			return;
	}

	if (len >= e->size - e->bytes)
		len = e->size - e->bytes - 1;
	memcpy(e->buf + e->bytes, str, len);

	__i915_error_advance(e, len);
}

#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
#define err_puts(e, s) i915_error_puts(e, s)

static void print_error_buffers(struct drm_i915_error_state_buf *m,
				const char *name,
				struct drm_i915_error_buffer *err,
				int count)
{
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	int i;

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	err_printf(m, "  %s [%d]:\n", name, count);
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	while (count--) {
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		err_printf(m, "    %08x_%08x %8u %02x %02x [ ",
			   upper_32_bits(err->gtt_offset),
			   lower_32_bits(err->gtt_offset),
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			   err->size,
			   err->read_domains,
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			   err->write_domain);
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		for (i = 0; i < I915_NUM_ENGINES; i++)
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			err_printf(m, "%02x ", err->rseqno[i]);

		err_printf(m, "] %02x", err->wseqno);
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		err_puts(m, pin_flag(err->pinned));
		err_puts(m, tiling_flag(err->tiling));
		err_puts(m, dirty_flag(err->dirty));
		err_puts(m, purgeable_flag(err->purgeable));
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		err_puts(m, err->userptr ? " userptr" : "");
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		err_puts(m, err->engine != -1 ? " " : "");
		err_puts(m, engine_str(err->engine));
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		err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
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		if (err->name)
			err_printf(m, " (name: %d)", err->name);
		if (err->fence_reg != I915_FENCE_REG_NONE)
			err_printf(m, " (fence: %d)", err->fence_reg);

		err_puts(m, "\n");
		err++;
	}
}

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static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
{
	switch (a) {
	case HANGCHECK_IDLE:
		return "idle";
	case HANGCHECK_WAIT:
		return "wait";
	case HANGCHECK_ACTIVE:
		return "active";
	case HANGCHECK_KICK:
		return "kick";
	case HANGCHECK_HUNG:
		return "hung";
	}

	return "unknown";
}

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static void error_print_engine(struct drm_i915_error_state_buf *m,
			       struct drm_i915_error_engine *ee)
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{
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	err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
	err_printf(m, "  START: 0x%08x\n", ee->start);
	err_printf(m, "  HEAD:  0x%08x\n", ee->head);
	err_printf(m, "  TAIL:  0x%08x\n", ee->tail);
	err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
	err_printf(m, "  HWS:   0x%08x\n", ee->hws);
	err_printf(m, "  ACTHD: 0x%08x %08x\n",
		   (u32)(ee->acthd>>32), (u32)ee->acthd);
	err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
	err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
	err_printf(m, "  INSTDONE: 0x%08x\n", ee->instdone);
	if (INTEL_GEN(m->i915) >= 4) {
		err_printf(m, "  BBADDR: 0x%08x %08x\n",
			   (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
		err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
		err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
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	}
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	err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
	err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
		   lower_32_bits(ee->faddr));
	if (INTEL_GEN(m->i915) >= 6) {
		err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
		err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
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		err_printf(m, "  SYNC_0: 0x%08x [last synced 0x%08x]\n",
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			   ee->semaphore_mboxes[0],
			   ee->semaphore_seqno[0]);
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		err_printf(m, "  SYNC_1: 0x%08x [last synced 0x%08x]\n",
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			   ee->semaphore_mboxes[1],
			   ee->semaphore_seqno[1]);
		if (HAS_VEBOX(m->i915)) {
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			err_printf(m, "  SYNC_2: 0x%08x [last synced 0x%08x]\n",
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				   ee->semaphore_mboxes[2],
				   ee->semaphore_seqno[2]);
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		}
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	}
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	if (USES_PPGTT(m->i915)) {
		err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
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		if (INTEL_GEN(m->i915) >= 8) {
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			int i;
			for (i = 0; i < 4; i++)
				err_printf(m, "  PDP%d: 0x%016llx\n",
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					   i, ee->vm_info.pdp[i]);
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		} else {
			err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
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				   ee->vm_info.pp_dir_base);
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		}
	}
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	err_printf(m, "  seqno: 0x%08x\n", ee->seqno);
	err_printf(m, "  last_seqno: 0x%08x\n", ee->last_seqno);
	err_printf(m, "  waiting: %s\n", yesno(ee->waiting));
	err_printf(m, "  ring->head: 0x%08x\n", ee->cpu_ring_head);
	err_printf(m, "  ring->tail: 0x%08x\n", ee->cpu_ring_tail);
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	err_printf(m, "  hangcheck: %s [%d]\n",
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		   hangcheck_action_to_str(ee->hangcheck_action),
		   ee->hangcheck_score);
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}

void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
{
	va_list args;

	va_start(args, f);
	i915_error_vprintf(e, f, args);
	va_end(args);
}

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static void print_error_obj(struct drm_i915_error_state_buf *m,
			    struct drm_i915_error_object *obj)
{
	int page, offset, elt;

	for (page = offset = 0; page < obj->page_count; page++) {
		for (elt = 0; elt < PAGE_SIZE/4; elt++) {
			err_printf(m, "%08x :  %08x\n", offset,
				   obj->pages[page][elt]);
			offset += 4;
		}
	}
}

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int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
			    const struct i915_error_state_file_priv *error_priv)
{
	struct drm_device *dev = error_priv->dev;
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	struct drm_i915_private *dev_priv = to_i915(dev);
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	struct drm_i915_error_state *error = error_priv->error;
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	struct drm_i915_error_object *obj;
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	int i, j, offset, elt;
	int max_hangcheck_score;
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	if (!error) {
		err_printf(m, "no error state collected\n");
		goto out;
	}

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	err_printf(m, "%s\n", error->error_msg);
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	err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
		   error->time.tv_usec);
	err_printf(m, "Kernel: " UTS_RELEASE "\n");
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	max_hangcheck_score = 0;
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	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		if (error->engine[i].hangcheck_score > max_hangcheck_score)
			max_hangcheck_score = error->engine[i].hangcheck_score;
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	}
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	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		if (error->engine[i].hangcheck_score == max_hangcheck_score &&
		    error->engine[i].pid != -1) {
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			err_printf(m, "Active process (on ring %s): %s [%d]\n",
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				   engine_str(i),
				   error->engine[i].comm,
				   error->engine[i].pid);
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		}
	}
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	err_printf(m, "Reset count: %u\n", error->reset_count);
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	err_printf(m, "Suspend count: %u\n", error->suspend_count);
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	err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
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	err_printf(m, "PCI Revision: 0x%02x\n", dev->pdev->revision);
	err_printf(m, "PCI Subsystem: %04x:%04x\n",
		   dev->pdev->subsystem_vendor,
		   dev->pdev->subsystem_device);
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	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
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	if (HAS_CSR(dev)) {
		struct intel_csr *csr = &dev_priv->csr;

		err_printf(m, "DMC loaded: %s\n",
			   yesno(csr->dmc_payload != NULL));
		err_printf(m, "DMC fw version: %d.%d\n",
			   CSR_VERSION_MAJOR(csr->version),
			   CSR_VERSION_MINOR(csr->version));
	}

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	err_printf(m, "EIR: 0x%08x\n", error->eir);
	err_printf(m, "IER: 0x%08x\n", error->ier);
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	if (INTEL_INFO(dev)->gen >= 8) {
		for (i = 0; i < 4; i++)
			err_printf(m, "GTIER gt %d: 0x%08x\n", i,
				   error->gtier[i]);
	} else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
		err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
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	err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
	err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
	err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
	err_printf(m, "CCID: 0x%08x\n", error->ccid);
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	err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
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	for (i = 0; i < dev_priv->num_fence_regs; i++)
		err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);

	for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
		err_printf(m, "  INSTDONE_%d: 0x%08x\n", i,
			   error->extra_instdone[i]);

	if (INTEL_INFO(dev)->gen >= 6) {
		err_printf(m, "ERROR: 0x%08x\n", error->error);
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		if (INTEL_INFO(dev)->gen >= 8)
			err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
				   error->fault_data1, error->fault_data0);

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		err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
	}

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	if (IS_GEN7(dev))
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		err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);

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	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		if (error->engine[i].engine_id != -1)
			error_print_engine(m, &error->engine[i]);
	}
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	for (i = 0; i < error->vm_count; i++) {
		err_printf(m, "vm[%d]\n", i);

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		print_error_buffers(m, "Active",
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				    error->active_bo[i],
				    error->active_bo_count[i]);
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		print_error_buffers(m, "Pinned",
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				    error->pinned_bo[i],
				    error->pinned_bo_count[i]);
	}
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	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		struct drm_i915_error_engine *ee = &error->engine[i];

		obj = ee->batchbuffer;
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		if (obj) {
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			err_puts(m, dev_priv->engine[i].name);
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			if (ee->pid != -1)
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				err_printf(m, " (submitted by %s [%d])",
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					   ee->comm,
					   ee->pid);
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			err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
				   upper_32_bits(obj->gtt_offset),
				   lower_32_bits(obj->gtt_offset));
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			print_error_obj(m, obj);
		}

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		obj = ee->wa_batchbuffer;
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		if (obj) {
			err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
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				   dev_priv->engine[i].name,
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				   lower_32_bits(obj->gtt_offset));
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			print_error_obj(m, obj);
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		}

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		if (ee->num_requests) {
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			err_printf(m, "%s --- %d requests\n",
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				   dev_priv->engine[i].name,
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				   ee->num_requests);
			for (j = 0; j < ee->num_requests; j++) {
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				err_printf(m, "  seqno 0x%08x, emitted %ld, tail 0x%08x\n",
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					   ee->requests[j].seqno,
					   ee->requests[j].jiffies,
					   ee->requests[j].tail);
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			}
		}

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		if (ee->num_waiters) {
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			err_printf(m, "%s --- %d waiters\n",
				   dev_priv->engine[i].name,
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				   ee->num_waiters);
			for (j = 0; j < ee->num_waiters; j++) {
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				err_printf(m, " seqno 0x%08x for %s [%d]\n",
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					   ee->waiters[j].seqno,
					   ee->waiters[j].comm,
					   ee->waiters[j].pid);
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			}
		}

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		if ((obj = ee->ringbuffer)) {
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			err_printf(m, "%s --- ringbuffer = 0x%08x\n",
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				   dev_priv->engine[i].name,
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				   lower_32_bits(obj->gtt_offset));
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			print_error_obj(m, obj);
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		}

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		if ((obj = ee->hws_page)) {
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			u64 hws_offset = obj->gtt_offset;
			u32 *hws_page = &obj->pages[0][0];

			if (i915.enable_execlists) {
				hws_offset += LRC_PPHWSP_PN * PAGE_SIZE;
				hws_page = &obj->pages[LRC_PPHWSP_PN][0];
			}
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			err_printf(m, "%s --- HW Status = 0x%08llx\n",
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				   dev_priv->engine[i].name, hws_offset);
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			offset = 0;
			for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
				err_printf(m, "[%04x] %08x %08x %08x %08x\n",
					   offset,
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					   hws_page[elt],
					   hws_page[elt+1],
					   hws_page[elt+2],
					   hws_page[elt+3]);
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				offset += 16;
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			}
		}

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		obj = ee->wa_ctx;
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		if (obj) {
			u64 wa_ctx_offset = obj->gtt_offset;
			u32 *wa_ctx_page = &obj->pages[0][0];
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			struct intel_engine_cs *engine = &dev_priv->engine[RCS];
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			u32 wa_ctx_size = (engine->wa_ctx.indirect_ctx.size +
					   engine->wa_ctx.per_ctx.size);
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			err_printf(m, "%s --- WA ctx batch buffer = 0x%08llx\n",
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				   dev_priv->engine[i].name, wa_ctx_offset);
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			offset = 0;
			for (elt = 0; elt < wa_ctx_size; elt += 4) {
				err_printf(m, "[%04x] %08x %08x %08x %08x\n",
					   offset,
					   wa_ctx_page[elt + 0],
					   wa_ctx_page[elt + 1],
					   wa_ctx_page[elt + 2],
					   wa_ctx_page[elt + 3]);
				offset += 16;
			}
		}

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		if ((obj = ee->ctx)) {
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			err_printf(m, "%s --- HW Context = 0x%08x\n",
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				   dev_priv->engine[i].name,
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				   lower_32_bits(obj->gtt_offset));
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			print_error_obj(m, obj);
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		}
	}

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	if ((obj = error->semaphore_obj)) {
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		err_printf(m, "Semaphore page = 0x%08x\n",
			   lower_32_bits(obj->gtt_offset));
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		for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
			err_printf(m, "[%04x] %08x %08x %08x %08x\n",
				   elt * 4,
				   obj->pages[0][elt],
				   obj->pages[0][elt+1],
				   obj->pages[0][elt+2],
				   obj->pages[0][elt+3]);
		}
	}

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	if (error->overlay)
		intel_overlay_print_error_state(m, error->overlay);

	if (error->display)
		intel_display_print_error_state(m, dev, error->display);

out:
	if (m->bytes == 0 && m->err)
		return m->err;

	return 0;
}

int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
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			      struct drm_i915_private *i915,
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			      size_t count, loff_t pos)
{
	memset(ebuf, 0, sizeof(*ebuf));
567
	ebuf->i915 = i915;
568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612

	/* We need to have enough room to store any i915_error_state printf
	 * so that we can move it to start position.
	 */
	ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
	ebuf->buf = kmalloc(ebuf->size,
				GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);

	if (ebuf->buf == NULL) {
		ebuf->size = PAGE_SIZE;
		ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
	}

	if (ebuf->buf == NULL) {
		ebuf->size = 128;
		ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
	}

	if (ebuf->buf == NULL)
		return -ENOMEM;

	ebuf->start = pos;

	return 0;
}

static void i915_error_object_free(struct drm_i915_error_object *obj)
{
	int page;

	if (obj == NULL)
		return;

	for (page = 0; page < obj->page_count; page++)
		kfree(obj->pages[page]);

	kfree(obj);
}

static void i915_error_state_free(struct kref *error_ref)
{
	struct drm_i915_error_state *error = container_of(error_ref,
							  typeof(*error), ref);
	int i;

613 614 615 616 617 618 619 620 621 622 623 624
	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		struct drm_i915_error_engine *ee = &error->engine[i];

		i915_error_object_free(ee->batchbuffer);
		i915_error_object_free(ee->wa_batchbuffer);
		i915_error_object_free(ee->ringbuffer);
		i915_error_object_free(ee->hws_page);
		i915_error_object_free(ee->ctx);
		i915_error_object_free(ee->wa_ctx);

		kfree(ee->requests);
		kfree(ee->waiters);
625 626
	}

627
	i915_error_object_free(error->semaphore_obj);
628 629 630 631

	for (i = 0; i < error->vm_count; i++)
		kfree(error->active_bo[i]);

632
	kfree(error->active_bo);
633 634 635
	kfree(error->active_bo_count);
	kfree(error->pinned_bo);
	kfree(error->pinned_bo_count);
636 637 638 639 640 641
	kfree(error->overlay);
	kfree(error->display);
	kfree(error);
}

static struct drm_i915_error_object *
642 643 644
i915_error_object_create(struct drm_i915_private *dev_priv,
			 struct drm_i915_gem_object *src,
			 struct i915_address_space *vm)
645
{
646
	struct i915_ggtt *ggtt = &dev_priv->ggtt;
647
	struct drm_i915_error_object *dst;
648
	struct i915_vma *vma = NULL;
649
	int num_pages;
650 651
	bool use_ggtt;
	int i = 0;
652
	u64 reloc_offset;
653 654 655 656

	if (src == NULL || src->pages == NULL)
		return NULL;

657 658
	num_pages = src->base.size >> PAGE_SHIFT;

659 660 661 662
	dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
	if (dst == NULL)
		return NULL;

663 664 665 666
	if (i915_gem_obj_bound(src, vm))
		dst->gtt_offset = i915_gem_obj_offset(src, vm);
	else
		dst->gtt_offset = -1;
667 668

	reloc_offset = dst->gtt_offset;
669 670
	if (i915_is_ggtt(vm))
		vma = i915_gem_obj_to_ggtt(src);
671
	use_ggtt = (src->cache_level == I915_CACHE_NONE &&
672
		   vma && (vma->bound & GLOBAL_BIND) &&
673
		   reloc_offset + num_pages * PAGE_SIZE <= ggtt->mappable_end);
674 675 676 677 678

	/* Cannot access stolen address directly, try to use the aperture */
	if (src->stolen) {
		use_ggtt = true;

679
		if (!(vma && vma->bound & GLOBAL_BIND))
680 681 682
			goto unwind;

		reloc_offset = i915_gem_obj_ggtt_offset(src);
683
		if (reloc_offset + num_pages * PAGE_SIZE > ggtt->mappable_end)
684 685 686 687
			goto unwind;
	}

	/* Cannot access snooped pages through the aperture */
688 689
	if (use_ggtt && src->cache_level != I915_CACHE_NONE &&
	    !HAS_LLC(dev_priv))
690 691 692 693
		goto unwind;

	dst->page_count = num_pages;
	while (num_pages--) {
694 695 696 697 698 699 700 701
		unsigned long flags;
		void *d;

		d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
		if (d == NULL)
			goto unwind;

		local_irq_save(flags);
702
		if (use_ggtt) {
703 704 705 706 707 708 709
			void __iomem *s;

			/* Simply ignore tiling or any overlapping fence.
			 * It's part of the error state, and this hopefully
			 * captures what the GPU read.
			 */

710
			s = io_mapping_map_atomic_wc(ggtt->mappable,
711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729
						     reloc_offset);
			memcpy_fromio(d, s, PAGE_SIZE);
			io_mapping_unmap_atomic(s);
		} else {
			struct page *page;
			void *s;

			page = i915_gem_object_get_page(src, i);

			drm_clflush_pages(&page, 1);

			s = kmap_atomic(page);
			memcpy(d, s, PAGE_SIZE);
			kunmap_atomic(s);

			drm_clflush_pages(&page, 1);
		}
		local_irq_restore(flags);

730
		dst->pages[i++] = d;
731 732 733 734 735 736 737 738 739 740 741
		reloc_offset += PAGE_SIZE;
	}

	return dst;

unwind:
	while (i--)
		kfree(dst->pages[i]);
	kfree(dst);
	return NULL;
}
742
#define i915_error_ggtt_object_create(dev_priv, src) \
743
	i915_error_object_create((dev_priv), (src), &(dev_priv)->ggtt.base)
744 745

static void capture_bo(struct drm_i915_error_buffer *err,
746
		       struct i915_vma *vma)
747
{
748
	struct drm_i915_gem_object *obj = vma->obj;
749
	int i;
750

751 752
	err->size = obj->base.size;
	err->name = obj->base.name;
753
	for (i = 0; i < I915_NUM_ENGINES; i++)
754
		err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]);
755
	err->wseqno = i915_gem_request_get_seqno(obj->last_write_req);
756
	err->gtt_offset = vma->node.start;
757 758 759 760
	err->read_domains = obj->base.read_domains;
	err->write_domain = obj->base.write_domain;
	err->fence_reg = obj->fence_reg;
	err->pinned = 0;
B
Ben Widawsky 已提交
761
	if (i915_gem_obj_is_pinned(obj))
762 763 764 765
		err->pinned = 1;
	err->tiling = obj->tiling_mode;
	err->dirty = obj->dirty;
	err->purgeable = obj->madv != I915_MADV_WILLNEED;
766
	err->userptr = obj->userptr.mm != NULL;
767 768
	err->engine = obj->last_write_req ?
		i915_gem_request_get_engine(obj->last_write_req)->id : -1;
769 770 771 772 773 774
	err->cache_level = obj->cache_level;
}

static u32 capture_active_bo(struct drm_i915_error_buffer *err,
			     int count, struct list_head *head)
{
B
Ben Widawsky 已提交
775
	struct i915_vma *vma;
776 777
	int i = 0;

778
	list_for_each_entry(vma, head, vm_link) {
779
		capture_bo(err++, vma);
780 781 782 783 784 785 786 787
		if (++i == count)
			break;
	}

	return i;
}

static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
788 789
			     int count, struct list_head *head,
			     struct i915_address_space *vm)
790 791
{
	struct drm_i915_gem_object *obj;
792 793
	struct drm_i915_error_buffer * const first = err;
	struct drm_i915_error_buffer * const last = err + count;
794 795

	list_for_each_entry(obj, head, global_list) {
796
		struct i915_vma *vma;
797

798
		if (err == last)
799
			break;
800

801
		list_for_each_entry(vma, &obj->vma_list, obj_link)
802
			if (vma->vm == vm && vma->pin_count > 0)
803
				capture_bo(err++, vma);
804 805
	}

806
	return err - first;
807 808
}

809 810 811 812 813 814 815 816 817 818
/* Generate a semi-unique error code. The code is not meant to have meaning, The
 * code's only purpose is to try to prevent false duplicated bug reports by
 * grossly estimating a GPU error state.
 *
 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
 * the hang if we could strip the GTT offset information from it.
 *
 * It's only a small step better than a random number in its current form.
 */
static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
819
					 struct drm_i915_error_state *error,
820
					 int *engine_id)
821 822 823 824 825 826 827 828 829
{
	uint32_t error_code = 0;
	int i;

	/* IPEHR would be an ideal way to detect errors, as it's the gross
	 * measure of "the command that hung." However, has some very common
	 * synchronization commands which almost always appear in the case
	 * strictly a client bug. Use instdone to differentiate those some.
	 */
830
	for (i = 0; i < I915_NUM_ENGINES; i++) {
831 832 833
		if (error->engine[i].hangcheck_action == HANGCHECK_HUNG) {
			if (engine_id)
				*engine_id = i;
834

835
			return error->engine[i].ipehr ^ error->engine[i].instdone;
836 837
		}
	}
838 839 840 841

	return error_code;
}

842
static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
843 844 845 846
				   struct drm_i915_error_state *error)
{
	int i;

847
	if (IS_GEN3(dev_priv) || IS_GEN2(dev_priv)) {
848
		for (i = 0; i < dev_priv->num_fence_regs; i++)
849
			error->fence[i] = I915_READ(FENCE_REG(i));
850
	} else if (IS_GEN5(dev_priv) || IS_GEN4(dev_priv)) {
851 852
		for (i = 0; i < dev_priv->num_fence_regs; i++)
			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
853
	} else if (INTEL_GEN(dev_priv) >= 6) {
854 855 856
		for (i = 0; i < dev_priv->num_fence_regs; i++)
			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
	}
857 858
}

859

860
static void gen8_record_semaphore_state(struct drm_i915_error_state *error,
861
					struct intel_engine_cs *engine,
862
					struct drm_i915_error_engine *ee)
863
{
864
	struct drm_i915_private *dev_priv = engine->i915;
865
	struct intel_engine_cs *to;
866
	enum intel_engine_id id;
867 868

	if (!error->semaphore_obj)
869
		return;
870

871
	for_each_engine_id(to, dev_priv, id) {
872 873 874
		int idx;
		u16 signal_offset;
		u32 *tmp;
875

876
		if (engine == to)
877 878
			continue;

879 880
		signal_offset =
			(GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1)) / 4;
881
		tmp = error->semaphore_obj->pages[0];
882
		idx = intel_ring_sync_index(engine, to);
883

884 885
		ee->semaphore_mboxes[idx] = tmp[signal_offset];
		ee->semaphore_seqno[idx] = engine->semaphore.sync_seqno[idx];
886 887 888
	}
}

889 890
static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
					struct drm_i915_error_engine *ee)
891
{
892 893 894 895 896 897
	struct drm_i915_private *dev_priv = engine->i915;

	ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
	ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
	ee->semaphore_seqno[0] = engine->semaphore.sync_seqno[0];
	ee->semaphore_seqno[1] = engine->semaphore.sync_seqno[1];
898

899
	if (HAS_VEBOX(dev_priv)) {
900
		ee->semaphore_mboxes[2] =
901
			I915_READ(RING_SYNC_2(engine->mmio_base));
902
		ee->semaphore_seqno[2] = engine->semaphore.sync_seqno[2];
903 904 905
	}
}

906 907
static void error_record_engine_waiters(struct intel_engine_cs *engine,
					struct drm_i915_error_engine *ee)
908 909 910 911 912 913
{
	struct intel_breadcrumbs *b = &engine->breadcrumbs;
	struct drm_i915_error_waiter *waiter;
	struct rb_node *rb;
	int count;

914 915
	ee->num_waiters = 0;
	ee->waiters = NULL;
916 917 918 919 920 921 922 923 924 925 926 927 928 929 930

	spin_lock(&b->lock);
	count = 0;
	for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb))
		count++;
	spin_unlock(&b->lock);

	waiter = NULL;
	if (count)
		waiter = kmalloc_array(count,
				       sizeof(struct drm_i915_error_waiter),
				       GFP_ATOMIC);
	if (!waiter)
		return;

931
	ee->waiters = waiter;
932 933 934 935 936 937 938 939 940 941

	spin_lock(&b->lock);
	for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
		struct intel_wait *w = container_of(rb, typeof(*w), node);

		strcpy(waiter->comm, w->tsk->comm);
		waiter->pid = w->tsk->pid;
		waiter->seqno = w->seqno;
		waiter++;

942
		if (++ee->num_waiters == count)
943 944 945 946 947
			break;
	}
	spin_unlock(&b->lock);
}

948 949 950
static void error_record_engine_registers(struct drm_i915_error_state *error,
					  struct intel_engine_cs *engine,
					  struct drm_i915_error_engine *ee)
951
{
952 953
	struct drm_i915_private *dev_priv = engine->i915;

954
	if (INTEL_GEN(dev_priv) >= 6) {
955 956
		ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
		ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
957
		if (INTEL_GEN(dev_priv) >= 8)
958
			gen8_record_semaphore_state(error, engine, ee);
959
		else
960
			gen6_record_semaphore_state(engine, ee);
961 962
	}

963
	if (INTEL_GEN(dev_priv) >= 4) {
964 965 966 967 968 969
		ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
		ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
		ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
		ee->instdone = I915_READ(RING_INSTDONE(engine->mmio_base));
		ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
		ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
970
		if (INTEL_GEN(dev_priv) >= 8) {
971 972
			ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
			ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
973
		}
974
		ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
975
	} else {
976 977 978 979
		ee->faddr = I915_READ(DMA_FADD_I8XX);
		ee->ipeir = I915_READ(IPEIR);
		ee->ipehr = I915_READ(IPEHR);
		ee->instdone = I915_READ(GEN2_INSTDONE);
980 981
	}

982 983 984 985 986 987 988 989 990
	ee->waiting = intel_engine_has_waiter(engine);
	ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
	ee->acthd = intel_ring_get_active_head(engine);
	ee->seqno = intel_engine_get_seqno(engine);
	ee->last_seqno = engine->last_submitted_seqno;
	ee->start = I915_READ_START(engine);
	ee->head = I915_READ_HEAD(engine);
	ee->tail = I915_READ_TAIL(engine);
	ee->ctl = I915_READ_CTL(engine);
991

992
	if (I915_NEED_GFX_HWS(dev_priv)) {
993
		i915_reg_t mmio;
994

995
		if (IS_GEN7(dev_priv)) {
996
			switch (engine->id) {
997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010
			default:
			case RCS:
				mmio = RENDER_HWS_PGA_GEN7;
				break;
			case BCS:
				mmio = BLT_HWS_PGA_GEN7;
				break;
			case VCS:
				mmio = BSD_HWS_PGA_GEN7;
				break;
			case VECS:
				mmio = VEBOX_HWS_PGA_GEN7;
				break;
			}
1011
		} else if (IS_GEN6(engine->i915)) {
1012
			mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1013 1014
		} else {
			/* XXX: gen8 returns to sanity */
1015
			mmio = RING_HWS_PGA(engine->mmio_base);
1016 1017
		}

1018
		ee->hws = I915_READ(mmio);
1019 1020
	}

1021 1022
	ee->hangcheck_score = engine->hangcheck.score;
	ee->hangcheck_action = engine->hangcheck.action;
1023

1024
	if (USES_PPGTT(dev_priv)) {
1025 1026
		int i;

1027
		ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
1028

1029
		if (IS_GEN6(dev_priv))
1030
			ee->vm_info.pp_dir_base =
1031
				I915_READ(RING_PP_DIR_BASE_READ(engine));
1032
		else if (IS_GEN7(dev_priv))
1033
			ee->vm_info.pp_dir_base =
1034
				I915_READ(RING_PP_DIR_BASE(engine));
1035
		else if (INTEL_GEN(dev_priv) >= 8)
1036
			for (i = 0; i < 4; i++) {
1037
				ee->vm_info.pdp[i] =
1038
					I915_READ(GEN8_RING_PDP_UDW(engine, i));
1039 1040
				ee->vm_info.pdp[i] <<= 32;
				ee->vm_info.pdp[i] |=
1041
					I915_READ(GEN8_RING_PDP_LDW(engine, i));
1042 1043
			}
	}
1044 1045 1046
}


1047
static void i915_gem_record_active_context(struct intel_engine_cs *engine,
1048
					   struct drm_i915_error_state *error,
1049
					   struct drm_i915_error_engine *ee)
1050
{
1051
	struct drm_i915_private *dev_priv = engine->i915;
1052 1053 1054
	struct drm_i915_gem_object *obj;

	/* Currently render ring is the only HW context user */
1055
	if (engine->id != RCS || !error->ccid)
1056 1057 1058
		return;

	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1059 1060 1061
		if (!i915_gem_obj_ggtt_bound(obj))
			continue;

1062
		if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
1063
			ee->ctx = i915_error_ggtt_object_create(dev_priv, obj);
1064 1065 1066 1067 1068
			break;
		}
	}
}

1069
static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
1070 1071
				  struct drm_i915_error_state *error)
{
1072
	struct i915_ggtt *ggtt = &dev_priv->ggtt;
1073 1074 1075
	struct drm_i915_gem_request *request;
	int i, count;

1076 1077 1078 1079 1080 1081
	if (dev_priv->semaphore_obj) {
		error->semaphore_obj =
			i915_error_ggtt_object_create(dev_priv,
						      dev_priv->semaphore_obj);
	}

1082
	for (i = 0; i < I915_NUM_ENGINES; i++) {
1083
		struct intel_engine_cs *engine = &dev_priv->engine[i];
1084
		struct drm_i915_error_engine *ee = &error->engine[i];
1085

1086 1087
		ee->pid = -1;
		ee->engine_id = -1;
1088

1089
		if (!intel_engine_initialized(engine))
1090 1091
			continue;

1092
		ee->engine_id = i;
1093

1094 1095
		error_record_engine_registers(error, engine, ee);
		error_record_engine_waiters(engine, ee);
1096

1097
		request = i915_gem_find_active_request(engine);
1098
		if (request) {
1099
			struct i915_address_space *vm;
1100
			struct intel_ringbuffer *rb;
1101

1102 1103
			vm = request->ctx->ppgtt ?
				&request->ctx->ppgtt->base : &ggtt->base;
1104

1105 1106 1107 1108
			/* We need to copy these to an anonymous buffer
			 * as the simplest method to avoid being overwritten
			 * by userspace.
			 */
1109
			ee->batchbuffer =
1110 1111
				i915_error_object_create(dev_priv,
							 request->batch_obj,
1112
							 vm);
1113

1114
			if (HAS_BROKEN_CS_TLB(dev_priv))
1115
				ee->wa_batchbuffer =
1116
					i915_error_ggtt_object_create(dev_priv,
1117
							     engine->scratch.obj);
1118

1119
			if (request->pid) {
1120 1121 1122
				struct task_struct *task;

				rcu_read_lock();
1123
				task = pid_task(request->pid, PIDTYPE_PID);
1124
				if (task) {
1125 1126
					strcpy(ee->comm, task->comm);
					ee->pid = task->pid;
1127 1128 1129
				}
				rcu_read_unlock();
			}
1130

1131 1132 1133
			error->simulated |=
				request->ctx->flags & CONTEXT_NO_ERROR_CAPTURE;

1134
			rb = request->ringbuf;
1135 1136 1137
			ee->cpu_ring_head = rb->head;
			ee->cpu_ring_tail = rb->tail;
			ee->ringbuffer =
1138 1139 1140
				i915_error_ggtt_object_create(dev_priv,
							      rb->obj);
		}
1141

1142
		ee->hws_page =
1143 1144
			i915_error_ggtt_object_create(dev_priv,
						      engine->status_page.obj);
1145

1146
		if (engine->wa_ctx.obj) {
1147
			ee->wa_ctx =
1148
				i915_error_ggtt_object_create(dev_priv,
1149
							      engine->wa_ctx.obj);
1150 1151
		}

1152
		i915_gem_record_active_context(engine, error, ee);
1153 1154

		count = 0;
1155
		list_for_each_entry(request, &engine->request_list, list)
1156 1157
			count++;

1158 1159 1160 1161 1162
		ee->num_requests = count;
		ee->requests =
			kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
		if (!ee->requests) {
			ee->num_requests = 0;
1163 1164 1165 1166
			continue;
		}

		count = 0;
1167
		list_for_each_entry(request, &engine->request_list, list) {
1168 1169
			struct drm_i915_error_request *erq;

1170
			if (count >= ee->num_requests) {
1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188
				/*
				 * If the ring request list was changed in
				 * between the point where the error request
				 * list was created and dimensioned and this
				 * point then just exit early to avoid crashes.
				 *
				 * We don't need to communicate that the
				 * request list changed state during error
				 * state capture and that the error state is
				 * slightly incorrect as a consequence since we
				 * are typically only interested in the request
				 * list state at the point of error state
				 * capture, not in any changes happening during
				 * the capture.
				 */
				break;
			}

1189
			erq = &ee->requests[count++];
1190
			erq->seqno = request->fence.seqno;
1191
			erq->jiffies = request->emitted_jiffies;
1192
			erq->tail = request->postfix;
1193 1194 1195 1196
		}
	}
}

1197 1198 1199 1200 1201 1202 1203
/* FIXME: Since pin count/bound list is global, we duplicate what we capture per
 * VM.
 */
static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
				struct drm_i915_error_state *error,
				struct i915_address_space *vm,
				const int ndx)
1204
{
1205
	struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
1206
	struct drm_i915_gem_object *obj;
1207
	struct i915_vma *vma;
1208 1209 1210
	int i;

	i = 0;
1211
	list_for_each_entry(vma, &vm->active_list, vm_link)
1212
		i++;
1213
	error->active_bo_count[ndx] = i;
1214 1215

	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1216
		list_for_each_entry(vma, &obj->vma_list, obj_link)
1217
			if (vma->vm == vm && vma->pin_count > 0)
1218 1219
				i++;
	}
1220
	error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
1221 1222

	if (i) {
D
Daniel Vetter 已提交
1223
		active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
1224 1225
		if (active_bo)
			pinned_bo = active_bo + error->active_bo_count[ndx];
1226 1227
	}

1228 1229 1230 1231
	if (active_bo)
		error->active_bo_count[ndx] =
			capture_active_bo(active_bo,
					  error->active_bo_count[ndx],
1232
					  &vm->active_list);
1233

1234 1235 1236 1237
	if (pinned_bo)
		error->pinned_bo_count[ndx] =
			capture_pinned_bo(pinned_bo,
					  error->pinned_bo_count[ndx],
1238
					  &dev_priv->mm.bound_list, vm);
1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258
	error->active_bo[ndx] = active_bo;
	error->pinned_bo[ndx] = pinned_bo;
}

static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
				     struct drm_i915_error_state *error)
{
	struct i915_address_space *vm;
	int cnt = 0, i = 0;

	list_for_each_entry(vm, &dev_priv->vm_list, global_link)
		cnt++;

	error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
	error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
	error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
					 GFP_ATOMIC);
	error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
					 GFP_ATOMIC);

1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277
	if (error->active_bo == NULL ||
	    error->pinned_bo == NULL ||
	    error->active_bo_count == NULL ||
	    error->pinned_bo_count == NULL) {
		kfree(error->active_bo);
		kfree(error->active_bo_count);
		kfree(error->pinned_bo);
		kfree(error->pinned_bo_count);

		error->active_bo = NULL;
		error->active_bo_count = NULL;
		error->pinned_bo = NULL;
		error->pinned_bo_count = NULL;
	} else {
		list_for_each_entry(vm, &dev_priv->vm_list, global_link)
			i915_gem_capture_vm(dev_priv, error, vm, i++);

		error->vm_count = cnt;
	}
1278 1279
}

1280 1281 1282
/* Capture all registers which don't fit into another category. */
static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
				   struct drm_i915_error_state *error)
1283
{
1284
	struct drm_device *dev = &dev_priv->drm;
1285
	int i;
1286

1287 1288 1289 1290 1291 1292 1293
	/* General organization
	 * 1. Registers specific to a single generation
	 * 2. Registers which belong to multiple generations
	 * 3. Feature specific registers.
	 * 4. Everything else
	 * Please try to follow the order.
	 */
1294

1295 1296
	/* 1: Registers specific to a single generation */
	if (IS_VALLEYVIEW(dev)) {
1297
		error->gtier[0] = I915_READ(GTIER);
1298
		error->ier = I915_READ(VLV_IER);
1299
		error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
1300
	}
1301

1302 1303
	if (IS_GEN7(dev))
		error->err_int = I915_READ(GEN7_ERR_INT);
1304

1305 1306 1307 1308 1309
	if (INTEL_INFO(dev)->gen >= 8) {
		error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
		error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
	}

1310
	if (IS_GEN6(dev)) {
1311
		error->forcewake = I915_READ_FW(FORCEWAKE);
1312 1313 1314
		error->gab_ctl = I915_READ(GAB_CTL);
		error->gfx_mode = I915_READ(GFX_MODE);
	}
1315

1316 1317
	/* 2: Registers which belong to multiple generations */
	if (INTEL_INFO(dev)->gen >= 7)
1318
		error->forcewake = I915_READ_FW(FORCEWAKE_MT);
1319 1320

	if (INTEL_INFO(dev)->gen >= 6) {
1321
		error->derrmr = I915_READ(DERRMR);
1322 1323 1324 1325
		error->error = I915_READ(ERROR_GEN6);
		error->done_reg = I915_READ(DONE_REG);
	}

1326
	/* 3: Feature specific registers */
1327 1328 1329 1330 1331 1332
	if (IS_GEN6(dev) || IS_GEN7(dev)) {
		error->gam_ecochk = I915_READ(GAM_ECOCHK);
		error->gac_eco = I915_READ(GAC_ECO_BITS);
	}

	/* 4: Everything else */
1333 1334 1335
	if (HAS_HW_CONTEXTS(dev))
		error->ccid = I915_READ(CCID);

1336 1337 1338 1339 1340
	if (INTEL_INFO(dev)->gen >= 8) {
		error->ier = I915_READ(GEN8_DE_MISC_IER);
		for (i = 0; i < 4; i++)
			error->gtier[i] = I915_READ(GEN8_GT_IER(i));
	} else if (HAS_PCH_SPLIT(dev)) {
1341
		error->ier = I915_READ(DEIER);
1342
		error->gtier[0] = I915_READ(GTIER);
1343 1344 1345 1346
	} else if (IS_GEN2(dev)) {
		error->ier = I915_READ16(IER);
	} else if (!IS_VALLEYVIEW(dev)) {
		error->ier = I915_READ(IER);
1347 1348 1349
	}
	error->eir = I915_READ(EIR);
	error->pgtbl_er = I915_READ(PGTBL_ER);
1350

1351
	i915_get_extra_instdone(dev_priv, error->extra_instdone);
1352 1353
}

1354
static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
1355
				   struct drm_i915_error_state *error,
1356
				   u32 engine_mask,
1357
				   const char *error_msg)
1358 1359
{
	u32 ecode;
1360
	int engine_id = -1, len;
1361

1362
	ecode = i915_error_generate_code(dev_priv, error, &engine_id);
1363

1364
	len = scnprintf(error->error_msg, sizeof(error->error_msg),
1365
			"GPU HANG: ecode %d:%d:0x%08x",
1366
			INTEL_GEN(dev_priv), engine_id, ecode);
1367

1368
	if (engine_id != -1 && error->engine[engine_id].pid != -1)
1369 1370 1371
		len += scnprintf(error->error_msg + len,
				 sizeof(error->error_msg) - len,
				 ", in %s [%d]",
1372 1373
				 error->engine[engine_id].comm,
				 error->engine[engine_id].pid);
1374 1375 1376 1377

	scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
		  ", reason: %s, action: %s",
		  error_msg,
1378
		  engine_mask ? "reset" : "continue");
1379 1380
}

1381 1382 1383
static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
				   struct drm_i915_error_state *error)
{
1384 1385 1386 1387
	error->iommu = -1;
#ifdef CONFIG_INTEL_IOMMU
	error->iommu = intel_iommu_gfx_mapped;
#endif
1388
	error->reset_count = i915_reset_count(&dev_priv->gpu_error);
1389
	error->suspend_count = dev_priv->suspend_count;
1390 1391
}

1392 1393 1394 1395 1396 1397 1398 1399 1400
/**
 * i915_capture_error_state - capture an error record for later analysis
 * @dev: drm device
 *
 * Should be called when an error is detected (either a hang or an error
 * interrupt) to capture error state from the time of the error.  Fills
 * out a structure which becomes available in debugfs for user level tools
 * to pick up.
 */
1401 1402
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
1403
			      const char *error_msg)
1404
{
1405
	static bool warned;
1406 1407 1408
	struct drm_i915_error_state *error;
	unsigned long flags;

1409 1410 1411
	if (READ_ONCE(dev_priv->gpu_error.first_error))
		return;

1412 1413 1414 1415 1416 1417 1418
	/* Account for pipe specific data like PIPE*STAT */
	error = kzalloc(sizeof(*error), GFP_ATOMIC);
	if (!error) {
		DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
		return;
	}

1419 1420
	kref_init(&error->ref);

1421
	i915_capture_gen_state(dev_priv, error);
1422 1423
	i915_capture_reg_state(dev_priv, error);
	i915_gem_capture_buffers(dev_priv, error);
1424 1425
	i915_gem_record_fences(dev_priv, error);
	i915_gem_record_rings(dev_priv, error);
1426

1427 1428
	do_gettimeofday(&error->time);

1429 1430
	error->overlay = intel_overlay_capture_error_state(dev_priv);
	error->display = intel_display_capture_error_state(dev_priv);
1431

1432
	i915_error_capture_msg(dev_priv, error, engine_mask, error_msg);
1433 1434
	DRM_INFO("%s\n", error->error_msg);

1435 1436 1437 1438 1439 1440 1441
	if (!error->simulated) {
		spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
		if (!dev_priv->gpu_error.first_error) {
			dev_priv->gpu_error.first_error = error;
			error = NULL;
		}
		spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1442 1443
	}

1444
	if (error) {
1445
		i915_error_state_free(&error->ref);
1446 1447 1448 1449 1450 1451 1452 1453
		return;
	}

	if (!warned) {
		DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
		DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
		DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
		DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1454 1455
		DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
			 dev_priv->drm.primary->index);
1456 1457
		warned = true;
	}
1458 1459 1460 1461 1462
}

void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv)
{
1463
	struct drm_i915_private *dev_priv = to_i915(dev);
1464

1465
	spin_lock_irq(&dev_priv->gpu_error.lock);
1466 1467 1468
	error_priv->error = dev_priv->gpu_error.first_error;
	if (error_priv->error)
		kref_get(&error_priv->error->ref);
1469
	spin_unlock_irq(&dev_priv->gpu_error.lock);
1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480

}

void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
{
	if (error_priv->error)
		kref_put(&error_priv->error->ref, i915_error_state_free);
}

void i915_destroy_error_state(struct drm_device *dev)
{
1481
	struct drm_i915_private *dev_priv = to_i915(dev);
1482 1483
	struct drm_i915_error_state *error;

1484
	spin_lock_irq(&dev_priv->gpu_error.lock);
1485 1486
	error = dev_priv->gpu_error.first_error;
	dev_priv->gpu_error.first_error = NULL;
1487
	spin_unlock_irq(&dev_priv->gpu_error.lock);
1488 1489 1490 1491 1492

	if (error)
		kref_put(&error->ref, i915_error_state_free);
}

1493
const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
1494 1495 1496
{
	switch (type) {
	case I915_CACHE_NONE: return " uncached";
1497
	case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
1498
	case I915_CACHE_L3_LLC: return " L3+LLC";
1499
	case I915_CACHE_WT: return " WT";
1500 1501 1502 1503 1504
	default: return "";
	}
}

/* NB: please notice the memset */
1505 1506
void i915_get_extra_instdone(struct drm_i915_private *dev_priv,
			     uint32_t *instdone)
1507 1508 1509
{
	memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);

1510
	if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
1511
		instdone[0] = I915_READ(GEN2_INSTDONE);
1512
	else if (IS_GEN4(dev_priv) || IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) {
1513
		instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
1514
		instdone[1] = I915_READ(GEN4_INSTDONE1);
1515
	} else if (INTEL_GEN(dev_priv) >= 7) {
1516
		instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
1517 1518 1519 1520 1521
		instdone[1] = I915_READ(GEN7_SC_INSTDONE);
		instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
		instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
	}
}