i915_gpu_error.c 40.1 KB
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/*
 * Copyright (c) 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *    Keith Packard <keithp@keithp.com>
 *    Mika Kuoppala <mika.kuoppala@intel.com>
 *
 */

#include <generated/utsrelease.h>
#include "i915_drv.h"

static const char *ring_str(int ring)
{
	switch (ring) {
	case RCS: return "render";
	case VCS: return "bsd";
	case BCS: return "blt";
	case VECS: return "vebox";
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	case VCS2: return "bsd2";
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	default: return "";
	}
}

static const char *pin_flag(int pinned)
{
	if (pinned > 0)
		return " P";
	else if (pinned < 0)
		return " p";
	else
		return "";
}

static const char *tiling_flag(int tiling)
{
	switch (tiling) {
	default:
	case I915_TILING_NONE: return "";
	case I915_TILING_X: return " X";
	case I915_TILING_Y: return " Y";
	}
}

static const char *dirty_flag(int dirty)
{
	return dirty ? " dirty" : "";
}

static const char *purgeable_flag(int purgeable)
{
	return purgeable ? " purgeable" : "";
}

static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
{

	if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
		e->err = -ENOSPC;
		return false;
	}

	if (e->bytes == e->size - 1 || e->err)
		return false;

	return true;
}

static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
			      unsigned len)
{
	if (e->pos + len <= e->start) {
		e->pos += len;
		return false;
	}

	/* First vsnprintf needs to fit in its entirety for memmove */
	if (len >= e->size) {
		e->err = -EIO;
		return false;
	}

	return true;
}

static void __i915_error_advance(struct drm_i915_error_state_buf *e,
				 unsigned len)
{
	/* If this is first printf in this window, adjust it so that
	 * start position matches start of the buffer
	 */

	if (e->pos < e->start) {
		const size_t off = e->start - e->pos;

		/* Should not happen but be paranoid */
		if (off > len || e->bytes) {
			e->err = -EIO;
			return;
		}

		memmove(e->buf, e->buf + off, len - off);
		e->bytes = len - off;
		e->pos = e->start;
		return;
	}

	e->bytes += len;
	e->pos += len;
}

static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
			       const char *f, va_list args)
{
	unsigned len;

	if (!__i915_error_ok(e))
		return;

	/* Seek the first printf which is hits start position */
	if (e->pos < e->start) {
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		va_list tmp;

		va_copy(tmp, args);
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		len = vsnprintf(NULL, 0, f, tmp);
		va_end(tmp);

		if (!__i915_error_seek(e, len))
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			return;
	}

	len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
	if (len >= e->size - e->bytes)
		len = e->size - e->bytes - 1;

	__i915_error_advance(e, len);
}

static void i915_error_puts(struct drm_i915_error_state_buf *e,
			    const char *str)
{
	unsigned len;

	if (!__i915_error_ok(e))
		return;

	len = strlen(str);

	/* Seek the first printf which is hits start position */
	if (e->pos < e->start) {
		if (!__i915_error_seek(e, len))
			return;
	}

	if (len >= e->size - e->bytes)
		len = e->size - e->bytes - 1;
	memcpy(e->buf + e->bytes, str, len);

	__i915_error_advance(e, len);
}

#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
#define err_puts(e, s) i915_error_puts(e, s)

static void print_error_buffers(struct drm_i915_error_state_buf *m,
				const char *name,
				struct drm_i915_error_buffer *err,
				int count)
{
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	int i;

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	err_printf(m, "  %s [%d]:\n", name, count);
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	while (count--) {
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		err_printf(m, "    %08x_%08x %8u %02x %02x [ ",
			   upper_32_bits(err->gtt_offset),
			   lower_32_bits(err->gtt_offset),
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			   err->size,
			   err->read_domains,
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			   err->write_domain);
		for (i = 0; i < I915_NUM_RINGS; i++)
			err_printf(m, "%02x ", err->rseqno[i]);

		err_printf(m, "] %02x", err->wseqno);
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		err_puts(m, pin_flag(err->pinned));
		err_puts(m, tiling_flag(err->tiling));
		err_puts(m, dirty_flag(err->dirty));
		err_puts(m, purgeable_flag(err->purgeable));
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		err_puts(m, err->userptr ? " userptr" : "");
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		err_puts(m, err->ring != -1 ? " " : "");
		err_puts(m, ring_str(err->ring));
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		err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
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		if (err->name)
			err_printf(m, " (name: %d)", err->name);
		if (err->fence_reg != I915_FENCE_REG_NONE)
			err_printf(m, " (fence: %d)", err->fence_reg);

		err_puts(m, "\n");
		err++;
	}
}

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static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
{
	switch (a) {
	case HANGCHECK_IDLE:
		return "idle";
	case HANGCHECK_WAIT:
		return "wait";
	case HANGCHECK_ACTIVE:
		return "active";
	case HANGCHECK_KICK:
		return "kick";
	case HANGCHECK_HUNG:
		return "hung";
	}

	return "unknown";
}

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static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
				  struct drm_device *dev,
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				  struct drm_i915_error_state *error,
				  int ring_idx)
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{
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	struct drm_i915_error_ring *ring = &error->ring[ring_idx];

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	if (!ring->valid)
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		return;

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	err_printf(m, "%s command stream:\n", ring_str(ring_idx));
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	err_printf(m, "  START: 0x%08x\n", ring->start);
	err_printf(m, "  HEAD:  0x%08x\n", ring->head);
	err_printf(m, "  TAIL:  0x%08x\n", ring->tail);
	err_printf(m, "  CTL:   0x%08x\n", ring->ctl);
	err_printf(m, "  HWS:   0x%08x\n", ring->hws);
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	err_printf(m, "  ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
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	err_printf(m, "  IPEIR: 0x%08x\n", ring->ipeir);
	err_printf(m, "  IPEHR: 0x%08x\n", ring->ipehr);
	err_printf(m, "  INSTDONE: 0x%08x\n", ring->instdone);
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	if (INTEL_INFO(dev)->gen >= 4) {
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		err_printf(m, "  BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
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		err_printf(m, "  BB_STATE: 0x%08x\n", ring->bbstate);
		err_printf(m, "  INSTPS: 0x%08x\n", ring->instps);
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	}
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	err_printf(m, "  INSTPM: 0x%08x\n", ring->instpm);
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	err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
		   lower_32_bits(ring->faddr));
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	if (INTEL_INFO(dev)->gen >= 6) {
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		err_printf(m, "  RC PSMI: 0x%08x\n", ring->rc_psmi);
		err_printf(m, "  FAULT_REG: 0x%08x\n", ring->fault_reg);
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		err_printf(m, "  SYNC_0: 0x%08x [last synced 0x%08x]\n",
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			   ring->semaphore_mboxes[0],
			   ring->semaphore_seqno[0]);
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		err_printf(m, "  SYNC_1: 0x%08x [last synced 0x%08x]\n",
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			   ring->semaphore_mboxes[1],
			   ring->semaphore_seqno[1]);
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		if (HAS_VEBOX(dev)) {
			err_printf(m, "  SYNC_2: 0x%08x [last synced 0x%08x]\n",
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				   ring->semaphore_mboxes[2],
				   ring->semaphore_seqno[2]);
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		}
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	}
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	if (USES_PPGTT(dev)) {
		err_printf(m, "  GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);

		if (INTEL_INFO(dev)->gen >= 8) {
			int i;
			for (i = 0; i < 4; i++)
				err_printf(m, "  PDP%d: 0x%016llx\n",
					   i, ring->vm_info.pdp[i]);
		} else {
			err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
				   ring->vm_info.pp_dir_base);
		}
	}
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	err_printf(m, "  seqno: 0x%08x\n", ring->seqno);
	err_printf(m, "  waiting: %s\n", yesno(ring->waiting));
	err_printf(m, "  ring->head: 0x%08x\n", ring->cpu_ring_head);
	err_printf(m, "  ring->tail: 0x%08x\n", ring->cpu_ring_tail);
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	err_printf(m, "  hangcheck: %s [%d]\n",
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		   hangcheck_action_to_str(ring->hangcheck_action),
		   ring->hangcheck_score);
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}

void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
{
	va_list args;

	va_start(args, f);
	i915_error_vprintf(e, f, args);
	va_end(args);
}

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static void print_error_obj(struct drm_i915_error_state_buf *m,
			    struct drm_i915_error_object *obj)
{
	int page, offset, elt;

	for (page = offset = 0; page < obj->page_count; page++) {
		for (elt = 0; elt < PAGE_SIZE/4; elt++) {
			err_printf(m, "%08x :  %08x\n", offset,
				   obj->pages[page][elt]);
			offset += 4;
		}
	}
}

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int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
			    const struct i915_error_state_file_priv *error_priv)
{
	struct drm_device *dev = error_priv->dev;
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct drm_i915_error_state *error = error_priv->error;
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	struct drm_i915_error_object *obj;
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	int i, j, offset, elt;
	int max_hangcheck_score;
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	if (!error) {
		err_printf(m, "no error state collected\n");
		goto out;
	}

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	err_printf(m, "%s\n", error->error_msg);
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	err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
		   error->time.tv_usec);
	err_printf(m, "Kernel: " UTS_RELEASE "\n");
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	max_hangcheck_score = 0;
	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
		if (error->ring[i].hangcheck_score > max_hangcheck_score)
			max_hangcheck_score = error->ring[i].hangcheck_score;
	}
	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
		if (error->ring[i].hangcheck_score == max_hangcheck_score &&
		    error->ring[i].pid != -1) {
			err_printf(m, "Active process (on ring %s): %s [%d]\n",
				   ring_str(i),
				   error->ring[i].comm,
				   error->ring[i].pid);
		}
	}
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	err_printf(m, "Reset count: %u\n", error->reset_count);
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	err_printf(m, "Suspend count: %u\n", error->suspend_count);
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	err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
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	err_printf(m, "PCI Revision: 0x%02x\n", dev->pdev->revision);
	err_printf(m, "PCI Subsystem: %04x:%04x\n",
		   dev->pdev->subsystem_vendor,
		   dev->pdev->subsystem_device);
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	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
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	if (HAS_CSR(dev)) {
		struct intel_csr *csr = &dev_priv->csr;

		err_printf(m, "DMC loaded: %s\n",
			   yesno(csr->dmc_payload != NULL));
		err_printf(m, "DMC fw version: %d.%d\n",
			   CSR_VERSION_MAJOR(csr->version),
			   CSR_VERSION_MINOR(csr->version));
	}

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	err_printf(m, "EIR: 0x%08x\n", error->eir);
	err_printf(m, "IER: 0x%08x\n", error->ier);
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	if (INTEL_INFO(dev)->gen >= 8) {
		for (i = 0; i < 4; i++)
			err_printf(m, "GTIER gt %d: 0x%08x\n", i,
				   error->gtier[i]);
	} else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
		err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
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	err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
	err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
	err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
	err_printf(m, "CCID: 0x%08x\n", error->ccid);
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	err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
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	for (i = 0; i < dev_priv->num_fence_regs; i++)
		err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);

	for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
		err_printf(m, "  INSTDONE_%d: 0x%08x\n", i,
			   error->extra_instdone[i]);

	if (INTEL_INFO(dev)->gen >= 6) {
		err_printf(m, "ERROR: 0x%08x\n", error->error);
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		if (INTEL_INFO(dev)->gen >= 8)
			err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
				   error->fault_data1, error->fault_data0);

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		err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
	}

	if (INTEL_INFO(dev)->gen == 7)
		err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);

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	for (i = 0; i < ARRAY_SIZE(error->ring); i++)
		i915_ring_error_state(m, dev, error, i);
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	for (i = 0; i < error->vm_count; i++) {
		err_printf(m, "vm[%d]\n", i);

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		print_error_buffers(m, "Active",
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				    error->active_bo[i],
				    error->active_bo_count[i]);
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		print_error_buffers(m, "Pinned",
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				    error->pinned_bo[i],
				    error->pinned_bo_count[i]);
	}
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	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
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		obj = error->ring[i].batchbuffer;
		if (obj) {
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			err_puts(m, dev_priv->engine[i].name);
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			if (error->ring[i].pid != -1)
				err_printf(m, " (submitted by %s [%d])",
					   error->ring[i].comm,
					   error->ring[i].pid);
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			err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
				   upper_32_bits(obj->gtt_offset),
				   lower_32_bits(obj->gtt_offset));
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			print_error_obj(m, obj);
		}

		obj = error->ring[i].wa_batchbuffer;
		if (obj) {
			err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
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				   dev_priv->engine[i].name,
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				   lower_32_bits(obj->gtt_offset));
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			print_error_obj(m, obj);
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		}

		if (error->ring[i].num_requests) {
			err_printf(m, "%s --- %d requests\n",
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				   dev_priv->engine[i].name,
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				   error->ring[i].num_requests);
			for (j = 0; j < error->ring[i].num_requests; j++) {
				err_printf(m, "  seqno 0x%08x, emitted %ld, tail 0x%08x\n",
					   error->ring[i].requests[j].seqno,
					   error->ring[i].requests[j].jiffies,
					   error->ring[i].requests[j].tail);
			}
		}

		if ((obj = error->ring[i].ringbuffer)) {
			err_printf(m, "%s --- ringbuffer = 0x%08x\n",
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				   dev_priv->engine[i].name,
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				   lower_32_bits(obj->gtt_offset));
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			print_error_obj(m, obj);
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		}

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		if ((obj = error->ring[i].hws_page)) {
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			u64 hws_offset = obj->gtt_offset;
			u32 *hws_page = &obj->pages[0][0];

			if (i915.enable_execlists) {
				hws_offset += LRC_PPHWSP_PN * PAGE_SIZE;
				hws_page = &obj->pages[LRC_PPHWSP_PN][0];
			}
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			err_printf(m, "%s --- HW Status = 0x%08llx\n",
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				   dev_priv->engine[i].name, hws_offset);
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			offset = 0;
			for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
				err_printf(m, "[%04x] %08x %08x %08x %08x\n",
					   offset,
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					   hws_page[elt],
					   hws_page[elt+1],
					   hws_page[elt+2],
					   hws_page[elt+3]);
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					offset += 16;
			}
		}

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		obj = error->ring[i].wa_ctx;
		if (obj) {
			u64 wa_ctx_offset = obj->gtt_offset;
			u32 *wa_ctx_page = &obj->pages[0][0];
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			struct intel_engine_cs *engine = &dev_priv->engine[RCS];
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			u32 wa_ctx_size = (engine->wa_ctx.indirect_ctx.size +
					   engine->wa_ctx.per_ctx.size);
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			err_printf(m, "%s --- WA ctx batch buffer = 0x%08llx\n",
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				   dev_priv->engine[i].name, wa_ctx_offset);
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			offset = 0;
			for (elt = 0; elt < wa_ctx_size; elt += 4) {
				err_printf(m, "[%04x] %08x %08x %08x %08x\n",
					   offset,
					   wa_ctx_page[elt + 0],
					   wa_ctx_page[elt + 1],
					   wa_ctx_page[elt + 2],
					   wa_ctx_page[elt + 3]);
				offset += 16;
			}
		}

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		if ((obj = error->ring[i].ctx)) {
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			err_printf(m, "%s --- HW Context = 0x%08x\n",
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				   dev_priv->engine[i].name,
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				   lower_32_bits(obj->gtt_offset));
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			print_error_obj(m, obj);
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		}
	}

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	if ((obj = error->semaphore_obj)) {
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		err_printf(m, "Semaphore page = 0x%08x\n",
			   lower_32_bits(obj->gtt_offset));
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		for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
			err_printf(m, "[%04x] %08x %08x %08x %08x\n",
				   elt * 4,
				   obj->pages[0][elt],
				   obj->pages[0][elt+1],
				   obj->pages[0][elt+2],
				   obj->pages[0][elt+3]);
		}
	}

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	if (error->overlay)
		intel_overlay_print_error_state(m, error->overlay);

	if (error->display)
		intel_display_print_error_state(m, dev, error->display);

out:
	if (m->bytes == 0 && m->err)
		return m->err;

	return 0;
}

int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
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			      struct drm_i915_private *i915,
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			      size_t count, loff_t pos)
{
	memset(ebuf, 0, sizeof(*ebuf));
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	ebuf->i915 = i915;
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	/* We need to have enough room to store any i915_error_state printf
	 * so that we can move it to start position.
	 */
	ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
	ebuf->buf = kmalloc(ebuf->size,
				GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);

	if (ebuf->buf == NULL) {
		ebuf->size = PAGE_SIZE;
		ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
	}

	if (ebuf->buf == NULL) {
		ebuf->size = 128;
		ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
	}

	if (ebuf->buf == NULL)
		return -ENOMEM;

	ebuf->start = pos;

	return 0;
}

static void i915_error_object_free(struct drm_i915_error_object *obj)
{
	int page;

	if (obj == NULL)
		return;

	for (page = 0; page < obj->page_count; page++)
		kfree(obj->pages[page]);

	kfree(obj);
}

static void i915_error_state_free(struct kref *error_ref)
{
	struct drm_i915_error_state *error = container_of(error_ref,
							  typeof(*error), ref);
	int i;

	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
		i915_error_object_free(error->ring[i].batchbuffer);
603
		i915_error_object_free(error->ring[i].wa_batchbuffer);
604
		i915_error_object_free(error->ring[i].ringbuffer);
605
		i915_error_object_free(error->ring[i].hws_page);
606 607
		i915_error_object_free(error->ring[i].ctx);
		kfree(error->ring[i].requests);
608
		i915_error_object_free(error->ring[i].wa_ctx);
609 610
	}

611
	i915_error_object_free(error->semaphore_obj);
612 613 614 615

	for (i = 0; i < error->vm_count; i++)
		kfree(error->active_bo[i]);

616
	kfree(error->active_bo);
617 618 619
	kfree(error->active_bo_count);
	kfree(error->pinned_bo);
	kfree(error->pinned_bo_count);
620 621 622 623 624 625
	kfree(error->overlay);
	kfree(error->display);
	kfree(error);
}

static struct drm_i915_error_object *
626 627 628
i915_error_object_create(struct drm_i915_private *dev_priv,
			 struct drm_i915_gem_object *src,
			 struct i915_address_space *vm)
629 630
{
	struct drm_i915_error_object *dst;
631
	struct i915_vma *vma = NULL;
632
	int num_pages;
633 634
	bool use_ggtt;
	int i = 0;
635
	u64 reloc_offset;
636 637 638 639

	if (src == NULL || src->pages == NULL)
		return NULL;

640 641
	num_pages = src->base.size >> PAGE_SHIFT;

642 643 644 645
	dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
	if (dst == NULL)
		return NULL;

646 647 648 649
	if (i915_gem_obj_bound(src, vm))
		dst->gtt_offset = i915_gem_obj_offset(src, vm);
	else
		dst->gtt_offset = -1;
650 651

	reloc_offset = dst->gtt_offset;
652 653
	if (i915_is_ggtt(vm))
		vma = i915_gem_obj_to_ggtt(src);
654
	use_ggtt = (src->cache_level == I915_CACHE_NONE &&
655 656
		   vma && (vma->bound & GLOBAL_BIND) &&
		   reloc_offset + num_pages * PAGE_SIZE <= dev_priv->gtt.mappable_end);
657 658 659 660 661

	/* Cannot access stolen address directly, try to use the aperture */
	if (src->stolen) {
		use_ggtt = true;

662
		if (!(vma && vma->bound & GLOBAL_BIND))
663 664 665 666 667 668 669 670 671 672 673 674 675
			goto unwind;

		reloc_offset = i915_gem_obj_ggtt_offset(src);
		if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->gtt.mappable_end)
			goto unwind;
	}

	/* Cannot access snooped pages through the aperture */
	if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev))
		goto unwind;

	dst->page_count = num_pages;
	while (num_pages--) {
676 677 678 679 680 681 682 683
		unsigned long flags;
		void *d;

		d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
		if (d == NULL)
			goto unwind;

		local_irq_save(flags);
684
		if (use_ggtt) {
685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711
			void __iomem *s;

			/* Simply ignore tiling or any overlapping fence.
			 * It's part of the error state, and this hopefully
			 * captures what the GPU read.
			 */

			s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
						     reloc_offset);
			memcpy_fromio(d, s, PAGE_SIZE);
			io_mapping_unmap_atomic(s);
		} else {
			struct page *page;
			void *s;

			page = i915_gem_object_get_page(src, i);

			drm_clflush_pages(&page, 1);

			s = kmap_atomic(page);
			memcpy(d, s, PAGE_SIZE);
			kunmap_atomic(s);

			drm_clflush_pages(&page, 1);
		}
		local_irq_restore(flags);

712
		dst->pages[i++] = d;
713 714 715 716 717 718 719 720 721 722 723
		reloc_offset += PAGE_SIZE;
	}

	return dst;

unwind:
	while (i--)
		kfree(dst->pages[i]);
	kfree(dst);
	return NULL;
}
724
#define i915_error_ggtt_object_create(dev_priv, src) \
725
	i915_error_object_create((dev_priv), (src), &(dev_priv)->gtt.base)
726 727

static void capture_bo(struct drm_i915_error_buffer *err,
728
		       struct i915_vma *vma)
729
{
730
	struct drm_i915_gem_object *obj = vma->obj;
731
	int i;
732

733 734
	err->size = obj->base.size;
	err->name = obj->base.name;
735 736
	for (i = 0; i < I915_NUM_RINGS; i++)
		err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]);
737
	err->wseqno = i915_gem_request_get_seqno(obj->last_write_req);
738
	err->gtt_offset = vma->node.start;
739 740 741 742
	err->read_domains = obj->base.read_domains;
	err->write_domain = obj->base.write_domain;
	err->fence_reg = obj->fence_reg;
	err->pinned = 0;
B
Ben Widawsky 已提交
743
	if (i915_gem_obj_is_pinned(obj))
744 745 746 747
		err->pinned = 1;
	err->tiling = obj->tiling_mode;
	err->dirty = obj->dirty;
	err->purgeable = obj->madv != I915_MADV_WILLNEED;
748
	err->userptr = obj->userptr.mm != NULL;
749 750
	err->ring = obj->last_write_req ?
			i915_gem_request_get_ring(obj->last_write_req)->id : -1;
751 752 753 754 755 756
	err->cache_level = obj->cache_level;
}

static u32 capture_active_bo(struct drm_i915_error_buffer *err,
			     int count, struct list_head *head)
{
B
Ben Widawsky 已提交
757
	struct i915_vma *vma;
758 759
	int i = 0;

760
	list_for_each_entry(vma, head, vm_link) {
761
		capture_bo(err++, vma);
762 763 764 765 766 767 768 769
		if (++i == count)
			break;
	}

	return i;
}

static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
770 771
			     int count, struct list_head *head,
			     struct i915_address_space *vm)
772 773
{
	struct drm_i915_gem_object *obj;
774 775
	struct drm_i915_error_buffer * const first = err;
	struct drm_i915_error_buffer * const last = err + count;
776 777

	list_for_each_entry(obj, head, global_list) {
778
		struct i915_vma *vma;
779

780
		if (err == last)
781
			break;
782

783
		list_for_each_entry(vma, &obj->vma_list, obj_link)
784
			if (vma->vm == vm && vma->pin_count > 0)
785
				capture_bo(err++, vma);
786 787
	}

788
	return err - first;
789 790
}

791 792 793 794 795 796 797 798 799 800
/* Generate a semi-unique error code. The code is not meant to have meaning, The
 * code's only purpose is to try to prevent false duplicated bug reports by
 * grossly estimating a GPU error state.
 *
 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
 * the hang if we could strip the GTT offset information from it.
 *
 * It's only a small step better than a random number in its current form.
 */
static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
801 802
					 struct drm_i915_error_state *error,
					 int *ring_id)
803 804 805 806 807 808 809 810 811
{
	uint32_t error_code = 0;
	int i;

	/* IPEHR would be an ideal way to detect errors, as it's the gross
	 * measure of "the command that hung." However, has some very common
	 * synchronization commands which almost always appear in the case
	 * strictly a client bug. Use instdone to differentiate those some.
	 */
812 813 814 815 816
	for (i = 0; i < I915_NUM_RINGS; i++) {
		if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
			if (ring_id)
				*ring_id = i;

817
			return error->ring[i].ipehr ^ error->ring[i].instdone;
818 819
		}
	}
820 821 822 823

	return error_code;
}

824 825 826 827 828 829
static void i915_gem_record_fences(struct drm_device *dev,
				   struct drm_i915_error_state *error)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

830 831
	if (IS_GEN3(dev) || IS_GEN2(dev)) {
		for (i = 0; i < dev_priv->num_fence_regs; i++)
832 833 834 835 836 837 838 839
			error->fence[i] = I915_READ(FENCE_REG(i));
	} else if (IS_GEN5(dev) || IS_GEN4(dev)) {
		for (i = 0; i < dev_priv->num_fence_regs; i++)
			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
	} else if (INTEL_INFO(dev)->gen >= 6) {
		for (i = 0; i < dev_priv->num_fence_regs; i++)
			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
	}
840 841
}

842

843 844
static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
					struct drm_i915_error_state *error,
845
					struct intel_engine_cs *engine,
846 847
					struct drm_i915_error_ring *ering)
{
848
	struct intel_engine_cs *to;
849 850 851 852 853 854 855
	int i;

	if (!i915_semaphore_is_enabled(dev_priv->dev))
		return;

	if (!error->semaphore_obj)
		error->semaphore_obj =
856 857
			i915_error_ggtt_object_create(dev_priv,
						      dev_priv->semaphore_obj);
858

859 860 861 862
	for_each_ring(to, dev_priv, i) {
		int idx;
		u16 signal_offset;
		u32 *tmp;
863

864
		if (engine == to)
865 866
			continue;

867
		signal_offset = (GEN8_SIGNAL_OFFSET(engine, i) & (PAGE_SIZE - 1))
868
				/ 4;
869
		tmp = error->semaphore_obj->pages[0];
870
		idx = intel_ring_sync_index(engine, to);
871 872

		ering->semaphore_mboxes[idx] = tmp[signal_offset];
873
		ering->semaphore_seqno[idx] = engine->semaphore.sync_seqno[idx];
874 875 876
	}
}

877
static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
878
					struct intel_engine_cs *engine,
879 880
					struct drm_i915_error_ring *ering)
{
881 882 883 884
	ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
	ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
	ering->semaphore_seqno[0] = engine->semaphore.sync_seqno[0];
	ering->semaphore_seqno[1] = engine->semaphore.sync_seqno[1];
885 886 887

	if (HAS_VEBOX(dev_priv->dev)) {
		ering->semaphore_mboxes[2] =
888 889
			I915_READ(RING_SYNC_2(engine->mmio_base));
		ering->semaphore_seqno[2] = engine->semaphore.sync_seqno[2];
890 891 892
	}
}

893
static void i915_record_ring_state(struct drm_device *dev,
894
				   struct drm_i915_error_state *error,
895
				   struct intel_engine_cs *engine,
896
				   struct drm_i915_error_ring *ering)
897 898 899 900
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (INTEL_INFO(dev)->gen >= 6) {
901 902
		ering->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
		ering->fault_reg = I915_READ(RING_FAULT_REG(engine));
903
		if (INTEL_INFO(dev)->gen >= 8)
904 905
			gen8_record_semaphore_state(dev_priv, error, engine,
						    ering);
906
		else
907
			gen6_record_semaphore_state(dev_priv, engine, ering);
908 909
	}

910
	if (INTEL_INFO(dev)->gen >= 4) {
911 912 913 914 915 916
		ering->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
		ering->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
		ering->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
		ering->instdone = I915_READ(RING_INSTDONE(engine->mmio_base));
		ering->instps = I915_READ(RING_INSTPS(engine->mmio_base));
		ering->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
917
		if (INTEL_INFO(dev)->gen >= 8) {
918 919
			ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
			ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
920
		}
921
		ering->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
922
	} else {
923 924 925
		ering->faddr = I915_READ(DMA_FADD_I8XX);
		ering->ipeir = I915_READ(IPEIR);
		ering->ipehr = I915_READ(IPEHR);
926
		ering->instdone = I915_READ(GEN2_INSTDONE);
927 928
	}

929 930 931 932 933 934 935 936
	ering->waiting = waitqueue_active(&engine->irq_queue);
	ering->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
	ering->seqno = engine->get_seqno(engine, false);
	ering->acthd = intel_ring_get_active_head(engine);
	ering->start = I915_READ_START(engine);
	ering->head = I915_READ_HEAD(engine);
	ering->tail = I915_READ_TAIL(engine);
	ering->ctl = I915_READ_CTL(engine);
937

938
	if (I915_NEED_GFX_HWS(dev)) {
939
		i915_reg_t mmio;
940 941

		if (IS_GEN7(dev)) {
942
			switch (engine->id) {
943 944 945 946 947 948 949 950 951 952 953 954 955 956
			default:
			case RCS:
				mmio = RENDER_HWS_PGA_GEN7;
				break;
			case BCS:
				mmio = BLT_HWS_PGA_GEN7;
				break;
			case VCS:
				mmio = BSD_HWS_PGA_GEN7;
				break;
			case VECS:
				mmio = VEBOX_HWS_PGA_GEN7;
				break;
			}
957 958
		} else if (IS_GEN6(engine->dev)) {
			mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
959 960
		} else {
			/* XXX: gen8 returns to sanity */
961
			mmio = RING_HWS_PGA(engine->mmio_base);
962 963
		}

964
		ering->hws = I915_READ(mmio);
965 966
	}

967 968
	ering->hangcheck_score = engine->hangcheck.score;
	ering->hangcheck_action = engine->hangcheck.action;
969 970 971 972

	if (USES_PPGTT(dev)) {
		int i;

973
		ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
974

975 976
		if (IS_GEN6(dev))
			ering->vm_info.pp_dir_base =
977
				I915_READ(RING_PP_DIR_BASE_READ(engine));
978 979
		else if (IS_GEN7(dev))
			ering->vm_info.pp_dir_base =
980
				I915_READ(RING_PP_DIR_BASE(engine));
981
		else if (INTEL_INFO(dev)->gen >= 8)
982 983
			for (i = 0; i < 4; i++) {
				ering->vm_info.pdp[i] =
984
					I915_READ(GEN8_RING_PDP_UDW(engine, i));
985 986
				ering->vm_info.pdp[i] <<= 32;
				ering->vm_info.pdp[i] |=
987
					I915_READ(GEN8_RING_PDP_LDW(engine, i));
988 989
			}
	}
990 991 992
}


993
static void i915_gem_record_active_context(struct intel_engine_cs *engine,
994 995 996
					   struct drm_i915_error_state *error,
					   struct drm_i915_error_ring *ering)
{
997
	struct drm_i915_private *dev_priv = engine->dev->dev_private;
998 999 1000
	struct drm_i915_gem_object *obj;

	/* Currently render ring is the only HW context user */
1001
	if (engine->id != RCS || !error->ccid)
1002 1003 1004
		return;

	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1005 1006 1007
		if (!i915_gem_obj_ggtt_bound(obj))
			continue;

1008
		if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
1009
			ering->ctx = i915_error_ggtt_object_create(dev_priv, obj);
1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021
			break;
		}
	}
}

static void i915_gem_record_rings(struct drm_device *dev,
				  struct drm_i915_error_state *error)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_request *request;
	int i, count;

1022
	for (i = 0; i < I915_NUM_RINGS; i++) {
1023
		struct intel_engine_cs *engine = &dev_priv->engine[i];
1024
		struct intel_ringbuffer *rbuf;
1025

1026 1027
		error->ring[i].pid = -1;

1028
		if (engine->dev == NULL)
1029 1030 1031 1032
			continue;

		error->ring[i].valid = true;

1033
		i915_record_ring_state(dev, error, engine, &error->ring[i]);
1034

1035
		request = i915_gem_find_active_request(engine);
1036
		if (request) {
1037 1038 1039 1040 1041 1042
			struct i915_address_space *vm;

			vm = request->ctx && request->ctx->ppgtt ?
				&request->ctx->ppgtt->base :
				&dev_priv->gtt.base;

1043 1044 1045 1046 1047 1048 1049
			/* We need to copy these to an anonymous buffer
			 * as the simplest method to avoid being overwritten
			 * by userspace.
			 */
			error->ring[i].batchbuffer =
				i915_error_object_create(dev_priv,
							 request->batch_obj,
1050
							 vm);
1051

1052
			if (HAS_BROKEN_CS_TLB(dev_priv->dev))
1053 1054
				error->ring[i].wa_batchbuffer =
					i915_error_ggtt_object_create(dev_priv,
1055
							     engine->scratch.obj);
1056

1057
			if (request->pid) {
1058 1059 1060
				struct task_struct *task;

				rcu_read_lock();
1061
				task = pid_task(request->pid, PIDTYPE_PID);
1062 1063 1064 1065 1066 1067 1068
				if (task) {
					strcpy(error->ring[i].comm, task->comm);
					error->ring[i].pid = task->pid;
				}
				rcu_read_unlock();
			}
		}
1069

1070 1071 1072 1073 1074 1075 1076
		if (i915.enable_execlists) {
			/* TODO: This is only a small fix to keep basic error
			 * capture working, but we need to add more information
			 * for it to be useful (e.g. dump the context being
			 * executed).
			 */
			if (request)
1077
				rbuf = request->ctx->engine[engine->id].ringbuf;
1078
			else
1079
				rbuf = dev_priv->kernel_context->engine[engine->id].ringbuf;
1080
		} else
1081
			rbuf = engine->buffer;
1082 1083 1084 1085

		error->ring[i].cpu_ring_head = rbuf->head;
		error->ring[i].cpu_ring_tail = rbuf->tail;

1086
		error->ring[i].ringbuffer =
1087
			i915_error_ggtt_object_create(dev_priv, rbuf->obj);
1088

1089
		error->ring[i].hws_page =
1090 1091
			i915_error_ggtt_object_create(dev_priv,
						      engine->status_page.obj);
1092

1093
		if (engine->wa_ctx.obj) {
1094 1095
			error->ring[i].wa_ctx =
				i915_error_ggtt_object_create(dev_priv,
1096
							      engine->wa_ctx.obj);
1097 1098
		}

1099
		i915_gem_record_active_context(engine, error, &error->ring[i]);
1100 1101

		count = 0;
1102
		list_for_each_entry(request, &engine->request_list, list)
1103 1104 1105 1106
			count++;

		error->ring[i].num_requests = count;
		error->ring[i].requests =
D
Daniel Vetter 已提交
1107
			kcalloc(count, sizeof(*error->ring[i].requests),
1108 1109 1110 1111 1112 1113 1114
				GFP_ATOMIC);
		if (error->ring[i].requests == NULL) {
			error->ring[i].num_requests = 0;
			continue;
		}

		count = 0;
1115
		list_for_each_entry(request, &engine->request_list, list) {
1116 1117
			struct drm_i915_error_request *erq;

1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136
			if (count >= error->ring[i].num_requests) {
				/*
				 * If the ring request list was changed in
				 * between the point where the error request
				 * list was created and dimensioned and this
				 * point then just exit early to avoid crashes.
				 *
				 * We don't need to communicate that the
				 * request list changed state during error
				 * state capture and that the error state is
				 * slightly incorrect as a consequence since we
				 * are typically only interested in the request
				 * list state at the point of error state
				 * capture, not in any changes happening during
				 * the capture.
				 */
				break;
			}

1137 1138 1139
			erq = &error->ring[i].requests[count++];
			erq->seqno = request->seqno;
			erq->jiffies = request->emitted_jiffies;
1140
			erq->tail = request->postfix;
1141 1142 1143 1144
		}
	}
}

1145 1146 1147 1148 1149 1150 1151
/* FIXME: Since pin count/bound list is global, we duplicate what we capture per
 * VM.
 */
static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
				struct drm_i915_error_state *error,
				struct i915_address_space *vm,
				const int ndx)
1152
{
1153
	struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
1154
	struct drm_i915_gem_object *obj;
1155
	struct i915_vma *vma;
1156 1157 1158
	int i;

	i = 0;
1159
	list_for_each_entry(vma, &vm->active_list, vm_link)
1160
		i++;
1161
	error->active_bo_count[ndx] = i;
1162 1163

	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1164
		list_for_each_entry(vma, &obj->vma_list, obj_link)
1165
			if (vma->vm == vm && vma->pin_count > 0)
1166 1167
				i++;
	}
1168
	error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
1169 1170

	if (i) {
D
Daniel Vetter 已提交
1171
		active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
1172 1173
		if (active_bo)
			pinned_bo = active_bo + error->active_bo_count[ndx];
1174 1175
	}

1176 1177 1178 1179
	if (active_bo)
		error->active_bo_count[ndx] =
			capture_active_bo(active_bo,
					  error->active_bo_count[ndx],
1180
					  &vm->active_list);
1181

1182 1183 1184 1185
	if (pinned_bo)
		error->pinned_bo_count[ndx] =
			capture_pinned_bo(pinned_bo,
					  error->pinned_bo_count[ndx],
1186
					  &dev_priv->mm.bound_list, vm);
1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206
	error->active_bo[ndx] = active_bo;
	error->pinned_bo[ndx] = pinned_bo;
}

static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
				     struct drm_i915_error_state *error)
{
	struct i915_address_space *vm;
	int cnt = 0, i = 0;

	list_for_each_entry(vm, &dev_priv->vm_list, global_link)
		cnt++;

	error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
	error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
	error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
					 GFP_ATOMIC);
	error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
					 GFP_ATOMIC);

1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225
	if (error->active_bo == NULL ||
	    error->pinned_bo == NULL ||
	    error->active_bo_count == NULL ||
	    error->pinned_bo_count == NULL) {
		kfree(error->active_bo);
		kfree(error->active_bo_count);
		kfree(error->pinned_bo);
		kfree(error->pinned_bo_count);

		error->active_bo = NULL;
		error->active_bo_count = NULL;
		error->pinned_bo = NULL;
		error->pinned_bo_count = NULL;
	} else {
		list_for_each_entry(vm, &dev_priv->vm_list, global_link)
			i915_gem_capture_vm(dev_priv, error, vm, i++);

		error->vm_count = cnt;
	}
1226 1227
}

1228 1229 1230
/* Capture all registers which don't fit into another category. */
static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
				   struct drm_i915_error_state *error)
1231
{
1232
	struct drm_device *dev = dev_priv->dev;
1233
	int i;
1234

1235 1236 1237 1238 1239 1240 1241
	/* General organization
	 * 1. Registers specific to a single generation
	 * 2. Registers which belong to multiple generations
	 * 3. Feature specific registers.
	 * 4. Everything else
	 * Please try to follow the order.
	 */
1242

1243 1244
	/* 1: Registers specific to a single generation */
	if (IS_VALLEYVIEW(dev)) {
1245
		error->gtier[0] = I915_READ(GTIER);
1246
		error->ier = I915_READ(VLV_IER);
1247
		error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
1248
	}
1249

1250 1251
	if (IS_GEN7(dev))
		error->err_int = I915_READ(GEN7_ERR_INT);
1252

1253 1254 1255 1256 1257
	if (INTEL_INFO(dev)->gen >= 8) {
		error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
		error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
	}

1258
	if (IS_GEN6(dev)) {
1259
		error->forcewake = I915_READ_FW(FORCEWAKE);
1260 1261 1262
		error->gab_ctl = I915_READ(GAB_CTL);
		error->gfx_mode = I915_READ(GFX_MODE);
	}
1263

1264 1265
	/* 2: Registers which belong to multiple generations */
	if (INTEL_INFO(dev)->gen >= 7)
1266
		error->forcewake = I915_READ_FW(FORCEWAKE_MT);
1267 1268

	if (INTEL_INFO(dev)->gen >= 6) {
1269
		error->derrmr = I915_READ(DERRMR);
1270 1271 1272 1273
		error->error = I915_READ(ERROR_GEN6);
		error->done_reg = I915_READ(DONE_REG);
	}

1274
	/* 3: Feature specific registers */
1275 1276 1277 1278 1279 1280
	if (IS_GEN6(dev) || IS_GEN7(dev)) {
		error->gam_ecochk = I915_READ(GAM_ECOCHK);
		error->gac_eco = I915_READ(GAC_ECO_BITS);
	}

	/* 4: Everything else */
1281 1282 1283
	if (HAS_HW_CONTEXTS(dev))
		error->ccid = I915_READ(CCID);

1284 1285 1286 1287 1288
	if (INTEL_INFO(dev)->gen >= 8) {
		error->ier = I915_READ(GEN8_DE_MISC_IER);
		for (i = 0; i < 4; i++)
			error->gtier[i] = I915_READ(GEN8_GT_IER(i));
	} else if (HAS_PCH_SPLIT(dev)) {
1289
		error->ier = I915_READ(DEIER);
1290
		error->gtier[0] = I915_READ(GTIER);
1291 1292 1293 1294
	} else if (IS_GEN2(dev)) {
		error->ier = I915_READ16(IER);
	} else if (!IS_VALLEYVIEW(dev)) {
		error->ier = I915_READ(IER);
1295 1296 1297
	}
	error->eir = I915_READ(EIR);
	error->pgtbl_er = I915_READ(PGTBL_ER);
1298 1299

	i915_get_extra_instdone(dev, error->extra_instdone);
1300 1301
}

1302
static void i915_error_capture_msg(struct drm_device *dev,
1303 1304 1305
				   struct drm_i915_error_state *error,
				   bool wedged,
				   const char *error_msg)
1306 1307 1308
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 ecode;
1309
	int ring_id = -1, len;
1310 1311 1312

	ecode = i915_error_generate_code(dev_priv, error, &ring_id);

1313
	len = scnprintf(error->error_msg, sizeof(error->error_msg),
1314 1315
			"GPU HANG: ecode %d:%d:0x%08x",
			INTEL_INFO(dev)->gen, ring_id, ecode);
1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327

	if (ring_id != -1 && error->ring[ring_id].pid != -1)
		len += scnprintf(error->error_msg + len,
				 sizeof(error->error_msg) - len,
				 ", in %s [%d]",
				 error->ring[ring_id].comm,
				 error->ring[ring_id].pid);

	scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
		  ", reason: %s, action: %s",
		  error_msg,
		  wedged ? "reset" : "continue");
1328 1329
}

1330 1331 1332
static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
				   struct drm_i915_error_state *error)
{
1333 1334 1335 1336
	error->iommu = -1;
#ifdef CONFIG_INTEL_IOMMU
	error->iommu = intel_iommu_gfx_mapped;
#endif
1337
	error->reset_count = i915_reset_count(&dev_priv->gpu_error);
1338
	error->suspend_count = dev_priv->suspend_count;
1339 1340
}

1341 1342 1343 1344 1345 1346 1347 1348 1349
/**
 * i915_capture_error_state - capture an error record for later analysis
 * @dev: drm device
 *
 * Should be called when an error is detected (either a hang or an error
 * interrupt) to capture error state from the time of the error.  Fills
 * out a structure which becomes available in debugfs for user level tools
 * to pick up.
 */
1350 1351
void i915_capture_error_state(struct drm_device *dev, bool wedged,
			      const char *error_msg)
1352
{
1353
	static bool warned;
1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_error_state *error;
	unsigned long flags;

	/* Account for pipe specific data like PIPE*STAT */
	error = kzalloc(sizeof(*error), GFP_ATOMIC);
	if (!error) {
		DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
		return;
	}

1365 1366
	kref_init(&error->ref);

1367
	i915_capture_gen_state(dev_priv, error);
1368 1369 1370 1371
	i915_capture_reg_state(dev_priv, error);
	i915_gem_capture_buffers(dev_priv, error);
	i915_gem_record_fences(dev, error);
	i915_gem_record_rings(dev, error);
1372

1373 1374 1375 1376 1377
	do_gettimeofday(&error->time);

	error->overlay = intel_overlay_capture_error_state(dev);
	error->display = intel_display_capture_error_state(dev);

1378
	i915_error_capture_msg(dev, error, wedged, error_msg);
1379 1380
	DRM_INFO("%s\n", error->error_msg);

1381 1382 1383 1384 1385 1386 1387
	spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
	if (dev_priv->gpu_error.first_error == NULL) {
		dev_priv->gpu_error.first_error = error;
		error = NULL;
	}
	spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);

1388
	if (error) {
1389
		i915_error_state_free(&error->ref);
1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400
		return;
	}

	if (!warned) {
		DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
		DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
		DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
		DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
		DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
		warned = true;
	}
1401 1402 1403 1404 1405 1406 1407
}

void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1408
	spin_lock_irq(&dev_priv->gpu_error.lock);
1409 1410 1411
	error_priv->error = dev_priv->gpu_error.first_error;
	if (error_priv->error)
		kref_get(&error_priv->error->ref);
1412
	spin_unlock_irq(&dev_priv->gpu_error.lock);
1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426

}

void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
{
	if (error_priv->error)
		kref_put(&error_priv->error->ref, i915_error_state_free);
}

void i915_destroy_error_state(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_error_state *error;

1427
	spin_lock_irq(&dev_priv->gpu_error.lock);
1428 1429
	error = dev_priv->gpu_error.first_error;
	dev_priv->gpu_error.first_error = NULL;
1430
	spin_unlock_irq(&dev_priv->gpu_error.lock);
1431 1432 1433 1434 1435

	if (error)
		kref_put(&error->ref, i915_error_state_free);
}

1436
const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
1437 1438 1439
{
	switch (type) {
	case I915_CACHE_NONE: return " uncached";
1440
	case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
1441
	case I915_CACHE_L3_LLC: return " L3+LLC";
1442
	case I915_CACHE_WT: return " WT";
1443 1444 1445 1446 1447 1448 1449 1450 1451 1452
	default: return "";
	}
}

/* NB: please notice the memset */
void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);

1453
	if (IS_GEN2(dev) || IS_GEN3(dev))
1454
		instdone[0] = I915_READ(GEN2_INSTDONE);
1455
	else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
1456
		instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
1457
		instdone[1] = I915_READ(GEN4_INSTDONE1);
1458
	} else if (INTEL_INFO(dev)->gen >= 7) {
1459
		instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
1460 1461 1462 1463 1464
		instdone[1] = I915_READ(GEN7_SC_INSTDONE);
		instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
		instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
	}
}