i915_gpu_error.c 40.7 KB
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/*
 * Copyright (c) 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *    Keith Packard <keithp@keithp.com>
 *    Mika Kuoppala <mika.kuoppala@intel.com>
 *
 */

#include <generated/utsrelease.h>
#include "i915_drv.h"

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static const char *engine_str(int engine)
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{
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	switch (engine) {
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	case RCS: return "render";
	case VCS: return "bsd";
	case BCS: return "blt";
	case VECS: return "vebox";
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	case VCS2: return "bsd2";
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	default: return "";
	}
}

static const char *tiling_flag(int tiling)
{
	switch (tiling) {
	default:
	case I915_TILING_NONE: return "";
	case I915_TILING_X: return " X";
	case I915_TILING_Y: return " Y";
	}
}

static const char *dirty_flag(int dirty)
{
	return dirty ? " dirty" : "";
}

static const char *purgeable_flag(int purgeable)
{
	return purgeable ? " purgeable" : "";
}

static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
{

	if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
		e->err = -ENOSPC;
		return false;
	}

	if (e->bytes == e->size - 1 || e->err)
		return false;

	return true;
}

static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
			      unsigned len)
{
	if (e->pos + len <= e->start) {
		e->pos += len;
		return false;
	}

	/* First vsnprintf needs to fit in its entirety for memmove */
	if (len >= e->size) {
		e->err = -EIO;
		return false;
	}

	return true;
}

static void __i915_error_advance(struct drm_i915_error_state_buf *e,
				 unsigned len)
{
	/* If this is first printf in this window, adjust it so that
	 * start position matches start of the buffer
	 */

	if (e->pos < e->start) {
		const size_t off = e->start - e->pos;

		/* Should not happen but be paranoid */
		if (off > len || e->bytes) {
			e->err = -EIO;
			return;
		}

		memmove(e->buf, e->buf + off, len - off);
		e->bytes = len - off;
		e->pos = e->start;
		return;
	}

	e->bytes += len;
	e->pos += len;
}

static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
			       const char *f, va_list args)
{
	unsigned len;

	if (!__i915_error_ok(e))
		return;

	/* Seek the first printf which is hits start position */
	if (e->pos < e->start) {
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		va_list tmp;

		va_copy(tmp, args);
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		len = vsnprintf(NULL, 0, f, tmp);
		va_end(tmp);

		if (!__i915_error_seek(e, len))
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			return;
	}

	len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
	if (len >= e->size - e->bytes)
		len = e->size - e->bytes - 1;

	__i915_error_advance(e, len);
}

static void i915_error_puts(struct drm_i915_error_state_buf *e,
			    const char *str)
{
	unsigned len;

	if (!__i915_error_ok(e))
		return;

	len = strlen(str);

	/* Seek the first printf which is hits start position */
	if (e->pos < e->start) {
		if (!__i915_error_seek(e, len))
			return;
	}

	if (len >= e->size - e->bytes)
		len = e->size - e->bytes - 1;
	memcpy(e->buf + e->bytes, str, len);

	__i915_error_advance(e, len);
}

#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
#define err_puts(e, s) i915_error_puts(e, s)

static void print_error_buffers(struct drm_i915_error_state_buf *m,
				const char *name,
				struct drm_i915_error_buffer *err,
				int count)
{
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	int i;

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	err_printf(m, "%s [%d]:\n", name, count);
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	while (count--) {
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		err_printf(m, "    %08x_%08x %8u %02x %02x [ ",
			   upper_32_bits(err->gtt_offset),
			   lower_32_bits(err->gtt_offset),
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			   err->size,
			   err->read_domains,
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			   err->write_domain);
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		for (i = 0; i < I915_NUM_ENGINES; i++)
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			err_printf(m, "%02x ", err->rseqno[i]);

		err_printf(m, "] %02x", err->wseqno);
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		err_puts(m, tiling_flag(err->tiling));
		err_puts(m, dirty_flag(err->dirty));
		err_puts(m, purgeable_flag(err->purgeable));
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		err_puts(m, err->userptr ? " userptr" : "");
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		err_puts(m, err->engine != -1 ? " " : "");
		err_puts(m, engine_str(err->engine));
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		err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
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		if (err->name)
			err_printf(m, " (name: %d)", err->name);
		if (err->fence_reg != I915_FENCE_REG_NONE)
			err_printf(m, " (fence: %d)", err->fence_reg);

		err_puts(m, "\n");
		err++;
	}
}

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static const char *hangcheck_action_to_str(enum intel_engine_hangcheck_action a)
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{
	switch (a) {
	case HANGCHECK_IDLE:
		return "idle";
	case HANGCHECK_WAIT:
		return "wait";
	case HANGCHECK_ACTIVE:
		return "active";
	case HANGCHECK_KICK:
		return "kick";
	case HANGCHECK_HUNG:
		return "hung";
	}

	return "unknown";
}

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static void error_print_engine(struct drm_i915_error_state_buf *m,
			       struct drm_i915_error_engine *ee)
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{
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	err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
	err_printf(m, "  START: 0x%08x\n", ee->start);
	err_printf(m, "  HEAD:  0x%08x\n", ee->head);
	err_printf(m, "  TAIL:  0x%08x\n", ee->tail);
	err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
	err_printf(m, "  HWS:   0x%08x\n", ee->hws);
	err_printf(m, "  ACTHD: 0x%08x %08x\n",
		   (u32)(ee->acthd>>32), (u32)ee->acthd);
	err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
	err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
	err_printf(m, "  INSTDONE: 0x%08x\n", ee->instdone);
	if (INTEL_GEN(m->i915) >= 4) {
		err_printf(m, "  BBADDR: 0x%08x %08x\n",
			   (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
		err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
		err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
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	}
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	err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
	err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
		   lower_32_bits(ee->faddr));
	if (INTEL_GEN(m->i915) >= 6) {
		err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
		err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
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		err_printf(m, "  SYNC_0: 0x%08x [last synced 0x%08x]\n",
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			   ee->semaphore_mboxes[0],
			   ee->semaphore_seqno[0]);
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		err_printf(m, "  SYNC_1: 0x%08x [last synced 0x%08x]\n",
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			   ee->semaphore_mboxes[1],
			   ee->semaphore_seqno[1]);
		if (HAS_VEBOX(m->i915)) {
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			err_printf(m, "  SYNC_2: 0x%08x [last synced 0x%08x]\n",
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				   ee->semaphore_mboxes[2],
				   ee->semaphore_seqno[2]);
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		}
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	}
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	if (USES_PPGTT(m->i915)) {
		err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
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		if (INTEL_GEN(m->i915) >= 8) {
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			int i;
			for (i = 0; i < 4; i++)
				err_printf(m, "  PDP%d: 0x%016llx\n",
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					   i, ee->vm_info.pdp[i]);
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		} else {
			err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
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				   ee->vm_info.pp_dir_base);
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		}
	}
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	err_printf(m, "  seqno: 0x%08x\n", ee->seqno);
	err_printf(m, "  last_seqno: 0x%08x\n", ee->last_seqno);
	err_printf(m, "  waiting: %s\n", yesno(ee->waiting));
	err_printf(m, "  ring->head: 0x%08x\n", ee->cpu_ring_head);
	err_printf(m, "  ring->tail: 0x%08x\n", ee->cpu_ring_tail);
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	err_printf(m, "  hangcheck: %s [%d]\n",
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		   hangcheck_action_to_str(ee->hangcheck_action),
		   ee->hangcheck_score);
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}

void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
{
	va_list args;

	va_start(args, f);
	i915_error_vprintf(e, f, args);
	va_end(args);
}

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static void print_error_obj(struct drm_i915_error_state_buf *m,
			    struct drm_i915_error_object *obj)
{
	int page, offset, elt;

	for (page = offset = 0; page < obj->page_count; page++) {
		for (elt = 0; elt < PAGE_SIZE/4; elt++) {
			err_printf(m, "%08x :  %08x\n", offset,
				   obj->pages[page][elt]);
			offset += 4;
		}
	}
}

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static void err_print_capabilities(struct drm_i915_error_state_buf *m,
				   const struct intel_device_info *info)
{
#define PRINT_FLAG(x)  err_printf(m, #x ": %s\n", yesno(info->x))
#define SEP_SEMICOLON ;
	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
#undef PRINT_FLAG
#undef SEP_SEMICOLON
}

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int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
			    const struct i915_error_state_file_priv *error_priv)
{
	struct drm_device *dev = error_priv->dev;
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	struct drm_i915_private *dev_priv = to_i915(dev);
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	struct drm_i915_error_state *error = error_priv->error;
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	struct drm_i915_error_object *obj;
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	int i, j, offset, elt;
	int max_hangcheck_score;
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	if (!error) {
		err_printf(m, "no error state collected\n");
		goto out;
	}

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	err_printf(m, "%s\n", error->error_msg);
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	err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
		   error->time.tv_usec);
	err_printf(m, "Kernel: " UTS_RELEASE "\n");
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	err_print_capabilities(m, &error->device_info);
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	max_hangcheck_score = 0;
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	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		if (error->engine[i].hangcheck_score > max_hangcheck_score)
			max_hangcheck_score = error->engine[i].hangcheck_score;
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	}
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	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		if (error->engine[i].hangcheck_score == max_hangcheck_score &&
		    error->engine[i].pid != -1) {
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			err_printf(m, "Active process (on ring %s): %s [%d]\n",
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				   engine_str(i),
				   error->engine[i].comm,
				   error->engine[i].pid);
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		}
	}
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	err_printf(m, "Reset count: %u\n", error->reset_count);
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	err_printf(m, "Suspend count: %u\n", error->suspend_count);
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	err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
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	err_printf(m, "PCI Revision: 0x%02x\n", dev->pdev->revision);
	err_printf(m, "PCI Subsystem: %04x:%04x\n",
		   dev->pdev->subsystem_vendor,
		   dev->pdev->subsystem_device);
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	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
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	if (HAS_CSR(dev)) {
		struct intel_csr *csr = &dev_priv->csr;

		err_printf(m, "DMC loaded: %s\n",
			   yesno(csr->dmc_payload != NULL));
		err_printf(m, "DMC fw version: %d.%d\n",
			   CSR_VERSION_MAJOR(csr->version),
			   CSR_VERSION_MINOR(csr->version));
	}

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	err_printf(m, "EIR: 0x%08x\n", error->eir);
	err_printf(m, "IER: 0x%08x\n", error->ier);
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	if (INTEL_INFO(dev)->gen >= 8) {
		for (i = 0; i < 4; i++)
			err_printf(m, "GTIER gt %d: 0x%08x\n", i,
				   error->gtier[i]);
	} else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
		err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
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	err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
	err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
	err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
	err_printf(m, "CCID: 0x%08x\n", error->ccid);
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	err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
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	for (i = 0; i < dev_priv->num_fence_regs; i++)
		err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);

	for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
		err_printf(m, "  INSTDONE_%d: 0x%08x\n", i,
			   error->extra_instdone[i]);

	if (INTEL_INFO(dev)->gen >= 6) {
		err_printf(m, "ERROR: 0x%08x\n", error->error);
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		if (INTEL_INFO(dev)->gen >= 8)
			err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
				   error->fault_data1, error->fault_data0);

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		err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
	}

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	if (IS_GEN7(dev))
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		err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);

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	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		if (error->engine[i].engine_id != -1)
			error_print_engine(m, &error->engine[i]);
	}
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	for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {
		char buf[128];
		int len, first = 1;
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		if (!error->active_vm[i])
			break;

		len = scnprintf(buf, sizeof(buf), "Active (");
		for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
			if (error->engine[j].vm != error->active_vm[i])
				continue;

			len += scnprintf(buf + len, sizeof(buf), "%s%s",
					 first ? "" : ", ",
					 dev_priv->engine[j].name);
			first = 0;
		}
		scnprintf(buf + len, sizeof(buf), ")");
		print_error_buffers(m, buf,
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				    error->active_bo[i],
				    error->active_bo_count[i]);
	}
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	print_error_buffers(m, "Pinned (global)",
			    error->pinned_bo,
			    error->pinned_bo_count);

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	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		struct drm_i915_error_engine *ee = &error->engine[i];

		obj = ee->batchbuffer;
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		if (obj) {
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			err_puts(m, dev_priv->engine[i].name);
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			if (ee->pid != -1)
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				err_printf(m, " (submitted by %s [%d])",
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					   ee->comm,
					   ee->pid);
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			err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
				   upper_32_bits(obj->gtt_offset),
				   lower_32_bits(obj->gtt_offset));
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			print_error_obj(m, obj);
		}

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		obj = ee->wa_batchbuffer;
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		if (obj) {
			err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
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				   dev_priv->engine[i].name,
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				   lower_32_bits(obj->gtt_offset));
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			print_error_obj(m, obj);
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		}

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		if (ee->num_requests) {
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			err_printf(m, "%s --- %d requests\n",
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				   dev_priv->engine[i].name,
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				   ee->num_requests);
			for (j = 0; j < ee->num_requests; j++) {
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				err_printf(m, "  seqno 0x%08x, emitted %ld, head 0x%08x, tail 0x%08x\n",
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					   ee->requests[j].seqno,
					   ee->requests[j].jiffies,
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					   ee->requests[j].head,
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					   ee->requests[j].tail);
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			}
		}

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		if (ee->num_waiters) {
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			err_printf(m, "%s --- %d waiters\n",
				   dev_priv->engine[i].name,
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				   ee->num_waiters);
			for (j = 0; j < ee->num_waiters; j++) {
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				err_printf(m, " seqno 0x%08x for %s [%d]\n",
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					   ee->waiters[j].seqno,
					   ee->waiters[j].comm,
					   ee->waiters[j].pid);
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			}
		}

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		if ((obj = ee->ringbuffer)) {
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			err_printf(m, "%s --- ringbuffer = 0x%08x\n",
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				   dev_priv->engine[i].name,
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				   lower_32_bits(obj->gtt_offset));
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			print_error_obj(m, obj);
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		}

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		if ((obj = ee->hws_page)) {
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			u64 hws_offset = obj->gtt_offset;
			u32 *hws_page = &obj->pages[0][0];

			if (i915.enable_execlists) {
				hws_offset += LRC_PPHWSP_PN * PAGE_SIZE;
				hws_page = &obj->pages[LRC_PPHWSP_PN][0];
			}
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			err_printf(m, "%s --- HW Status = 0x%08llx\n",
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				   dev_priv->engine[i].name, hws_offset);
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			offset = 0;
			for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
				err_printf(m, "[%04x] %08x %08x %08x %08x\n",
					   offset,
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					   hws_page[elt],
					   hws_page[elt+1],
					   hws_page[elt+2],
					   hws_page[elt+3]);
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				offset += 16;
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			}
		}

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		obj = ee->wa_ctx;
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		if (obj) {
			u64 wa_ctx_offset = obj->gtt_offset;
			u32 *wa_ctx_page = &obj->pages[0][0];
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			struct intel_engine_cs *engine = &dev_priv->engine[RCS];
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			u32 wa_ctx_size = (engine->wa_ctx.indirect_ctx.size +
					   engine->wa_ctx.per_ctx.size);
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			err_printf(m, "%s --- WA ctx batch buffer = 0x%08llx\n",
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				   dev_priv->engine[i].name, wa_ctx_offset);
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			offset = 0;
			for (elt = 0; elt < wa_ctx_size; elt += 4) {
				err_printf(m, "[%04x] %08x %08x %08x %08x\n",
					   offset,
					   wa_ctx_page[elt + 0],
					   wa_ctx_page[elt + 1],
					   wa_ctx_page[elt + 2],
					   wa_ctx_page[elt + 3]);
				offset += 16;
			}
		}

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		if ((obj = ee->ctx)) {
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			err_printf(m, "%s --- HW Context = 0x%08x\n",
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				   dev_priv->engine[i].name,
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				   lower_32_bits(obj->gtt_offset));
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			print_error_obj(m, obj);
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		}
	}

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	if ((obj = error->semaphore_obj)) {
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		err_printf(m, "Semaphore page = 0x%08x\n",
			   lower_32_bits(obj->gtt_offset));
555 556 557 558 559 560 561 562 563 564
		for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
			err_printf(m, "[%04x] %08x %08x %08x %08x\n",
				   elt * 4,
				   obj->pages[0][elt],
				   obj->pages[0][elt+1],
				   obj->pages[0][elt+2],
				   obj->pages[0][elt+3]);
		}
	}

565 566 567 568 569 570 571 572 573 574 575 576 577 578
	if (error->overlay)
		intel_overlay_print_error_state(m, error->overlay);

	if (error->display)
		intel_display_print_error_state(m, dev, error->display);

out:
	if (m->bytes == 0 && m->err)
		return m->err;

	return 0;
}

int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
579
			      struct drm_i915_private *i915,
580 581 582
			      size_t count, loff_t pos)
{
	memset(ebuf, 0, sizeof(*ebuf));
583
	ebuf->i915 = i915;
584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628

	/* We need to have enough room to store any i915_error_state printf
	 * so that we can move it to start position.
	 */
	ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
	ebuf->buf = kmalloc(ebuf->size,
				GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);

	if (ebuf->buf == NULL) {
		ebuf->size = PAGE_SIZE;
		ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
	}

	if (ebuf->buf == NULL) {
		ebuf->size = 128;
		ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
	}

	if (ebuf->buf == NULL)
		return -ENOMEM;

	ebuf->start = pos;

	return 0;
}

static void i915_error_object_free(struct drm_i915_error_object *obj)
{
	int page;

	if (obj == NULL)
		return;

	for (page = 0; page < obj->page_count; page++)
		kfree(obj->pages[page]);

	kfree(obj);
}

static void i915_error_state_free(struct kref *error_ref)
{
	struct drm_i915_error_state *error = container_of(error_ref,
							  typeof(*error), ref);
	int i;

629 630 631 632 633 634 635 636 637 638 639 640
	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		struct drm_i915_error_engine *ee = &error->engine[i];

		i915_error_object_free(ee->batchbuffer);
		i915_error_object_free(ee->wa_batchbuffer);
		i915_error_object_free(ee->ringbuffer);
		i915_error_object_free(ee->hws_page);
		i915_error_object_free(ee->ctx);
		i915_error_object_free(ee->wa_ctx);

		kfree(ee->requests);
		kfree(ee->waiters);
641 642
	}

643
	i915_error_object_free(error->semaphore_obj);
644

645
	for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
646 647
		kfree(error->active_bo[i]);
	kfree(error->pinned_bo);
648

649 650 651 652 653 654
	kfree(error->overlay);
	kfree(error->display);
	kfree(error);
}

static struct drm_i915_error_object *
655 656 657
i915_error_object_create(struct drm_i915_private *dev_priv,
			 struct drm_i915_gem_object *src,
			 struct i915_address_space *vm)
658
{
659
	struct i915_ggtt *ggtt = &dev_priv->ggtt;
660
	struct drm_i915_error_object *dst;
661
	struct i915_vma *vma = NULL;
662
	int num_pages;
663 664
	bool use_ggtt;
	int i = 0;
665
	u64 reloc_offset;
666 667 668 669

	if (src == NULL || src->pages == NULL)
		return NULL;

670 671
	num_pages = src->base.size >> PAGE_SHIFT;

672 673 674 675
	dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
	if (dst == NULL)
		return NULL;

676 677 678 679
	if (i915_gem_obj_bound(src, vm))
		dst->gtt_offset = i915_gem_obj_offset(src, vm);
	else
		dst->gtt_offset = -1;
680 681

	reloc_offset = dst->gtt_offset;
682 683
	if (i915_is_ggtt(vm))
		vma = i915_gem_obj_to_ggtt(src);
684
	use_ggtt = (src->cache_level == I915_CACHE_NONE &&
685
		   vma && (vma->flags & I915_VMA_GLOBAL_BIND) &&
686
		   reloc_offset + num_pages * PAGE_SIZE <= ggtt->mappable_end);
687 688 689 690 691

	/* Cannot access stolen address directly, try to use the aperture */
	if (src->stolen) {
		use_ggtt = true;

692
		if (!(vma && vma->flags & I915_VMA_GLOBAL_BIND))
693 694 695
			goto unwind;

		reloc_offset = i915_gem_obj_ggtt_offset(src);
696
		if (reloc_offset + num_pages * PAGE_SIZE > ggtt->mappable_end)
697 698 699 700
			goto unwind;
	}

	/* Cannot access snooped pages through the aperture */
701 702
	if (use_ggtt && src->cache_level != I915_CACHE_NONE &&
	    !HAS_LLC(dev_priv))
703 704 705 706
		goto unwind;

	dst->page_count = num_pages;
	while (num_pages--) {
707 708 709 710 711 712 713 714
		unsigned long flags;
		void *d;

		d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
		if (d == NULL)
			goto unwind;

		local_irq_save(flags);
715
		if (use_ggtt) {
716 717 718 719 720 721 722
			void __iomem *s;

			/* Simply ignore tiling or any overlapping fence.
			 * It's part of the error state, and this hopefully
			 * captures what the GPU read.
			 */

723
			s = io_mapping_map_atomic_wc(ggtt->mappable,
724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742
						     reloc_offset);
			memcpy_fromio(d, s, PAGE_SIZE);
			io_mapping_unmap_atomic(s);
		} else {
			struct page *page;
			void *s;

			page = i915_gem_object_get_page(src, i);

			drm_clflush_pages(&page, 1);

			s = kmap_atomic(page);
			memcpy(d, s, PAGE_SIZE);
			kunmap_atomic(s);

			drm_clflush_pages(&page, 1);
		}
		local_irq_restore(flags);

743
		dst->pages[i++] = d;
744 745 746 747 748 749 750 751 752 753 754
		reloc_offset += PAGE_SIZE;
	}

	return dst;

unwind:
	while (i--)
		kfree(dst->pages[i]);
	kfree(dst);
	return NULL;
}
755
#define i915_error_ggtt_object_create(dev_priv, src) \
756
	i915_error_object_create((dev_priv), (src), &(dev_priv)->ggtt.base)
757

758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775
/* The error capture is special as tries to run underneath the normal
 * locking rules - so we use the raw version of the i915_gem_active lookup.
 */
static inline uint32_t
__active_get_seqno(struct i915_gem_active *active)
{
	return i915_gem_request_get_seqno(__i915_gem_active_peek(active));
}

static inline int
__active_get_engine_id(struct i915_gem_active *active)
{
	struct intel_engine_cs *engine;

	engine = i915_gem_request_get_engine(__i915_gem_active_peek(active));
	return engine ? engine->id : -1;
}

776
static void capture_bo(struct drm_i915_error_buffer *err,
777
		       struct i915_vma *vma)
778
{
779
	struct drm_i915_gem_object *obj = vma->obj;
780
	int i;
781

782 783
	err->size = obj->base.size;
	err->name = obj->base.name;
784

785
	for (i = 0; i < I915_NUM_ENGINES; i++)
786 787 788 789
		err->rseqno[i] = __active_get_seqno(&obj->last_read[i]);
	err->wseqno = __active_get_seqno(&obj->last_write);
	err->engine = __active_get_engine_id(&obj->last_write);

790
	err->gtt_offset = vma->node.start;
791 792 793
	err->read_domains = obj->base.read_domains;
	err->write_domain = obj->base.write_domain;
	err->fence_reg = obj->fence_reg;
794
	err->tiling = i915_gem_object_get_tiling(obj);
795 796
	err->dirty = obj->dirty;
	err->purgeable = obj->madv != I915_MADV_WILLNEED;
797
	err->userptr = obj->userptr.mm != NULL;
798 799 800
	err->cache_level = obj->cache_level;
}

801 802 803
static u32 capture_error_bo(struct drm_i915_error_buffer *err,
			    int count, struct list_head *head,
			    bool pinned_only)
804
{
B
Ben Widawsky 已提交
805
	struct i915_vma *vma;
806 807
	int i = 0;

808
	list_for_each_entry(vma, head, vm_link) {
809 810 811
		if (pinned_only && !i915_vma_is_pinned(vma))
			continue;

812
		capture_bo(err++, vma);
813 814 815 816 817 818 819
		if (++i == count)
			break;
	}

	return i;
}

820 821 822 823 824 825 826 827 828 829
/* Generate a semi-unique error code. The code is not meant to have meaning, The
 * code's only purpose is to try to prevent false duplicated bug reports by
 * grossly estimating a GPU error state.
 *
 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
 * the hang if we could strip the GTT offset information from it.
 *
 * It's only a small step better than a random number in its current form.
 */
static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
830
					 struct drm_i915_error_state *error,
831
					 int *engine_id)
832 833 834 835 836 837 838 839 840
{
	uint32_t error_code = 0;
	int i;

	/* IPEHR would be an ideal way to detect errors, as it's the gross
	 * measure of "the command that hung." However, has some very common
	 * synchronization commands which almost always appear in the case
	 * strictly a client bug. Use instdone to differentiate those some.
	 */
841
	for (i = 0; i < I915_NUM_ENGINES; i++) {
842 843 844
		if (error->engine[i].hangcheck_action == HANGCHECK_HUNG) {
			if (engine_id)
				*engine_id = i;
845

846
			return error->engine[i].ipehr ^ error->engine[i].instdone;
847 848
		}
	}
849 850 851 852

	return error_code;
}

853
static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
854 855 856 857
				   struct drm_i915_error_state *error)
{
	int i;

858
	if (IS_GEN3(dev_priv) || IS_GEN2(dev_priv)) {
859
		for (i = 0; i < dev_priv->num_fence_regs; i++)
860
			error->fence[i] = I915_READ(FENCE_REG(i));
861
	} else if (IS_GEN5(dev_priv) || IS_GEN4(dev_priv)) {
862 863
		for (i = 0; i < dev_priv->num_fence_regs; i++)
			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
864
	} else if (INTEL_GEN(dev_priv) >= 6) {
865 866 867
		for (i = 0; i < dev_priv->num_fence_regs; i++)
			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
	}
868 869
}

870

871
static void gen8_record_semaphore_state(struct drm_i915_error_state *error,
872
					struct intel_engine_cs *engine,
873
					struct drm_i915_error_engine *ee)
874
{
875
	struct drm_i915_private *dev_priv = engine->i915;
876
	struct intel_engine_cs *to;
877
	enum intel_engine_id id;
878 879

	if (!error->semaphore_obj)
880
		return;
881

882
	for_each_engine_id(to, dev_priv, id) {
883 884 885
		int idx;
		u16 signal_offset;
		u32 *tmp;
886

887
		if (engine == to)
888 889
			continue;

890 891
		signal_offset =
			(GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1)) / 4;
892
		tmp = error->semaphore_obj->pages[0];
893
		idx = intel_engine_sync_index(engine, to);
894

895 896
		ee->semaphore_mboxes[idx] = tmp[signal_offset];
		ee->semaphore_seqno[idx] = engine->semaphore.sync_seqno[idx];
897 898 899
	}
}

900 901
static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
					struct drm_i915_error_engine *ee)
902
{
903 904 905 906 907 908
	struct drm_i915_private *dev_priv = engine->i915;

	ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
	ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
	ee->semaphore_seqno[0] = engine->semaphore.sync_seqno[0];
	ee->semaphore_seqno[1] = engine->semaphore.sync_seqno[1];
909

910
	if (HAS_VEBOX(dev_priv)) {
911
		ee->semaphore_mboxes[2] =
912
			I915_READ(RING_SYNC_2(engine->mmio_base));
913
		ee->semaphore_seqno[2] = engine->semaphore.sync_seqno[2];
914 915 916
	}
}

917 918
static void error_record_engine_waiters(struct intel_engine_cs *engine,
					struct drm_i915_error_engine *ee)
919 920 921 922 923 924
{
	struct intel_breadcrumbs *b = &engine->breadcrumbs;
	struct drm_i915_error_waiter *waiter;
	struct rb_node *rb;
	int count;

925 926
	ee->num_waiters = 0;
	ee->waiters = NULL;
927 928 929 930 931 932 933 934 935 936 937 938 939 940 941

	spin_lock(&b->lock);
	count = 0;
	for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb))
		count++;
	spin_unlock(&b->lock);

	waiter = NULL;
	if (count)
		waiter = kmalloc_array(count,
				       sizeof(struct drm_i915_error_waiter),
				       GFP_ATOMIC);
	if (!waiter)
		return;

942
	ee->waiters = waiter;
943 944 945 946 947 948 949 950 951 952

	spin_lock(&b->lock);
	for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
		struct intel_wait *w = container_of(rb, typeof(*w), node);

		strcpy(waiter->comm, w->tsk->comm);
		waiter->pid = w->tsk->pid;
		waiter->seqno = w->seqno;
		waiter++;

953
		if (++ee->num_waiters == count)
954 955 956 957 958
			break;
	}
	spin_unlock(&b->lock);
}

959 960 961
static void error_record_engine_registers(struct drm_i915_error_state *error,
					  struct intel_engine_cs *engine,
					  struct drm_i915_error_engine *ee)
962
{
963 964
	struct drm_i915_private *dev_priv = engine->i915;

965
	if (INTEL_GEN(dev_priv) >= 6) {
966 967
		ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
		ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
968
		if (INTEL_GEN(dev_priv) >= 8)
969
			gen8_record_semaphore_state(error, engine, ee);
970
		else
971
			gen6_record_semaphore_state(engine, ee);
972 973
	}

974
	if (INTEL_GEN(dev_priv) >= 4) {
975 976 977 978 979 980
		ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
		ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
		ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
		ee->instdone = I915_READ(RING_INSTDONE(engine->mmio_base));
		ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
		ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
981
		if (INTEL_GEN(dev_priv) >= 8) {
982 983
			ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
			ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
984
		}
985
		ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
986
	} else {
987 988 989 990
		ee->faddr = I915_READ(DMA_FADD_I8XX);
		ee->ipeir = I915_READ(IPEIR);
		ee->ipehr = I915_READ(IPEHR);
		ee->instdone = I915_READ(GEN2_INSTDONE);
991 992
	}

993 994
	ee->waiting = intel_engine_has_waiter(engine);
	ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
995
	ee->acthd = intel_engine_get_active_head(engine);
996 997 998 999 1000 1001
	ee->seqno = intel_engine_get_seqno(engine);
	ee->last_seqno = engine->last_submitted_seqno;
	ee->start = I915_READ_START(engine);
	ee->head = I915_READ_HEAD(engine);
	ee->tail = I915_READ_TAIL(engine);
	ee->ctl = I915_READ_CTL(engine);
1002

1003
	if (I915_NEED_GFX_HWS(dev_priv)) {
1004
		i915_reg_t mmio;
1005

1006
		if (IS_GEN7(dev_priv)) {
1007
			switch (engine->id) {
1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021
			default:
			case RCS:
				mmio = RENDER_HWS_PGA_GEN7;
				break;
			case BCS:
				mmio = BLT_HWS_PGA_GEN7;
				break;
			case VCS:
				mmio = BSD_HWS_PGA_GEN7;
				break;
			case VECS:
				mmio = VEBOX_HWS_PGA_GEN7;
				break;
			}
1022
		} else if (IS_GEN6(engine->i915)) {
1023
			mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1024 1025
		} else {
			/* XXX: gen8 returns to sanity */
1026
			mmio = RING_HWS_PGA(engine->mmio_base);
1027 1028
		}

1029
		ee->hws = I915_READ(mmio);
1030 1031
	}

1032 1033
	ee->hangcheck_score = engine->hangcheck.score;
	ee->hangcheck_action = engine->hangcheck.action;
1034

1035
	if (USES_PPGTT(dev_priv)) {
1036 1037
		int i;

1038
		ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
1039

1040
		if (IS_GEN6(dev_priv))
1041
			ee->vm_info.pp_dir_base =
1042
				I915_READ(RING_PP_DIR_BASE_READ(engine));
1043
		else if (IS_GEN7(dev_priv))
1044
			ee->vm_info.pp_dir_base =
1045
				I915_READ(RING_PP_DIR_BASE(engine));
1046
		else if (INTEL_GEN(dev_priv) >= 8)
1047
			for (i = 0; i < 4; i++) {
1048
				ee->vm_info.pdp[i] =
1049
					I915_READ(GEN8_RING_PDP_UDW(engine, i));
1050 1051
				ee->vm_info.pdp[i] <<= 32;
				ee->vm_info.pdp[i] |=
1052
					I915_READ(GEN8_RING_PDP_LDW(engine, i));
1053 1054
			}
	}
1055 1056
}

1057
static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
1058 1059
				  struct drm_i915_error_state *error)
{
1060
	struct i915_ggtt *ggtt = &dev_priv->ggtt;
1061 1062 1063
	struct drm_i915_gem_request *request;
	int i, count;

1064 1065 1066 1067 1068 1069
	if (dev_priv->semaphore_obj) {
		error->semaphore_obj =
			i915_error_ggtt_object_create(dev_priv,
						      dev_priv->semaphore_obj);
	}

1070
	for (i = 0; i < I915_NUM_ENGINES; i++) {
1071
		struct intel_engine_cs *engine = &dev_priv->engine[i];
1072
		struct drm_i915_error_engine *ee = &error->engine[i];
1073

1074 1075
		ee->pid = -1;
		ee->engine_id = -1;
1076

1077
		if (!intel_engine_initialized(engine))
1078 1079
			continue;

1080
		ee->engine_id = i;
1081

1082 1083
		error_record_engine_registers(error, engine, ee);
		error_record_engine_waiters(engine, ee);
1084

1085
		request = i915_gem_find_active_request(engine);
1086
		if (request) {
1087
			struct intel_ring *ring;
1088

1089
			ee->vm = request->ctx->ppgtt ?
1090
				&request->ctx->ppgtt->base : &ggtt->base;
1091

1092 1093 1094 1095
			/* We need to copy these to an anonymous buffer
			 * as the simplest method to avoid being overwritten
			 * by userspace.
			 */
1096
			ee->batchbuffer =
1097 1098
				i915_error_object_create(dev_priv,
							 request->batch_obj,
1099
							 ee->vm);
1100

1101
			if (HAS_BROKEN_CS_TLB(dev_priv))
1102
				ee->wa_batchbuffer =
1103
					i915_error_ggtt_object_create(dev_priv,
1104
								      engine->scratch->obj);
1105

1106 1107 1108 1109
			if (request->ctx->engine[i].state) {
				ee->ctx = i915_error_ggtt_object_create(dev_priv,
									request->ctx->engine[i].state->obj);
			}
1110

1111
			if (request->pid) {
1112 1113 1114
				struct task_struct *task;

				rcu_read_lock();
1115
				task = pid_task(request->pid, PIDTYPE_PID);
1116
				if (task) {
1117 1118
					strcpy(ee->comm, task->comm);
					ee->pid = task->pid;
1119 1120 1121
				}
				rcu_read_unlock();
			}
1122

1123 1124 1125
			error->simulated |=
				request->ctx->flags & CONTEXT_NO_ERROR_CAPTURE;

1126 1127 1128
			ring = request->ring;
			ee->cpu_ring_head = ring->head;
			ee->cpu_ring_tail = ring->tail;
1129
			ee->ringbuffer =
1130
				i915_error_ggtt_object_create(dev_priv,
1131
							      ring->vma->obj);
1132
		}
1133

1134
		ee->hws_page =
1135
			i915_error_ggtt_object_create(dev_priv,
1136
						      engine->status_page.vma->obj);
1137

1138 1139
		ee->wa_ctx = i915_error_ggtt_object_create(dev_priv,
							   engine->wa_ctx.obj);
1140

1141
		count = 0;
1142
		list_for_each_entry(request, &engine->request_list, link)
1143 1144
			count++;

1145 1146 1147 1148 1149
		ee->num_requests = count;
		ee->requests =
			kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
		if (!ee->requests) {
			ee->num_requests = 0;
1150 1151 1152 1153
			continue;
		}

		count = 0;
1154
		list_for_each_entry(request, &engine->request_list, link) {
1155 1156
			struct drm_i915_error_request *erq;

1157
			if (count >= ee->num_requests) {
1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175
				/*
				 * If the ring request list was changed in
				 * between the point where the error request
				 * list was created and dimensioned and this
				 * point then just exit early to avoid crashes.
				 *
				 * We don't need to communicate that the
				 * request list changed state during error
				 * state capture and that the error state is
				 * slightly incorrect as a consequence since we
				 * are typically only interested in the request
				 * list state at the point of error state
				 * capture, not in any changes happening during
				 * the capture.
				 */
				break;
			}

1176
			erq = &ee->requests[count++];
1177
			erq->seqno = request->fence.seqno;
1178
			erq->jiffies = request->emitted_jiffies;
1179 1180
			erq->head = request->head;
			erq->tail = request->tail;
1181 1182 1183 1184
		}
	}
}

1185 1186 1187
static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
				struct drm_i915_error_state *error,
				struct i915_address_space *vm,
1188
				int idx)
1189
{
1190
	struct drm_i915_error_buffer *active_bo;
1191
	struct i915_vma *vma;
1192
	int count;
1193

1194
	count = 0;
1195
	list_for_each_entry(vma, &vm->active_list, vm_link)
1196
		count++;
1197

1198 1199 1200
	active_bo = NULL;
	if (count)
		active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC);
1201
	if (active_bo)
1202 1203 1204 1205 1206 1207 1208
		count = capture_error_bo(active_bo, count, &vm->active_list, false);
	else
		count = 0;

	error->active_vm[idx] = vm;
	error->active_bo[idx] = active_bo;
	error->active_bo_count[idx] = count;
1209 1210
}

1211 1212
static void i915_capture_active_buffers(struct drm_i915_private *dev_priv,
					struct drm_i915_error_state *error)
1213
{
1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226
	int cnt = 0, i, j;

	BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
	BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));
	BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));

	/* Scan each engine looking for unique active contexts/vm */
	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		struct drm_i915_error_engine *ee = &error->engine[i];
		bool found;

		if (!ee->vm)
			continue;
1227

1228 1229 1230 1231 1232
		found = false;
		for (j = 0; j < i && !found; j++)
			found = error->engine[j].vm == ee->vm;
		if (!found)
			i915_gem_capture_vm(dev_priv, error, ee->vm, cnt++);
1233
	}
1234 1235
}

1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266
static void i915_capture_pinned_buffers(struct drm_i915_private *dev_priv,
					struct drm_i915_error_state *error)
{
	struct i915_address_space *vm = &dev_priv->ggtt.base;
	struct drm_i915_error_buffer *bo;
	struct i915_vma *vma;
	int count_inactive, count_active;

	count_inactive = 0;
	list_for_each_entry(vma, &vm->active_list, vm_link)
		count_inactive++;

	count_active = 0;
	list_for_each_entry(vma, &vm->inactive_list, vm_link)
		count_active++;

	bo = NULL;
	if (count_inactive + count_active)
		bo = kcalloc(count_inactive + count_active,
			     sizeof(*bo), GFP_ATOMIC);
	if (!bo)
		return;

	count_inactive = capture_error_bo(bo, count_inactive,
					  &vm->active_list, true);
	count_active = capture_error_bo(bo + count_inactive, count_active,
					&vm->inactive_list, true);
	error->pinned_bo_count = count_inactive + count_active;
	error->pinned_bo = bo;
}

1267 1268 1269
/* Capture all registers which don't fit into another category. */
static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
				   struct drm_i915_error_state *error)
1270
{
1271
	struct drm_device *dev = &dev_priv->drm;
1272
	int i;
1273

1274 1275 1276 1277 1278 1279 1280
	/* General organization
	 * 1. Registers specific to a single generation
	 * 2. Registers which belong to multiple generations
	 * 3. Feature specific registers.
	 * 4. Everything else
	 * Please try to follow the order.
	 */
1281

1282 1283
	/* 1: Registers specific to a single generation */
	if (IS_VALLEYVIEW(dev)) {
1284
		error->gtier[0] = I915_READ(GTIER);
1285
		error->ier = I915_READ(VLV_IER);
1286
		error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
1287
	}
1288

1289 1290
	if (IS_GEN7(dev))
		error->err_int = I915_READ(GEN7_ERR_INT);
1291

1292 1293 1294 1295 1296
	if (INTEL_INFO(dev)->gen >= 8) {
		error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
		error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
	}

1297
	if (IS_GEN6(dev)) {
1298
		error->forcewake = I915_READ_FW(FORCEWAKE);
1299 1300 1301
		error->gab_ctl = I915_READ(GAB_CTL);
		error->gfx_mode = I915_READ(GFX_MODE);
	}
1302

1303 1304
	/* 2: Registers which belong to multiple generations */
	if (INTEL_INFO(dev)->gen >= 7)
1305
		error->forcewake = I915_READ_FW(FORCEWAKE_MT);
1306 1307

	if (INTEL_INFO(dev)->gen >= 6) {
1308
		error->derrmr = I915_READ(DERRMR);
1309 1310 1311 1312
		error->error = I915_READ(ERROR_GEN6);
		error->done_reg = I915_READ(DONE_REG);
	}

1313
	/* 3: Feature specific registers */
1314 1315 1316 1317 1318 1319
	if (IS_GEN6(dev) || IS_GEN7(dev)) {
		error->gam_ecochk = I915_READ(GAM_ECOCHK);
		error->gac_eco = I915_READ(GAC_ECO_BITS);
	}

	/* 4: Everything else */
1320 1321 1322
	if (HAS_HW_CONTEXTS(dev))
		error->ccid = I915_READ(CCID);

1323 1324 1325 1326 1327
	if (INTEL_INFO(dev)->gen >= 8) {
		error->ier = I915_READ(GEN8_DE_MISC_IER);
		for (i = 0; i < 4; i++)
			error->gtier[i] = I915_READ(GEN8_GT_IER(i));
	} else if (HAS_PCH_SPLIT(dev)) {
1328
		error->ier = I915_READ(DEIER);
1329
		error->gtier[0] = I915_READ(GTIER);
1330 1331 1332 1333
	} else if (IS_GEN2(dev)) {
		error->ier = I915_READ16(IER);
	} else if (!IS_VALLEYVIEW(dev)) {
		error->ier = I915_READ(IER);
1334 1335 1336
	}
	error->eir = I915_READ(EIR);
	error->pgtbl_er = I915_READ(PGTBL_ER);
1337

1338
	i915_get_extra_instdone(dev_priv, error->extra_instdone);
1339 1340
}

1341
static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
1342
				   struct drm_i915_error_state *error,
1343
				   u32 engine_mask,
1344
				   const char *error_msg)
1345 1346
{
	u32 ecode;
1347
	int engine_id = -1, len;
1348

1349
	ecode = i915_error_generate_code(dev_priv, error, &engine_id);
1350

1351
	len = scnprintf(error->error_msg, sizeof(error->error_msg),
1352
			"GPU HANG: ecode %d:%d:0x%08x",
1353
			INTEL_GEN(dev_priv), engine_id, ecode);
1354

1355
	if (engine_id != -1 && error->engine[engine_id].pid != -1)
1356 1357 1358
		len += scnprintf(error->error_msg + len,
				 sizeof(error->error_msg) - len,
				 ", in %s [%d]",
1359 1360
				 error->engine[engine_id].comm,
				 error->engine[engine_id].pid);
1361 1362 1363 1364

	scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
		  ", reason: %s, action: %s",
		  error_msg,
1365
		  engine_mask ? "reset" : "continue");
1366 1367
}

1368 1369 1370
static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
				   struct drm_i915_error_state *error)
{
1371 1372 1373 1374
	error->iommu = -1;
#ifdef CONFIG_INTEL_IOMMU
	error->iommu = intel_iommu_gfx_mapped;
#endif
1375
	error->reset_count = i915_reset_count(&dev_priv->gpu_error);
1376
	error->suspend_count = dev_priv->suspend_count;
1377 1378 1379 1380

	memcpy(&error->device_info,
	       INTEL_INFO(dev_priv),
	       sizeof(error->device_info));
1381 1382
}

1383 1384 1385 1386 1387 1388 1389 1390 1391
/**
 * i915_capture_error_state - capture an error record for later analysis
 * @dev: drm device
 *
 * Should be called when an error is detected (either a hang or an error
 * interrupt) to capture error state from the time of the error.  Fills
 * out a structure which becomes available in debugfs for user level tools
 * to pick up.
 */
1392 1393
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
1394
			      const char *error_msg)
1395
{
1396
	static bool warned;
1397 1398 1399
	struct drm_i915_error_state *error;
	unsigned long flags;

1400 1401 1402
	if (READ_ONCE(dev_priv->gpu_error.first_error))
		return;

1403 1404 1405 1406 1407 1408 1409
	/* Account for pipe specific data like PIPE*STAT */
	error = kzalloc(sizeof(*error), GFP_ATOMIC);
	if (!error) {
		DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
		return;
	}

1410 1411
	kref_init(&error->ref);

1412
	i915_capture_gen_state(dev_priv, error);
1413
	i915_capture_reg_state(dev_priv, error);
1414 1415
	i915_gem_record_fences(dev_priv, error);
	i915_gem_record_rings(dev_priv, error);
1416 1417
	i915_capture_active_buffers(dev_priv, error);
	i915_capture_pinned_buffers(dev_priv, error);
1418

1419 1420
	do_gettimeofday(&error->time);

1421 1422
	error->overlay = intel_overlay_capture_error_state(dev_priv);
	error->display = intel_display_capture_error_state(dev_priv);
1423

1424
	i915_error_capture_msg(dev_priv, error, engine_mask, error_msg);
1425 1426
	DRM_INFO("%s\n", error->error_msg);

1427 1428 1429 1430 1431 1432 1433
	if (!error->simulated) {
		spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
		if (!dev_priv->gpu_error.first_error) {
			dev_priv->gpu_error.first_error = error;
			error = NULL;
		}
		spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1434 1435
	}

1436
	if (error) {
1437
		i915_error_state_free(&error->ref);
1438 1439 1440 1441 1442 1443 1444 1445
		return;
	}

	if (!warned) {
		DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
		DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
		DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
		DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1446 1447
		DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
			 dev_priv->drm.primary->index);
1448 1449
		warned = true;
	}
1450 1451 1452 1453 1454
}

void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv)
{
1455
	struct drm_i915_private *dev_priv = to_i915(dev);
1456

1457
	spin_lock_irq(&dev_priv->gpu_error.lock);
1458 1459 1460
	error_priv->error = dev_priv->gpu_error.first_error;
	if (error_priv->error)
		kref_get(&error_priv->error->ref);
1461
	spin_unlock_irq(&dev_priv->gpu_error.lock);
1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472

}

void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
{
	if (error_priv->error)
		kref_put(&error_priv->error->ref, i915_error_state_free);
}

void i915_destroy_error_state(struct drm_device *dev)
{
1473
	struct drm_i915_private *dev_priv = to_i915(dev);
1474 1475
	struct drm_i915_error_state *error;

1476
	spin_lock_irq(&dev_priv->gpu_error.lock);
1477 1478
	error = dev_priv->gpu_error.first_error;
	dev_priv->gpu_error.first_error = NULL;
1479
	spin_unlock_irq(&dev_priv->gpu_error.lock);
1480 1481 1482 1483 1484

	if (error)
		kref_put(&error->ref, i915_error_state_free);
}

1485
const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
1486 1487 1488
{
	switch (type) {
	case I915_CACHE_NONE: return " uncached";
1489
	case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
1490
	case I915_CACHE_L3_LLC: return " L3+LLC";
1491
	case I915_CACHE_WT: return " WT";
1492 1493 1494 1495 1496
	default: return "";
	}
}

/* NB: please notice the memset */
1497 1498
void i915_get_extra_instdone(struct drm_i915_private *dev_priv,
			     uint32_t *instdone)
1499 1500 1501
{
	memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);

1502
	if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
1503
		instdone[0] = I915_READ(GEN2_INSTDONE);
1504
	else if (IS_GEN4(dev_priv) || IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) {
1505
		instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
1506
		instdone[1] = I915_READ(GEN4_INSTDONE1);
1507
	} else if (INTEL_GEN(dev_priv) >= 7) {
1508
		instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
1509 1510 1511 1512 1513
		instdone[1] = I915_READ(GEN7_SC_INSTDONE);
		instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
		instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
	}
}