intel_ringbuffer.h 20.8 KB
Newer Older
1 2 3
#ifndef _INTEL_RINGBUFFER_H_
#define _INTEL_RINGBUFFER_H_

4
#include <linux/hashtable.h>
5
#include "i915_gem_batch_pool.h"
6
#include "i915_gem_request.h"
7 8 9

#define I915_CMD_HASH_ORDER 9

10 11 12 13 14 15
/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
 * to give some inclination as to some of the magic values used in the various
 * workarounds!
 */
#define CACHELINE_BYTES 64
16
#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
17

18 19 20 21 22 23 24 25 26 27 28
/*
 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
 *
 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
 * cacheline, the Head Pointer must not be greater than the Tail
 * Pointer."
 */
#define I915_RING_FREE_SPACE 64

29 30 31 32
struct intel_hw_status_page {
	struct i915_vma *vma;
	u32 *page_addr;
	u32 ggtt_offset;
33 34
};

35 36
#define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base))
#define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val)
37

38 39
#define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base))
#define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val)
40

41 42
#define I915_READ_HEAD(engine)  I915_READ(RING_HEAD((engine)->mmio_base))
#define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val)
43

44 45
#define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base))
#define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val)
46

47 48
#define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base))
#define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val)
49

50 51
#define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base))
#define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val)
52

53 54 55
/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
 */
56 57 58
#define gen8_semaphore_seqno_size sizeof(uint64_t)
#define GEN8_SEMAPHORE_OFFSET(__from, __to)			     \
	(((__from) * I915_NUM_ENGINES  + (__to)) * gen8_semaphore_seqno_size)
59
#define GEN8_SIGNAL_OFFSET(__ring, to)			     \
60
	(dev_priv->semaphore->node.start + \
61
	 GEN8_SEMAPHORE_OFFSET((__ring)->id, (to)))
62
#define GEN8_WAIT_OFFSET(__ring, from)			     \
63
	(dev_priv->semaphore->node.start + \
64
	 GEN8_SEMAPHORE_OFFSET(from, (__ring)->id))
65

66
enum intel_engine_hangcheck_action {
67
	HANGCHECK_IDLE = 0,
68 69 70 71 72
	HANGCHECK_WAIT,
	HANGCHECK_ACTIVE,
	HANGCHECK_KICK,
	HANGCHECK_HUNG,
};
73

74 75
#define HANGCHECK_SCORE_RING_HUNG 31

76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94
#define I915_MAX_SLICES	3
#define I915_MAX_SUBSLICES 3

#define instdone_slice_mask(dev_priv__) \
	(INTEL_GEN(dev_priv__) == 7 ? \
	 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)

#define instdone_subslice_mask(dev_priv__) \
	(INTEL_GEN(dev_priv__) == 7 ? \
	 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask)

#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
	for ((slice__) = 0, (subslice__) = 0; \
	     (slice__) < I915_MAX_SLICES; \
	     (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
	       (slice__) += ((subslice__) == 0)) \
		for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
			    (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))

95 96 97 98
struct intel_instdone {
	u32 instdone;
	/* The following exist only in the RCS engine */
	u32 slice_common;
99 100
	u32 sampler[I915_MAX_SLICES][I915_MAX_SUBSLICES];
	u32 row[I915_MAX_SLICES][I915_MAX_SUBSLICES];
101 102
};

103
struct intel_engine_hangcheck {
104
	u64 acthd;
105
	u32 seqno;
106
	int score;
107
	enum intel_engine_hangcheck_action action;
108
	int deadlock;
109
	struct intel_instdone instdone;
110 111
};

112
struct intel_ring {
113
	struct i915_vma *vma;
114
	void *vaddr;
115

116
	struct intel_engine_cs *engine;
117

118 119
	struct list_head request_list;

120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136
	u32 head;
	u32 tail;
	int space;
	int size;
	int effective_size;

	/** We track the position of the requests in the ring buffer, and
	 * when each is retired we increment last_retired_head as the GPU
	 * must have finished processing the request and so we know we
	 * can advance the ringbuffer up to that position.
	 *
	 * last_retired_head is set to -1 after the value is consumed so
	 * we can detect new retirements.
	 */
	u32 last_retired_head;
};

137
struct i915_gem_context;
138
struct drm_i915_reg_table;
139

140 141 142 143 144 145 146 147 148 149 150
/*
 * we use a single page to load ctx workarounds so all of these
 * values are referred in terms of dwords
 *
 * struct i915_wa_ctx_bb:
 *  offset: specifies batch starting position, also helpful in case
 *    if we want to have multiple batches at different offsets based on
 *    some criteria. It is not a requirement at the moment but provides
 *    an option for future use.
 *  size: size of the batch in DWORDS
 */
151
struct i915_ctx_workarounds {
152 153 154 155
	struct i915_wa_ctx_bb {
		u32 offset;
		u32 size;
	} indirect_ctx, per_ctx;
156
	struct i915_vma *vma;
157 158
};

159
struct drm_i915_gem_request;
160
struct intel_render_state;
161

162 163
struct intel_engine_cs {
	struct drm_i915_private *i915;
164
	const char	*name;
165
	enum intel_engine_id {
166
		RCS = 0,
167
		BCS,
168 169 170
		VCS,
		VCS2,	/* Keep instances of the same type engine together. */
		VECS
171
	} id;
172
#define I915_NUM_ENGINES 5
173
#define _VCS(n) (VCS + (n))
174
	unsigned int exec_id;
175 176 177 178 179 180 181 182
	enum intel_engine_hw_id {
		RCS_HW = 0,
		VCS_HW,
		BCS_HW,
		VECS_HW,
		VCS2_HW
	} hw_id;
	enum intel_engine_hw_id guc_id; /* XXX same as hw_id? */
183
	u64 fence_context;
184
	u32		mmio_base;
185
	unsigned int irq_shift;
186
	struct intel_ring *buffer;
187

188 189
	struct intel_render_state *render_state;

190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206
	/* Rather than have every client wait upon all user interrupts,
	 * with the herd waking after every interrupt and each doing the
	 * heavyweight seqno dance, we delegate the task (of being the
	 * bottom-half of the user interrupt) to the first client. After
	 * every interrupt, we wake up one client, who does the heavyweight
	 * coherent seqno read and either goes back to sleep (if incomplete),
	 * or wakes up all the completed clients in parallel, before then
	 * transferring the bottom-half status to the next client in the queue.
	 *
	 * Compared to walking the entire list of waiters in a single dedicated
	 * bottom-half, we reduce the latency of the first waiter by avoiding
	 * a context switch, but incur additional coherent seqno reads when
	 * following the chain of request breadcrumbs. Since it is most likely
	 * that we have a single client waiting on each seqno, then reducing
	 * the overhead of waking that client is much preferred.
	 */
	struct intel_breadcrumbs {
207
		struct task_struct __rcu *irq_seqno_bh; /* bh for interrupts */
208 209
		bool irq_posted;

210 211
		spinlock_t lock; /* protects the lists of requests */
		struct rb_root waiters; /* sorted by retirement, priority */
212
		struct rb_root signals; /* sorted by retirement */
213
		struct intel_wait *first_wait; /* oldest waiter by retirement */
214
		struct task_struct *signaler; /* used for fence signalling */
215
		struct drm_i915_gem_request *first_signal;
216
		struct timer_list fake_irq; /* used after a missed interrupt */
217 218 219
		struct timer_list hangcheck; /* detect missed interrupts */

		unsigned long timeout;
220 221 222

		bool irq_enabled : 1;
		bool rpm_wakelock : 1;
223 224
	} breadcrumbs;

225 226 227 228 229 230 231
	/*
	 * A pool of objects to use as shadow copies of client batch buffers
	 * when the command parser is enabled. Prevents the client from
	 * modifying the batch contents after software parsing.
	 */
	struct i915_gem_batch_pool batch_pool;

232
	struct intel_hw_status_page status_page;
233
	struct i915_ctx_workarounds wa_ctx;
234
	struct i915_vma *scratch;
235

236 237
	u32             irq_keep_mask; /* always keep these interrupts */
	u32		irq_enable_mask; /* bitmask to enable ring interrupt */
238 239
	void		(*irq_enable)(struct intel_engine_cs *engine);
	void		(*irq_disable)(struct intel_engine_cs *engine);
240

241
	int		(*init_hw)(struct intel_engine_cs *engine);
242 243
	void		(*reset_hw)(struct intel_engine_cs *engine,
				    struct drm_i915_gem_request *req);
244

245
	int		(*init_context)(struct drm_i915_gem_request *req);
246

247 248 249 250 251 252 253 254 255 256 257 258
	int		(*emit_flush)(struct drm_i915_gem_request *request,
				      u32 mode);
#define EMIT_INVALIDATE	BIT(0)
#define EMIT_FLUSH	BIT(1)
#define EMIT_BARRIER	(EMIT_INVALIDATE | EMIT_FLUSH)
	int		(*emit_bb_start)(struct drm_i915_gem_request *req,
					 u64 offset, u32 length,
					 unsigned int dispatch_flags);
#define I915_DISPATCH_SECURE BIT(0)
#define I915_DISPATCH_PINNED BIT(1)
#define I915_DISPATCH_RS     BIT(2)
	int		(*emit_request)(struct drm_i915_gem_request *req);
259 260 261 262 263 264 265

	/* Pass the request to the hardware queue (e.g. directly into
	 * the legacy ringbuffer or to the end of an execlist).
	 *
	 * This is called from an atomic context with irqs disabled; must
	 * be irq safe.
	 */
266
	void		(*submit_request)(struct drm_i915_gem_request *req);
267

268 269 270 271 272 273
	/* Some chipsets are not quite as coherent as advertised and need
	 * an expensive kick to force a true read of the up-to-date seqno.
	 * However, the up-to-date seqno is not always required and the last
	 * seen value is good enough. Note that the seqno will always be
	 * monotonic, even if not coherent.
	 */
274 275
	void		(*irq_seqno_barrier)(struct intel_engine_cs *engine);
	void		(*cleanup)(struct intel_engine_cs *engine);
276

277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313
	/* GEN8 signal/wait table - never trust comments!
	 *	  signal to	signal to    signal to   signal to      signal to
	 *	    RCS		   VCS          BCS        VECS		 VCS2
	 *      --------------------------------------------------------------------
	 *  RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
	 *	|-------------------------------------------------------------------
	 *  VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
	 *	|-------------------------------------------------------------------
	 *  BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
	 *	|-------------------------------------------------------------------
	 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) |  NOP (0x90) | VCS2 (0x98) |
	 *	|-------------------------------------------------------------------
	 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP  (0xc0) |
	 *	|-------------------------------------------------------------------
	 *
	 * Generalization:
	 *  f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
	 *  ie. transpose of g(x, y)
	 *
	 *	 sync from	sync from    sync from    sync from	sync from
	 *	    RCS		   VCS          BCS        VECS		 VCS2
	 *      --------------------------------------------------------------------
	 *  RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
	 *	|-------------------------------------------------------------------
	 *  VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
	 *	|-------------------------------------------------------------------
	 *  BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
	 *	|-------------------------------------------------------------------
	 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) |  NOP (0x90) | VCS2 (0xb8) |
	 *	|-------------------------------------------------------------------
	 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) |  NOP (0xc0) |
	 *	|-------------------------------------------------------------------
	 *
	 * Generalization:
	 *  g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
	 *  ie. transpose of f(x, y)
	 */
314
	struct {
315
		u32	sync_seqno[I915_NUM_ENGINES-1];
316

317
		union {
318 319 320
#define GEN6_SEMAPHORE_LAST	VECS_HW
#define GEN6_NUM_SEMAPHORES	(GEN6_SEMAPHORE_LAST + 1)
#define GEN6_SEMAPHORES_MASK	GENMASK(GEN6_SEMAPHORE_LAST, 0)
321 322
			struct {
				/* our mbox written by others */
323
				u32		wait[GEN6_NUM_SEMAPHORES];
324
				/* mboxes this ring signals to */
325
				i915_reg_t	signal[GEN6_NUM_SEMAPHORES];
326
			} mbox;
327
			u64		signal_ggtt[I915_NUM_ENGINES];
328
		};
329 330

		/* AKA wait() */
331 332 333
		int	(*sync_to)(struct drm_i915_gem_request *req,
				   struct drm_i915_gem_request *signal);
		int	(*signal)(struct drm_i915_gem_request *req);
334
	} semaphore;
335

336
	/* Execlists */
337 338
	struct tasklet_struct irq_tasklet;
	spinlock_t execlist_lock; /* used inside tasklet, use spin_lock_bh */
339 340 341 342
	struct execlist_port {
		struct drm_i915_gem_request *request;
		unsigned int count;
	} execlist_port[2];
343
	struct list_head execlist_queue;
344
	unsigned int fw_domains;
345
	bool disable_lite_restore_wa;
346
	bool preempt_wa;
347
	u32 ctx_desc_template;
348

349 350 351 352 353 354
	/**
	 * List of breadcrumbs associated with GPU requests currently
	 * outstanding.
	 */
	struct list_head request_list;

355 356 357 358 359 360
	/**
	 * Seqno of request most recently submitted to request_list.
	 * Used exclusively by hang checker to avoid grabbing lock while
	 * inspecting request list.
	 */
	u32 last_submitted_seqno;
361
	u32 last_pending_seqno;
362

363 364
	/* An RCU guarded pointer to the last request. No reference is
	 * held to the request, users must carefully acquire a reference to
365
	 * the request using i915_gem_active_get_rcu(), or hold the
366 367 368 369
	 * struct_mutex.
	 */
	struct i915_gem_active last_request;

370
	struct i915_gem_context *last_context;
371

372
	struct intel_engine_hangcheck hangcheck;
373

374 375
	bool needs_cmd_parser;

376
	/*
377
	 * Table of commands the command parser needs to know about
378
	 * for this engine.
379
	 */
380
	DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
381 382 383 384

	/*
	 * Table of registers allowed in commands that read/write registers.
	 */
385 386
	const struct drm_i915_reg_table *reg_tables;
	int reg_table_count;
387 388 389 390 391

	/*
	 * Returns the bitmask for the length field of the specified command.
	 * Return 0 for an unrecognized/invalid command.
	 *
392
	 * If the command parser finds an entry for a command in the engine's
393
	 * cmd_tables, it gets the command's length based on the table entry.
394 395 396
	 * If not, it calls this function to determine the per-engine length
	 * field encoding for the command (i.e. different opcode ranges use
	 * certain bits to encode the command length in the header).
397 398
	 */
	u32 (*get_cmd_length_mask)(u32 cmd_header);
399 400
};

401
static inline unsigned
402
intel_engine_flag(const struct intel_engine_cs *engine)
403
{
404
	return 1 << engine->id;
405 406
}

407
static inline u32
408 409
intel_engine_sync_index(struct intel_engine_cs *engine,
			struct intel_engine_cs *other)
410 411 412 413
{
	int idx;

	/*
R
Rodrigo Vivi 已提交
414 415 416 417 418
	 * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
	 * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
	 * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
	 * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
	 * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
419 420
	 */

421
	idx = (other->id - engine->id) - 1;
422
	if (idx < 0)
423
		idx += I915_NUM_ENGINES;
424 425 426 427

	return idx;
}

428
static inline void
429
intel_flush_status_page(struct intel_engine_cs *engine, int reg)
430
{
431 432 433
	mb();
	clflush(&engine->status_page.page_addr[reg]);
	mb();
434 435
}

436
static inline u32
437
intel_read_status_page(struct intel_engine_cs *engine, int reg)
438
{
439
	/* Ensure that the compiler doesn't optimize away the load. */
440
	return READ_ONCE(engine->status_page.page_addr[reg]);
441 442
}

M
Mika Kuoppala 已提交
443
static inline void
444
intel_write_status_page(struct intel_engine_cs *engine,
M
Mika Kuoppala 已提交
445 446
			int reg, u32 value)
{
447
	engine->status_page.page_addr[reg] = value;
M
Mika Kuoppala 已提交
448 449
}

450
/*
C
Chris Wilson 已提交
451 452 453 454 455 456 457 458 459 460 461
 * Reads a dword out of the status page, which is written to from the command
 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 * MI_STORE_DATA_IMM.
 *
 * The following dwords have a reserved meaning:
 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 * 0x04: ring 0 head pointer
 * 0x05: ring 1 head pointer (915-class)
 * 0x06: ring 2 head pointer (915-class)
 * 0x10-0x1b: Context status DWords (GM45)
 * 0x1f: Last written status offset. (GM45)
462
 * 0x20-0x2f: Reserved (Gen6+)
C
Chris Wilson 已提交
463
 *
464
 * The area from dword 0x30 to 0x3ff is available for driver usage.
C
Chris Wilson 已提交
465
 */
466
#define I915_GEM_HWS_INDEX		0x30
467
#define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
468
#define I915_GEM_HWS_SCRATCH_INDEX	0x40
469
#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
C
Chris Wilson 已提交
470

471 472
struct intel_ring *
intel_engine_create_ring(struct intel_engine_cs *engine, int size);
473 474
int intel_ring_pin(struct intel_ring *ring);
void intel_ring_unpin(struct intel_ring *ring);
475
void intel_ring_free(struct intel_ring *ring);
476

477 478
void intel_engine_stop(struct intel_engine_cs *engine);
void intel_engine_cleanup(struct intel_engine_cs *engine);
479

480 481
void intel_legacy_submission_resume(struct drm_i915_private *dev_priv);

482 483
int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);

484
int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n);
485
int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
486

487
static inline void intel_ring_emit(struct intel_ring *ring, u32 data)
488
{
489 490
	*(uint32_t *)(ring->vaddr + ring->tail) = data;
	ring->tail += 4;
491 492
}

493
static inline void intel_ring_emit_reg(struct intel_ring *ring, i915_reg_t reg)
494
{
495
	intel_ring_emit(ring, i915_mmio_reg_offset(reg));
496
}
497

498
static inline void intel_ring_advance(struct intel_ring *ring)
499
{
500 501 502 503 504 505 506
	/* Dummy function.
	 *
	 * This serves as a placeholder in the code so that the reader
	 * can compare against the preceding intel_ring_begin() and
	 * check that the number of dwords emitted matches the space
	 * reserved for the command packet (i.e. the value passed to
	 * intel_ring_begin()).
507
	 */
508 509 510 511 512 513
}

static inline u32 intel_ring_offset(struct intel_ring *ring, u32 value)
{
	/* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
	return value & (ring->size - 1);
514
}
515

516
int __intel_ring_space(int head, int tail, int size);
517
void intel_ring_update_space(struct intel_ring *ring);
518

519
void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno);
520

521 522
void intel_engine_setup_common(struct intel_engine_cs *engine);
int intel_engine_init_common(struct intel_engine_cs *engine);
523
int intel_engine_create_scratch(struct intel_engine_cs *engine, int size);
524
void intel_engine_cleanup_common(struct intel_engine_cs *engine);
525

526
static inline int intel_engine_idle(struct intel_engine_cs *engine,
527
				    unsigned int flags)
528 529
{
	/* Wait upon the last request to be completed */
530
	return i915_gem_active_wait(&engine->last_request, flags);
531 532
}

533 534 535 536 537
int intel_init_render_ring_buffer(struct intel_engine_cs *engine);
int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine);
int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine);
int intel_init_blt_ring_buffer(struct intel_engine_cs *engine);
int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine);
538

539
u64 intel_engine_get_active_head(struct intel_engine_cs *engine);
540 541
u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine);

542 543 544 545
static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)
{
	return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
}
546

547
int init_workarounds_ring(struct intel_engine_cs *engine);
548

549 550 551
void intel_engine_get_instdone(struct intel_engine_cs *engine,
			       struct intel_instdone *instdone);

552 553 554
/*
 * Arbitrary size for largest possible 'add request' sequence. The code paths
 * are complex and variable. Empirical measurement shows that the worst case
555 556 557
 * is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However,
 * we need to allocate double the largest single packet within that emission
 * to account for tail wraparound (so 6 + 6 + 72 dwords for BDW).
558
 */
559
#define MIN_SPACE_FOR_ADD_REQUEST 336
560

561 562
static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine)
{
563
	return engine->status_page.ggtt_offset + I915_GEM_HWS_INDEX_ADDR;
564 565
}

566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583
/* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */
int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);

static inline void intel_wait_init(struct intel_wait *wait, u32 seqno)
{
	wait->tsk = current;
	wait->seqno = seqno;
}

static inline bool intel_wait_complete(const struct intel_wait *wait)
{
	return RB_EMPTY_NODE(&wait->node);
}

bool intel_engine_add_wait(struct intel_engine_cs *engine,
			   struct intel_wait *wait);
void intel_engine_remove_wait(struct intel_engine_cs *engine,
			      struct intel_wait *wait);
584
void intel_engine_enable_signaling(struct drm_i915_gem_request *request);
585

586
static inline bool intel_engine_has_waiter(const struct intel_engine_cs *engine)
587
{
588
	return rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh);
589 590
}

591
static inline bool intel_engine_wakeup(const struct intel_engine_cs *engine)
592 593
{
	bool wakeup = false;
594

595
	/* Note that for this not to dangerously chase a dangling pointer,
596
	 * we must hold the rcu_read_lock here.
597 598 599 600 601
	 *
	 * Also note that tsk is likely to be in !TASK_RUNNING state so an
	 * early test for tsk->state != TASK_RUNNING before wake_up_process()
	 * is unlikely to be beneficial.
	 */
602 603 604 605 606 607 608 609 610 611
	if (intel_engine_has_waiter(engine)) {
		struct task_struct *tsk;

		rcu_read_lock();
		tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
		if (tsk)
			wakeup = wake_up_process(tsk);
		rcu_read_unlock();
	}

612 613 614
	return wakeup;
}

615
void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine);
616 617
void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
unsigned int intel_kick_waiters(struct drm_i915_private *i915);
618
unsigned int intel_kick_signalers(struct drm_i915_private *i915);
619

620 621 622 623 624
static inline bool intel_engine_is_active(struct intel_engine_cs *engine)
{
	return i915_gem_active_isset(&engine->last_request);
}

625
#endif /* _INTEL_RINGBUFFER_H_ */