exynos_drm_fimd.c 28.9 KB
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/* exynos_drm_fimd.c
 *
 * Copyright (C) 2011 Samsung Electronics Co.Ltd
 * Authors:
 *	Joonyoung Shim <jy0922.shim@samsung.com>
 *	Inki Dae <inki.dae@samsung.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */
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#include <drm/drmP.h>
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#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/component.h>
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#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
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#include <video/of_display_timing.h>
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#include <video/of_videomode.h>
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#include <video/samsung_fimd.h>
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#include <drm/exynos_drm.h>

#include "exynos_drm_drv.h"
#include "exynos_drm_fbdev.h"
#include "exynos_drm_crtc.h"
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#include "exynos_drm_plane.h"
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#include "exynos_drm_iommu.h"
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/*
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 * FIMD stands for Fully Interactive Mobile Display and
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 * as a display controller, it transfers contents drawn on memory
 * to a LCD Panel through Display Interfaces such as RGB or
 * CPU Interface.
 */

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#define FIMD_DEFAULT_FRAMERATE 60
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#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
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/* position control register for hardware window 0, 2 ~ 4.*/
#define VIDOSD_A(win)		(VIDOSD_BASE + 0x00 + (win) * 16)
#define VIDOSD_B(win)		(VIDOSD_BASE + 0x04 + (win) * 16)
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/*
 * size control register for hardware windows 0 and alpha control register
 * for hardware windows 1 ~ 4
 */
#define VIDOSD_C(win)		(VIDOSD_BASE + 0x08 + (win) * 16)
/* size control register for hardware windows 1 ~ 2. */
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#define VIDOSD_D(win)		(VIDOSD_BASE + 0x0C + (win) * 16)

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#define VIDWnALPHA0(win)	(VIDW_ALPHA + 0x00 + (win) * 8)
#define VIDWnALPHA1(win)	(VIDW_ALPHA + 0x04 + (win) * 8)

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#define VIDWx_BUF_START(win, buf)	(VIDW_BUF_START(buf) + (win) * 8)
#define VIDWx_BUF_END(win, buf)		(VIDW_BUF_END(buf) + (win) * 8)
#define VIDWx_BUF_SIZE(win, buf)	(VIDW_BUF_SIZE(buf) + (win) * 4)

/* color key control register for hardware window 1 ~ 4. */
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#define WKEYCON0_BASE(x)		((WKEYCON0 + 0x140) + ((x - 1) * 8))
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/* color key value register for hardware window 1 ~ 4. */
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#define WKEYCON1_BASE(x)		((WKEYCON1 + 0x140) + ((x - 1) * 8))
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/* I80 / RGB trigger control register */
#define TRIGCON				0x1A4
#define TRGMODE_I80_RGB_ENABLE_I80	(1 << 0)
#define SWTRGCMD_I80_RGB_ENABLE		(1 << 1)

/* display mode change control register except exynos4 */
#define VIDOUT_CON			0x000
#define VIDOUT_CON_F_I80_LDI0		(0x2 << 8)

/* I80 interface control for main LDI register */
#define I80IFCONFAx(x)			(0x1B0 + (x) * 4)
#define I80IFCONFBx(x)			(0x1B8 + (x) * 4)
#define LCD_CS_SETUP(x)			((x) << 16)
#define LCD_WR_SETUP(x)			((x) << 12)
#define LCD_WR_ACTIVE(x)		((x) << 8)
#define LCD_WR_HOLD(x)			((x) << 4)
#define I80IFEN_ENABLE			(1 << 0)

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/* FIMD has totally five hardware windows. */
#define WINDOWS_NR	5

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struct fimd_driver_data {
	unsigned int timing_base;
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	unsigned int lcdblk_offset;
	unsigned int lcdblk_vt_shift;
	unsigned int lcdblk_bypass_shift;
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	unsigned int has_shadowcon:1;
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	unsigned int has_clksel:1;
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	unsigned int has_limited_fmt:1;
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	unsigned int has_vidoutcon:1;
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	unsigned int has_vtsel:1;
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};

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static struct fimd_driver_data s3c64xx_fimd_driver_data = {
	.timing_base = 0x0,
	.has_clksel = 1,
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	.has_limited_fmt = 1,
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};

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static struct fimd_driver_data exynos3_fimd_driver_data = {
	.timing_base = 0x20000,
	.lcdblk_offset = 0x210,
	.lcdblk_bypass_shift = 1,
	.has_shadowcon = 1,
	.has_vidoutcon = 1,
};

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static struct fimd_driver_data exynos4_fimd_driver_data = {
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	.timing_base = 0x0,
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	.lcdblk_offset = 0x210,
	.lcdblk_vt_shift = 10,
	.lcdblk_bypass_shift = 1,
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	.has_shadowcon = 1,
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	.has_vtsel = 1,
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};

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static struct fimd_driver_data exynos4415_fimd_driver_data = {
	.timing_base = 0x20000,
	.lcdblk_offset = 0x210,
	.lcdblk_vt_shift = 10,
	.lcdblk_bypass_shift = 1,
	.has_shadowcon = 1,
	.has_vidoutcon = 1,
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	.has_vtsel = 1,
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};

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static struct fimd_driver_data exynos5_fimd_driver_data = {
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	.timing_base = 0x20000,
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	.lcdblk_offset = 0x214,
	.lcdblk_vt_shift = 24,
	.lcdblk_bypass_shift = 15,
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	.has_shadowcon = 1,
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	.has_vidoutcon = 1,
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	.has_vtsel = 1,
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};

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struct fimd_context {
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	struct device			*dev;
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	struct drm_device		*drm_dev;
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	struct exynos_drm_crtc		*crtc;
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	struct exynos_drm_plane		planes[WINDOWS_NR];
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	struct clk			*bus_clk;
	struct clk			*lcd_clk;
	void __iomem			*regs;
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	struct regmap			*sysreg;
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	unsigned int			default_win;
	unsigned long			irq_flags;
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	u32				vidcon0;
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	u32				vidcon1;
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	u32				vidout_con;
	u32				i80ifcon;
	bool				i80_if;
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	bool				suspended;
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	int				pipe;
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	wait_queue_head_t		wait_vsync_queue;
	atomic_t			wait_vsync_event;
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	atomic_t			win_updated;
	atomic_t			triggering;
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	struct exynos_drm_panel_info panel;
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	struct fimd_driver_data *driver_data;
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	struct exynos_drm_display *display;
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};

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static const struct of_device_id fimd_driver_dt_match[] = {
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	{ .compatible = "samsung,s3c6400-fimd",
	  .data = &s3c64xx_fimd_driver_data },
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	{ .compatible = "samsung,exynos3250-fimd",
	  .data = &exynos3_fimd_driver_data },
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	{ .compatible = "samsung,exynos4210-fimd",
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	  .data = &exynos4_fimd_driver_data },
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	{ .compatible = "samsung,exynos4415-fimd",
	  .data = &exynos4415_fimd_driver_data },
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	{ .compatible = "samsung,exynos5250-fimd",
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	  .data = &exynos5_fimd_driver_data },
	{},
};
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MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
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static inline struct fimd_driver_data *drm_fimd_get_driver_data(
	struct platform_device *pdev)
{
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	const struct of_device_id *of_id =
			of_match_device(fimd_driver_dt_match, &pdev->dev);

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	return (struct fimd_driver_data *)of_id->data;
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}

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static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
{
	struct fimd_context *ctx = crtc->ctx;
	u32 val;

	if (ctx->suspended)
		return -EPERM;

	if (!test_and_set_bit(0, &ctx->irq_flags)) {
		val = readl(ctx->regs + VIDINTCON0);

		val |= VIDINTCON0_INT_ENABLE;

		if (ctx->i80_if) {
			val |= VIDINTCON0_INT_I80IFDONE;
			val |= VIDINTCON0_INT_SYSMAINCON;
			val &= ~VIDINTCON0_INT_SYSSUBCON;
		} else {
			val |= VIDINTCON0_INT_FRAME;

			val &= ~VIDINTCON0_FRAMESEL0_MASK;
			val |= VIDINTCON0_FRAMESEL0_VSYNC;
			val &= ~VIDINTCON0_FRAMESEL1_MASK;
			val |= VIDINTCON0_FRAMESEL1_NONE;
		}

		writel(val, ctx->regs + VIDINTCON0);
	}

	return 0;
}

static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
{
	struct fimd_context *ctx = crtc->ctx;
	u32 val;

	if (ctx->suspended)
		return;

	if (test_and_clear_bit(0, &ctx->irq_flags)) {
		val = readl(ctx->regs + VIDINTCON0);

		val &= ~VIDINTCON0_INT_ENABLE;

		if (ctx->i80_if) {
			val &= ~VIDINTCON0_INT_I80IFDONE;
			val &= ~VIDINTCON0_INT_SYSMAINCON;
			val &= ~VIDINTCON0_INT_SYSSUBCON;
		} else
			val &= ~VIDINTCON0_INT_FRAME;

		writel(val, ctx->regs + VIDINTCON0);
	}
}

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static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
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{
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	struct fimd_context *ctx = crtc->ctx;
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	if (ctx->suspended)
		return;

	atomic_set(&ctx->wait_vsync_event, 1);

	/*
	 * wait for FIMD to signal VSYNC interrupt or return after
	 * timeout which is set to 50ms (refresh rate of 20).
	 */
	if (!wait_event_timeout(ctx->wait_vsync_queue,
				!atomic_read(&ctx->wait_vsync_event),
				HZ/20))
		DRM_DEBUG_KMS("vblank wait timed out.\n");
}

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static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
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					bool enable)
{
	u32 val = readl(ctx->regs + WINCON(win));

	if (enable)
		val |= WINCONx_ENWIN;
	else
		val &= ~WINCONx_ENWIN;

	writel(val, ctx->regs + WINCON(win));
}

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static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
						unsigned int win,
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						bool enable)
{
	u32 val = readl(ctx->regs + SHADOWCON);

	if (enable)
		val |= SHADOWCON_CHx_ENABLE(win);
	else
		val &= ~SHADOWCON_CHx_ENABLE(win);

	writel(val, ctx->regs + SHADOWCON);
}

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static void fimd_clear_channel(struct fimd_context *ctx)
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{
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	unsigned int win, ch_enabled = 0;
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	DRM_DEBUG_KMS("%s\n", __FILE__);

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	/* Hardware is in unknown state, so ensure it gets enabled properly */
	pm_runtime_get_sync(ctx->dev);

	clk_prepare_enable(ctx->bus_clk);
	clk_prepare_enable(ctx->lcd_clk);

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	/* Check if any channel is enabled. */
	for (win = 0; win < WINDOWS_NR; win++) {
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		u32 val = readl(ctx->regs + WINCON(win));

		if (val & WINCONx_ENWIN) {
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			fimd_enable_video_output(ctx, win, false);
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			if (ctx->driver_data->has_shadowcon)
				fimd_enable_shadow_channel_path(ctx, win,
								false);

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			ch_enabled = 1;
		}
	}

	/* Wait for vsync, as disable channel takes effect at next vsync */
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	if (ch_enabled) {
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		int pipe = ctx->pipe;

		/* ensure that vblank interrupt won't be reported to core */
		ctx->suspended = false;
		ctx->pipe = -1;
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		fimd_enable_vblank(ctx->crtc);
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		fimd_wait_for_vblank(ctx->crtc);
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		fimd_disable_vblank(ctx->crtc);

		ctx->suspended = true;
		ctx->pipe = pipe;
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	}
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	clk_disable_unprepare(ctx->lcd_clk);
	clk_disable_unprepare(ctx->bus_clk);

	pm_runtime_put(ctx->dev);
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}

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static int fimd_iommu_attach_devices(struct fimd_context *ctx,
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			struct drm_device *drm_dev)
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{

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	/* attach this sub driver to iommu mapping if supported. */
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	if (is_drm_iommu_supported(ctx->drm_dev)) {
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		int ret;

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		/*
		 * If any channel is already active, iommu will throw
		 * a PAGE FAULT when enabled. So clear any channel if enabled.
		 */
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		fimd_clear_channel(ctx);
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		ret = drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
		if (ret) {
			DRM_ERROR("drm_iommu_attach failed.\n");
			return ret;
		}

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	}
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	return 0;
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}

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static void fimd_iommu_detach_devices(struct fimd_context *ctx)
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{
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	/* detach this sub driver from iommu mapping if supported. */
	if (is_drm_iommu_supported(ctx->drm_dev))
		drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
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}

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static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
		const struct drm_display_mode *mode)
{
	unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
	u32 clkdiv;

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	if (ctx->i80_if) {
		/*
		 * The frame done interrupt should be occurred prior to the
		 * next TE signal.
		 */
		ideal_clk *= 2;
	}

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	/* Find the clock divider value that gets us closest to ideal_clk */
	clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);

	return (clkdiv < 0x100) ? clkdiv : 0xff;
}

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static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc,
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		const struct drm_display_mode *mode,
		struct drm_display_mode *adjusted_mode)
{
	if (adjusted_mode->vrefresh == 0)
		adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;

	return true;
}

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static void fimd_commit(struct exynos_drm_crtc *crtc)
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{
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	struct fimd_context *ctx = crtc->ctx;
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	struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
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	struct fimd_driver_data *driver_data = ctx->driver_data;
	void *timing_base = ctx->regs + driver_data->timing_base;
	u32 val, clkdiv;
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	if (ctx->suspended)
		return;

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	/* nothing to do if we haven't set the mode yet */
	if (mode->htotal == 0 || mode->vtotal == 0)
		return;

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	if (ctx->i80_if) {
		val = ctx->i80ifcon | I80IFEN_ENABLE;
		writel(val, timing_base + I80IFCONFAx(0));

		/* disable auto frame rate */
		writel(0, timing_base + I80IFCONFBx(0));

		/* set video type selection to I80 interface */
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		if (driver_data->has_vtsel && ctx->sysreg &&
				regmap_update_bits(ctx->sysreg,
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					driver_data->lcdblk_offset,
					0x3 << driver_data->lcdblk_vt_shift,
					0x1 << driver_data->lcdblk_vt_shift)) {
			DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
			return;
		}
	} else {
		int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
		u32 vidcon1;

		/* setup polarity values */
		vidcon1 = ctx->vidcon1;
		if (mode->flags & DRM_MODE_FLAG_NVSYNC)
			vidcon1 |= VIDCON1_INV_VSYNC;
		if (mode->flags & DRM_MODE_FLAG_NHSYNC)
			vidcon1 |= VIDCON1_INV_HSYNC;
		writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);

		/* setup vertical timing values. */
		vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
		vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
		vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;

		val = VIDTCON0_VBPD(vbpd - 1) |
			VIDTCON0_VFPD(vfpd - 1) |
			VIDTCON0_VSPW(vsync_len - 1);
		writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);

		/* setup horizontal timing values.  */
		hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
		hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
		hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;

		val = VIDTCON1_HBPD(hbpd - 1) |
			VIDTCON1_HFPD(hfpd - 1) |
			VIDTCON1_HSPW(hsync_len - 1);
		writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
	}

	if (driver_data->has_vidoutcon)
		writel(ctx->vidout_con, timing_base + VIDOUT_CON);

	/* set bypass selection */
	if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
				driver_data->lcdblk_offset,
				0x1 << driver_data->lcdblk_bypass_shift,
				0x1 << driver_data->lcdblk_bypass_shift)) {
		DRM_ERROR("Failed to update sysreg for bypass setting.\n");
		return;
	}
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	/* setup horizontal and vertical display size. */
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	val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
	       VIDTCON2_HOZVAL(mode->hdisplay - 1) |
	       VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
	       VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
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	writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
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	/*
	 * fields of register with prefix '_F' would be updated
	 * at vsync(same as dma start)
	 */
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	val = ctx->vidcon0;
	val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
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	if (ctx->driver_data->has_clksel)
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		val |= VIDCON0_CLKSEL_LCD;

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	clkdiv = fimd_calc_clkdiv(ctx, mode);
	if (clkdiv > 1)
		val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
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	writel(val, ctx->regs + VIDCON0);
}


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static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
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{
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	struct exynos_drm_plane *plane = &ctx->planes[win];
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	unsigned long val;

	val = WINCONx_ENWIN;

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	/*
	 * In case of s3c64xx, window 0 doesn't support alpha channel.
	 * So the request format is ARGB8888 then change it to XRGB8888.
	 */
	if (ctx->driver_data->has_limited_fmt && !win) {
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		if (plane->pixel_format == DRM_FORMAT_ARGB8888)
			plane->pixel_format = DRM_FORMAT_XRGB8888;
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	}

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	switch (plane->pixel_format) {
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	case DRM_FORMAT_C8:
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		val |= WINCON0_BPPMODE_8BPP_PALETTE;
		val |= WINCONx_BURSTLEN_8WORD;
		val |= WINCONx_BYTSWP;
		break;
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	case DRM_FORMAT_XRGB1555:
		val |= WINCON0_BPPMODE_16BPP_1555;
		val |= WINCONx_HAWSWP;
		val |= WINCONx_BURSTLEN_16WORD;
		break;
	case DRM_FORMAT_RGB565:
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		val |= WINCON0_BPPMODE_16BPP_565;
		val |= WINCONx_HAWSWP;
		val |= WINCONx_BURSTLEN_16WORD;
		break;
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	case DRM_FORMAT_XRGB8888:
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		val |= WINCON0_BPPMODE_24BPP_888;
		val |= WINCONx_WSWP;
		val |= WINCONx_BURSTLEN_16WORD;
		break;
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	case DRM_FORMAT_ARGB8888:
		val |= WINCON1_BPPMODE_25BPP_A1888
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			| WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
		val |= WINCONx_WSWP;
		val |= WINCONx_BURSTLEN_16WORD;
		break;
	default:
		DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");

		val |= WINCON0_BPPMODE_24BPP_888;
		val |= WINCONx_WSWP;
		val |= WINCONx_BURSTLEN_16WORD;
		break;
	}

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	DRM_DEBUG_KMS("bpp = %d\n", plane->bpp);
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	/*
	 * In case of exynos, setting dma-burst to 16Word causes permanent
	 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
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	 * switching which is based on plane size is not recommended as
	 * plane size varies alot towards the end of the screen and rapid
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	 * movement causes unstable DMA which results into iommu crash/tear.
	 */

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	if (plane->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
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		val &= ~WINCONx_BURSTLEN_MASK;
		val |= WINCONx_BURSTLEN_4WORD;
	}

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	writel(val, ctx->regs + WINCON(win));
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	/* hardware window 0 doesn't support alpha channel. */
	if (win != 0) {
		/* OSD alpha */
		val = VIDISD14C_ALPHA0_R(0xf) |
			VIDISD14C_ALPHA0_G(0xf) |
			VIDISD14C_ALPHA0_B(0xf) |
			VIDISD14C_ALPHA1_R(0xf) |
			VIDISD14C_ALPHA1_G(0xf) |
			VIDISD14C_ALPHA1_B(0xf);

		writel(val, ctx->regs + VIDOSD_C(win));

		val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
			VIDW_ALPHA_G(0xf);
		writel(val, ctx->regs + VIDWnALPHA0(win));
		writel(val, ctx->regs + VIDWnALPHA1(win));
	}
598 599
}

600
static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
601 602 603 604 605 606 607 608 609 610 611 612
{
	unsigned int keycon0 = 0, keycon1 = 0;

	keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
			WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);

	keycon1 = WxKEYCON1_COLVAL(0xffffffff);

	writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
	writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
}

613 614 615 616 617 618 619
/**
 * shadow_protect_win() - disable updating values from shadow registers at vsync
 *
 * @win: window to protect registers for
 * @protect: 1 to protect (disable updates)
 */
static void fimd_shadow_protect_win(struct fimd_context *ctx,
620
				    unsigned int win, bool protect)
621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639
{
	u32 reg, bits, val;

	if (ctx->driver_data->has_shadowcon) {
		reg = SHADOWCON;
		bits = SHADOWCON_WINx_PROTECT(win);
	} else {
		reg = PRTCON;
		bits = PRTCON_PROTECT;
	}

	val = readl(ctx->regs + reg);
	if (protect)
		val |= bits;
	else
		val &= ~bits;
	writel(val, ctx->regs + reg);
}

640
static void fimd_win_commit(struct exynos_drm_crtc *crtc, unsigned int win)
641
{
642
	struct fimd_context *ctx = crtc->ctx;
643 644 645 646
	struct exynos_drm_plane *plane;
	dma_addr_t dma_addr;
	unsigned long val, size, offset;
	unsigned int last_x, last_y, buf_offsize, line_size;
647

I
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648 649 650
	if (ctx->suspended)
		return;

651
	if (win < 0 || win >= WINDOWS_NR)
652 653
		return;

654
	plane = &ctx->planes[win];
655

656
	if (ctx->suspended)
657 658
		return;

659
	/*
660
	 * SHADOWCON/PRTCON register is used for enabling timing.
661 662 663 664 665 666 667 668 669
	 *
	 * for example, once only width value of a register is set,
	 * if the dma is started then fimd hardware could malfunction so
	 * with protect window setting, the register fields with prefix '_F'
	 * wouldn't be updated at vsync also but updated once unprotect window
	 * is set.
	 */

	/* protect windows */
670
	fimd_shadow_protect_win(ctx, win, true);
671

672

673 674
	offset = plane->src_x * (plane->bpp >> 3);
	offset += plane->src_y * plane->pitch;
675

676
	/* buffer start address */
677 678
	dma_addr = plane->dma_addr[0] + offset;
	val = (unsigned long)dma_addr;
679 680 681
	writel(val, ctx->regs + VIDWx_BUF_START(win, 0));

	/* buffer end address */
682
	size = plane->pitch * plane->crtc_height;
683
	val = (unsigned long)(dma_addr + size);
684 685 686
	writel(val, ctx->regs + VIDWx_BUF_END(win, 0));

	DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
687
			(unsigned long)dma_addr, val, size);
688
	DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
689
			plane->crtc_width, plane->crtc_height);
690 691

	/* buffer size */
692
	buf_offsize = plane->pitch - (plane->crtc_width * (plane->bpp >> 3));
693 694 695 696 697
	line_size = plane->crtc_width * (plane->bpp >> 3);
	val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
		VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
		VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
		VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
698 699 700
	writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));

	/* OSD position */
701 702 703 704
	val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) |
		VIDOSDxA_TOPLEFT_Y(plane->crtc_y) |
		VIDOSDxA_TOPLEFT_X_E(plane->crtc_x) |
		VIDOSDxA_TOPLEFT_Y_E(plane->crtc_y);
705 706
	writel(val, ctx->regs + VIDOSD_A(win));

707
	last_x = plane->crtc_x + plane->crtc_width;
708 709
	if (last_x)
		last_x--;
710
	last_y = plane->crtc_y + plane->crtc_height;
711 712 713
	if (last_y)
		last_y--;

714 715 716
	val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
		VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);

717 718
	writel(val, ctx->regs + VIDOSD_B(win));

719
	DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
720
			plane->crtc_x, plane->crtc_y, last_x, last_y);
721 722 723 724 725

	/* OSD size */
	if (win != 3 && win != 4) {
		u32 offset = VIDOSD_D(win);
		if (win == 0)
726
			offset = VIDOSD_C(win);
727
		val = plane->crtc_width * plane->crtc_height;
728 729 730 731 732
		writel(val, ctx->regs + offset);

		DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
	}

733
	fimd_win_set_pixfmt(ctx, win);
734 735 736

	/* hardware window 0 doesn't support color key. */
	if (win != 0)
737
		fimd_win_set_colkey(ctx, win);
738

739
	fimd_enable_video_output(ctx, win, true);
740

741 742
	if (ctx->driver_data->has_shadowcon)
		fimd_enable_shadow_channel_path(ctx, win, true);
743

744 745 746
	/* Enable DMA channel and unprotect windows */
	fimd_shadow_protect_win(ctx, win, false);

747 748
	if (ctx->i80_if)
		atomic_set(&ctx->win_updated, 1);
749 750
}

751
static void fimd_win_disable(struct exynos_drm_crtc *crtc, unsigned int win)
752
{
753
	struct fimd_context *ctx = crtc->ctx;
754
	struct exynos_drm_plane *plane;
755

756
	if (win < 0 || win >= WINDOWS_NR)
757 758
		return;

759
	plane = &ctx->planes[win];
760

761
	if (ctx->suspended)
762 763
		return;

764
	/* protect windows */
765
	fimd_shadow_protect_win(ctx, win, true);
766

767
	fimd_enable_video_output(ctx, win, false);
768

769 770
	if (ctx->driver_data->has_shadowcon)
		fimd_enable_shadow_channel_path(ctx, win, false);
771

772
	/* unprotect windows */
773
	fimd_shadow_protect_win(ctx, win, false);
774 775
}

776
static void fimd_enable(struct exynos_drm_crtc *crtc)
777
{
778
	struct fimd_context *ctx = crtc->ctx;
779
	int ret;
780 781

	if (!ctx->suspended)
782
		return;
783 784 785

	ctx->suspended = false;

786 787
	pm_runtime_get_sync(ctx->dev);

788 789 790 791 792 793 794 795 796 797 798
	ret = clk_prepare_enable(ctx->bus_clk);
	if (ret < 0) {
		DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
		return;
	}

	ret = clk_prepare_enable(ctx->lcd_clk);
	if  (ret < 0) {
		DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
		return;
	}
799 800

	/* if vblank was enabled status, enable it again. */
801 802
	if (test_and_clear_bit(0, &ctx->irq_flags))
		fimd_enable_vblank(ctx->crtc);
803

804
	fimd_commit(ctx->crtc);
805 806
}

807
static void fimd_disable(struct exynos_drm_crtc *crtc)
808
{
809
	struct fimd_context *ctx = crtc->ctx;
810
	int i;
811

812
	if (ctx->suspended)
813
		return;
814 815 816 817 818 819

	/*
	 * We need to make sure that all windows are disabled before we
	 * suspend that connector. Otherwise we might try to scan from
	 * a destroyed buffer later.
	 */
820 821
	for (i = 0; i < WINDOWS_NR; i++)
		fimd_win_disable(crtc, i);
822

823 824
	writel(0, ctx->regs + VIDCON0);

825 826 827
	clk_disable_unprepare(ctx->lcd_clk);
	clk_disable_unprepare(ctx->bus_clk);

828 829
	pm_runtime_put_sync(ctx->dev);

830
	ctx->suspended = true;
831 832
}

833 834
static void fimd_trigger(struct device *dev)
{
835
	struct fimd_context *ctx = dev_get_drvdata(dev);
836 837 838 839
	struct fimd_driver_data *driver_data = ctx->driver_data;
	void *timing_base = ctx->regs + driver_data->timing_base;
	u32 reg;

840
	 /*
841 842 843
	  * Skips triggering if in triggering state, because multiple triggering
	  * requests can cause panel reset.
	  */
844 845 846
	if (atomic_read(&ctx->triggering))
		return;

847
	/* Enters triggering mode */
848 849 850 851 852
	atomic_set(&ctx->triggering, 1);

	reg = readl(timing_base + TRIGCON);
	reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
	writel(reg, timing_base + TRIGCON);
853 854 855 856 857 858 859

	/*
	 * Exits triggering mode if vblank is not enabled yet, because when the
	 * VIDINTCON0 register is not set, it can not exit from triggering mode.
	 */
	if (!test_bit(0, &ctx->irq_flags))
		atomic_set(&ctx->triggering, 0);
860 861
}

862
static void fimd_te_handler(struct exynos_drm_crtc *crtc)
863
{
864
	struct fimd_context *ctx = crtc->ctx;
865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881

	/* Checks the crtc is detached already from encoder */
	if (ctx->pipe < 0 || !ctx->drm_dev)
		return;

	/*
	 * If there is a page flip request, triggers and handles the page flip
	 * event so that current fb can be updated into panel GRAM.
	 */
	if (atomic_add_unless(&ctx->win_updated, -1, 0))
		fimd_trigger(ctx->dev);

	/* Wakes up vsync event queue */
	if (atomic_read(&ctx->wait_vsync_event)) {
		atomic_set(&ctx->wait_vsync_event, 0);
		wake_up(&ctx->wait_vsync_queue);
	}
882

883
	if (test_bit(0, &ctx->irq_flags))
884
		drm_handle_vblank(ctx->drm_dev, ctx->pipe);
885 886
}

887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903
static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable)
{
	struct fimd_context *ctx = crtc->ctx;
	u32 val;

	/*
	 * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE
	 * clock. On these SoCs the bootloader may enable it but any
	 * power domain off/on will reset it to disable state.
	 */
	if (ctx->driver_data != &exynos5_fimd_driver_data)
		return;

	val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
	writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON);
}

904
static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
905 906
	.enable = fimd_enable,
	.disable = fimd_disable,
907
	.mode_fixup = fimd_mode_fixup,
908 909 910 911 912 913
	.commit = fimd_commit,
	.enable_vblank = fimd_enable_vblank,
	.disable_vblank = fimd_disable_vblank,
	.wait_for_vblank = fimd_wait_for_vblank,
	.win_commit = fimd_win_commit,
	.win_disable = fimd_win_disable,
914
	.te_handler = fimd_te_handler,
915
	.clock_enable = fimd_dp_clock_enable,
916 917 918 919 920
};

static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
{
	struct fimd_context *ctx = (struct fimd_context *)dev_id;
921
	u32 val, clear_bit;
922 923 924

	val = readl(ctx->regs + VIDINTCON1);

925 926 927
	clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
	if (val & clear_bit)
		writel(clear_bit, ctx->regs + VIDINTCON1);
928

929
	/* check the crtc is detached already from encoder */
930
	if (ctx->pipe < 0 || !ctx->drm_dev)
931
		goto out;
I
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932

933
	if (ctx->i80_if) {
934 935
		exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);

936
		/* Exits triggering mode */
937 938
		atomic_set(&ctx->triggering, 0);
	} else {
939 940 941
		drm_handle_vblank(ctx->drm_dev, ctx->pipe);
		exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);

942 943 944 945 946
		/* set wait vsync event to zero and wake up queue. */
		if (atomic_read(&ctx->wait_vsync_event)) {
			atomic_set(&ctx->wait_vsync_event, 0);
			wake_up(&ctx->wait_vsync_queue);
		}
947
	}
948

949
out:
950 951 952
	return IRQ_HANDLED;
}

953
static int fimd_bind(struct device *dev, struct device *master, void *data)
954
{
955
	struct fimd_context *ctx = dev_get_drvdata(dev);
956
	struct drm_device *drm_dev = data;
957
	struct exynos_drm_private *priv = drm_dev->dev_private;
958 959
	struct exynos_drm_plane *exynos_plane;
	enum drm_plane_type type;
960 961
	unsigned int zpos;
	int ret;
962

963 964
	ctx->drm_dev = drm_dev;
	ctx->pipe = priv->pipe++;
965

966 967 968 969
	for (zpos = 0; zpos < WINDOWS_NR; zpos++) {
		type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY :
						DRM_PLANE_TYPE_OVERLAY;
		ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
970
					1 << ctx->pipe, type, zpos);
971 972 973 974 975 976 977
		if (ret)
			return ret;
	}

	exynos_plane = &ctx->planes[ctx->default_win];
	ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
					   ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
978
					   &fimd_crtc_ops, ctx);
979 980
	if (IS_ERR(ctx->crtc))
		return PTR_ERR(ctx->crtc);
981

982 983 984
	if (ctx->display)
		exynos_drm_create_enc_conn(drm_dev, ctx->display);

985
	return fimd_iommu_attach_devices(ctx, drm_dev);
986 987 988 989 990
}

static void fimd_unbind(struct device *dev, struct device *master,
			void *data)
{
991
	struct fimd_context *ctx = dev_get_drvdata(dev);
992

993
	fimd_disable(ctx->crtc);
994

995 996
	fimd_iommu_detach_devices(ctx);

997
	if (ctx->display)
998
		exynos_dpi_remove(ctx->display);
999 1000 1001 1002 1003 1004 1005 1006 1007 1008
}

static const struct component_ops fimd_component_ops = {
	.bind	= fimd_bind,
	.unbind = fimd_unbind,
};

static int fimd_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
1009
	struct fimd_context *ctx;
1010
	struct device_node *i80_if_timings;
1011
	struct resource *res;
1012
	int ret;
1013

1014 1015
	if (!dev->of_node)
		return -ENODEV;
1016

1017
	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1018 1019 1020
	if (!ctx)
		return -ENOMEM;

1021
	ctx->dev = dev;
1022
	ctx->suspended = true;
1023
	ctx->driver_data = drm_fimd_get_driver_data(pdev);
1024

1025 1026 1027 1028
	if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
		ctx->vidcon1 |= VIDCON1_INV_VDEN;
	if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
		ctx->vidcon1 |= VIDCON1_INV_VCLK;
1029

1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067
	i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
	if (i80_if_timings) {
		u32 val;

		ctx->i80_if = true;

		if (ctx->driver_data->has_vidoutcon)
			ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
		else
			ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
		/*
		 * The user manual describes that this "DSI_EN" bit is required
		 * to enable I80 24-bit data interface.
		 */
		ctx->vidcon0 |= VIDCON0_DSI_EN;

		if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
			val = 0;
		ctx->i80ifcon = LCD_CS_SETUP(val);
		if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
			val = 0;
		ctx->i80ifcon |= LCD_WR_SETUP(val);
		if (of_property_read_u32(i80_if_timings, "wr-active", &val))
			val = 1;
		ctx->i80ifcon |= LCD_WR_ACTIVE(val);
		if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
			val = 0;
		ctx->i80ifcon |= LCD_WR_HOLD(val);
	}
	of_node_put(i80_if_timings);

	ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
							"samsung,sysreg");
	if (IS_ERR(ctx->sysreg)) {
		dev_warn(dev, "failed to get system register.\n");
		ctx->sysreg = NULL;
	}

1068 1069 1070
	ctx->bus_clk = devm_clk_get(dev, "fimd");
	if (IS_ERR(ctx->bus_clk)) {
		dev_err(dev, "failed to get bus clock\n");
1071
		return PTR_ERR(ctx->bus_clk);
1072 1073 1074 1075 1076
	}

	ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
	if (IS_ERR(ctx->lcd_clk)) {
		dev_err(dev, "failed to get lcd clock\n");
1077
		return PTR_ERR(ctx->lcd_clk);
1078
	}
1079 1080 1081

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

1082
	ctx->regs = devm_ioremap_resource(dev, res);
1083 1084
	if (IS_ERR(ctx->regs))
		return PTR_ERR(ctx->regs);
1085

1086 1087
	res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
					   ctx->i80_if ? "lcd_sys" : "vsync");
1088 1089
	if (!res) {
		dev_err(dev, "irq request failed.\n");
1090
		return -ENXIO;
1091 1092
	}

1093
	ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1094 1095
							0, "drm_fimd", ctx);
	if (ret) {
1096
		dev_err(dev, "irq request failed.\n");
1097
		return ret;
1098 1099
	}

1100
	init_waitqueue_head(&ctx->wait_vsync_queue);
1101
	atomic_set(&ctx->wait_vsync_event, 0);
1102

1103
	platform_set_drvdata(pdev, ctx);
1104

1105
	ctx->display = exynos_dpi_probe(dev);
1106
	if (IS_ERR(ctx->display)) {
1107
		return PTR_ERR(ctx->display);
1108
	}
1109

1110
	pm_runtime_enable(dev);
1111

1112
	ret = component_add(dev, &fimd_component_ops);
1113 1114 1115 1116 1117 1118
	if (ret)
		goto err_disable_pm_runtime;

	return ret;

err_disable_pm_runtime:
1119
	pm_runtime_disable(dev);
1120 1121

	return ret;
1122
}
1123

1124 1125
static int fimd_remove(struct platform_device *pdev)
{
1126
	pm_runtime_disable(&pdev->dev);
1127

1128 1129
	component_del(&pdev->dev, &fimd_component_ops);

1130
	return 0;
I
Inki Dae 已提交
1131 1132
}

1133
struct platform_driver fimd_driver = {
1134
	.probe		= fimd_probe,
1135
	.remove		= fimd_remove,
1136 1137 1138
	.driver		= {
		.name	= "exynos4-fb",
		.owner	= THIS_MODULE,
1139
		.of_match_table = fimd_driver_dt_match,
1140 1141
	},
};