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/*
 * Low-level exception handling code
 *
 * Copyright (C) 2012 ARM Ltd.
 * Authors:	Catalin Marinas <catalin.marinas@arm.com>
 *		Will Deacon <will.deacon@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

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#include <linux/arm-smccc.h>
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#include <linux/init.h>
#include <linux/linkage.h>

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#include <asm/alternative.h>
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#include <asm/assembler.h>
#include <asm/asm-offsets.h>
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#include <asm/cpufeature.h>
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#include <asm/errno.h>
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#include <asm/esr.h>
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#include <asm/irq.h>
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#include <asm/memory.h>
#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/ptrace.h>
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#include <asm/thread_info.h>
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#include <asm/asm-uaccess.h>
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#include <asm/unistd.h>

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/*
 * Context tracking subsystem.  Used to instrument transitions
 * between user and kernel mode.
 */
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	.macro ct_user_exit
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#ifdef CONFIG_CONTEXT_TRACKING
	bl	context_tracking_user_exit
#endif
	.endm

	.macro ct_user_enter
#ifdef CONFIG_CONTEXT_TRACKING
	bl	context_tracking_user_enter
#endif
	.endm

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	.macro	clear_gp_regs
	.irp	n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
	mov	x\n, xzr
	.endr
	.endm

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/*
 * Bad Abort numbers
 *-----------------
 */
#define BAD_SYNC	0
#define BAD_IRQ		1
#define BAD_FIQ		2
#define BAD_ERROR	3

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	.macro kernel_ventry, el, label, regsize = 64
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	.align 7
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#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
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alternative_if ARM64_UNMAP_KERNEL_AT_EL0
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	.if	\el == 0
	.if	\regsize == 64
	mrs	x30, tpidrro_el0
	msr	tpidrro_el0, xzr
	.else
	mov	x30, xzr
	.endif
	.endif
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alternative_else_nop_endif
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#endif

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	sub	sp, sp, #S_FRAME_SIZE
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#ifdef CONFIG_VMAP_STACK
	/*
	 * Test whether the SP has overflowed, without corrupting a GPR.
	 * Task and IRQ stacks are aligned to (1 << THREAD_SHIFT).
	 */
	add	sp, sp, x0			// sp' = sp + x0
	sub	x0, sp, x0			// x0' = sp' - x0 = (sp + x0) - x0 = sp
	tbnz	x0, #THREAD_SHIFT, 0f
	sub	x0, sp, x0			// x0'' = sp' - x0' = (sp + x0) - sp = x0
	sub	sp, sp, x0			// sp'' = sp' - x0 = (sp + x0) - x0 = sp
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	b	el\()\el\()_\label
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	/*
	 * Either we've just detected an overflow, or we've taken an exception
	 * while on the overflow stack. Either way, we won't return to
	 * userspace, and can clobber EL0 registers to free up GPRs.
	 */

	/* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */
	msr	tpidr_el0, x0

	/* Recover the original x0 value and stash it in tpidrro_el0 */
	sub	x0, sp, x0
	msr	tpidrro_el0, x0

	/* Switch to the overflow stack */
	adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0

	/*
	 * Check whether we were already on the overflow stack. This may happen
	 * after panic() re-enables interrupts.
	 */
	mrs	x0, tpidr_el0			// sp of interrupted context
	sub	x0, sp, x0			// delta with top of overflow stack
	tst	x0, #~(OVERFLOW_STACK_SIZE - 1)	// within range?
	b.ne	__bad_stack			// no? -> bad stack pointer

	/* We were already on the overflow stack. Restore sp/x0 and carry on. */
	sub	sp, sp, x0
	mrs	x0, tpidrro_el0
#endif
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	b	el\()\el\()_\label
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	.endm

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	.macro tramp_alias, dst, sym
	mov_q	\dst, TRAMP_VALIAS
	add	\dst, \dst, #(\sym - .entry.tramp.text)
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	.endm

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	// This macro corrupts x0-x3. It is the caller's duty
	// to save/restore them if required.
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	.macro	apply_ssbd, state, tmp1, tmp2
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#ifdef CONFIG_ARM64_SSBD
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alternative_cb	arm64_enable_wa2_handling
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	b	.L__asm_ssbd_skip\@
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alternative_cb_end
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	ldr_this_cpu	\tmp2, arm64_ssbd_callback_required, \tmp1
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	cbz	\tmp2,	.L__asm_ssbd_skip\@
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	ldr	\tmp2, [tsk, #TSK_TI_FLAGS]
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	tbnz	\tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@
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	mov	w0, #ARM_SMCCC_ARCH_WORKAROUND_2
	mov	w1, #\state
alternative_cb	arm64_update_smccc_conduit
	nop					// Patched to SMC/HVC #0
alternative_cb_end
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.L__asm_ssbd_skip\@:
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#endif
	.endm

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	.macro	kernel_entry, el, regsize = 64
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	.if	\regsize == 32
	mov	w0, w0				// zero upper 32 bits of x0
	.endif
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	stp	x0, x1, [sp, #16 * 0]
	stp	x2, x3, [sp, #16 * 1]
	stp	x4, x5, [sp, #16 * 2]
	stp	x6, x7, [sp, #16 * 3]
	stp	x8, x9, [sp, #16 * 4]
	stp	x10, x11, [sp, #16 * 5]
	stp	x12, x13, [sp, #16 * 6]
	stp	x14, x15, [sp, #16 * 7]
	stp	x16, x17, [sp, #16 * 8]
	stp	x18, x19, [sp, #16 * 9]
	stp	x20, x21, [sp, #16 * 10]
	stp	x22, x23, [sp, #16 * 11]
	stp	x24, x25, [sp, #16 * 12]
	stp	x26, x27, [sp, #16 * 13]
	stp	x28, x29, [sp, #16 * 14]

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	.if	\el == 0
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	clear_gp_regs
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	mrs	x21, sp_el0
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	ldr_this_cpu	tsk, __entry_task, x20	// Ensure MDSCR_EL1.SS is clear,
	ldr	x19, [tsk, #TSK_TI_FLAGS]	// since we can unmask debug
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	disable_step_tsk x19, x20		// exceptions when scheduling.
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	apply_ssbd 1, x22, x23
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	.else
	add	x21, sp, #S_FRAME_SIZE
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	get_thread_info tsk
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	/* Save the task's original addr_limit and set USER_DS */
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	ldr	x20, [tsk, #TSK_TI_ADDR_LIMIT]
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	str	x20, [sp, #S_ORIG_ADDR_LIMIT]
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	mov	x20, #USER_DS
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	str	x20, [tsk, #TSK_TI_ADDR_LIMIT]
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	/* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
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	.endif /* \el == 0 */
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	mrs	x22, elr_el1
	mrs	x23, spsr_el1
	stp	lr, x21, [sp, #S_LR]
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	/*
	 * In order to be able to dump the contents of struct pt_regs at the
	 * time the exception was taken (in case we attempt to walk the call
	 * stack later), chain it together with the stack frames.
	 */
	.if \el == 0
	stp	xzr, xzr, [sp, #S_STACKFRAME]
	.else
	stp	x29, x22, [sp, #S_STACKFRAME]
	.endif
	add	x29, sp, #S_STACKFRAME

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#ifdef CONFIG_ARM64_SW_TTBR0_PAN
	/*
	 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
	 * EL0, there is no need to check the state of TTBR0_EL1 since
	 * accesses are always enabled.
	 * Note that the meaning of this bit differs from the ARMv8.1 PAN
	 * feature as all TTBR0_EL1 accesses are disabled, not just those to
	 * user mappings.
	 */
alternative_if ARM64_HAS_PAN
	b	1f				// skip TTBR0 PAN
alternative_else_nop_endif

	.if	\el != 0
	mrs	x21, ttbr0_el1
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	tst	x21, #TTBR_ASID_MASK		// Check for the reserved ASID
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	orr	x23, x23, #PSR_PAN_BIT		// Set the emulated PAN in the saved SPSR
	b.eq	1f				// TTBR0 access already disabled
	and	x23, x23, #~PSR_PAN_BIT		// Clear the emulated PAN in the saved SPSR
	.endif

	__uaccess_ttbr0_disable x21
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#endif

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	stp	x22, x23, [sp, #S_PC]

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	/* Not in a syscall by default (el0_svc overwrites for real syscall) */
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	.if	\el == 0
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	mov	w21, #NO_SYSCALL
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	str	w21, [sp, #S_SYSCALLNO]
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	.endif

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	/*
	 * Set sp_el0 to current thread_info.
	 */
	.if	\el == 0
	msr	sp_el0, tsk
	.endif

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	/*
	 * Registers that may be useful after this macro is invoked:
	 *
	 * x21 - aborted SP
	 * x22 - aborted PC
	 * x23 - aborted PSTATE
	*/
	.endm

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	.macro	kernel_exit, el
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	.if	\el != 0
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	disable_daif

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	/* Restore the task's original addr_limit. */
	ldr	x20, [sp, #S_ORIG_ADDR_LIMIT]
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	str	x20, [tsk, #TSK_TI_ADDR_LIMIT]
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	/* No need to restore UAO, it will be restored from SPSR_EL1 */
	.endif

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	ldp	x21, x22, [sp, #S_PC]		// load ELR, SPSR
	.if	\el == 0
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	ct_user_enter
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	.endif

#ifdef CONFIG_ARM64_SW_TTBR0_PAN
	/*
	 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
	 * PAN bit checking.
	 */
alternative_if ARM64_HAS_PAN
	b	2f				// skip TTBR0 PAN
alternative_else_nop_endif

	.if	\el != 0
	tbnz	x22, #22, 1f			// Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
	.endif

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	__uaccess_ttbr0_enable x0, x1
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	.if	\el == 0
	/*
	 * Enable errata workarounds only if returning to user. The only
	 * workaround currently required for TTBR0_EL1 changes are for the
	 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
	 * corruption).
	 */
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	bl	post_ttbr_update_workaround
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	.endif
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	.if	\el != 0
	and	x22, x22, #~PSR_PAN_BIT		// ARMv8.0 CPUs do not understand this bit
	.endif
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#endif

	.if	\el == 0
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	ldr	x23, [sp, #S_SP]		// load return stack pointer
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	msr	sp_el0, x23
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	tst	x22, #PSR_MODE32_BIT		// native task?
	b.eq	3f

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#ifdef CONFIG_ARM64_ERRATUM_845719
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alternative_if ARM64_WORKAROUND_845719
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#ifdef CONFIG_PID_IN_CONTEXTIDR
	mrs	x29, contextidr_el1
	msr	contextidr_el1, x29
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#else
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	msr contextidr_el1, xzr
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#endif
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alternative_else_nop_endif
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1188873
alternative_if_not ARM64_WORKAROUND_1188873
	b	4f
alternative_else_nop_endif
	/*
	 * if (x22.mode32 == cntkctl_el1.el0vcten)
	 *     cntkctl_el1.el0vcten = ~cntkctl_el1.el0vcten
	 */
	mrs	x1, cntkctl_el1
	eon	x0, x1, x22, lsr #3
	tbz	x0, #1, 4f
	eor	x1, x1, #2	// ARCH_TIMER_USR_VCT_ACCESS_EN
	msr	cntkctl_el1, x1
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#endif
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	apply_ssbd 0, x0, x1
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	.endif
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	msr	elr_el1, x21			// set up the return data
	msr	spsr_el1, x22
	ldp	x0, x1, [sp, #16 * 0]
	ldp	x2, x3, [sp, #16 * 1]
	ldp	x4, x5, [sp, #16 * 2]
	ldp	x6, x7, [sp, #16 * 3]
	ldp	x8, x9, [sp, #16 * 4]
	ldp	x10, x11, [sp, #16 * 5]
	ldp	x12, x13, [sp, #16 * 6]
	ldp	x14, x15, [sp, #16 * 7]
	ldp	x16, x17, [sp, #16 * 8]
	ldp	x18, x19, [sp, #16 * 9]
	ldp	x20, x21, [sp, #16 * 10]
	ldp	x22, x23, [sp, #16 * 11]
	ldp	x24, x25, [sp, #16 * 12]
	ldp	x26, x27, [sp, #16 * 13]
	ldp	x28, x29, [sp, #16 * 14]
	ldr	lr, [sp, #S_LR]
	add	sp, sp, #S_FRAME_SIZE		// restore sp
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	/*
	 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on eret context synchronization
	 * when returning from IPI handler, and when returning to user-space.
	 */
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	.if	\el == 0
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alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
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	bne	5f
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	msr	far_el1, x30
	tramp_alias	x30, tramp_exit_native
	br	x30
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	tramp_alias	x30, tramp_exit_compat
	br	x30
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#endif
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	.else
	eret
	.endif
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	.endm

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	.macro	irq_stack_entry
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	mov	x19, sp			// preserve the original sp

	/*
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	 * Compare sp with the base of the task stack.
	 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
	 * and should switch to the irq stack.
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	 */
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	ldr	x25, [tsk, TSK_STACK]
	eor	x25, x25, x19
	and	x25, x25, #~(THREAD_SIZE - 1)
	cbnz	x25, 9998f
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	ldr_this_cpu x25, irq_stack_ptr, x26
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	mov	x26, #IRQ_STACK_SIZE
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	add	x26, x25, x26
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	/* switch to the irq stack */
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	mov	sp, x26
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	.endm

	/*
	 * x19 should be preserved between irq_stack_entry and
	 * irq_stack_exit.
	 */
	.macro	irq_stack_exit
	mov	sp, x19
	.endm

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/*
 * These are the registers used in the syscall handler, and allow us to
 * have in theory up to 7 arguments to a function - x0 to x6.
 *
 * x7 is reserved for the system call number in 32-bit mode.
 */
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wsc_nr	.req	w25		// number of system calls
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xsc_nr	.req	x25		// number of system calls (zero-extended)
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wscno	.req	w26		// syscall number
xscno	.req	x26		// syscall number (zero-extended)
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stbl	.req	x27		// syscall table pointer
tsk	.req	x28		// current thread_info

/*
 * Interrupt handling.
 */
	.macro	irq_handler
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	ldr_l	x1, handle_arch_irq
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	mov	x0, sp
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	irq_stack_entry
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	blr	x1
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	irq_stack_exit
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	.endm

	.text

/*
 * Exception vectors.
 */
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	.pushsection ".entry.text", "ax"
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	.align	11
ENTRY(vectors)
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	kernel_ventry	1, sync_invalid			// Synchronous EL1t
	kernel_ventry	1, irq_invalid			// IRQ EL1t
	kernel_ventry	1, fiq_invalid			// FIQ EL1t
	kernel_ventry	1, error_invalid		// Error EL1t
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	kernel_ventry	1, sync				// Synchronous EL1h
	kernel_ventry	1, irq				// IRQ EL1h
	kernel_ventry	1, fiq_invalid			// FIQ EL1h
	kernel_ventry	1, error			// Error EL1h
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	kernel_ventry	0, sync				// Synchronous 64-bit EL0
	kernel_ventry	0, irq				// IRQ 64-bit EL0
	kernel_ventry	0, fiq_invalid			// FIQ 64-bit EL0
	kernel_ventry	0, error			// Error 64-bit EL0
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#ifdef CONFIG_COMPAT
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	kernel_ventry	0, sync_compat, 32		// Synchronous 32-bit EL0
	kernel_ventry	0, irq_compat, 32		// IRQ 32-bit EL0
	kernel_ventry	0, fiq_invalid_compat, 32	// FIQ 32-bit EL0
	kernel_ventry	0, error_compat, 32		// Error 32-bit EL0
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#else
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	kernel_ventry	0, sync_invalid, 32		// Synchronous 32-bit EL0
	kernel_ventry	0, irq_invalid, 32		// IRQ 32-bit EL0
	kernel_ventry	0, fiq_invalid, 32		// FIQ 32-bit EL0
	kernel_ventry	0, error_invalid, 32		// Error 32-bit EL0
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#endif
END(vectors)

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#ifdef CONFIG_VMAP_STACK
	/*
	 * We detected an overflow in kernel_ventry, which switched to the
	 * overflow stack. Stash the exception regs, and head to our overflow
	 * handler.
	 */
__bad_stack:
	/* Restore the original x0 value */
	mrs	x0, tpidrro_el0

	/*
	 * Store the original GPRs to the new stack. The orginal SP (minus
	 * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry.
	 */
	sub	sp, sp, #S_FRAME_SIZE
	kernel_entry 1
	mrs	x0, tpidr_el0
	add	x0, x0, #S_FRAME_SIZE
	str	x0, [sp, #S_SP]

	/* Stash the regs for handle_bad_stack */
	mov	x0, sp

	/* Time to die */
	bl	handle_bad_stack
	ASM_BUG()
#endif /* CONFIG_VMAP_STACK */

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/*
 * Invalid mode handlers
 */
	.macro	inv_entry, el, reason, regsize = 64
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	kernel_entry \el, \regsize
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	mov	x0, sp
	mov	x1, #\reason
	mrs	x2, esr_el1
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	bl	bad_mode
	ASM_BUG()
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	.endm

el0_sync_invalid:
	inv_entry 0, BAD_SYNC
ENDPROC(el0_sync_invalid)

el0_irq_invalid:
	inv_entry 0, BAD_IRQ
ENDPROC(el0_irq_invalid)

el0_fiq_invalid:
	inv_entry 0, BAD_FIQ
ENDPROC(el0_fiq_invalid)

el0_error_invalid:
	inv_entry 0, BAD_ERROR
ENDPROC(el0_error_invalid)

#ifdef CONFIG_COMPAT
el0_fiq_invalid_compat:
	inv_entry 0, BAD_FIQ, 32
ENDPROC(el0_fiq_invalid_compat)
#endif

el1_sync_invalid:
	inv_entry 1, BAD_SYNC
ENDPROC(el1_sync_invalid)

el1_irq_invalid:
	inv_entry 1, BAD_IRQ
ENDPROC(el1_irq_invalid)

el1_fiq_invalid:
	inv_entry 1, BAD_FIQ
ENDPROC(el1_fiq_invalid)

el1_error_invalid:
	inv_entry 1, BAD_ERROR
ENDPROC(el1_error_invalid)

/*
 * EL1 mode handlers.
 */
	.align	6
el1_sync:
	kernel_entry 1
	mrs	x1, esr_el1			// read the syndrome register
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	lsr	x24, x1, #ESR_ELx_EC_SHIFT	// exception class
	cmp	x24, #ESR_ELx_EC_DABT_CUR	// data abort in EL1
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	b.eq	el1_da
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	cmp	x24, #ESR_ELx_EC_IABT_CUR	// instruction abort in EL1
	b.eq	el1_ia
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	cmp	x24, #ESR_ELx_EC_SYS64		// configurable trap
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	b.eq	el1_undef
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	cmp	x24, #ESR_ELx_EC_SP_ALIGN	// stack alignment exception
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	b.eq	el1_sp_pc
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	cmp	x24, #ESR_ELx_EC_PC_ALIGN	// pc alignment exception
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	b.eq	el1_sp_pc
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	cmp	x24, #ESR_ELx_EC_UNKNOWN	// unknown exception in EL1
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	b.eq	el1_undef
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	cmp	x24, #ESR_ELx_EC_BREAKPT_CUR	// debug exception in EL1
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	b.ge	el1_dbg
	b	el1_inv
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el1_ia:
	/*
	 * Fall through to the Data abort case
	 */
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el1_da:
	/*
	 * Data abort handling
	 */
584
	mrs	x3, far_el1
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	inherit_daif	pstate=x23, tmp=x2
586
	clear_address_tag x0, x3
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	mov	x2, sp				// struct pt_regs
	bl	do_mem_abort

	kernel_exit 1
el1_sp_pc:
	/*
	 * Stack or PC alignment exception handling
	 */
	mrs	x0, far_el1
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	inherit_daif	pstate=x23, tmp=x2
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	mov	x2, sp
598 599
	bl	do_sp_pc_abort
	ASM_BUG()
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el1_undef:
	/*
	 * Undefined instruction
	 */
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	inherit_daif	pstate=x23, tmp=x2
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	mov	x0, sp
606
	bl	do_undefinstr
607
	kernel_exit 1
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el1_dbg:
	/*
	 * Debug exception handling
	 */
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	cmp	x24, #ESR_ELx_EC_BRK64		// if BRK64
613
	cinc	x24, x24, eq			// set bit '0'
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	tbz	x24, #0, el1_inv		// EL1 only
	mrs	x0, far_el1
	mov	x2, sp				// struct pt_regs
	bl	do_debug_exception
	kernel_exit 1
el1_inv:
	// TODO: add support for undefined instructions in kernel mode
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	inherit_daif	pstate=x23, tmp=x2
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	mov	x0, sp
623
	mov	x2, x1
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	mov	x1, #BAD_SYNC
625 626
	bl	bad_mode
	ASM_BUG()
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ENDPROC(el1_sync)

	.align	6
el1_irq:
	kernel_entry 1
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	enable_da_f
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#ifdef CONFIG_TRACE_IRQFLAGS
	bl	trace_hardirqs_off
#endif
636

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	irq_handler
638

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#ifdef CONFIG_PREEMPT
640 641 642 643
	ldr	w24, [tsk, #TSK_TI_PREEMPT]	// get preempt count
	cbnz	w24, 1f				// preempt count != 0
	ldr	x0, [tsk, #TSK_TI_FLAGS]	// get flags
	tbz	x0, #TIF_NEED_RESCHED, 1f	// needs rescheduling?
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	bl	el1_preempt
1:
#endif
#ifdef CONFIG_TRACE_IRQFLAGS
	bl	trace_hardirqs_on
#endif
	kernel_exit 1
ENDPROC(el1_irq)

#ifdef CONFIG_PREEMPT
el1_preempt:
	mov	x24, lr
656
1:	bl	preempt_schedule_irq		// irq en/disable is done inside
657
	ldr	x0, [tsk, #TSK_TI_FLAGS]	// get new tasks TI_FLAGS
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	tbnz	x0, #TIF_NEED_RESCHED, 1b	// needs rescheduling?
	ret	x24
#endif

/*
 * EL0 mode handlers.
 */
	.align	6
el0_sync:
	kernel_entry 0
	mrs	x25, esr_el1			// read the syndrome register
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	lsr	x24, x25, #ESR_ELx_EC_SHIFT	// exception class
	cmp	x24, #ESR_ELx_EC_SVC64		// SVC in 64-bit state
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	b.eq	el0_svc
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	cmp	x24, #ESR_ELx_EC_DABT_LOW	// data abort in EL0
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	b.eq	el0_da
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	cmp	x24, #ESR_ELx_EC_IABT_LOW	// instruction abort in EL0
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	b.eq	el0_ia
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	cmp	x24, #ESR_ELx_EC_FP_ASIMD	// FP/ASIMD access
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	b.eq	el0_fpsimd_acc
678 679
	cmp	x24, #ESR_ELx_EC_SVE		// SVE access
	b.eq	el0_sve_acc
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	cmp	x24, #ESR_ELx_EC_FP_EXC64	// FP/ASIMD exception
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	b.eq	el0_fpsimd_exc
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	cmp	x24, #ESR_ELx_EC_SYS64		// configurable trap
683
	b.eq	el0_sys
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	cmp	x24, #ESR_ELx_EC_SP_ALIGN	// stack alignment exception
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	b.eq	el0_sp_pc
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	cmp	x24, #ESR_ELx_EC_PC_ALIGN	// pc alignment exception
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	b.eq	el0_sp_pc
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	cmp	x24, #ESR_ELx_EC_UNKNOWN	// unknown exception in EL0
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	b.eq	el0_undef
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	cmp	x24, #ESR_ELx_EC_BREAKPT_LOW	// debug exception in EL0
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	b.ge	el0_dbg
	b	el0_inv

#ifdef CONFIG_COMPAT
	.align	6
el0_sync_compat:
	kernel_entry 0, 32
	mrs	x25, esr_el1			// read the syndrome register
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	lsr	x24, x25, #ESR_ELx_EC_SHIFT	// exception class
	cmp	x24, #ESR_ELx_EC_SVC32		// SVC in 32-bit state
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	b.eq	el0_svc_compat
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	cmp	x24, #ESR_ELx_EC_DABT_LOW	// data abort in EL0
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	b.eq	el0_da
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	cmp	x24, #ESR_ELx_EC_IABT_LOW	// instruction abort in EL0
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	b.eq	el0_ia
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	cmp	x24, #ESR_ELx_EC_FP_ASIMD	// FP/ASIMD access
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	b.eq	el0_fpsimd_acc
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	cmp	x24, #ESR_ELx_EC_FP_EXC32	// FP/ASIMD exception
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	b.eq	el0_fpsimd_exc
710 711
	cmp	x24, #ESR_ELx_EC_PC_ALIGN	// pc alignment exception
	b.eq	el0_sp_pc
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	cmp	x24, #ESR_ELx_EC_UNKNOWN	// unknown exception in EL0
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	b.eq	el0_undef
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	cmp	x24, #ESR_ELx_EC_CP15_32	// CP15 MRC/MCR trap
715
	b.eq	el0_undef
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	cmp	x24, #ESR_ELx_EC_CP15_64	// CP15 MRRC/MCRR trap
717
	b.eq	el0_undef
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	cmp	x24, #ESR_ELx_EC_CP14_MR	// CP14 MRC/MCR trap
719
	b.eq	el0_undef
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	cmp	x24, #ESR_ELx_EC_CP14_LS	// CP14 LDC/STC trap
721
	b.eq	el0_undef
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	cmp	x24, #ESR_ELx_EC_CP14_64	// CP14 MRRC/MCRR trap
723
	b.eq	el0_undef
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	cmp	x24, #ESR_ELx_EC_BREAKPT_LOW	// debug exception in EL0
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	b.ge	el0_dbg
	b	el0_inv
el0_svc_compat:
728 729 730
	mov	x0, sp
	bl	el0_svc_compat_handler
	b	ret_to_user
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	.align	6
el0_irq_compat:
	kernel_entry 0, 32
	b	el0_irq_naked
736 737 738 739

el0_error_compat:
	kernel_entry 0, 32
	b	el0_error_naked
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#endif

el0_da:
	/*
	 * Data abort handling
	 */
746
	mrs	x26, far_el1
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	enable_daif
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	ct_user_exit
749
	clear_address_tag x0, x26
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	mov	x1, x25
	mov	x2, sp
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	bl	do_mem_abort
	b	ret_to_user
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el0_ia:
	/*
	 * Instruction abort handling
	 */
758
	mrs	x26, far_el1
759 760 761 762
	enable_da_f
#ifdef CONFIG_TRACE_IRQFLAGS
	bl	trace_hardirqs_off
#endif
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	ct_user_exit
764
	mov	x0, x26
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	mov	x1, x25
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	mov	x2, sp
767
	bl	do_el0_ia_bp_hardening
768
	b	ret_to_user
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el0_fpsimd_acc:
	/*
	 * Floating Point or Advanced SIMD access
	 */
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	enable_daif
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	ct_user_exit
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	mov	x0, x25
	mov	x1, sp
777 778
	bl	do_fpsimd_acc
	b	ret_to_user
779 780 781 782 783 784 785 786 787 788
el0_sve_acc:
	/*
	 * Scalable Vector Extension access
	 */
	enable_daif
	ct_user_exit
	mov	x0, x25
	mov	x1, sp
	bl	do_sve_acc
	b	ret_to_user
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el0_fpsimd_exc:
	/*
791
	 * Floating Point, Advanced SIMD or SVE exception
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	 */
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	enable_daif
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	ct_user_exit
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	mov	x0, x25
	mov	x1, sp
797 798
	bl	do_fpsimd_exc
	b	ret_to_user
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el0_sp_pc:
	/*
	 * Stack or PC alignment exception handling
	 */
803
	mrs	x26, far_el1
804 805 806 807
	enable_da_f
#ifdef CONFIG_TRACE_IRQFLAGS
	bl	trace_hardirqs_off
#endif
808
	ct_user_exit
809
	mov	x0, x26
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	mov	x1, x25
	mov	x2, sp
812 813
	bl	do_sp_pc_abort
	b	ret_to_user
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el0_undef:
	/*
	 * Undefined instruction
	 */
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	enable_daif
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	ct_user_exit
820
	mov	x0, sp
821 822
	bl	do_undefinstr
	b	ret_to_user
823 824 825 826
el0_sys:
	/*
	 * System instructions, for trapped cache maintenance instructions
	 */
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	enable_daif
828 829 830 831 832
	ct_user_exit
	mov	x0, x25
	mov	x1, sp
	bl	do_sysinstr
	b	ret_to_user
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el0_dbg:
	/*
	 * Debug exception handling
	 */
	tbnz	x24, #0, el0_inv		// EL0 only
	mrs	x0, far_el1
	mov	x1, x25
	mov	x2, sp
841
	bl	do_debug_exception
842
	enable_da_f
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	ct_user_exit
844
	b	ret_to_user
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el0_inv:
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	enable_daif
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	ct_user_exit
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	mov	x0, sp
	mov	x1, #BAD_SYNC
850
	mov	x2, x25
851
	bl	bad_el0_sync
852
	b	ret_to_user
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ENDPROC(el0_sync)

	.align	6
el0_irq:
	kernel_entry 0
el0_irq_naked:
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	enable_da_f
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#ifdef CONFIG_TRACE_IRQFLAGS
	bl	trace_hardirqs_off
#endif
863

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	ct_user_exit
865 866 867 868 869
#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
	tbz	x22, #55, 1f
	bl	do_el0_irq_bp_hardening
1:
#endif
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	irq_handler
871

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#ifdef CONFIG_TRACE_IRQFLAGS
	bl	trace_hardirqs_on
#endif
	b	ret_to_user
ENDPROC(el0_irq)

878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893
el1_error:
	kernel_entry 1
	mrs	x1, esr_el1
	enable_dbg
	mov	x0, sp
	bl	do_serror
	kernel_exit 1
ENDPROC(el1_error)

el0_error:
	kernel_entry 0
el0_error_naked:
	mrs	x1, esr_el1
	enable_dbg
	mov	x0, sp
	bl	do_serror
894
	enable_da_f
895 896 897 898
	ct_user_exit
	b	ret_to_user
ENDPROC(el0_error)

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/*
 * Ok, we need to do extra processing, enter the slow path.
 */
work_pending:
	mov	x0, sp				// 'regs'
	bl	do_notify_resume
905
#ifdef CONFIG_TRACE_IRQFLAGS
906
	bl	trace_hardirqs_on		// enabled while in userspace
907
#endif
908
	ldr	x1, [tsk, #TSK_TI_FLAGS]	// re-check for single-step
909
	b	finish_ret_to_user
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/*
 * "slow" syscall return path.
 */
913
ret_to_user:
914
	disable_daif
915
	ldr	x1, [tsk, #TSK_TI_FLAGS]
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	and	x2, x1, #_TIF_WORK_MASK
	cbnz	x2, work_pending
918
finish_ret_to_user:
919
	enable_step_tsk x1, x2
920 921 922
#ifdef CONFIG_GCC_PLUGIN_STACKLEAK
	bl	stackleak_erase
#endif
923
	kernel_exit 0
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ENDPROC(ret_to_user)

/*
 * SVC handler.
 */
	.align	6
el0_svc:
	mov	x0, sp
932
	bl	el0_svc_handler
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	b	ret_to_user
934
ENDPROC(el0_svc)
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936 937
	.popsection				// .entry.text

938 939 940 941 942 943 944 945
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
/*
 * Exception vectors trampoline.
 */
	.pushsection ".entry.tramp.text", "ax"

	.macro tramp_map_kernel, tmp
	mrs	\tmp, ttbr1_el1
946
	add	\tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE)
947 948
	bic	\tmp, \tmp, #USER_ASID_FLAG
	msr	ttbr1_el1, \tmp
949 950 951 952 953 954 955 956 957 958 959 960
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
	/* ASID already in \tmp[63:48] */
	movk	\tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12)
	movk	\tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12)
	/* 2MB boundary containing the vectors, so we nobble the walk cache */
	movk	\tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
	isb
	tlbi	vae1, \tmp
	dsb	nsh
alternative_else_nop_endif
#endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */
961 962 963 964
	.endm

	.macro tramp_unmap_kernel, tmp
	mrs	\tmp, ttbr1_el1
965
	sub	\tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE)
966 967 968
	orr	\tmp, \tmp, #USER_ASID_FLAG
	msr	ttbr1_el1, \tmp
	/*
969 970 971
	 * We avoid running the post_ttbr_update_workaround here because
	 * it's only needed by Cavium ThunderX, which requires KPTI to be
	 * disabled.
972 973 974 975 976 977 978 979 980
	 */
	.endm

	.macro tramp_ventry, regsize = 64
	.align	7
1:
	.if	\regsize == 64
	msr	tpidrro_el0, x30	// Restored in kernel_ventry
	.endif
981 982 983 984 985 986 987 988
	/*
	 * Defend against branch aliasing attacks by pushing a dummy
	 * entry onto the return stack and using a RET instruction to
	 * enter the full-fat kernel vectors.
	 */
	bl	2f
	b	.
2:
989
	tramp_map_kernel	x30
990 991 992 993 994
#ifdef CONFIG_RANDOMIZE_BASE
	adr	x30, tramp_vectors + PAGE_SIZE
alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
	ldr	x30, [x30]
#else
995
	ldr	x30, =vectors
996
#endif
997 998 999 1000
	prfm	plil1strm, [x30, #(1b - tramp_vectors)]
	msr	vbar_el1, x30
	add	x30, x30, #(1b - tramp_vectors)
	isb
1001
	ret
1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038
	.endm

	.macro tramp_exit, regsize = 64
	adr	x30, tramp_vectors
	msr	vbar_el1, x30
	tramp_unmap_kernel	x30
	.if	\regsize == 64
	mrs	x30, far_el1
	.endif
	eret
	.endm

	.align	11
ENTRY(tramp_vectors)
	.space	0x400

	tramp_ventry
	tramp_ventry
	tramp_ventry
	tramp_ventry

	tramp_ventry	32
	tramp_ventry	32
	tramp_ventry	32
	tramp_ventry	32
END(tramp_vectors)

ENTRY(tramp_exit_native)
	tramp_exit
END(tramp_exit_native)

ENTRY(tramp_exit_compat)
	tramp_exit	32
END(tramp_exit_compat)

	.ltorg
	.popsection				// .entry.tramp.text
1039 1040 1041 1042 1043 1044 1045 1046
#ifdef CONFIG_RANDOMIZE_BASE
	.pushsection ".rodata", "a"
	.align PAGE_SHIFT
	.globl	__entry_tramp_data_start
__entry_tramp_data_start:
	.quad	vectors
	.popsection				// .rodata
#endif /* CONFIG_RANDOMIZE_BASE */
1047 1048
#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */

1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086
/*
 * Register switch for AArch64. The callee-saved registers need to be saved
 * and restored. On entry:
 *   x0 = previous task_struct (must be preserved across the switch)
 *   x1 = next task_struct
 * Previous and next are guaranteed not to be the same.
 *
 */
ENTRY(cpu_switch_to)
	mov	x10, #THREAD_CPU_CONTEXT
	add	x8, x0, x10
	mov	x9, sp
	stp	x19, x20, [x8], #16		// store callee-saved registers
	stp	x21, x22, [x8], #16
	stp	x23, x24, [x8], #16
	stp	x25, x26, [x8], #16
	stp	x27, x28, [x8], #16
	stp	x29, x9, [x8], #16
	str	lr, [x8]
	add	x8, x1, x10
	ldp	x19, x20, [x8], #16		// restore callee-saved registers
	ldp	x21, x22, [x8], #16
	ldp	x23, x24, [x8], #16
	ldp	x25, x26, [x8], #16
	ldp	x27, x28, [x8], #16
	ldp	x29, x9, [x8], #16
	ldr	lr, [x8]
	mov	sp, x9
	msr	sp_el0, x1
	ret
ENDPROC(cpu_switch_to)
NOKPROBE(cpu_switch_to)

/*
 * This is how we return from a fork.
 */
ENTRY(ret_from_fork)
	bl	schedule_tail
1087
	cbz	x19, 1f				// not a kernel thread
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	mov	x0, x20
	blr	x19
1090
1:	get_thread_info tsk
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	b	ret_to_user
ENDPROC(ret_from_fork)
NOKPROBE(ret_from_fork)
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#ifdef CONFIG_ARM_SDE_INTERFACE

#include <asm/sdei.h>
#include <uapi/linux/arm_sdei.h>

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.macro sdei_handler_exit exit_mode
	/* On success, this call never returns... */
	cmp	\exit_mode, #SDEI_EXIT_SMC
	b.ne	99f
	smc	#0
	b	.
99:	hvc	#0
	b	.
.endm

#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
/*
 * The regular SDEI entry point may have been unmapped along with the rest of
 * the kernel. This trampoline restores the kernel mapping to make the x1 memory
 * argument accessible.
 *
 * This clobbers x4, __sdei_handler() will restore this from firmware's
 * copy.
 */
.ltorg
.pushsection ".entry.tramp.text", "ax"
ENTRY(__sdei_asm_entry_trampoline)
	mrs	x4, ttbr1_el1
	tbz	x4, #USER_ASID_BIT, 1f

	tramp_map_kernel tmp=x4
	isb
	mov	x4, xzr

	/*
	 * Use reg->interrupted_regs.addr_limit to remember whether to unmap
	 * the kernel on exit.
	 */
1:	str	x4, [x1, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)]

#ifdef CONFIG_RANDOMIZE_BASE
	adr	x4, tramp_vectors + PAGE_SIZE
	add	x4, x4, #:lo12:__sdei_asm_trampoline_next_handler
	ldr	x4, [x4]
#else
	ldr	x4, =__sdei_asm_handler
#endif
	br	x4
ENDPROC(__sdei_asm_entry_trampoline)
NOKPROBE(__sdei_asm_entry_trampoline)

/*
 * Make the exit call and restore the original ttbr1_el1
 *
 * x0 & x1: setup for the exit API call
 * x2: exit_mode
 * x4: struct sdei_registered_event argument from registration time.
 */
ENTRY(__sdei_asm_exit_trampoline)
	ldr	x4, [x4, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)]
	cbnz	x4, 1f

	tramp_unmap_kernel	tmp=x4

1:	sdei_handler_exit exit_mode=x2
ENDPROC(__sdei_asm_exit_trampoline)
NOKPROBE(__sdei_asm_exit_trampoline)
	.ltorg
.popsection		// .entry.tramp.text
#ifdef CONFIG_RANDOMIZE_BASE
.pushsection ".rodata", "a"
__sdei_asm_trampoline_next_handler:
	.quad	__sdei_asm_handler
.popsection		// .rodata
#endif /* CONFIG_RANDOMIZE_BASE */
#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */

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/*
 * Software Delegated Exception entry point.
 *
 * x0: Event number
 * x1: struct sdei_registered_event argument from registration time.
 * x2: interrupted PC
 * x3: interrupted PSTATE
1179
 * x4: maybe clobbered by the trampoline
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 *
 * Firmware has preserved x0->x17 for us, we must save/restore the rest to
 * follow SMC-CC. We save (or retrieve) all the registers as the handler may
 * want them.
 */
ENTRY(__sdei_asm_handler)
	stp     x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC]
	stp     x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2]
	stp     x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3]
	stp     x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4]
	stp     x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5]
	stp     x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6]
	stp     x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7]
	stp     x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8]
	stp     x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9]
	stp     x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
	stp     x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11]
	stp     x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12]
	stp     x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13]
	stp     x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
	mov	x4, sp
	stp     lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR]

	mov	x19, x1

#ifdef CONFIG_VMAP_STACK
	/*
	 * entry.S may have been using sp as a scratch register, find whether
	 * this is a normal or critical event and switch to the appropriate
	 * stack for this CPU.
	 */
	ldrb	w4, [x19, #SDEI_EVENT_PRIORITY]
	cbnz	w4, 1f
	ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6
	b	2f
1:	ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6
2:	mov	x6, #SDEI_STACK_SIZE
	add	x5, x5, x6
	mov	sp, x5
#endif

	/*
	 * We may have interrupted userspace, or a guest, or exit-from or
	 * return-to either of these. We can't trust sp_el0, restore it.
	 */
	mrs	x28, sp_el0
	ldr_this_cpu	dst=x0, sym=__entry_task, tmp=x1
	msr	sp_el0, x0

	/* If we interrupted the kernel point to the previous stack/frame. */
	and     x0, x3, #0xc
	mrs     x1, CurrentEL
	cmp     x0, x1
	csel	x29, x29, xzr, eq	// fp, or zero
	csel	x4, x2, xzr, eq		// elr, or zero

	stp	x29, x4, [sp, #-16]!
	mov	x29, sp

	add	x0, x19, #SDEI_EVENT_INTREGS
	mov	x1, x19
	bl	__sdei_handler

	msr	sp_el0, x28
	/* restore regs >x17 that we clobbered */
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	mov	x4, x19         // keep x4 for __sdei_asm_exit_trampoline
	ldp	x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]
	ldp	x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9]
	ldp	lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR]
	mov	sp, x1
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	mov	x1, x0			// address to complete_and_resume
	/* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */
	cmp	x0, #1
	mov_q	x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE
	mov_q	x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME
	csel	x0, x2, x3, ls

	ldr_l	x2, sdei_exit_mode
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alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
	sdei_handler_exit exit_mode=x2
alternative_else_nop_endif

#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
	tramp_alias	dst=x5, sym=__sdei_asm_exit_trampoline
	br	x5
#endif
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ENDPROC(__sdei_asm_handler)
NOKPROBE(__sdei_asm_handler)
#endif /* CONFIG_ARM_SDE_INTERFACE */