pci.c 85.8 KB
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/*
 * Copyright (c) 2005-2011 Atheros Communications Inc.
 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/pci.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
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#include <linux/bitops.h>
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#include "core.h"
#include "debug.h"

#include "targaddrs.h"
#include "bmi.h"

#include "hif.h"
#include "htc.h"

#include "ce.h"
#include "pci.h"

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enum ath10k_pci_reset_mode {
	ATH10K_PCI_RESET_AUTO = 0,
	ATH10K_PCI_RESET_WARM_ONLY = 1,
};

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static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
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static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
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module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");

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module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");

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/* how long wait to wait for target to initialise, in ms */
#define ATH10K_PCI_TARGET_WAIT 3000
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#define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
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static const struct pci_device_id ath10k_pci_id_table[] = {
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	{ PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
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	{ PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
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	{ PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
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	{ PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */
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	{ PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */
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	{ PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */
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	{ PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */
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	{ PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */
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	{0}
};

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static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = {
	/* QCA988X pre 2.0 chips are not supported because they need some nasty
	 * hacks. ath10k doesn't have them and these devices crash horribly
	 * because of that.
	 */
	{ QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV },
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	{ QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
	{ QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
	{ QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
	{ QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
	{ QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },

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	{ QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
	{ QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
	{ QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
	{ QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
	{ QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
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	{ QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV },
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	{ QCA9984_1_0_DEVICE_ID, QCA9984_HW_1_0_CHIP_ID_REV },

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	{ QCA9888_2_0_DEVICE_ID, QCA9888_HW_2_0_CHIP_ID_REV },

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	{ QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV },
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	{ QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV },
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	{ QCA9887_1_0_DEVICE_ID, QCA9887_HW_1_0_CHIP_ID_REV },
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};

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static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
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static int ath10k_pci_cold_reset(struct ath10k *ar);
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static int ath10k_pci_safe_chip_reset(struct ath10k *ar);
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static int ath10k_pci_init_irq(struct ath10k *ar);
static int ath10k_pci_deinit_irq(struct ath10k *ar);
static int ath10k_pci_request_irq(struct ath10k *ar);
static void ath10k_pci_free_irq(struct ath10k *ar);
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static int ath10k_pci_bmi_wait(struct ath10k *ar,
			       struct ath10k_ce_pipe *tx_pipe,
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			       struct ath10k_ce_pipe *rx_pipe,
			       struct bmi_xfer *xfer);
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static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar);
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static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state);
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static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
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static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state);
static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state);
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static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
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static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state);
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static struct ce_attr host_ce_config_wlan[] = {
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	/* CE0: host->target HTC control and raw streams */
	{
		.flags = CE_ATTR_FLAGS,
		.src_nentries = 16,
		.src_sz_max = 256,
		.dest_nentries = 0,
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		.send_cb = ath10k_pci_htc_tx_cb,
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	},

	/* CE1: target->host HTT + HTC control */
	{
		.flags = CE_ATTR_FLAGS,
		.src_nentries = 0,
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		.src_sz_max = 2048,
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		.dest_nentries = 512,
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		.recv_cb = ath10k_pci_htt_htc_rx_cb,
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	},

	/* CE2: target->host WMI */
	{
		.flags = CE_ATTR_FLAGS,
		.src_nentries = 0,
		.src_sz_max = 2048,
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		.dest_nentries = 128,
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		.recv_cb = ath10k_pci_htc_rx_cb,
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	},

	/* CE3: host->target WMI */
	{
		.flags = CE_ATTR_FLAGS,
		.src_nentries = 32,
		.src_sz_max = 2048,
		.dest_nentries = 0,
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		.send_cb = ath10k_pci_htc_tx_cb,
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	},

	/* CE4: host->target HTT */
	{
		.flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
		.src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
		.src_sz_max = 256,
		.dest_nentries = 0,
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		.send_cb = ath10k_pci_htt_tx_cb,
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	},

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	/* CE5: target->host HTT (HIF->HTT) */
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	{
		.flags = CE_ATTR_FLAGS,
		.src_nentries = 0,
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		.src_sz_max = 512,
		.dest_nentries = 512,
		.recv_cb = ath10k_pci_htt_rx_cb,
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	},

	/* CE6: target autonomous hif_memcpy */
	{
		.flags = CE_ATTR_FLAGS,
		.src_nentries = 0,
		.src_sz_max = 0,
		.dest_nentries = 0,
	},

	/* CE7: ce_diag, the Diagnostic Window */
	{
		.flags = CE_ATTR_FLAGS,
		.src_nentries = 2,
		.src_sz_max = DIAG_TRANSFER_LIMIT,
		.dest_nentries = 2,
	},
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	/* CE8: target->host pktlog */
	{
		.flags = CE_ATTR_FLAGS,
		.src_nentries = 0,
		.src_sz_max = 2048,
		.dest_nentries = 128,
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		.recv_cb = ath10k_pci_pktlog_rx_cb,
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	},

	/* CE9 target autonomous qcache memcpy */
	{
		.flags = CE_ATTR_FLAGS,
		.src_nentries = 0,
		.src_sz_max = 0,
		.dest_nentries = 0,
	},

	/* CE10: target autonomous hif memcpy */
	{
		.flags = CE_ATTR_FLAGS,
		.src_nentries = 0,
		.src_sz_max = 0,
		.dest_nentries = 0,
	},

	/* CE11: target autonomous hif memcpy */
	{
		.flags = CE_ATTR_FLAGS,
		.src_nentries = 0,
		.src_sz_max = 0,
		.dest_nentries = 0,
	},
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};

/* Target firmware's Copy Engine configuration. */
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static struct ce_pipe_config target_ce_config_wlan[] = {
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	/* CE0: host->target HTC control and raw streams */
	{
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		.pipenum = __cpu_to_le32(0),
		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
		.nentries = __cpu_to_le32(32),
		.nbytes_max = __cpu_to_le32(256),
		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
		.reserved = __cpu_to_le32(0),
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	},

	/* CE1: target->host HTT + HTC control */
	{
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		.pipenum = __cpu_to_le32(1),
		.pipedir = __cpu_to_le32(PIPEDIR_IN),
		.nentries = __cpu_to_le32(32),
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		.nbytes_max = __cpu_to_le32(2048),
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		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
		.reserved = __cpu_to_le32(0),
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	},

	/* CE2: target->host WMI */
	{
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		.pipenum = __cpu_to_le32(2),
		.pipedir = __cpu_to_le32(PIPEDIR_IN),
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		.nentries = __cpu_to_le32(64),
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		.nbytes_max = __cpu_to_le32(2048),
		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
		.reserved = __cpu_to_le32(0),
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	},

	/* CE3: host->target WMI */
	{
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		.pipenum = __cpu_to_le32(3),
		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
		.nentries = __cpu_to_le32(32),
		.nbytes_max = __cpu_to_le32(2048),
		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
		.reserved = __cpu_to_le32(0),
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	},

	/* CE4: host->target HTT */
	{
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		.pipenum = __cpu_to_le32(4),
		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
		.nentries = __cpu_to_le32(256),
		.nbytes_max = __cpu_to_le32(256),
		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
		.reserved = __cpu_to_le32(0),
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	},

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	/* NB: 50% of src nentries, since tx has 2 frags */
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	/* CE5: target->host HTT (HIF->HTT) */
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	{
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		.pipenum = __cpu_to_le32(5),
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		.pipedir = __cpu_to_le32(PIPEDIR_IN),
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		.nentries = __cpu_to_le32(32),
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		.nbytes_max = __cpu_to_le32(512),
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		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
		.reserved = __cpu_to_le32(0),
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	},

	/* CE6: Reserved for target autonomous hif_memcpy */
	{
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		.pipenum = __cpu_to_le32(6),
		.pipedir = __cpu_to_le32(PIPEDIR_INOUT),
		.nentries = __cpu_to_le32(32),
		.nbytes_max = __cpu_to_le32(4096),
		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
		.reserved = __cpu_to_le32(0),
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	},

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	/* CE7 used only by Host */
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	{
		.pipenum = __cpu_to_le32(7),
		.pipedir = __cpu_to_le32(PIPEDIR_INOUT),
		.nentries = __cpu_to_le32(0),
		.nbytes_max = __cpu_to_le32(0),
		.flags = __cpu_to_le32(0),
		.reserved = __cpu_to_le32(0),
	},

	/* CE8 target->host packtlog */
	{
		.pipenum = __cpu_to_le32(8),
		.pipedir = __cpu_to_le32(PIPEDIR_IN),
		.nentries = __cpu_to_le32(64),
		.nbytes_max = __cpu_to_le32(2048),
		.flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
		.reserved = __cpu_to_le32(0),
	},

	/* CE9 target autonomous qcache memcpy */
	{
		.pipenum = __cpu_to_le32(9),
		.pipedir = __cpu_to_le32(PIPEDIR_INOUT),
		.nentries = __cpu_to_le32(32),
		.nbytes_max = __cpu_to_le32(2048),
		.flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
		.reserved = __cpu_to_le32(0),
	},

	/* It not necessary to send target wlan configuration for CE10 & CE11
	 * as these CEs are not actively used in target.
	 */
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};

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/*
 * Map from service/endpoint to Copy Engine.
 * This table is derived from the CE_PCI TABLE, above.
 * It is passed to the Target at startup for use by firmware.
 */
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static struct service_to_pipe target_service_to_ce_map_wlan[] = {
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	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
		__cpu_to_le32(3),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
		__cpu_to_le32(2),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
		__cpu_to_le32(3),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
		__cpu_to_le32(2),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
		__cpu_to_le32(3),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
		__cpu_to_le32(2),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
		__cpu_to_le32(3),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
		__cpu_to_le32(2),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
		__cpu_to_le32(3),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
		__cpu_to_le32(2),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
		__cpu_to_le32(0),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
		__cpu_to_le32(1),
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	},
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	{ /* not used */
		__cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
		__cpu_to_le32(0),
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	},
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	{ /* not used */
		__cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
		__cpu_to_le32(1),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
		__cpu_to_le32(4),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
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		__cpu_to_le32(5),
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	},

	/* (Additions here) */

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	{ /* must be last */
		__cpu_to_le32(0),
		__cpu_to_le32(0),
		__cpu_to_le32(0),
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	},
};

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static bool ath10k_pci_is_awake(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
			   RTC_STATE_ADDRESS);

	return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
}

static void __ath10k_pci_wake(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	lockdep_assert_held(&ar_pci->ps_lock);

	ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n",
		   ar_pci->ps_wake_refcount, ar_pci->ps_awake);

	iowrite32(PCIE_SOC_WAKE_V_MASK,
		  ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
		  PCIE_SOC_WAKE_ADDRESS);
}

static void __ath10k_pci_sleep(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	lockdep_assert_held(&ar_pci->ps_lock);

	ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n",
		   ar_pci->ps_wake_refcount, ar_pci->ps_awake);

	iowrite32(PCIE_SOC_WAKE_RESET,
		  ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
		  PCIE_SOC_WAKE_ADDRESS);
	ar_pci->ps_awake = false;
}

static int ath10k_pci_wake_wait(struct ath10k *ar)
{
	int tot_delay = 0;
	int curr_delay = 5;

	while (tot_delay < PCIE_WAKE_TIMEOUT) {
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		if (ath10k_pci_is_awake(ar)) {
			if (tot_delay > PCIE_WAKE_LATE_US)
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				ath10k_warn(ar, "device wakeup took %d ms which is unusually long, otherwise it works normally.\n",
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					    tot_delay / 1000);
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			return 0;
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		}
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		udelay(curr_delay);
		tot_delay += curr_delay;

		if (curr_delay < 50)
			curr_delay += 5;
	}

	return -ETIMEDOUT;
}

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static int ath10k_pci_force_wake(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	unsigned long flags;
	int ret = 0;

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	if (ar_pci->pci_ps)
		return ret;

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	spin_lock_irqsave(&ar_pci->ps_lock, flags);

	if (!ar_pci->ps_awake) {
		iowrite32(PCIE_SOC_WAKE_V_MASK,
			  ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
			  PCIE_SOC_WAKE_ADDRESS);

		ret = ath10k_pci_wake_wait(ar);
		if (ret == 0)
			ar_pci->ps_awake = true;
	}

	spin_unlock_irqrestore(&ar_pci->ps_lock, flags);

	return ret;
}

static void ath10k_pci_force_sleep(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	unsigned long flags;

	spin_lock_irqsave(&ar_pci->ps_lock, flags);

	iowrite32(PCIE_SOC_WAKE_RESET,
		  ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
		  PCIE_SOC_WAKE_ADDRESS);
	ar_pci->ps_awake = false;

	spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
}

528 529 530 531 532 533
static int ath10k_pci_wake(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	unsigned long flags;
	int ret = 0;

534 535 536
	if (ar_pci->pci_ps == 0)
		return ret;

537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567
	spin_lock_irqsave(&ar_pci->ps_lock, flags);

	ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n",
		   ar_pci->ps_wake_refcount, ar_pci->ps_awake);

	/* This function can be called very frequently. To avoid excessive
	 * CPU stalls for MMIO reads use a cache var to hold the device state.
	 */
	if (!ar_pci->ps_awake) {
		__ath10k_pci_wake(ar);

		ret = ath10k_pci_wake_wait(ar);
		if (ret == 0)
			ar_pci->ps_awake = true;
	}

	if (ret == 0) {
		ar_pci->ps_wake_refcount++;
		WARN_ON(ar_pci->ps_wake_refcount == 0);
	}

	spin_unlock_irqrestore(&ar_pci->ps_lock, flags);

	return ret;
}

static void ath10k_pci_sleep(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	unsigned long flags;

568 569 570
	if (ar_pci->pci_ps == 0)
		return;

571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612
	spin_lock_irqsave(&ar_pci->ps_lock, flags);

	ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n",
		   ar_pci->ps_wake_refcount, ar_pci->ps_awake);

	if (WARN_ON(ar_pci->ps_wake_refcount == 0))
		goto skip;

	ar_pci->ps_wake_refcount--;

	mod_timer(&ar_pci->ps_timer, jiffies +
		  msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC));

skip:
	spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
}

static void ath10k_pci_ps_timer(unsigned long ptr)
{
	struct ath10k *ar = (void *)ptr;
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	unsigned long flags;

	spin_lock_irqsave(&ar_pci->ps_lock, flags);

	ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n",
		   ar_pci->ps_wake_refcount, ar_pci->ps_awake);

	if (ar_pci->ps_wake_refcount > 0)
		goto skip;

	__ath10k_pci_sleep(ar);

skip:
	spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
}

static void ath10k_pci_sleep_sync(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	unsigned long flags;

613 614 615 616 617
	if (ar_pci->pci_ps == 0) {
		ath10k_pci_force_sleep(ar);
		return;
	}

618 619 620 621 622 623 624 625
	del_timer_sync(&ar_pci->ps_timer);

	spin_lock_irqsave(&ar_pci->ps_lock, flags);
	WARN_ON(ar_pci->ps_wake_refcount > 0);
	__ath10k_pci_sleep(ar);
	spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
}

626
static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value)
627 628 629 630
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	int ret;

631 632 633 634 635 636
	if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) {
		ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
			    offset, offset + sizeof(value), ar_pci->mem_len);
		return;
	}

637 638 639 640 641 642 643 644 645 646 647
	ret = ath10k_pci_wake(ar);
	if (ret) {
		ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n",
			    value, offset, ret);
		return;
	}

	iowrite32(value, ar_pci->mem + offset);
	ath10k_pci_sleep(ar);
}

648
static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset)
649 650 651 652 653
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	u32 val;
	int ret;

654 655 656 657 658 659
	if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) {
		ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
			    offset, offset + sizeof(val), ar_pci->mem_len);
		return 0;
	}

660 661 662 663 664 665 666 667 668 669 670 671 672
	ret = ath10k_pci_wake(ar);
	if (ret) {
		ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n",
			    offset, ret);
		return 0xffffffff;
	}

	val = ioread32(ar_pci->mem + offset);
	ath10k_pci_sleep(ar);

	return val;
}

673 674
inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value)
{
675
	struct ath10k_ce *ce = ath10k_ce_priv(ar);
676

677
	ce->bus_ops->write32(ar, offset, value);
678 679 680 681
}

inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
{
682
	struct ath10k_ce *ce = ath10k_ce_priv(ar);
683

684
	return ce->bus_ops->read32(ar, offset);
685 686
}

687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706
u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
{
	return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
}

void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
{
	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
}

u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
{
	return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr);
}

void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
{
	ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val);
}

707
bool ath10k_pci_irq_pending(struct ath10k *ar)
708 709 710 711 712 713 714 715 716 717 718 719
{
	u32 cause;

	/* Check if the shared legacy irq is for us */
	cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
				  PCIE_INTR_CAUSE_ADDRESS);
	if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
		return true;

	return false;
}

720
void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
721 722 723
{
	/* IMPORTANT: INTR_CLR register has to be set after
	 * INTR_ENABLE is set to 0, otherwise interrupt can not be
724 725
	 * really cleared.
	 */
726 727 728 729 730 731
	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
			   0);
	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
			   PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);

	/* IMPORTANT: this extra read transaction is required to
732 733
	 * flush the posted write buffer.
	 */
734 735
	(void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
				PCIE_INTR_ENABLE_ADDRESS);
736 737
}

738
void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
739 740 741 742 743 744
{
	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
			   PCIE_INTR_ENABLE_ADDRESS,
			   PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);

	/* IMPORTANT: this extra read transaction is required to
745 746
	 * flush the posted write buffer.
	 */
747 748
	(void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
				PCIE_INTR_ENABLE_ADDRESS);
749 750
}

751
static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar)
752 753 754
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

755
	if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI)
756
		return "msi";
757 758

	return "legacy";
759 760
}

761
static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
762
{
763
	struct ath10k *ar = pipe->hif_ce_state;
764
	struct ath10k_ce *ce = ath10k_ce_priv(ar);
765 766 767
	struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
	struct sk_buff *skb;
	dma_addr_t paddr;
768 769
	int ret;

770 771 772 773 774 775 776 777 778 779
	skb = dev_alloc_skb(pipe->buf_sz);
	if (!skb)
		return -ENOMEM;

	WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");

	paddr = dma_map_single(ar->dev, skb->data,
			       skb->len + skb_tailroom(skb),
			       DMA_FROM_DEVICE);
	if (unlikely(dma_mapping_error(ar->dev, paddr))) {
780
		ath10k_warn(ar, "failed to dma map pci rx buf\n");
781 782 783 784
		dev_kfree_skb_any(skb);
		return -EIO;
	}

785
	ATH10K_SKB_RXCB(skb)->paddr = paddr;
786

787
	spin_lock_bh(&ce->ce_lock);
788
	ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr);
789
	spin_unlock_bh(&ce->ce_lock);
790
	if (ret) {
791 792 793
		dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
				 DMA_FROM_DEVICE);
		dev_kfree_skb_any(skb);
794 795 796 797 798 799
		return ret;
	}

	return 0;
}

800
static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
801
{
802 803
	struct ath10k *ar = pipe->hif_ce_state;
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
804
	struct ath10k_ce *ce = ath10k_ce_priv(ar);
805 806 807 808 809 810 811 812 813
	struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
	int ret, num;

	if (pipe->buf_sz == 0)
		return;

	if (!ce_pipe->dest_ring)
		return;

814
	spin_lock_bh(&ce->ce_lock);
815
	num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
816
	spin_unlock_bh(&ce->ce_lock);
817 818

	while (num >= 0) {
819 820
		ret = __ath10k_pci_rx_post_buf(pipe);
		if (ret) {
821 822
			if (ret == -ENOSPC)
				break;
823
			ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
824 825 826 827
			mod_timer(&ar_pci->rx_post_retry, jiffies +
				  ATH10K_PCI_RX_POST_RETRY_MS);
			break;
		}
828
		num--;
829 830 831
	}
}

832
void ath10k_pci_rx_post(struct ath10k *ar)
833 834 835 836 837
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	int i;

	for (i = 0; i < CE_COUNT; i++)
838
		ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]);
839 840
}

841
void ath10k_pci_rx_replenish_retry(unsigned long ptr)
842 843 844 845
{
	struct ath10k *ar = (void *)ptr;

	ath10k_pci_rx_post(ar);
846 847
}

848
static u32 ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
849
{
850
	u32 val = 0, region = addr & 0xfffff;
851

852 853 854 855 856 857 858 859 860
	val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)
				 & 0x7ff) << 21;
	val |= 0x100000 | region;
	return val;
}

static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
{
	u32 val = 0, region = addr & 0xfffff;
861

862 863
	val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
	val |= 0x100000 | region;
864 865 866
	return val;
}

867 868 869 870 871 872 873 874 875 876
static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	if (WARN_ON_ONCE(!ar_pci->targ_cpu_to_ce_addr))
		return -ENOTSUPP;

	return ar_pci->targ_cpu_to_ce_addr(ar, addr);
}

877 878 879 880 881 882 883 884 885
/*
 * Diagnostic read/write access is provided for startup/config/debug usage.
 * Caller must guarantee proper alignment, when applicable, and single user
 * at any moment.
 */
static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
				    int nbytes)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
886
	struct ath10k_ce *ce = ath10k_ce_priv(ar);
887
	int ret = 0;
888
	u32 *buf;
889
	unsigned int completed_nbytes, alloc_nbytes, remaining_bytes;
890
	struct ath10k_ce_pipe *ce_diag;
891 892 893 894 895 896
	/* Host buffer address in CE space */
	u32 ce_data;
	dma_addr_t ce_data_base = 0;
	void *data_buf = NULL;
	int i;

897
	spin_lock_bh(&ce->ce_lock);
K
Kalle Valo 已提交
898

899 900 901 902 903 904 905 906
	ce_diag = ar_pci->ce_diag;

	/*
	 * Allocate a temporary bounce buffer to hold caller's data
	 * to be DMA'ed from Target. This guarantees
	 *   1) 4-byte alignment
	 *   2) Buffer in DMA-able space
	 */
907 908
	alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT);

909
	data_buf = (unsigned char *)dma_zalloc_coherent(ar->dev,
910
						       alloc_nbytes,
911 912
						       &ce_data_base,
						       GFP_ATOMIC);
913 914 915 916 917 918

	if (!data_buf) {
		ret = -ENOMEM;
		goto done;
	}

919
	remaining_bytes = nbytes;
920 921 922 923 924
	ce_data = ce_data_base;
	while (remaining_bytes) {
		nbytes = min_t(unsigned int, remaining_bytes,
			       DIAG_TRANSFER_LIMIT);

925
		ret = __ath10k_ce_rx_post_buf(ce_diag, &ce_data, ce_data);
926 927 928 929 930 931 932 933 934 935 936 937
		if (ret != 0)
			goto done;

		/* Request CE to send from Target(!) address to Host buffer */
		/*
		 * The address supplied by the caller is in the
		 * Target CPU virtual address space.
		 *
		 * In order to use this address with the diagnostic CE,
		 * convert it from Target CPU virtual address space
		 * to CE address space
		 */
938
		address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
939

K
Kalle Valo 已提交
940 941
		ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0,
					    0);
942 943 944 945
		if (ret)
			goto done;

		i = 0;
946 947
		while (ath10k_ce_completed_send_next_nolock(ce_diag,
							    NULL) != 0) {
948 949 950 951 952 953 954 955
			mdelay(1);
			if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
				ret = -EBUSY;
				goto done;
			}
		}

		i = 0;
956 957 958 959
		while (ath10k_ce_completed_recv_next_nolock(ce_diag,
							    (void **)&buf,
							    &completed_nbytes)
								!= 0) {
960 961 962 963 964 965 966 967 968 969 970 971 972
			mdelay(1);

			if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
				ret = -EBUSY;
				goto done;
			}
		}

		if (nbytes != completed_nbytes) {
			ret = -EIO;
			goto done;
		}

973
		if (*buf != ce_data) {
974 975 976 977 978
			ret = -EIO;
			goto done;
		}

		remaining_bytes -= nbytes;
979 980
		memcpy(data, data_buf, nbytes);

981
		address += nbytes;
982
		data += nbytes;
983 984 985 986 987
	}

done:

	if (data_buf)
988
		dma_free_coherent(ar->dev, alloc_nbytes, data_buf,
989
				  ce_data_base);
990

991
	spin_unlock_bh(&ce->ce_lock);
K
Kalle Valo 已提交
992

993 994 995
	return ret;
}

996 997
static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value)
{
998 999 1000 1001 1002 1003 1004
	__le32 val = 0;
	int ret;

	ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val));
	*value = __le32_to_cpu(val);

	return ret;
1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016
}

static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest,
				     u32 src, u32 len)
{
	u32 host_addr, addr;
	int ret;

	host_addr = host_interest_item_address(src);

	ret = ath10k_pci_diag_read32(ar, host_addr, &addr);
	if (ret != 0) {
1017
		ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n",
1018 1019 1020 1021 1022 1023
			    src, ret);
		return ret;
	}

	ret = ath10k_pci_diag_read_mem(ar, addr, dest, len);
	if (ret != 0) {
1024
		ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n",
1025 1026 1027 1028 1029 1030 1031 1032
			    addr, len, ret);
		return ret;
	}

	return 0;
}

#define ath10k_pci_diag_read_hi(ar, dest, src, len)		\
1033
	__ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
1034

1035 1036
int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
			      const void *data, int nbytes)
1037 1038
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1039
	struct ath10k_ce *ce = ath10k_ce_priv(ar);
1040
	int ret = 0;
1041
	u32 *buf;
1042
	unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
1043
	struct ath10k_ce_pipe *ce_diag;
1044 1045 1046 1047 1048
	void *data_buf = NULL;
	u32 ce_data;	/* Host buffer address in CE space */
	dma_addr_t ce_data_base = 0;
	int i;

1049
	spin_lock_bh(&ce->ce_lock);
K
Kalle Valo 已提交
1050

1051 1052 1053 1054 1055 1056 1057 1058 1059
	ce_diag = ar_pci->ce_diag;

	/*
	 * Allocate a temporary bounce buffer to hold caller's data
	 * to be DMA'ed to Target. This guarantees
	 *   1) 4-byte alignment
	 *   2) Buffer in DMA-able space
	 */
	orig_nbytes = nbytes;
1060 1061 1062 1063
	data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
						       orig_nbytes,
						       &ce_data_base,
						       GFP_ATOMIC);
1064 1065 1066 1067 1068 1069
	if (!data_buf) {
		ret = -ENOMEM;
		goto done;
	}

	/* Copy caller's data to allocated DMA buf */
1070
	memcpy(data_buf, data, orig_nbytes);
1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081

	/*
	 * The address supplied by the caller is in the
	 * Target CPU virtual address space.
	 *
	 * In order to use this address with the diagnostic CE,
	 * convert it from
	 *    Target CPU virtual address space
	 * to
	 *    CE address space
	 */
1082
	address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
1083 1084 1085 1086 1087 1088 1089 1090

	remaining_bytes = orig_nbytes;
	ce_data = ce_data_base;
	while (remaining_bytes) {
		/* FIXME: check cast */
		nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);

		/* Set up to receive directly into Target(!) address */
1091
		ret = __ath10k_ce_rx_post_buf(ce_diag, &address, address);
1092 1093 1094 1095 1096 1097 1098
		if (ret != 0)
			goto done;

		/*
		 * Request CE to send caller-supplied data that
		 * was copied to bounce buffer to Target(!) address.
		 */
K
Kalle Valo 已提交
1099 1100
		ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)ce_data,
					    nbytes, 0, 0);
1101 1102 1103 1104
		if (ret != 0)
			goto done;

		i = 0;
1105 1106
		while (ath10k_ce_completed_send_next_nolock(ce_diag,
							    NULL) != 0) {
1107 1108 1109 1110 1111 1112 1113 1114 1115
			mdelay(1);

			if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
				ret = -EBUSY;
				goto done;
			}
		}

		i = 0;
1116 1117 1118 1119
		while (ath10k_ce_completed_recv_next_nolock(ce_diag,
							    (void **)&buf,
							    &completed_nbytes)
								!= 0) {
1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132
			mdelay(1);

			if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
				ret = -EBUSY;
				goto done;
			}
		}

		if (nbytes != completed_nbytes) {
			ret = -EIO;
			goto done;
		}

1133
		if (*buf != address) {
1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144
			ret = -EIO;
			goto done;
		}

		remaining_bytes -= nbytes;
		address += nbytes;
		ce_data += nbytes;
	}

done:
	if (data_buf) {
1145 1146
		dma_free_coherent(ar->dev, orig_nbytes, data_buf,
				  ce_data_base);
1147 1148 1149
	}

	if (ret != 0)
1150
		ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n",
K
Kalle Valo 已提交
1151
			    address, ret);
1152

1153
	spin_unlock_bh(&ce->ce_lock);
K
Kalle Valo 已提交
1154

1155 1156 1157
	return ret;
}

1158 1159 1160 1161 1162 1163 1164
static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value)
{
	__le32 val = __cpu_to_le32(value);

	return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val));
}

1165
/* Called by lower (CE) layer when a send to Target completes. */
1166
static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state)
1167 1168
{
	struct ath10k *ar = ce_state->ar;
1169 1170
	struct sk_buff_head list;
	struct sk_buff *skb;
1171

1172
	__skb_queue_head_init(&list);
1173
	while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1174
		/* no need to call tx completion for NULL pointers */
1175
		if (skb == NULL)
1176 1177
			continue;

1178
		__skb_queue_tail(&list, skb);
1179
	}
1180 1181

	while ((skb = __skb_dequeue(&list)))
1182
		ath10k_htc_tx_completion_handler(ar, skb);
1183 1184
}

1185 1186 1187
static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state,
				     void (*callback)(struct ath10k *ar,
						      struct sk_buff *skb))
1188 1189 1190
{
	struct ath10k *ar = ce_state->ar;
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1191
	struct ath10k_pci_pipe *pipe_info =  &ar_pci->pipe_info[ce_state->id];
1192
	struct sk_buff *skb;
1193
	struct sk_buff_head list;
1194
	void *transfer_context;
1195
	unsigned int nbytes, max_nbytes;
1196

1197
	__skb_queue_head_init(&list);
1198
	while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
1199
					     &nbytes) == 0) {
1200
		skb = transfer_context;
1201
		max_nbytes = skb->len + skb_tailroom(skb);
1202
		dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1203 1204 1205
				 max_nbytes, DMA_FROM_DEVICE);

		if (unlikely(max_nbytes < nbytes)) {
1206
			ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1207 1208 1209 1210
				    nbytes, max_nbytes);
			dev_kfree_skb_any(skb);
			continue;
		}
1211

1212
		skb_put(skb, nbytes);
1213 1214
		__skb_queue_tail(&list, skb);
	}
1215

1216
	while ((skb = __skb_dequeue(&list))) {
1217 1218 1219 1220 1221
		ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
			   ce_state->id, skb->len);
		ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
				skb->data, skb->len);

1222
		callback(ar, skb);
1223
	}
1224

1225
	ath10k_pci_rx_post_pipe(pipe_info);
1226 1227
}

1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284
static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe *ce_state,
					 void (*callback)(struct ath10k *ar,
							  struct sk_buff *skb))
{
	struct ath10k *ar = ce_state->ar;
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	struct ath10k_pci_pipe *pipe_info =  &ar_pci->pipe_info[ce_state->id];
	struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl;
	struct sk_buff *skb;
	struct sk_buff_head list;
	void *transfer_context;
	unsigned int nbytes, max_nbytes, nentries;
	int orig_len;

	/* No need to aquire ce_lock for CE5, since this is the only place CE5
	 * is processed other than init and deinit. Before releasing CE5
	 * buffers, interrupts are disabled. Thus CE5 access is serialized.
	 */
	__skb_queue_head_init(&list);
	while (ath10k_ce_completed_recv_next_nolock(ce_state, &transfer_context,
						    &nbytes) == 0) {
		skb = transfer_context;
		max_nbytes = skb->len + skb_tailroom(skb);

		if (unlikely(max_nbytes < nbytes)) {
			ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
				    nbytes, max_nbytes);
			continue;
		}

		dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
					max_nbytes, DMA_FROM_DEVICE);
		skb_put(skb, nbytes);
		__skb_queue_tail(&list, skb);
	}

	nentries = skb_queue_len(&list);
	while ((skb = __skb_dequeue(&list))) {
		ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
			   ce_state->id, skb->len);
		ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
				skb->data, skb->len);

		orig_len = skb->len;
		callback(ar, skb);
		skb_push(skb, orig_len - skb->len);
		skb_reset_tail_pointer(skb);
		skb_trim(skb, 0);

		/*let device gain the buffer again*/
		dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
					   skb->len + skb_tailroom(skb),
					   DMA_FROM_DEVICE);
	}
	ath10k_ce_rx_update_write_idx(ce_pipe, nentries);
}

1285 1286 1287 1288
/* Called by lower (CE) layer when data is received from the Target. */
static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
{
	ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1289 1290 1291 1292 1293 1294 1295 1296 1297 1298
}

static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
{
	/* CE4 polling needs to be done whenever CE pipe which transports
	 * HTT Rx (target->host) is processed.
	 */
	ath10k_ce_per_engine_service(ce_state->ar, 4);

	ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1299 1300
}

1301 1302 1303 1304 1305 1306 1307 1308 1309
/* Called by lower (CE) layer when data is received from the Target.
 * Only 10.4 firmware uses separate CE to transfer pktlog data.
 */
static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state)
{
	ath10k_pci_process_rx_cb(ce_state,
				 ath10k_htt_rx_pktlog_completion_handler);
}

1310 1311 1312 1313 1314 1315
/* Called by lower (CE) layer when a send to HTT Target completes. */
static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state)
{
	struct ath10k *ar = ce_state->ar;
	struct sk_buff *skb;

1316
	while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340
		/* no need to call tx completion for NULL pointers */
		if (!skb)
			continue;

		dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
				 skb->len, DMA_TO_DEVICE);
		ath10k_htt_hif_tx_complete(ar, skb);
	}
}

static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb)
{
	skb_pull(skb, sizeof(struct ath10k_htc_hdr));
	ath10k_htt_t2h_msg_handler(ar, skb);
}

/* Called by lower (CE) layer when HTT data is received from the Target. */
static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state)
{
	/* CE4 polling needs to be done whenever CE pipe which transports
	 * HTT Rx (target->host) is processed.
	 */
	ath10k_ce_per_engine_service(ce_state->ar, 4);

1341
	ath10k_pci_process_htt_rx_cb(ce_state, ath10k_pci_htt_rx_deliver);
1342 1343
}

1344 1345
int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
			 struct ath10k_hif_sg_item *items, int n_items)
1346 1347
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1348
	struct ath10k_ce *ce = ath10k_ce_priv(ar);
1349 1350 1351
	struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
	struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
	struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
1352 1353 1354
	unsigned int nentries_mask;
	unsigned int sw_index;
	unsigned int write_index;
1355
	int err, i = 0;
1356

1357
	spin_lock_bh(&ce->ce_lock);
1358

1359 1360 1361 1362
	nentries_mask = src_ring->nentries_mask;
	sw_index = src_ring->sw_index;
	write_index = src_ring->write_index;

1363 1364 1365
	if (unlikely(CE_RING_DELTA(nentries_mask,
				   write_index, sw_index - 1) < n_items)) {
		err = -ENOBUFS;
1366
		goto err;
1367
	}
1368

1369
	for (i = 0; i < n_items - 1; i++) {
1370
		ath10k_dbg(ar, ATH10K_DBG_PCI,
1371 1372
			   "pci tx item %d paddr 0x%08x len %d n_items %d\n",
			   i, items[i].paddr, items[i].len, n_items);
1373
		ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1374
				items[i].vaddr, items[i].len);
1375

1376 1377 1378 1379 1380 1381 1382
		err = ath10k_ce_send_nolock(ce_pipe,
					    items[i].transfer_context,
					    items[i].paddr,
					    items[i].len,
					    items[i].transfer_id,
					    CE_SEND_FLAG_GATHER);
		if (err)
1383
			goto err;
1384 1385 1386 1387
	}

	/* `i` is equal to `n_items -1` after for() */

1388
	ath10k_dbg(ar, ATH10K_DBG_PCI,
1389 1390
		   "pci tx item %d paddr 0x%08x len %d n_items %d\n",
		   i, items[i].paddr, items[i].len, n_items);
1391
	ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1392 1393 1394 1395 1396 1397 1398 1399 1400
			items[i].vaddr, items[i].len);

	err = ath10k_ce_send_nolock(ce_pipe,
				    items[i].transfer_context,
				    items[i].paddr,
				    items[i].len,
				    items[i].transfer_id,
				    0);
	if (err)
1401 1402
		goto err;

1403
	spin_unlock_bh(&ce->ce_lock);
1404 1405 1406 1407 1408
	return 0;

err:
	for (; i > 0; i--)
		__ath10k_ce_send_revert(ce_pipe);
1409

1410
	spin_unlock_bh(&ce->ce_lock);
1411
	return err;
1412 1413
}

1414 1415
int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
			     size_t buf_len)
K
Kalle Valo 已提交
1416 1417 1418 1419
{
	return ath10k_pci_diag_read_mem(ar, address, buf, buf_len);
}

1420
u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
1421 1422
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
K
Kalle Valo 已提交
1423

1424
	ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n");
K
Kalle Valo 已提交
1425

M
Michal Kazior 已提交
1426
	return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
1427 1428
}

1429 1430
static void ath10k_pci_dump_registers(struct ath10k *ar,
				      struct ath10k_fw_crash_data *crash_data)
1431
{
1432 1433
	__le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
	int i, ret;
1434

1435
	lockdep_assert_held(&ar->data_lock);
1436

1437 1438
	ret = ath10k_pci_diag_read_hi(ar, &reg_dump_values[0],
				      hi_failure_state,
1439
				      REG_DUMP_COUNT_QCA988X * sizeof(__le32));
1440
	if (ret) {
1441
		ath10k_err(ar, "failed to read firmware dump area: %d\n", ret);
1442 1443 1444 1445 1446
		return;
	}

	BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);

1447
	ath10k_err(ar, "firmware register dump:\n");
1448
	for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
1449
		ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
1450
			   i,
1451 1452 1453 1454
			   __le32_to_cpu(reg_dump_values[i]),
			   __le32_to_cpu(reg_dump_values[i + 1]),
			   __le32_to_cpu(reg_dump_values[i + 2]),
			   __le32_to_cpu(reg_dump_values[i + 3]));
1455

M
Michal Kazior 已提交
1456 1457 1458
	if (!crash_data)
		return;

1459
	for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++)
1460
		crash_data->registers[i] = reg_dump_values[i];
1461 1462
}

1463
static void ath10k_pci_fw_crashed_dump(struct ath10k *ar)
1464 1465
{
	struct ath10k_fw_crash_data *crash_data;
1466
	char guid[UUID_STRING_LEN + 1];
1467 1468 1469

	spin_lock_bh(&ar->data_lock);

B
Ben Greear 已提交
1470 1471
	ar->stats.fw_crash_counter++;

1472 1473 1474
	crash_data = ath10k_debug_get_new_fw_crash_data(ar);

	if (crash_data)
1475
		scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid);
1476
	else
1477
		scnprintf(guid, sizeof(guid), "n/a");
1478

1479
	ath10k_err(ar, "firmware crashed! (guid %s)\n", guid);
1480
	ath10k_print_driver_info(ar);
1481
	ath10k_pci_dump_registers(ar, crash_data);
1482
	ath10k_ce_dump_registers(ar, crash_data);
1483 1484

	spin_unlock_bh(&ar->data_lock);
1485

1486
	queue_work(ar->workqueue, &ar->restart_work);
1487 1488
}

1489 1490
void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
					int force)
1491
{
1492
	ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n");
K
Kalle Valo 已提交
1493

1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514
	if (!force) {
		int resources;
		/*
		 * Decide whether to actually poll for completions, or just
		 * wait for a later chance.
		 * If there seem to be plenty of resources left, then just wait
		 * since checking involves reading a CE register, which is a
		 * relatively expensive operation.
		 */
		resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);

		/*
		 * If at least 50% of the total resources are still available,
		 * don't bother checking again yet.
		 */
		if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
			return;
	}
	ath10k_ce_per_engine_service(ar, pipe);
}

1515
static void ath10k_pci_rx_retry_sync(struct ath10k *ar)
1516 1517 1518
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

1519
	del_timer_sync(&ar_pci->rx_post_retry);
1520 1521
}

1522 1523
int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
				       u8 *ul_pipe, u8 *dl_pipe)
1524
{
1525 1526 1527
	const struct service_to_pipe *entry;
	bool ul_set = false, dl_set = false;
	int i;
1528

1529
	ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n");
K
Kalle Valo 已提交
1530

1531 1532
	for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
		entry = &target_service_to_ce_map_wlan[i];
1533

1534
		if (__le32_to_cpu(entry->service_id) != service_id)
1535
			continue;
1536

1537
		switch (__le32_to_cpu(entry->pipedir)) {
1538 1539 1540 1541
		case PIPEDIR_NONE:
			break;
		case PIPEDIR_IN:
			WARN_ON(dl_set);
1542
			*dl_pipe = __le32_to_cpu(entry->pipenum);
1543 1544 1545 1546
			dl_set = true;
			break;
		case PIPEDIR_OUT:
			WARN_ON(ul_set);
1547
			*ul_pipe = __le32_to_cpu(entry->pipenum);
1548 1549 1550 1551 1552
			ul_set = true;
			break;
		case PIPEDIR_INOUT:
			WARN_ON(dl_set);
			WARN_ON(ul_set);
1553 1554
			*dl_pipe = __le32_to_cpu(entry->pipenum);
			*ul_pipe = __le32_to_cpu(entry->pipenum);
1555 1556 1557 1558
			dl_set = true;
			ul_set = true;
			break;
		}
1559 1560
	}

1561 1562
	if (WARN_ON(!ul_set || !dl_set))
		return -ENOENT;
1563

1564
	return 0;
1565 1566
}

1567 1568
void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
				     u8 *ul_pipe, u8 *dl_pipe)
1569
{
1570
	ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n");
K
Kalle Valo 已提交
1571

1572 1573
	(void)ath10k_pci_hif_map_service_to_pipe(ar,
						 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1574
						 ul_pipe, dl_pipe);
1575 1576
}

1577
void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar)
1578
{
M
Michal Kazior 已提交
1579 1580
	u32 val;

1581 1582
	switch (ar->hw_rev) {
	case ATH10K_HW_QCA988X:
1583
	case ATH10K_HW_QCA9887:
1584
	case ATH10K_HW_QCA6174:
1585
	case ATH10K_HW_QCA9377:
1586 1587 1588 1589 1590 1591 1592
		val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
					CORE_CTRL_ADDRESS);
		val &= ~CORE_CTRL_PCIE_REG_31_MASK;
		ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
				   CORE_CTRL_ADDRESS, val);
		break;
	case ATH10K_HW_QCA99X0:
1593
	case ATH10K_HW_QCA9984:
1594
	case ATH10K_HW_QCA9888:
1595
	case ATH10K_HW_QCA4019:
1596 1597 1598
		/* TODO: Find appropriate register configuration for QCA99X0
		 *  to mask irq/MSI.
		 */
K
Kalle Valo 已提交
1599
		break;
1600 1601
	case ATH10K_HW_WCN3990:
		break;
1602
	}
M
Michal Kazior 已提交
1603 1604 1605 1606 1607 1608
}

static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar)
{
	u32 val;

1609 1610
	switch (ar->hw_rev) {
	case ATH10K_HW_QCA988X:
1611
	case ATH10K_HW_QCA9887:
1612
	case ATH10K_HW_QCA6174:
1613
	case ATH10K_HW_QCA9377:
1614 1615 1616 1617 1618 1619 1620
		val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
					CORE_CTRL_ADDRESS);
		val |= CORE_CTRL_PCIE_REG_31_MASK;
		ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
				   CORE_CTRL_ADDRESS, val);
		break;
	case ATH10K_HW_QCA99X0:
1621
	case ATH10K_HW_QCA9984:
1622
	case ATH10K_HW_QCA9888:
1623
	case ATH10K_HW_QCA4019:
1624 1625 1626 1627
		/* TODO: Find appropriate register configuration for QCA99X0
		 *  to unmask irq/MSI.
		 */
		break;
1628 1629
	case ATH10K_HW_WCN3990:
		break;
1630
	}
M
Michal Kazior 已提交
1631
}
1632

M
Michal Kazior 已提交
1633 1634
static void ath10k_pci_irq_disable(struct ath10k *ar)
{
1635
	ath10k_ce_disable_interrupts(ar);
1636
	ath10k_pci_disable_and_clear_legacy_irq(ar);
M
Michal Kazior 已提交
1637 1638 1639 1640 1641 1642
	ath10k_pci_irq_msi_fw_mask(ar);
}

static void ath10k_pci_irq_sync(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1643

1644
	synchronize_irq(ar_pci->pdev->irq);
1645 1646
}

1647
static void ath10k_pci_irq_enable(struct ath10k *ar)
1648
{
1649
	ath10k_ce_enable_interrupts(ar);
1650
	ath10k_pci_enable_legacy_irq(ar);
M
Michal Kazior 已提交
1651
	ath10k_pci_irq_msi_fw_unmask(ar);
1652 1653 1654 1655
}

static int ath10k_pci_hif_start(struct ath10k *ar)
{
J
Janusz Dziedzic 已提交
1656
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
K
Kalle Valo 已提交
1657

1658
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
1659

1660 1661
	napi_enable(&ar->napi);

1662
	ath10k_pci_irq_enable(ar);
1663
	ath10k_pci_rx_post(ar);
K
Kalle Valo 已提交
1664

J
Janusz Dziedzic 已提交
1665 1666 1667
	pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
				   ar_pci->link_ctl);

1668 1669 1670
	return 0;
}

1671
static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1672 1673
{
	struct ath10k *ar;
1674 1675 1676 1677
	struct ath10k_ce_pipe *ce_pipe;
	struct ath10k_ce_ring *ce_ring;
	struct sk_buff *skb;
	int i;
1678

1679 1680 1681
	ar = pci_pipe->hif_ce_state;
	ce_pipe = pci_pipe->ce_hdl;
	ce_ring = ce_pipe->dest_ring;
1682

1683
	if (!ce_ring)
1684 1685
		return;

1686 1687
	if (!pci_pipe->buf_sz)
		return;
1688

1689 1690 1691 1692 1693 1694 1695
	for (i = 0; i < ce_ring->nentries; i++) {
		skb = ce_ring->per_transfer_context[i];
		if (!skb)
			continue;

		ce_ring->per_transfer_context[i] = NULL;

1696
		dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1697
				 skb->len + skb_tailroom(skb),
1698
				 DMA_FROM_DEVICE);
1699
		dev_kfree_skb_any(skb);
1700 1701 1702
	}
}

1703
static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1704 1705
{
	struct ath10k *ar;
1706 1707 1708 1709
	struct ath10k_ce_pipe *ce_pipe;
	struct ath10k_ce_ring *ce_ring;
	struct sk_buff *skb;
	int i;
1710

1711 1712 1713
	ar = pci_pipe->hif_ce_state;
	ce_pipe = pci_pipe->ce_hdl;
	ce_ring = ce_pipe->src_ring;
1714

1715
	if (!ce_ring)
1716 1717
		return;

1718 1719
	if (!pci_pipe->buf_sz)
		return;
1720

1721 1722 1723
	for (i = 0; i < ce_ring->nentries; i++) {
		skb = ce_ring->per_transfer_context[i];
		if (!skb)
1724 1725
			continue;

1726 1727
		ce_ring->per_transfer_context[i] = NULL;

1728
		ath10k_htc_tx_completion_handler(ar, skb);
1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744
	}
}

/*
 * Cleanup residual buffers for device shutdown:
 *    buffers that were enqueued for receive
 *    buffers that were to be sent
 * Note: Buffers that had completed but which were
 * not yet processed are on a completion queue. They
 * are handled when the completion thread shuts down.
 */
static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	int pipe_num;

M
Michal Kazior 已提交
1745
	for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1746
		struct ath10k_pci_pipe *pipe_info;
1747 1748 1749 1750 1751 1752 1753

		pipe_info = &ar_pci->pipe_info[pipe_num];
		ath10k_pci_rx_pipe_cleanup(pipe_info);
		ath10k_pci_tx_pipe_cleanup(pipe_info);
	}
}

1754
void ath10k_pci_ce_deinit(struct ath10k *ar)
1755
{
1756
	int i;
1757

1758 1759
	for (i = 0; i < CE_COUNT; i++)
		ath10k_ce_deinit_pipe(ar, i);
1760 1761
}

1762
void ath10k_pci_flush(struct ath10k *ar)
1763
{
1764
	ath10k_pci_rx_retry_sync(ar);
1765 1766
	ath10k_pci_buffer_cleanup(ar);
}
1767 1768 1769

static void ath10k_pci_hif_stop(struct ath10k *ar)
{
1770 1771 1772
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	unsigned long flags;

1773
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
1774

1775 1776 1777
	/* Most likely the device has HTT Rx ring configured. The only way to
	 * prevent the device from accessing (and possible corrupting) host
	 * memory is to reset the chip now.
1778 1779 1780 1781 1782 1783 1784
	 *
	 * There's also no known way of masking MSI interrupts on the device.
	 * For ranged MSI the CE-related interrupts can be masked. However
	 * regardless how many MSI interrupts are assigned the first one
	 * is always used for firmware indications (crashes) and cannot be
	 * masked. To prevent the device from asserting the interrupt reset it
	 * before proceeding with cleanup.
1785
	 */
1786
	ath10k_pci_safe_chip_reset(ar);
1787 1788

	ath10k_pci_irq_disable(ar);
M
Michal Kazior 已提交
1789
	ath10k_pci_irq_sync(ar);
1790
	ath10k_pci_flush(ar);
1791 1792
	napi_synchronize(&ar->napi);
	napi_disable(&ar->napi);
1793 1794 1795 1796

	spin_lock_irqsave(&ar_pci->ps_lock, flags);
	WARN_ON(ar_pci->ps_wake_refcount > 0);
	spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
1797 1798
}

1799 1800 1801
int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
				    void *req, u32 req_len,
				    void *resp, u32 *resp_len)
1802 1803
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1804 1805 1806 1807
	struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
	struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
	struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
	struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
1808 1809 1810 1811 1812 1813
	dma_addr_t req_paddr = 0;
	dma_addr_t resp_paddr = 0;
	struct bmi_xfer xfer = {};
	void *treq, *tresp = NULL;
	int ret = 0;

1814 1815
	might_sleep();

1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827
	if (resp && !resp_len)
		return -EINVAL;

	if (resp && resp_len && *resp_len == 0)
		return -EINVAL;

	treq = kmemdup(req, req_len, GFP_KERNEL);
	if (!treq)
		return -ENOMEM;

	req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
	ret = dma_mapping_error(ar->dev, req_paddr);
1828 1829
	if (ret) {
		ret = -EIO;
1830
		goto err_dma;
1831
	}
1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842

	if (resp && resp_len) {
		tresp = kzalloc(*resp_len, GFP_KERNEL);
		if (!tresp) {
			ret = -ENOMEM;
			goto err_req;
		}

		resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
					    DMA_FROM_DEVICE);
		ret = dma_mapping_error(ar->dev, resp_paddr);
1843
		if (ret) {
1844
			ret = -EIO;
1845
			goto err_req;
1846
		}
1847 1848 1849 1850

		xfer.wait_for_resp = true;
		xfer.resp_len = 0;

1851
		ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr);
1852 1853 1854 1855 1856 1857
	}

	ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
	if (ret)
		goto err_resp;

1858
	ret = ath10k_pci_bmi_wait(ar, ce_tx, ce_rx, &xfer);
1859
	if (ret) {
1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892
		u32 unused_buffer;
		unsigned int unused_nbytes;
		unsigned int unused_id;

		ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
					   &unused_nbytes, &unused_id);
	} else {
		/* non-zero means we did not time out */
		ret = 0;
	}

err_resp:
	if (resp) {
		u32 unused_buffer;

		ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
		dma_unmap_single(ar->dev, resp_paddr,
				 *resp_len, DMA_FROM_DEVICE);
	}
err_req:
	dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);

	if (ret == 0 && resp_len) {
		*resp_len = min(*resp_len, xfer.resp_len);
		memcpy(resp, tresp, xfer.resp_len);
	}
err_dma:
	kfree(treq);
	kfree(tresp);

	return ret;
}

1893
static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
1894
{
1895 1896
	struct bmi_xfer *xfer;

1897
	if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer))
1898
		return;
1899

1900
	xfer->tx_done = true;
1901 1902
}

1903
static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
1904
{
1905
	struct ath10k *ar = ce_state->ar;
1906 1907 1908
	struct bmi_xfer *xfer;
	unsigned int nbytes;

1909 1910
	if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer,
					  &nbytes))
1911
		return;
1912

M
Michal Kazior 已提交
1913 1914 1915
	if (WARN_ON_ONCE(!xfer))
		return;

1916
	if (!xfer->wait_for_resp) {
1917
		ath10k_warn(ar, "unexpected: BMI data received; ignoring\n");
1918 1919 1920 1921
		return;
	}

	xfer->resp_len = nbytes;
1922
	xfer->rx_done = true;
1923 1924
}

1925 1926
static int ath10k_pci_bmi_wait(struct ath10k *ar,
			       struct ath10k_ce_pipe *tx_pipe,
1927 1928 1929 1930
			       struct ath10k_ce_pipe *rx_pipe,
			       struct bmi_xfer *xfer)
{
	unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1931 1932 1933
	unsigned long started = jiffies;
	unsigned long dur;
	int ret;
1934 1935 1936 1937 1938

	while (time_before_eq(jiffies, timeout)) {
		ath10k_pci_bmi_send_done(tx_pipe);
		ath10k_pci_bmi_recv_data(rx_pipe);

1939 1940 1941 1942
		if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) {
			ret = 0;
			goto out;
		}
1943 1944 1945

		schedule();
	}
1946

1947 1948 1949 1950 1951 1952 1953 1954 1955
	ret = -ETIMEDOUT;

out:
	dur = jiffies - started;
	if (dur > HZ)
		ath10k_dbg(ar, ATH10K_DBG_BMI,
			   "bmi cmd took %lu jiffies hz %d ret %d\n",
			   dur, HZ, ret);
	return ret;
1956
}
1957 1958 1959 1960 1961 1962 1963

/*
 * Send an interrupt to the device to wake up the Target CPU
 * so it has an opportunity to notice any changed state.
 */
static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
{
1964
	u32 addr, val;
1965

1966
	addr = SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS;
1967 1968 1969
	val = ath10k_pci_read32(ar, addr);
	val |= CORE_CTRL_CPU_INTR_MASK;
	ath10k_pci_write32(ar, addr, val);
1970

1971
	return 0;
1972 1973
}

M
Michal Kazior 已提交
1974 1975 1976 1977 1978 1979
static int ath10k_pci_get_num_banks(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	switch (ar_pci->pdev->device) {
	case QCA988X_2_0_DEVICE_ID:
1980
	case QCA99X0_2_0_DEVICE_ID:
1981
	case QCA9888_2_0_DEVICE_ID:
1982
	case QCA9984_1_0_DEVICE_ID:
1983
	case QCA9887_1_0_DEVICE_ID:
M
Michal Kazior 已提交
1984
		return 1;
M
Michal Kazior 已提交
1985
	case QCA6164_2_1_DEVICE_ID:
M
Michal Kazior 已提交
1986 1987 1988 1989
	case QCA6174_2_1_DEVICE_ID:
		switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) {
		case QCA6174_HW_1_0_CHIP_ID_REV:
		case QCA6174_HW_1_1_CHIP_ID_REV:
1990 1991
		case QCA6174_HW_2_1_CHIP_ID_REV:
		case QCA6174_HW_2_2_CHIP_ID_REV:
M
Michal Kazior 已提交
1992 1993 1994 1995 1996 1997 1998 1999 2000
			return 3;
		case QCA6174_HW_1_3_CHIP_ID_REV:
			return 2;
		case QCA6174_HW_3_0_CHIP_ID_REV:
		case QCA6174_HW_3_1_CHIP_ID_REV:
		case QCA6174_HW_3_2_CHIP_ID_REV:
			return 9;
		}
		break;
2001
	case QCA9377_1_0_DEVICE_ID:
2002
		return 4;
M
Michal Kazior 已提交
2003 2004 2005 2006 2007 2008
	}

	ath10k_warn(ar, "unknown number of banks, assuming 1\n");
	return 1;
}

2009 2010
static int ath10k_bus_get_num_banks(struct ath10k *ar)
{
2011
	struct ath10k_ce *ce = ath10k_ce_priv(ar);
2012

2013
	return ce->bus_ops->get_num_banks(ar);
2014 2015
}

2016
int ath10k_pci_init_config(struct ath10k *ar)
2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033
{
	u32 interconnect_targ_addr;
	u32 pcie_state_targ_addr = 0;
	u32 pipe_cfg_targ_addr = 0;
	u32 svc_to_pipe_map = 0;
	u32 pcie_config_flags = 0;
	u32 ealloc_value;
	u32 ealloc_targ_addr;
	u32 flag2_value;
	u32 flag2_targ_addr;
	int ret = 0;

	/* Download to Target the CE Config and the service-to-CE map */
	interconnect_targ_addr =
		host_interest_item_address(HI_ITEM(hi_interconnect_state));

	/* Supply Target-side CE configuration */
2034 2035
	ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr,
				     &pcie_state_targ_addr);
2036
	if (ret != 0) {
2037
		ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret);
2038 2039 2040 2041 2042
		return ret;
	}

	if (pcie_state_targ_addr == 0) {
		ret = -EIO;
2043
		ath10k_err(ar, "Invalid pcie state addr\n");
2044 2045 2046
		return ret;
	}

2047
	ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2048
					  offsetof(struct pcie_state,
2049 2050
						   pipe_cfg_addr)),
				     &pipe_cfg_targ_addr);
2051
	if (ret != 0) {
2052
		ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret);
2053 2054 2055 2056 2057
		return ret;
	}

	if (pipe_cfg_targ_addr == 0) {
		ret = -EIO;
2058
		ath10k_err(ar, "Invalid pipe cfg addr\n");
2059 2060 2061 2062
		return ret;
	}

	ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
2063
					target_ce_config_wlan,
2064 2065
					sizeof(struct ce_pipe_config) *
					NUM_TARGET_CE_CONFIG_WLAN);
2066 2067

	if (ret != 0) {
2068
		ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret);
2069 2070 2071
		return ret;
	}

2072
	ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2073
					  offsetof(struct pcie_state,
2074 2075
						   svc_to_pipe_map)),
				     &svc_to_pipe_map);
2076
	if (ret != 0) {
2077
		ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret);
2078 2079 2080 2081 2082
		return ret;
	}

	if (svc_to_pipe_map == 0) {
		ret = -EIO;
2083
		ath10k_err(ar, "Invalid svc_to_pipe map\n");
2084 2085 2086 2087
		return ret;
	}

	ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
2088 2089
					target_service_to_ce_map_wlan,
					sizeof(target_service_to_ce_map_wlan));
2090
	if (ret != 0) {
2091
		ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
2092 2093 2094
		return ret;
	}

2095
	ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2096
					  offsetof(struct pcie_state,
2097 2098
						   config_flags)),
				     &pcie_config_flags);
2099
	if (ret != 0) {
2100
		ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret);
2101 2102 2103 2104 2105
		return ret;
	}

	pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;

2106 2107 2108 2109
	ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr +
					   offsetof(struct pcie_state,
						    config_flags)),
				      pcie_config_flags);
2110
	if (ret != 0) {
2111
		ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret);
2112 2113 2114 2115 2116 2117
		return ret;
	}

	/* configure early allocation */
	ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));

2118
	ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value);
2119
	if (ret != 0) {
2120
		ath10k_err(ar, "Failed to get early alloc val: %d\n", ret);
2121 2122 2123 2124 2125 2126
		return ret;
	}

	/* first bank is switched to IRAM */
	ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
			 HI_EARLY_ALLOC_MAGIC_MASK);
2127
	ealloc_value |= ((ath10k_bus_get_num_banks(ar) <<
M
Michal Kazior 已提交
2128
			  HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
2129 2130
			 HI_EARLY_ALLOC_IRAM_BANKS_MASK);

2131
	ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value);
2132
	if (ret != 0) {
2133
		ath10k_err(ar, "Failed to set early alloc val: %d\n", ret);
2134 2135 2136 2137 2138 2139
		return ret;
	}

	/* Tell Target to proceed with initialization */
	flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));

2140
	ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value);
2141
	if (ret != 0) {
2142
		ath10k_err(ar, "Failed to get option val: %d\n", ret);
2143 2144 2145 2146 2147
		return ret;
	}

	flag2_value |= HI_OPTION_EARLY_CFG_DONE;

2148
	ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value);
2149
	if (ret != 0) {
2150
		ath10k_err(ar, "Failed to set option val: %d\n", ret);
2151 2152 2153 2154 2155 2156
		return ret;
	}

	return 0;
}

2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179
static void ath10k_pci_override_ce_config(struct ath10k *ar)
{
	struct ce_attr *attr;
	struct ce_pipe_config *config;

	/* For QCA6174 we're overriding the Copy Engine 5 configuration,
	 * since it is currently used for other feature.
	 */

	/* Override Host's Copy Engine 5 configuration */
	attr = &host_ce_config_wlan[5];
	attr->src_sz_max = 0;
	attr->dest_nentries = 0;

	/* Override Target firmware's Copy Engine configuration */
	config = &target_ce_config_wlan[5];
	config->pipedir = __cpu_to_le32(PIPEDIR_OUT);
	config->nbytes_max = __cpu_to_le32(2048);

	/* Map from service/endpoint to Copy Engine */
	target_service_to_ce_map_wlan[15].pipenum = __cpu_to_le32(1);
}

2180
int ath10k_pci_alloc_pipes(struct ath10k *ar)
2181
{
2182 2183
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	struct ath10k_pci_pipe *pipe;
2184
	struct ath10k_ce *ce = ath10k_ce_priv(ar);
2185 2186 2187
	int i, ret;

	for (i = 0; i < CE_COUNT; i++) {
2188
		pipe = &ar_pci->pipe_info[i];
2189
		pipe->ce_hdl = &ce->ce_states[i];
2190 2191 2192
		pipe->pipe_num = i;
		pipe->hif_ce_state = ar;

2193
		ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
2194
		if (ret) {
2195
			ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
2196 2197 2198
				   i, ret);
			return ret;
		}
2199 2200

		/* Last CE is Diagnostic Window */
2201
		if (i == CE_DIAG_PIPE) {
2202 2203 2204 2205 2206
			ar_pci->ce_diag = pipe->ce_hdl;
			continue;
		}

		pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max);
2207 2208 2209 2210 2211
	}

	return 0;
}

2212
void ath10k_pci_free_pipes(struct ath10k *ar)
2213 2214
{
	int i;
2215

2216 2217 2218
	for (i = 0; i < CE_COUNT; i++)
		ath10k_ce_free_pipe(ar, i);
}
2219

2220
int ath10k_pci_init_pipes(struct ath10k *ar)
2221
{
2222
	int i, ret;
2223

2224 2225
	for (i = 0; i < CE_COUNT; i++) {
		ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]);
2226
		if (ret) {
2227
			ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
2228
				   i, ret);
2229
			return ret;
2230 2231 2232 2233 2234 2235
		}
	}

	return 0;
}

2236
static bool ath10k_pci_has_fw_crashed(struct ath10k *ar)
2237
{
2238 2239 2240
	return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &
	       FW_IND_EVENT_PENDING;
}
2241

2242 2243 2244
static void ath10k_pci_fw_crashed_clear(struct ath10k *ar)
{
	u32 val;
2245

2246 2247 2248
	val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
	val &= ~FW_IND_EVENT_PENDING;
	ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);
2249 2250
}

2251 2252 2253 2254 2255 2256 2257 2258
static bool ath10k_pci_has_device_gone(struct ath10k *ar)
{
	u32 val;

	val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
	return (val == 0xffffffff);
}

2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278
/* this function effectively clears target memory controller assert line */
static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
{
	u32 val;

	val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
	ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
			       val | SOC_RESET_CONTROL_SI0_RST_MASK);
	val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);

	msleep(10);

	val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
	ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
			       val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
	val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);

	msleep(10);
}

2279
static void ath10k_pci_warm_reset_cpu(struct ath10k *ar)
2280 2281 2282
{
	u32 val;

2283
	ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
2284 2285

	val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2286 2287 2288 2289 2290 2291 2292 2293
				SOC_RESET_CONTROL_ADDRESS);
	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
			   val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
}

static void ath10k_pci_warm_reset_ce(struct ath10k *ar)
{
	u32 val;
2294 2295 2296

	val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
				SOC_RESET_CONTROL_ADDRESS);
2297

2298 2299 2300 2301 2302
	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
			   val | SOC_RESET_CONTROL_CE_RST_MASK);
	msleep(10);
	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
			   val & ~SOC_RESET_CONTROL_CE_RST_MASK);
2303 2304 2305 2306 2307 2308
}

static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar)
{
	u32 val;

2309
	val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2310 2311 2312 2313 2314
				SOC_LF_TIMER_CONTROL0_ADDRESS);
	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
			   SOC_LF_TIMER_CONTROL0_ADDRESS,
			   val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
}
2315

2316 2317 2318 2319 2320
static int ath10k_pci_warm_reset(struct ath10k *ar)
{
	int ret;

	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
2321

2322 2323 2324
	spin_lock_bh(&ar->data_lock);
	ar->stats.fw_warm_reset_counter++;
	spin_unlock_bh(&ar->data_lock);
2325

2326
	ath10k_pci_irq_disable(ar);
2327

2328 2329 2330 2331 2332 2333 2334 2335 2336
	/* Make sure the target CPU is not doing anything dangerous, e.g. if it
	 * were to access copy engine while host performs copy engine reset
	 * then it is possible for the device to confuse pci-e controller to
	 * the point of bringing host system to a complete stop (i.e. hang).
	 */
	ath10k_pci_warm_reset_si0(ar);
	ath10k_pci_warm_reset_cpu(ar);
	ath10k_pci_init_pipes(ar);
	ath10k_pci_wait_for_target_init(ar);
2337

2338 2339 2340 2341
	ath10k_pci_warm_reset_clear_lf(ar);
	ath10k_pci_warm_reset_ce(ar);
	ath10k_pci_warm_reset_cpu(ar);
	ath10k_pci_init_pipes(ar);
2342

2343 2344 2345 2346 2347
	ret = ath10k_pci_wait_for_target_init(ar);
	if (ret) {
		ath10k_warn(ar, "failed to wait for target init: %d\n", ret);
		return ret;
	}
2348

2349
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n");
2350

2351
	return 0;
2352 2353
}

2354 2355 2356 2357 2358 2359
static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar)
{
	ath10k_pci_irq_disable(ar);
	return ath10k_pci_qca99x0_chip_reset(ar);
}

2360 2361
static int ath10k_pci_safe_chip_reset(struct ath10k *ar)
{
2362 2363 2364
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	if (!ar_pci->pci_soft_reset)
2365
		return -ENOTSUPP;
2366 2367

	return ar_pci->pci_soft_reset(ar);
2368 2369
}

M
Michal Kazior 已提交
2370
static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar)
2371 2372 2373 2374
{
	int i, ret;
	u32 val;

M
Michal Kazior 已提交
2375
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n");
2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438

	/* Some hardware revisions (e.g. CUS223v2) has issues with cold reset.
	 * It is thus preferred to use warm reset which is safer but may not be
	 * able to recover the device from all possible fail scenarios.
	 *
	 * Warm reset doesn't always work on first try so attempt it a few
	 * times before giving up.
	 */
	for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
		ret = ath10k_pci_warm_reset(ar);
		if (ret) {
			ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n",
				    i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS,
				    ret);
			continue;
		}

		/* FIXME: Sometimes copy engine doesn't recover after warm
		 * reset. In most cases this needs cold reset. In some of these
		 * cases the device is in such a state that a cold reset may
		 * lock up the host.
		 *
		 * Reading any host interest register via copy engine is
		 * sufficient to verify if device is capable of booting
		 * firmware blob.
		 */
		ret = ath10k_pci_init_pipes(ar);
		if (ret) {
			ath10k_warn(ar, "failed to init copy engine: %d\n",
				    ret);
			continue;
		}

		ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS,
					     &val);
		if (ret) {
			ath10k_warn(ar, "failed to poke copy engine: %d\n",
				    ret);
			continue;
		}

		ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n");
		return 0;
	}

	if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) {
		ath10k_warn(ar, "refusing cold reset as requested\n");
		return -EPERM;
	}

	ret = ath10k_pci_cold_reset(ar);
	if (ret) {
		ath10k_warn(ar, "failed to cold reset: %d\n", ret);
		return ret;
	}

	ret = ath10k_pci_wait_for_target_init(ar);
	if (ret) {
		ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
			    ret);
		return ret;
	}

M
Michal Kazior 已提交
2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n");

	return 0;
}

static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar)
{
	int ret;

	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n");

	/* FIXME: QCA6174 requires cold + warm reset to work. */

	ret = ath10k_pci_cold_reset(ar);
	if (ret) {
		ath10k_warn(ar, "failed to cold reset: %d\n", ret);
		return ret;
	}

	ret = ath10k_pci_wait_for_target_init(ar);
	if (ret) {
		ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
K
Kalle Valo 已提交
2461
			    ret);
M
Michal Kazior 已提交
2462 2463 2464 2465 2466 2467 2468 2469 2470 2471
		return ret;
	}

	ret = ath10k_pci_warm_reset(ar);
	if (ret) {
		ath10k_warn(ar, "failed to warm reset: %d\n", ret);
		return ret;
	}

	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n");
2472 2473 2474 2475

	return 0;
}

2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499
static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar)
{
	int ret;

	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n");

	ret = ath10k_pci_cold_reset(ar);
	if (ret) {
		ath10k_warn(ar, "failed to cold reset: %d\n", ret);
		return ret;
	}

	ret = ath10k_pci_wait_for_target_init(ar);
	if (ret) {
		ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
			    ret);
		return ret;
	}

	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n");

	return 0;
}

M
Michal Kazior 已提交
2500 2501
static int ath10k_pci_chip_reset(struct ath10k *ar)
{
2502 2503 2504
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	if (WARN_ON(!ar_pci->pci_hard_reset))
M
Michal Kazior 已提交
2505
		return -ENOTSUPP;
2506 2507

	return ar_pci->pci_hard_reset(ar);
M
Michal Kazior 已提交
2508 2509
}

2510
static int ath10k_pci_hif_power_up(struct ath10k *ar)
2511
{
J
Janusz Dziedzic 已提交
2512
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2513 2514
	int ret;

2515 2516
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");

J
Janusz Dziedzic 已提交
2517 2518 2519 2520 2521
	pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL,
				  &ar_pci->link_ctl);
	pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
				   ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);

2522 2523 2524 2525 2526 2527 2528 2529 2530 2531
	/*
	 * Bring the target up cleanly.
	 *
	 * The target may be in an undefined state with an AUX-powered Target
	 * and a Host in WoW mode. If the Host crashes, loses power, or is
	 * restarted (without unloading the driver) then the Target is left
	 * (aux) powered and running. On a subsequent driver load, the Target
	 * is in an unexpected state. We try to catch that here in order to
	 * reset the Target and retry the probe.
	 */
2532
	ret = ath10k_pci_chip_reset(ar);
2533
	if (ret) {
M
Michal Kazior 已提交
2534 2535 2536 2537 2538 2539
		if (ath10k_pci_has_fw_crashed(ar)) {
			ath10k_warn(ar, "firmware crashed during chip reset\n");
			ath10k_pci_fw_crashed_clear(ar);
			ath10k_pci_fw_crashed_dump(ar);
		}

2540
		ath10k_err(ar, "failed to reset chip: %d\n", ret);
2541
		goto err_sleep;
2542
	}
2543

2544
	ret = ath10k_pci_init_pipes(ar);
2545
	if (ret) {
2546
		ath10k_err(ar, "failed to initialize CE: %d\n", ret);
2547
		goto err_sleep;
2548 2549
	}

M
Michal Kazior 已提交
2550 2551
	ret = ath10k_pci_init_config(ar);
	if (ret) {
2552
		ath10k_err(ar, "failed to setup init config: %d\n", ret);
2553
		goto err_ce;
M
Michal Kazior 已提交
2554
	}
2555 2556 2557

	ret = ath10k_pci_wake_target_cpu(ar);
	if (ret) {
2558
		ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
2559
		goto err_ce;
2560 2561 2562 2563 2564 2565
	}

	return 0;

err_ce:
	ath10k_pci_ce_deinit(ar);
2566

2567
err_sleep:
2568 2569 2570
	return ret;
}

2571
void ath10k_pci_hif_power_down(struct ath10k *ar)
2572
{
2573
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
K
Kalle Valo 已提交
2574

2575 2576 2577
	/* Currently hif_power_up performs effectively a reset and hif_stop
	 * resets the chip as well so there's no point in resetting here.
	 */
2578 2579
}

M
Michal Kazior 已提交
2580 2581 2582 2583
#ifdef CONFIG_PM

static int ath10k_pci_hif_suspend(struct ath10k *ar)
{
2584 2585 2586 2587 2588 2589
	/* The grace timer can still be counting down and ar->ps_awake be true.
	 * It is known that the device may be asleep after resuming regardless
	 * of the SoC powersave state before suspending. Hence make sure the
	 * device is asleep before proceeding.
	 */
	ath10k_pci_sleep_sync(ar);
2590

M
Michal Kazior 已提交
2591 2592 2593 2594 2595 2596 2597 2598
	return 0;
}

static int ath10k_pci_hif_resume(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	struct pci_dev *pdev = ar_pci->pdev;
	u32 val;
2599 2600
	int ret = 0;

2601 2602 2603 2604
	ret = ath10k_pci_force_wake(ar);
	if (ret) {
		ath10k_err(ar, "failed to wake up target: %d\n", ret);
		return ret;
2605
	}
M
Michal Kazior 已提交
2606

2607 2608 2609 2610 2611 2612 2613 2614
	/* Suspend/Resume resets the PCI configuration space, so we have to
	 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
	 * from interfering with C3 CPU state. pci_restore_state won't help
	 * here since it only restores the first 64 bytes pci config header.
	 */
	pci_read_config_dword(pdev, 0x40, &val);
	if ((val & 0x0000ff00) != 0)
		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
M
Michal Kazior 已提交
2615

2616
	return ret;
M
Michal Kazior 已提交
2617 2618 2619
}
#endif

2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752
static bool ath10k_pci_validate_cal(void *data, size_t size)
{
	__le16 *cal_words = data;
	u16 checksum = 0;
	size_t i;

	if (size % 2 != 0)
		return false;

	for (i = 0; i < size / 2; i++)
		checksum ^= le16_to_cpu(cal_words[i]);

	return checksum == 0xffff;
}

static void ath10k_pci_enable_eeprom(struct ath10k *ar)
{
	/* Enable SI clock */
	ath10k_pci_soc_write32(ar, CLOCK_CONTROL_OFFSET, 0x0);

	/* Configure GPIOs for I2C operation */
	ath10k_pci_write32(ar,
			   GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET +
			   4 * QCA9887_1_0_I2C_SDA_GPIO_PIN,
			   SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG,
			      GPIO_PIN0_CONFIG) |
			   SM(1, GPIO_PIN0_PAD_PULL));

	ath10k_pci_write32(ar,
			   GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET +
			   4 * QCA9887_1_0_SI_CLK_GPIO_PIN,
			   SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) |
			   SM(1, GPIO_PIN0_PAD_PULL));

	ath10k_pci_write32(ar,
			   GPIO_BASE_ADDRESS +
			   QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS,
			   1u << QCA9887_1_0_SI_CLK_GPIO_PIN);

	/* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */
	ath10k_pci_write32(ar,
			   SI_BASE_ADDRESS + SI_CONFIG_OFFSET,
			   SM(1, SI_CONFIG_ERR_INT) |
			   SM(1, SI_CONFIG_BIDIR_OD_DATA) |
			   SM(1, SI_CONFIG_I2C) |
			   SM(1, SI_CONFIG_POS_SAMPLE) |
			   SM(1, SI_CONFIG_INACTIVE_DATA) |
			   SM(1, SI_CONFIG_INACTIVE_CLK) |
			   SM(8, SI_CONFIG_DIVIDER));
}

static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out)
{
	u32 reg;
	int wait_limit;

	/* set device select byte and for the read operation */
	reg = QCA9887_EEPROM_SELECT_READ |
	      SM(addr, QCA9887_EEPROM_ADDR_LO) |
	      SM(addr >> 8, QCA9887_EEPROM_ADDR_HI);
	ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg);

	/* write transmit data, transfer length, and START bit */
	ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET,
			   SM(1, SI_CS_START) | SM(1, SI_CS_RX_CNT) |
			   SM(4, SI_CS_TX_CNT));

	/* wait max 1 sec */
	wait_limit = 100000;

	/* wait for SI_CS_DONE_INT */
	do {
		reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET);
		if (MS(reg, SI_CS_DONE_INT))
			break;

		wait_limit--;
		udelay(10);
	} while (wait_limit > 0);

	if (!MS(reg, SI_CS_DONE_INT)) {
		ath10k_err(ar, "timeout while reading device EEPROM at %04x\n",
			   addr);
		return -ETIMEDOUT;
	}

	/* clear SI_CS_DONE_INT */
	ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg);

	if (MS(reg, SI_CS_DONE_ERR)) {
		ath10k_err(ar, "failed to read device EEPROM at %04x\n", addr);
		return -EIO;
	}

	/* extract receive data */
	reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET);
	*out = reg;

	return 0;
}

static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data,
					   size_t *data_len)
{
	u8 *caldata = NULL;
	size_t calsize, i;
	int ret;

	if (!QCA_REV_9887(ar))
		return -EOPNOTSUPP;

	calsize = ar->hw_params.cal_data_len;
	caldata = kmalloc(calsize, GFP_KERNEL);
	if (!caldata)
		return -ENOMEM;

	ath10k_pci_enable_eeprom(ar);

	for (i = 0; i < calsize; i++) {
		ret = ath10k_pci_read_eeprom(ar, i, &caldata[i]);
		if (ret)
			goto err_free;
	}

	if (!ath10k_pci_validate_cal(caldata, calsize))
		goto err_free;

	*data = caldata;
	*data_len = calsize;

	return 0;

err_free:
2753
	kfree(caldata);
2754 2755 2756 2757

	return -EINVAL;
}

2758
static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
2759
	.tx_sg			= ath10k_pci_hif_tx_sg,
K
Kalle Valo 已提交
2760
	.diag_read		= ath10k_pci_hif_diag_read,
2761
	.diag_write		= ath10k_pci_diag_write_mem,
2762 2763 2764 2765 2766 2767 2768
	.exchange_bmi_msg	= ath10k_pci_hif_exchange_bmi_msg,
	.start			= ath10k_pci_hif_start,
	.stop			= ath10k_pci_hif_stop,
	.map_service_to_pipe	= ath10k_pci_hif_map_service_to_pipe,
	.get_default_pipe	= ath10k_pci_hif_get_default_pipe,
	.send_complete_check	= ath10k_pci_hif_send_complete_check,
	.get_free_queue_number	= ath10k_pci_hif_get_free_queue_number,
2769 2770
	.power_up		= ath10k_pci_hif_power_up,
	.power_down		= ath10k_pci_hif_power_down,
2771 2772
	.read32			= ath10k_pci_read32,
	.write32		= ath10k_pci_write32,
M
Michal Kazior 已提交
2773 2774 2775 2776
#ifdef CONFIG_PM
	.suspend		= ath10k_pci_hif_suspend,
	.resume			= ath10k_pci_hif_resume,
#endif
2777
	.fetch_cal_eeprom	= ath10k_pci_hif_fetch_cal_eeprom,
2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788
};

/*
 * Top-level interrupt handler for all PCI interrupts from a Target.
 * When a block of MSI interrupts is allocated, this top-level handler
 * is not used; instead, we directly call the correct sub-handler.
 */
static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
{
	struct ath10k *ar = arg;
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2789 2790
	int ret;

2791 2792 2793
	if (ath10k_pci_has_device_gone(ar))
		return IRQ_NONE;

2794 2795 2796 2797
	ret = ath10k_pci_force_wake(ar);
	if (ret) {
		ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret);
		return IRQ_NONE;
2798
	}
2799

2800 2801 2802
	if ((ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) &&
	    !ath10k_pci_irq_pending(ar))
		return IRQ_NONE;
2803

2804 2805 2806
	ath10k_pci_disable_and_clear_legacy_irq(ar);
	ath10k_pci_irq_msi_fw_mask(ar);
	napi_schedule(&ar->napi);
2807 2808 2809 2810

	return IRQ_HANDLED;
}

2811
static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget)
2812
{
2813 2814
	struct ath10k *ar = container_of(ctx, struct ath10k, napi);
	int done = 0;
2815

2816 2817
	if (ath10k_pci_has_fw_crashed(ar)) {
		ath10k_pci_fw_crashed_clear(ar);
2818
		ath10k_pci_fw_crashed_dump(ar);
2819 2820
		napi_complete(ctx);
		return done;
2821 2822
	}

2823 2824
	ath10k_ce_per_engine_service_any(ar);

2825 2826 2827
	done = ath10k_htt_txrx_compl_task(ar, budget);

	if (done < budget) {
2828
		napi_complete_done(ctx, done);
2829 2830 2831 2832 2833 2834 2835 2836
		/* In case of MSI, it is possible that interrupts are received
		 * while NAPI poll is inprogress. So pending interrupts that are
		 * received after processing all copy engine pipes by NAPI poll
		 * will not be handled again. This is causing failure to
		 * complete boot sequence in x86 platform. So before enabling
		 * interrupts safer to check for pending interrupts for
		 * immediate servicing.
		 */
2837
		if (ath10k_ce_interrupt_summary(ar)) {
2838 2839 2840
			napi_reschedule(ctx);
			goto out;
		}
2841
		ath10k_pci_enable_legacy_irq(ar);
2842 2843 2844 2845 2846
		ath10k_pci_irq_msi_fw_unmask(ar);
	}

out:
	return done;
2847 2848
}

M
Michal Kazior 已提交
2849
static int ath10k_pci_request_irq_msi(struct ath10k *ar)
2850 2851 2852 2853 2854 2855 2856
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	int ret;

	ret = request_irq(ar_pci->pdev->irq,
			  ath10k_pci_interrupt_handler,
			  IRQF_SHARED, "ath10k_pci", ar);
M
Michal Kazior 已提交
2857
	if (ret) {
2858
		ath10k_warn(ar, "failed to request MSI irq %d: %d\n",
M
Michal Kazior 已提交
2859
			    ar_pci->pdev->irq, ret);
2860 2861 2862 2863 2864 2865
		return ret;
	}

	return 0;
}

M
Michal Kazior 已提交
2866
static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
2867 2868 2869 2870 2871 2872 2873
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	int ret;

	ret = request_irq(ar_pci->pdev->irq,
			  ath10k_pci_interrupt_handler,
			  IRQF_SHARED, "ath10k_pci", ar);
2874
	if (ret) {
2875
		ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
M
Michal Kazior 已提交
2876
			    ar_pci->pdev->irq, ret);
2877
		return ret;
2878
	}
2879 2880 2881 2882

	return 0;
}

M
Michal Kazior 已提交
2883 2884 2885
static int ath10k_pci_request_irq(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2886

2887 2888
	switch (ar_pci->oper_irq_mode) {
	case ATH10K_PCI_IRQ_LEGACY:
M
Michal Kazior 已提交
2889
		return ath10k_pci_request_irq_legacy(ar);
2890
	case ATH10K_PCI_IRQ_MSI:
M
Michal Kazior 已提交
2891
		return ath10k_pci_request_irq_msi(ar);
2892
	default:
2893
		return -EINVAL;
M
Michal Kazior 已提交
2894
	}
2895 2896
}

M
Michal Kazior 已提交
2897 2898 2899 2900
static void ath10k_pci_free_irq(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

2901
	free_irq(ar_pci->pdev->irq, ar);
M
Michal Kazior 已提交
2902 2903
}

2904
void ath10k_pci_init_napi(struct ath10k *ar)
2905
{
2906 2907
	netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_pci_napi_poll,
		       ATH10K_NAPI_BUDGET);
M
Michal Kazior 已提交
2908 2909 2910 2911 2912 2913
}

static int ath10k_pci_init_irq(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	int ret;
2914

2915
	ath10k_pci_init_napi(ar);
2916

2917
	if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO)
2918 2919
		ath10k_info(ar, "limiting irq mode to: %d\n",
			    ath10k_pci_irq_mode);
2920

M
Michal Kazior 已提交
2921
	/* Try MSI */
2922
	if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) {
2923
		ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI;
2924
		ret = pci_enable_msi(ar_pci->pdev);
2925
		if (ret == 0)
2926
			return 0;
2927

2928
		/* fall-through */
2929 2930
	}

M
Michal Kazior 已提交
2931 2932 2933 2934 2935 2936 2937
	/* Try legacy irq
	 *
	 * A potential race occurs here: The CORE_BASE write
	 * depends on target correctly decoding AXI address but
	 * host won't know when target writes BAR to CORE_CTRL.
	 * This write might get lost if target has NOT written BAR.
	 * For now, fix the race by repeating the write in below
2938 2939
	 * synchronization checking.
	 */
2940
	ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY;
2941

M
Michal Kazior 已提交
2942 2943 2944 2945
	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
			   PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);

	return 0;
2946 2947
}

2948
static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
2949
{
M
Michal Kazior 已提交
2950 2951
	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
			   0);
2952 2953
}

M
Michal Kazior 已提交
2954
static int ath10k_pci_deinit_irq(struct ath10k *ar)
2955 2956 2957
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

2958 2959
	switch (ar_pci->oper_irq_mode) {
	case ATH10K_PCI_IRQ_LEGACY:
2960
		ath10k_pci_deinit_irq_legacy(ar);
2961
		break;
2962 2963
	default:
		pci_disable_msi(ar_pci->pdev);
2964
		break;
M
Michal Kazior 已提交
2965 2966
	}

2967
	return 0;
2968 2969
}

2970
int ath10k_pci_wait_for_target_init(struct ath10k *ar)
2971 2972
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2973 2974
	unsigned long timeout;
	u32 val;
2975

2976
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
2977

2978 2979 2980 2981 2982
	timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);

	do {
		val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);

2983 2984
		ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n",
			   val);
K
Kalle Valo 已提交
2985

2986 2987 2988 2989
		/* target should never return this */
		if (val == 0xffffffff)
			continue;

2990 2991 2992 2993
		/* the device has crashed so don't bother trying anymore */
		if (val & FW_IND_EVENT_PENDING)
			break;

2994 2995 2996
		if (val & FW_IND_INITIALIZED)
			break;

2997
		if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY)
2998
			/* Fix potential race by repeating CORE_BASE writes */
2999
			ath10k_pci_enable_legacy_irq(ar);
3000

3001
		mdelay(10);
3002
	} while (time_before(jiffies, timeout));
3003

3004
	ath10k_pci_disable_and_clear_legacy_irq(ar);
M
Michal Kazior 已提交
3005
	ath10k_pci_irq_msi_fw_mask(ar);
3006

3007
	if (val == 0xffffffff) {
3008
		ath10k_err(ar, "failed to read device register, device is gone\n");
3009
		return -EIO;
3010 3011
	}

3012
	if (val & FW_IND_EVENT_PENDING) {
3013
		ath10k_warn(ar, "device has crashed during init\n");
3014
		return -ECOMM;
3015 3016
	}

3017
	if (!(val & FW_IND_INITIALIZED)) {
3018
		ath10k_err(ar, "failed to receive initialized event from target: %08x\n",
3019
			   val);
3020
		return -ETIMEDOUT;
3021 3022
	}

3023
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n");
3024
	return 0;
3025 3026
}

3027
static int ath10k_pci_cold_reset(struct ath10k *ar)
3028 3029 3030
{
	u32 val;

3031
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
3032

B
Ben Greear 已提交
3033 3034 3035 3036 3037 3038
	spin_lock_bh(&ar->data_lock);

	ar->stats.fw_cold_reset_counter++;

	spin_unlock_bh(&ar->data_lock);

3039
	/* Put Target, including PCIe, into RESET. */
3040
	val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
3041
	val |= 1;
3042
	ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
3043

3044 3045 3046 3047 3048 3049
	/* After writing into SOC_GLOBAL_RESET to put device into
	 * reset and pulling out of reset pcie may not be stable
	 * for any immediate pcie register access and cause bus error,
	 * add delay before any pcie access request to fix this issue.
	 */
	msleep(20);
3050 3051 3052

	/* Pull Target, including PCIe, out of RESET. */
	val &= ~1;
3053
	ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
3054

3055
	msleep(20);
3056

3057
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");
K
Kalle Valo 已提交
3058

3059
	return 0;
3060 3061
}

3062
static int ath10k_pci_claim(struct ath10k *ar)
3063
{
3064 3065 3066
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	struct pci_dev *pdev = ar_pci->pdev;
	int ret;
3067 3068 3069 3070 3071

	pci_set_drvdata(pdev, ar);

	ret = pci_enable_device(pdev);
	if (ret) {
3072
		ath10k_err(ar, "failed to enable pci device: %d\n", ret);
3073
		return ret;
3074 3075 3076 3077
	}

	ret = pci_request_region(pdev, BAR_NUM, "ath");
	if (ret) {
3078
		ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM,
3079
			   ret);
3080 3081 3082
		goto err_device;
	}

3083
	/* Target expects 32 bit DMA. Enforce it. */
3084 3085
	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
	if (ret) {
3086
		ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret);
3087 3088 3089 3090 3091
		goto err_region;
	}

	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
	if (ret) {
3092
		ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n",
3093
			   ret);
3094 3095 3096 3097 3098 3099
		goto err_region;
	}

	pci_set_master(pdev);

	/* Arrange for access to Target SoC registers. */
3100
	ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM);
3101 3102
	ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0);
	if (!ar_pci->mem) {
3103
		ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM);
3104 3105 3106 3107
		ret = -EIO;
		goto err_master;
	}

3108
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%pK\n", ar_pci->mem);
3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133
	return 0;

err_master:
	pci_clear_master(pdev);

err_region:
	pci_release_region(pdev, BAR_NUM);

err_device:
	pci_disable_device(pdev);

	return ret;
}

static void ath10k_pci_release(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	struct pci_dev *pdev = ar_pci->pdev;

	pci_iounmap(pdev, ar_pci->mem);
	pci_release_region(pdev, BAR_NUM);
	pci_clear_master(pdev);
	pci_disable_device(pdev);
}

3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150
static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id)
{
	const struct ath10k_pci_supp_chip *supp_chip;
	int i;
	u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV);

	for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) {
		supp_chip = &ath10k_pci_supp_chips[i];

		if (supp_chip->dev_id == dev_id &&
		    supp_chip->rev_id == rev_id)
			return true;
	}

	return false;
}

3151 3152 3153
int ath10k_pci_setup_resource(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3154
	struct ath10k_ce *ce = ath10k_ce_priv(ar);
3155 3156
	int ret;

3157
	spin_lock_init(&ce->ce_lock);
3158 3159 3160 3161 3162
	spin_lock_init(&ar_pci->ps_lock);

	setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry,
		    (unsigned long)ar);

3163
	if (QCA_REV_6174(ar) || QCA_REV_9377(ar))
3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177
		ath10k_pci_override_ce_config(ar);

	ret = ath10k_pci_alloc_pipes(ar);
	if (ret) {
		ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
			   ret);
		return ret;
	}

	return 0;
}

void ath10k_pci_release_resource(struct ath10k *ar)
{
3178 3179
	ath10k_pci_rx_retry_sync(ar);
	netif_napi_del(&ar->napi);
3180 3181 3182 3183
	ath10k_pci_ce_deinit(ar);
	ath10k_pci_free_pipes(ar);
}

3184 3185 3186 3187 3188 3189
static const struct ath10k_bus_ops ath10k_pci_bus_ops = {
	.read32		= ath10k_bus_pci_read32,
	.write32	= ath10k_bus_pci_write32,
	.get_num_banks	= ath10k_pci_get_num_banks,
};

3190 3191 3192 3193 3194 3195
static int ath10k_pci_probe(struct pci_dev *pdev,
			    const struct pci_device_id *pci_dev)
{
	int ret = 0;
	struct ath10k *ar;
	struct ath10k_pci *ar_pci;
M
Michal Kazior 已提交
3196
	enum ath10k_hw_rev hw_rev;
3197
	u32 chip_id;
3198
	bool pci_ps;
3199 3200
	int (*pci_soft_reset)(struct ath10k *ar);
	int (*pci_hard_reset)(struct ath10k *ar);
3201
	u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
3202

M
Michal Kazior 已提交
3203 3204 3205
	switch (pci_dev->device) {
	case QCA988X_2_0_DEVICE_ID:
		hw_rev = ATH10K_HW_QCA988X;
3206
		pci_ps = false;
3207 3208
		pci_soft_reset = ath10k_pci_warm_reset;
		pci_hard_reset = ath10k_pci_qca988x_chip_reset;
3209
		targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
M
Michal Kazior 已提交
3210
		break;
3211 3212 3213 3214 3215
	case QCA9887_1_0_DEVICE_ID:
		hw_rev = ATH10K_HW_QCA9887;
		pci_ps = false;
		pci_soft_reset = ath10k_pci_warm_reset;
		pci_hard_reset = ath10k_pci_qca988x_chip_reset;
3216
		targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3217
		break;
M
Michal Kazior 已提交
3218
	case QCA6164_2_1_DEVICE_ID:
M
Michal Kazior 已提交
3219 3220
	case QCA6174_2_1_DEVICE_ID:
		hw_rev = ATH10K_HW_QCA6174;
3221
		pci_ps = true;
3222 3223
		pci_soft_reset = ath10k_pci_warm_reset;
		pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3224
		targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
M
Michal Kazior 已提交
3225
		break;
3226 3227
	case QCA99X0_2_0_DEVICE_ID:
		hw_rev = ATH10K_HW_QCA99X0;
3228
		pci_ps = false;
3229 3230
		pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
		pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3231
		targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3232
		break;
3233 3234 3235 3236 3237
	case QCA9984_1_0_DEVICE_ID:
		hw_rev = ATH10K_HW_QCA9984;
		pci_ps = false;
		pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
		pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3238
		targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3239
		break;
3240 3241 3242 3243 3244
	case QCA9888_2_0_DEVICE_ID:
		hw_rev = ATH10K_HW_QCA9888;
		pci_ps = false;
		pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
		pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3245
		targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3246
		break;
3247 3248 3249
	case QCA9377_1_0_DEVICE_ID:
		hw_rev = ATH10K_HW_QCA9377;
		pci_ps = true;
3250 3251
		pci_soft_reset = NULL;
		pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3252
		targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3253
		break;
M
Michal Kazior 已提交
3254 3255 3256 3257 3258 3259 3260
	default:
		WARN_ON(1);
		return -ENOTSUPP;
	}

	ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI,
				hw_rev, &ath10k_pci_hif_ops);
3261
	if (!ar) {
3262
		dev_err(&pdev->dev, "failed to allocate core\n");
3263 3264 3265
		return -ENOMEM;
	}

3266 3267 3268
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
		   pdev->vendor, pdev->device,
		   pdev->subsystem_vendor, pdev->subsystem_device);
3269

3270 3271 3272 3273
	ar_pci = ath10k_pci_priv(ar);
	ar_pci->pdev = pdev;
	ar_pci->dev = &pdev->dev;
	ar_pci->ar = ar;
M
Michal Kazior 已提交
3274
	ar->dev_id = pci_dev->device;
3275
	ar_pci->pci_ps = pci_ps;
3276
	ar_pci->ce.bus_ops = &ath10k_pci_bus_ops;
3277 3278
	ar_pci->pci_soft_reset = pci_soft_reset;
	ar_pci->pci_hard_reset = pci_hard_reset;
3279
	ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr;
3280
	ar->ce_priv = &ar_pci->ce;
3281

3282 3283 3284 3285
	ar->id.vendor = pdev->vendor;
	ar->id.device = pdev->device;
	ar->id.subsystem_vendor = pdev->subsystem_vendor;
	ar->id.subsystem_device = pdev->subsystem_device;
3286

3287 3288
	setup_timer(&ar_pci->ps_timer, ath10k_pci_ps_timer,
		    (unsigned long)ar);
3289

3290
	ret = ath10k_pci_setup_resource(ar);
3291
	if (ret) {
3292
		ath10k_err(ar, "failed to setup resource: %d\n", ret);
3293
		goto err_core_destroy;
3294 3295
	}

3296
	ret = ath10k_pci_claim(ar);
3297
	if (ret) {
3298 3299
		ath10k_err(ar, "failed to claim device: %d\n", ret);
		goto err_free_pipes;
3300 3301
	}

3302 3303 3304
	ret = ath10k_pci_force_wake(ar);
	if (ret) {
		ath10k_warn(ar, "failed to wake up device : %d\n", ret);
3305
		goto err_sleep;
3306 3307
	}

3308 3309 3310
	ath10k_pci_ce_deinit(ar);
	ath10k_pci_irq_disable(ar);

3311
	ret = ath10k_pci_init_irq(ar);
3312
	if (ret) {
3313
		ath10k_err(ar, "failed to init irqs: %d\n", ret);
3314
		goto err_sleep;
3315 3316
	}

3317 3318
	ath10k_info(ar, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n",
		    ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode,
3319 3320
		    ath10k_pci_irq_mode, ath10k_pci_reset_mode);

3321 3322
	ret = ath10k_pci_request_irq(ar);
	if (ret) {
3323
		ath10k_warn(ar, "failed to request irqs: %d\n", ret);
3324 3325 3326
		goto err_deinit_irq;
	}

3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341
	ret = ath10k_pci_chip_reset(ar);
	if (ret) {
		ath10k_err(ar, "failed to reset chip: %d\n", ret);
		goto err_free_irq;
	}

	chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
	if (chip_id == 0xffffffff) {
		ath10k_err(ar, "failed to get chip id\n");
		goto err_free_irq;
	}

	if (!ath10k_pci_chip_is_supported(pdev->device, chip_id)) {
		ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
			   pdev->device, chip_id);
3342
		goto err_free_irq;
3343 3344
	}

3345
	ret = ath10k_core_register(ar, chip_id);
3346
	if (ret) {
3347
		ath10k_err(ar, "failed to register driver core: %d\n", ret);
3348
		goto err_free_irq;
3349 3350 3351 3352
	}

	return 0;

3353 3354
err_free_irq:
	ath10k_pci_free_irq(ar);
3355
	ath10k_pci_rx_retry_sync(ar);
3356

3357 3358 3359
err_deinit_irq:
	ath10k_pci_deinit_irq(ar);

3360
err_sleep:
3361
	ath10k_pci_sleep_sync(ar);
3362 3363
	ath10k_pci_release(ar);

3364 3365 3366
err_free_pipes:
	ath10k_pci_free_pipes(ar);

M
Michal Kazior 已提交
3367
err_core_destroy:
3368 3369 3370 3371 3372 3373 3374 3375 3376 3377
	ath10k_core_destroy(ar);

	return ret;
}

static void ath10k_pci_remove(struct pci_dev *pdev)
{
	struct ath10k *ar = pci_get_drvdata(pdev);
	struct ath10k_pci *ar_pci;

3378
	ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n");
3379 3380 3381 3382 3383 3384 3385 3386 3387 3388

	if (!ar)
		return;

	ar_pci = ath10k_pci_priv(ar);

	if (!ar_pci)
		return;

	ath10k_core_unregister(ar);
3389
	ath10k_pci_free_irq(ar);
3390
	ath10k_pci_deinit_irq(ar);
3391
	ath10k_pci_release_resource(ar);
3392
	ath10k_pci_sleep_sync(ar);
3393
	ath10k_pci_release(ar);
3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411
	ath10k_core_destroy(ar);
}

MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);

static struct pci_driver ath10k_pci_driver = {
	.name = "ath10k_pci",
	.id_table = ath10k_pci_id_table,
	.probe = ath10k_pci_probe,
	.remove = ath10k_pci_remove,
};

static int __init ath10k_pci_init(void)
{
	int ret;

	ret = pci_register_driver(&ath10k_pci_driver);
	if (ret)
3412 3413
		printk(KERN_ERR "failed to register ath10k pci driver: %d\n",
		       ret);
3414

3415 3416 3417 3418
	ret = ath10k_ahb_init();
	if (ret)
		printk(KERN_ERR "ahb init failed: %d\n", ret);

3419 3420 3421 3422 3423 3424 3425
	return ret;
}
module_init(ath10k_pci_init);

static void __exit ath10k_pci_exit(void)
{
	pci_unregister_driver(&ath10k_pci_driver);
3426
	ath10k_ahb_exit();
3427 3428 3429 3430 3431
}

module_exit(ath10k_pci_exit);

MODULE_AUTHOR("Qualcomm Atheros");
3432
MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN PCIe/AHB devices");
3433
MODULE_LICENSE("Dual BSD/GPL");
3434 3435

/* QCA988x 2.0 firmware files */
3436 3437
MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE);
MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE);
3438
MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE);
K
Kalle Valo 已提交
3439
MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3440
MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
3441
MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3442

3443 3444 3445 3446 3447
/* QCA9887 1.0 firmware files */
MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" QCA9887_HW_1_0_BOARD_DATA_FILE);
MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);

3448 3449
/* QCA6174 2.1 firmware files */
MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE);
3450
MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE);
3451
MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE);
3452
MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3453 3454 3455

/* QCA6174 3.1 firmware files */
MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3456
MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE);
R
Ryan Hsu 已提交
3457
MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API6_FILE);
3458
MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE);
3459
MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3460 3461 3462 3463

/* QCA9377 1.0 firmware files */
MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE);