imx-sdma.c 48.1 KB
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/*
 * drivers/dma/imx-sdma.c
 *
 * This file contains a driver for the Freescale Smart DMA engine
 *
 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
 *
 * Based on code from Freescale:
 *
 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
#include <linux/semaphore.h>
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/firmware.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/dmaengine.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_dma.h>
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#include <asm/irq.h>
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#include <linux/platform_data/dma-imx-sdma.h>
#include <linux/platform_data/dma-imx.h>
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#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include "dmaengine.h"

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/* SDMA registers */
#define SDMA_H_C0PTR		0x000
#define SDMA_H_INTR		0x004
#define SDMA_H_STATSTOP		0x008
#define SDMA_H_START		0x00c
#define SDMA_H_EVTOVR		0x010
#define SDMA_H_DSPOVR		0x014
#define SDMA_H_HOSTOVR		0x018
#define SDMA_H_EVTPEND		0x01c
#define SDMA_H_DSPENBL		0x020
#define SDMA_H_RESET		0x024
#define SDMA_H_EVTERR		0x028
#define SDMA_H_INTRMSK		0x02c
#define SDMA_H_PSW		0x030
#define SDMA_H_EVTERRDBG	0x034
#define SDMA_H_CONFIG		0x038
#define SDMA_ONCE_ENB		0x040
#define SDMA_ONCE_DATA		0x044
#define SDMA_ONCE_INSTR		0x048
#define SDMA_ONCE_STAT		0x04c
#define SDMA_ONCE_CMD		0x050
#define SDMA_EVT_MIRROR		0x054
#define SDMA_ILLINSTADDR	0x058
#define SDMA_CHN0ADDR		0x05c
#define SDMA_ONCE_RTB		0x060
#define SDMA_XTRIG_CONF1	0x070
#define SDMA_XTRIG_CONF2	0x074
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#define SDMA_CHNENBL0_IMX35	0x200
#define SDMA_CHNENBL0_IMX31	0x080
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#define SDMA_CHNPRI_0		0x100

/*
 * Buffer descriptor status values.
 */
#define BD_DONE  0x01
#define BD_WRAP  0x02
#define BD_CONT  0x04
#define BD_INTR  0x08
#define BD_RROR  0x10
#define BD_LAST  0x20
#define BD_EXTD  0x80

/*
 * Data Node descriptor status values.
 */
#define DND_END_OF_FRAME  0x80
#define DND_END_OF_XFER   0x40
#define DND_DONE          0x20
#define DND_UNUSED        0x01

/*
 * IPCV2 descriptor status values.
 */
#define BD_IPCV2_END_OF_FRAME  0x40

#define IPCV2_MAX_NODES        50
/*
 * Error bit set in the CCB status field by the SDMA,
 * in setbd routine, in case of a transfer error
 */
#define DATA_ERROR  0x10000000

/*
 * Buffer descriptor commands.
 */
#define C0_ADDR             0x01
#define C0_LOAD             0x02
#define C0_DUMP             0x03
#define C0_SETCTX           0x07
#define C0_GETCTX           0x03
#define C0_SETDM            0x01
#define C0_SETPM            0x04
#define C0_GETDM            0x02
#define C0_GETPM            0x08
/*
 * Change endianness indicator in the BD command field
 */
#define CHANGE_ENDIANNESS   0x80

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/*
 *  p_2_p watermark_level description
 *	Bits		Name			Description
 *	0-7		Lower WML		Lower watermark level
 *	8		PS			1: Pad Swallowing
 *						0: No Pad Swallowing
 *	9		PA			1: Pad Adding
 *						0: No Pad Adding
 *	10		SPDIF			If this bit is set both source
 *						and destination are on SPBA
 *	11		Source Bit(SP)		1: Source on SPBA
 *						0: Source on AIPS
 *	12		Destination Bit(DP)	1: Destination on SPBA
 *						0: Destination on AIPS
 *	13-15		---------		MUST BE 0
 *	16-23		Higher WML		HWML
 *	24-27		N			Total number of samples after
 *						which Pad adding/Swallowing
 *						must be done. It must be odd.
 *	28		Lower WML Event(LWE)	SDMA events reg to check for
 *						LWML event mask
 *						0: LWE in EVENTS register
 *						1: LWE in EVENTS2 register
 *	29		Higher WML Event(HWE)	SDMA events reg to check for
 *						HWML event mask
 *						0: HWE in EVENTS register
 *						1: HWE in EVENTS2 register
 *	30		---------		MUST BE 0
 *	31		CONT			1: Amount of samples to be
 *						transferred is unknown and
 *						script will keep on
 *						transferring samples as long as
 *						both events are detected and
 *						script must be manually stopped
 *						by the application
 *						0: The amount of samples to be
 *						transferred is equal to the
 *						count field of mode word
 */
#define SDMA_WATERMARK_LEVEL_LWML	0xFF
#define SDMA_WATERMARK_LEVEL_PS		BIT(8)
#define SDMA_WATERMARK_LEVEL_PA		BIT(9)
#define SDMA_WATERMARK_LEVEL_SPDIF	BIT(10)
#define SDMA_WATERMARK_LEVEL_SP		BIT(11)
#define SDMA_WATERMARK_LEVEL_DP		BIT(12)
#define SDMA_WATERMARK_LEVEL_HWML	(0xFF << 16)
#define SDMA_WATERMARK_LEVEL_LWE	BIT(28)
#define SDMA_WATERMARK_LEVEL_HWE	BIT(29)
#define SDMA_WATERMARK_LEVEL_CONT	BIT(31)

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/*
 * Mode/Count of data node descriptors - IPCv2
 */
struct sdma_mode_count {
	u32 count   : 16; /* size of the buffer pointed by this BD */
	u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
	u32 command :  8; /* command mostlky used for channel 0 */
};

/*
 * Buffer descriptor
 */
struct sdma_buffer_descriptor {
	struct sdma_mode_count  mode;
	u32 buffer_addr;	/* address of the buffer described */
	u32 ext_buffer_addr;	/* extended buffer address */
} __attribute__ ((packed));

/**
 * struct sdma_channel_control - Channel control Block
 *
 * @current_bd_ptr	current buffer descriptor processed
 * @base_bd_ptr		first element of buffer descriptor array
 * @unused		padding. The SDMA engine expects an array of 128 byte
 *			control blocks
 */
struct sdma_channel_control {
	u32 current_bd_ptr;
	u32 base_bd_ptr;
	u32 unused[2];
} __attribute__ ((packed));

/**
 * struct sdma_state_registers - SDMA context for a channel
 *
 * @pc:		program counter
 * @t:		test bit: status of arithmetic & test instruction
 * @rpc:	return program counter
 * @sf:		source fault while loading data
 * @spc:	loop start program counter
 * @df:		destination fault while storing data
 * @epc:	loop end program counter
 * @lm:		loop mode
 */
struct sdma_state_registers {
	u32 pc     :14;
	u32 unused1: 1;
	u32 t      : 1;
	u32 rpc    :14;
	u32 unused0: 1;
	u32 sf     : 1;
	u32 spc    :14;
	u32 unused2: 1;
	u32 df     : 1;
	u32 epc    :14;
	u32 lm     : 2;
} __attribute__ ((packed));

/**
 * struct sdma_context_data - sdma context specific to a channel
 *
 * @channel_state:	channel state bits
 * @gReg:		general registers
 * @mda:		burst dma destination address register
 * @msa:		burst dma source address register
 * @ms:			burst dma status register
 * @md:			burst dma data register
 * @pda:		peripheral dma destination address register
 * @psa:		peripheral dma source address register
 * @ps:			peripheral dma status register
 * @pd:			peripheral dma data register
 * @ca:			CRC polynomial register
 * @cs:			CRC accumulator register
 * @dda:		dedicated core destination address register
 * @dsa:		dedicated core source address register
 * @ds:			dedicated core status register
 * @dd:			dedicated core data register
 */
struct sdma_context_data {
	struct sdma_state_registers  channel_state;
	u32  gReg[8];
	u32  mda;
	u32  msa;
	u32  ms;
	u32  md;
	u32  pda;
	u32  psa;
	u32  ps;
	u32  pd;
	u32  ca;
	u32  cs;
	u32  dda;
	u32  dsa;
	u32  ds;
	u32  dd;
	u32  scratch0;
	u32  scratch1;
	u32  scratch2;
	u32  scratch3;
	u32  scratch4;
	u32  scratch5;
	u32  scratch6;
	u32  scratch7;
} __attribute__ ((packed));

#define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))

struct sdma_engine;

/**
 * struct sdma_channel - housekeeping for a SDMA channel
 *
 * @sdma		pointer to the SDMA engine for this channel
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 * @channel		the channel number, matches dmaengine chan_id + 1
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 * @direction		transfer type. Needed for setting SDMA script
 * @peripheral_type	Peripheral type. Needed for setting SDMA script
 * @event_id0		aka dma request line
 * @event_id1		for channels that use 2 events
 * @word_size		peripheral access size
 * @buf_tail		ID of the buffer that was processed
 * @num_bd		max NUM_BD. number of descriptors currently handling
 */
struct sdma_channel {
	struct sdma_engine		*sdma;
	unsigned int			channel;
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	enum dma_transfer_direction		direction;
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	enum sdma_peripheral_type	peripheral_type;
	unsigned int			event_id0;
	unsigned int			event_id1;
	enum dma_slave_buswidth		word_size;
	unsigned int			buf_tail;
	unsigned int			num_bd;
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	unsigned int			period_len;
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	struct sdma_buffer_descriptor	*bd;
	dma_addr_t			bd_phys;
	unsigned int			pc_from_device, pc_to_device;
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	unsigned int			device_to_device;
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	unsigned long			flags;
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	dma_addr_t			per_address, per_address2;
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	unsigned long			event_mask[2];
	unsigned long			watermark_level;
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	u32				shp_addr, per_addr;
	struct dma_chan			chan;
	spinlock_t			lock;
	struct dma_async_tx_descriptor	desc;
	enum dma_status			status;
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	unsigned int			chn_count;
	unsigned int			chn_real_count;
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	struct tasklet_struct		tasklet;
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	struct imx_dma_data		data;
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};

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#define IMX_DMA_SG_LOOP		BIT(0)
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#define MAX_DMA_CHANNELS 32
#define MXC_SDMA_DEFAULT_PRIORITY 1
#define MXC_SDMA_MIN_PRIORITY 1
#define MXC_SDMA_MAX_PRIORITY 7

#define SDMA_FIRMWARE_MAGIC 0x414d4453

/**
 * struct sdma_firmware_header - Layout of the firmware image
 *
 * @magic		"SDMA"
 * @version_major	increased whenever layout of struct sdma_script_start_addrs
 *			changes.
 * @version_minor	firmware minor version (for binary compatible changes)
 * @script_addrs_start	offset of struct sdma_script_start_addrs in this image
 * @num_script_addrs	Number of script addresses in this image
 * @ram_code_start	offset of SDMA ram image in this firmware image
 * @ram_code_size	size of SDMA ram image
 * @script_addrs	Stores the start address of the SDMA scripts
 *			(in SDMA memory space)
 */
struct sdma_firmware_header {
	u32	magic;
	u32	version_major;
	u32	version_minor;
	u32	script_addrs_start;
	u32	num_script_addrs;
	u32	ram_code_start;
	u32	ram_code_size;
};

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struct sdma_driver_data {
	int chnenbl0;
	int num_events;
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	struct sdma_script_start_addrs	*script_addrs;
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};

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struct sdma_engine {
	struct device			*dev;
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	struct device_dma_parameters	dma_parms;
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	struct sdma_channel		channel[MAX_DMA_CHANNELS];
	struct sdma_channel_control	*channel_control;
	void __iomem			*regs;
	struct sdma_context_data	*context;
	dma_addr_t			context_phys;
	struct dma_device		dma_device;
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	struct clk			*clk_ipg;
	struct clk			*clk_ahb;
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	spinlock_t			channel_0_lock;
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	u32				script_number;
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	struct sdma_script_start_addrs	*script_addrs;
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	const struct sdma_driver_data	*drvdata;
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	u32				spba_start_addr;
	u32				spba_end_addr;
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};

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static struct sdma_driver_data sdma_imx31 = {
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	.chnenbl0 = SDMA_CHNENBL0_IMX31,
	.num_events = 32,
};

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static struct sdma_script_start_addrs sdma_script_imx25 = {
	.ap_2_ap_addr = 729,
	.uart_2_mcu_addr = 904,
	.per_2_app_addr = 1255,
	.mcu_2_app_addr = 834,
	.uartsh_2_mcu_addr = 1120,
	.per_2_shp_addr = 1329,
	.mcu_2_shp_addr = 1048,
	.ata_2_mcu_addr = 1560,
	.mcu_2_ata_addr = 1479,
	.app_2_per_addr = 1189,
	.app_2_mcu_addr = 770,
	.shp_2_per_addr = 1407,
	.shp_2_mcu_addr = 979,
};

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static struct sdma_driver_data sdma_imx25 = {
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	.chnenbl0 = SDMA_CHNENBL0_IMX35,
	.num_events = 48,
	.script_addrs = &sdma_script_imx25,
};

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static struct sdma_driver_data sdma_imx35 = {
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	.chnenbl0 = SDMA_CHNENBL0_IMX35,
	.num_events = 48,
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};

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static struct sdma_script_start_addrs sdma_script_imx51 = {
	.ap_2_ap_addr = 642,
	.uart_2_mcu_addr = 817,
	.mcu_2_app_addr = 747,
	.mcu_2_shp_addr = 961,
	.ata_2_mcu_addr = 1473,
	.mcu_2_ata_addr = 1392,
	.app_2_per_addr = 1033,
	.app_2_mcu_addr = 683,
	.shp_2_per_addr = 1251,
	.shp_2_mcu_addr = 892,
};

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static struct sdma_driver_data sdma_imx51 = {
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	.chnenbl0 = SDMA_CHNENBL0_IMX35,
	.num_events = 48,
	.script_addrs = &sdma_script_imx51,
};

static struct sdma_script_start_addrs sdma_script_imx53 = {
	.ap_2_ap_addr = 642,
	.app_2_mcu_addr = 683,
	.mcu_2_app_addr = 747,
	.uart_2_mcu_addr = 817,
	.shp_2_mcu_addr = 891,
	.mcu_2_shp_addr = 960,
	.uartsh_2_mcu_addr = 1032,
	.spdif_2_mcu_addr = 1100,
	.mcu_2_spdif_addr = 1134,
	.firi_2_mcu_addr = 1193,
	.mcu_2_firi_addr = 1290,
};

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static struct sdma_driver_data sdma_imx53 = {
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	.chnenbl0 = SDMA_CHNENBL0_IMX35,
	.num_events = 48,
	.script_addrs = &sdma_script_imx53,
};

static struct sdma_script_start_addrs sdma_script_imx6q = {
	.ap_2_ap_addr = 642,
	.uart_2_mcu_addr = 817,
	.mcu_2_app_addr = 747,
	.per_2_per_addr = 6331,
	.uartsh_2_mcu_addr = 1032,
	.mcu_2_shp_addr = 960,
	.app_2_mcu_addr = 683,
	.shp_2_mcu_addr = 891,
	.spdif_2_mcu_addr = 1100,
	.mcu_2_spdif_addr = 1134,
};

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static struct sdma_driver_data sdma_imx6q = {
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	.chnenbl0 = SDMA_CHNENBL0_IMX35,
	.num_events = 48,
	.script_addrs = &sdma_script_imx6q,
};

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static const struct platform_device_id sdma_devtypes[] = {
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	{
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		.name = "imx25-sdma",
		.driver_data = (unsigned long)&sdma_imx25,
	}, {
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		.name = "imx31-sdma",
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		.driver_data = (unsigned long)&sdma_imx31,
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	}, {
		.name = "imx35-sdma",
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		.driver_data = (unsigned long)&sdma_imx35,
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	}, {
		.name = "imx51-sdma",
		.driver_data = (unsigned long)&sdma_imx51,
	}, {
		.name = "imx53-sdma",
		.driver_data = (unsigned long)&sdma_imx53,
	}, {
		.name = "imx6q-sdma",
		.driver_data = (unsigned long)&sdma_imx6q,
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	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(platform, sdma_devtypes);

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static const struct of_device_id sdma_dt_ids[] = {
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	{ .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
	{ .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
	{ .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
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	{ .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
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	{ .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
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	{ .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
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	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sdma_dt_ids);

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#define SDMA_H_CONFIG_DSPDMA	BIT(12) /* indicates if the DSPDMA is used */
#define SDMA_H_CONFIG_RTD_PINS	BIT(11) /* indicates if Real-Time Debug pins are enabled */
#define SDMA_H_CONFIG_ACR	BIT(4)  /* indicates if AHB freq /core freq = 2 or 1 */
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#define SDMA_H_CONFIG_CSM	(3)       /* indicates which context switch mode is selected*/

static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
{
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	u32 chnenbl0 = sdma->drvdata->chnenbl0;
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	return chnenbl0 + event * 4;
}

static int sdma_config_ownership(struct sdma_channel *sdmac,
		bool event_override, bool mcu_override, bool dsp_override)
{
	struct sdma_engine *sdma = sdmac->sdma;
	int channel = sdmac->channel;
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	unsigned long evt, mcu, dsp;
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	if (event_override && mcu_override && dsp_override)
		return -EINVAL;

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	evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
	mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
	dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
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	if (dsp_override)
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		__clear_bit(channel, &dsp);
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	else
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		__set_bit(channel, &dsp);
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	if (event_override)
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		__clear_bit(channel, &evt);
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	else
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		__set_bit(channel, &evt);
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	if (mcu_override)
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		__clear_bit(channel, &mcu);
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	else
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		__set_bit(channel, &mcu);
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	writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
	writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
	writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
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	return 0;
}

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static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
{
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	writel(BIT(channel), sdma->regs + SDMA_H_START);
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}

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/*
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 * sdma_run_channel0 - run a channel and wait till it's done
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 */
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static int sdma_run_channel0(struct sdma_engine *sdma)
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{
	int ret;
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	unsigned long timeout = 500;
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	sdma_enable_channel(sdma, 0);
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	while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) {
		if (timeout-- <= 0)
			break;
		udelay(1);
	}
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	if (ret) {
		/* Clear the interrupt status */
		writel_relaxed(ret, sdma->regs + SDMA_H_INTR);
	} else {
		dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
	}
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	/* Set bits of CONFIG register with dynamic context switching */
	if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
		writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);

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	return ret ? 0 : -ETIMEDOUT;
}

static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
		u32 address)
{
	struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
	void *buf_virt;
	dma_addr_t buf_phys;
	int ret;
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	unsigned long flags;
606

607 608 609
	buf_virt = dma_alloc_coherent(NULL,
			size,
			&buf_phys, GFP_KERNEL);
610
	if (!buf_virt) {
611
		return -ENOMEM;
612
	}
613

614 615
	spin_lock_irqsave(&sdma->channel_0_lock, flags);

616 617 618 619 620 621 622 623
	bd0->mode.command = C0_SETPM;
	bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
	bd0->mode.count = size / 2;
	bd0->buffer_addr = buf_phys;
	bd0->ext_buffer_addr = address;

	memcpy(buf_virt, buf, size);

624
	ret = sdma_run_channel0(sdma);
625

626
	spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
627

628
	dma_free_coherent(NULL, size, buf_virt, buf_phys);
629

630 631 632 633 634 635 636
	return ret;
}

static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
{
	struct sdma_engine *sdma = sdmac->sdma;
	int channel = sdmac->channel;
637
	unsigned long val;
638 639
	u32 chnenbl = chnenbl_ofs(sdma, event);

640
	val = readl_relaxed(sdma->regs + chnenbl);
641
	__set_bit(channel, &val);
642
	writel_relaxed(val, sdma->regs + chnenbl);
643 644 645 646 647 648 649
}

static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
{
	struct sdma_engine *sdma = sdmac->sdma;
	int channel = sdmac->channel;
	u32 chnenbl = chnenbl_ofs(sdma, event);
650
	unsigned long val;
651

652
	val = readl_relaxed(sdma->regs + chnenbl);
653
	__clear_bit(channel, &val);
654
	writel_relaxed(val, sdma->regs + chnenbl);
655 656 657
}

static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
658 659 660 661 662 663
{
	if (sdmac->desc.callback)
		sdmac->desc.callback(sdmac->desc.callback_param);
}

static void sdma_update_channel_loop(struct sdma_channel *sdmac)
664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690
{
	struct sdma_buffer_descriptor *bd;

	/*
	 * loop mode. Iterate over descriptors, re-setup them and
	 * call callback function.
	 */
	while (1) {
		bd = &sdmac->bd[sdmac->buf_tail];

		if (bd->mode.status & BD_DONE)
			break;

		if (bd->mode.status & BD_RROR)
			sdmac->status = DMA_ERROR;

		bd->mode.status |= BD_DONE;
		sdmac->buf_tail++;
		sdmac->buf_tail %= sdmac->num_bd;
	}
}

static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
{
	struct sdma_buffer_descriptor *bd;
	int i, error = 0;

691
	sdmac->chn_real_count = 0;
692 693 694 695 696 697 698 699 700
	/*
	 * non loop mode. Iterate over all descriptors, collect
	 * errors and call callback function
	 */
	for (i = 0; i < sdmac->num_bd; i++) {
		bd = &sdmac->bd[i];

		 if (bd->mode.status & (BD_DONE | BD_RROR))
			error = -EIO;
701
		 sdmac->chn_real_count += bd->mode.count;
702 703 704 705 706
	}

	if (error)
		sdmac->status = DMA_ERROR;
	else
707
		sdmac->status = DMA_COMPLETE;
708

709
	dma_cookie_complete(&sdmac->desc);
710 711 712 713
	if (sdmac->desc.callback)
		sdmac->desc.callback(sdmac->desc.callback_param);
}

714
static void sdma_tasklet(unsigned long data)
715
{
716 717
	struct sdma_channel *sdmac = (struct sdma_channel *) data;

718 719 720 721 722 723 724 725 726
	if (sdmac->flags & IMX_DMA_SG_LOOP)
		sdma_handle_channel_loop(sdmac);
	else
		mxc_sdma_handle_channel_normal(sdmac);
}

static irqreturn_t sdma_int_handler(int irq, void *dev_id)
{
	struct sdma_engine *sdma = dev_id;
727
	unsigned long stat;
728

729
	stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
730 731
	/* not interested in channel 0 interrupts */
	stat &= ~1;
732
	writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
733 734 735 736 737

	while (stat) {
		int channel = fls(stat) - 1;
		struct sdma_channel *sdmac = &sdma->channel[channel];

738 739 740
		if (sdmac->flags & IMX_DMA_SG_LOOP)
			sdma_update_channel_loop(sdmac);

741
		tasklet_schedule(&sdmac->tasklet);
742

743
		__clear_bit(channel, &stat);
744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764
	}

	return IRQ_HANDLED;
}

/*
 * sets the pc of SDMA script according to the peripheral type
 */
static void sdma_get_pc(struct sdma_channel *sdmac,
		enum sdma_peripheral_type peripheral_type)
{
	struct sdma_engine *sdma = sdmac->sdma;
	int per_2_emi = 0, emi_2_per = 0;
	/*
	 * These are needed once we start to support transfers between
	 * two peripherals or memory-to-memory transfers
	 */
	int per_2_per = 0, emi_2_emi = 0;

	sdmac->pc_from_device = 0;
	sdmac->pc_to_device = 0;
765
	sdmac->device_to_device = 0;
766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793

	switch (peripheral_type) {
	case IMX_DMATYPE_MEMORY:
		emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
		break;
	case IMX_DMATYPE_DSP:
		emi_2_per = sdma->script_addrs->bp_2_ap_addr;
		per_2_emi = sdma->script_addrs->ap_2_bp_addr;
		break;
	case IMX_DMATYPE_FIRI:
		per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
		break;
	case IMX_DMATYPE_UART:
		per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_app_addr;
		break;
	case IMX_DMATYPE_UART_SP:
		per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
		break;
	case IMX_DMATYPE_ATA:
		per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
		break;
	case IMX_DMATYPE_CSPI:
	case IMX_DMATYPE_EXT:
	case IMX_DMATYPE_SSI:
794
	case IMX_DMATYPE_SAI:
795 796 797
		per_2_emi = sdma->script_addrs->app_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_app_addr;
		break;
798 799 800 801
	case IMX_DMATYPE_SSI_DUAL:
		per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
		break;
802 803 804 805 806 807 808 809 810 811 812 813 814 815
	case IMX_DMATYPE_SSI_SP:
	case IMX_DMATYPE_MMC:
	case IMX_DMATYPE_SDHC:
	case IMX_DMATYPE_CSPI_SP:
	case IMX_DMATYPE_ESAI:
	case IMX_DMATYPE_MSHC_SP:
		per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
		break;
	case IMX_DMATYPE_ASRC:
		per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
		emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
		per_2_per = sdma->script_addrs->per_2_per_addr;
		break;
816 817 818 819 820
	case IMX_DMATYPE_ASRC_SP:
		per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
		per_2_per = sdma->script_addrs->per_2_per_addr;
		break;
821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840
	case IMX_DMATYPE_MSHC:
		per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
		break;
	case IMX_DMATYPE_CCM:
		per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
		break;
	case IMX_DMATYPE_SPDIF:
		per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
		break;
	case IMX_DMATYPE_IPU_MEMORY:
		emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
		break;
	default:
		break;
	}

	sdmac->pc_from_device = per_2_emi;
	sdmac->pc_to_device = emi_2_per;
841
	sdmac->device_to_device = per_2_per;
842 843 844 845 846 847 848 849 850 851
}

static int sdma_load_context(struct sdma_channel *sdmac)
{
	struct sdma_engine *sdma = sdmac->sdma;
	int channel = sdmac->channel;
	int load_address;
	struct sdma_context_data *context = sdma->context;
	struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
	int ret;
852
	unsigned long flags;
853

854
	if (sdmac->direction == DMA_DEV_TO_MEM)
855
		load_address = sdmac->pc_from_device;
856 857 858
	else if (sdmac->direction == DMA_DEV_TO_DEV)
		load_address = sdmac->device_to_device;
	else
859 860 861 862 863 864
		load_address = sdmac->pc_to_device;

	if (load_address < 0)
		return load_address;

	dev_dbg(sdma->dev, "load_address = %d\n", load_address);
865
	dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
866 867
	dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
	dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
868 869
	dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
	dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
870

871
	spin_lock_irqsave(&sdma->channel_0_lock, flags);
872

873 874 875 876 877 878
	memset(context, 0, sizeof(*context));
	context->channel_state.pc = load_address;

	/* Send by context the event mask,base address for peripheral
	 * and watermark level
	 */
879 880
	context->gReg[0] = sdmac->event_mask[1];
	context->gReg[1] = sdmac->event_mask[0];
881 882 883 884 885 886 887 888 889
	context->gReg[2] = sdmac->per_addr;
	context->gReg[6] = sdmac->shp_addr;
	context->gReg[7] = sdmac->watermark_level;

	bd0->mode.command = C0_SETDM;
	bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
	bd0->mode.count = sizeof(*context) / 4;
	bd0->buffer_addr = sdma->context_phys;
	bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
890
	ret = sdma_run_channel0(sdma);
891

892
	spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
893

894 895 896
	return ret;
}

897 898 899 900 901 902
static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
{
	return container_of(chan, struct sdma_channel, chan);
}

static int sdma_disable_channel(struct dma_chan *chan)
903
{
904
	struct sdma_channel *sdmac = to_sdma_chan(chan);
905 906 907
	struct sdma_engine *sdma = sdmac->sdma;
	int channel = sdmac->channel;

908
	writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
909
	sdmac->status = DMA_ERROR;
910 911

	return 0;
912 913
}

914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953
static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
{
	struct sdma_engine *sdma = sdmac->sdma;

	int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
	int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;

	set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
	set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);

	if (sdmac->event_id0 > 31)
		sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;

	if (sdmac->event_id1 > 31)
		sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;

	/*
	 * If LWML(src_maxburst) > HWML(dst_maxburst), we need
	 * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
	 * r0(event_mask[1]) and r1(event_mask[0]).
	 */
	if (lwml > hwml) {
		sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
						SDMA_WATERMARK_LEVEL_HWML);
		sdmac->watermark_level |= hwml;
		sdmac->watermark_level |= lwml << 16;
		swap(sdmac->event_mask[0], sdmac->event_mask[1]);
	}

	if (sdmac->per_address2 >= sdma->spba_start_addr &&
			sdmac->per_address2 <= sdma->spba_end_addr)
		sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;

	if (sdmac->per_address >= sdma->spba_start_addr &&
			sdmac->per_address <= sdma->spba_end_addr)
		sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;

	sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
}

954
static int sdma_config_channel(struct dma_chan *chan)
955
{
956
	struct sdma_channel *sdmac = to_sdma_chan(chan);
957 958
	int ret;

959
	sdma_disable_channel(chan);
960

961 962
	sdmac->event_mask[0] = 0;
	sdmac->event_mask[1] = 0;
963 964 965 966
	sdmac->shp_addr = 0;
	sdmac->per_addr = 0;

	if (sdmac->event_id0) {
967
		if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
968 969 970 971
			return -EINVAL;
		sdma_event_enable(sdmac, sdmac->event_id0);
	}

972 973 974 975 976 977
	if (sdmac->event_id1) {
		if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
			return -EINVAL;
		sdma_event_enable(sdmac, sdmac->event_id1);
	}

978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995
	switch (sdmac->peripheral_type) {
	case IMX_DMATYPE_DSP:
		sdma_config_ownership(sdmac, false, true, true);
		break;
	case IMX_DMATYPE_MEMORY:
		sdma_config_ownership(sdmac, false, true, false);
		break;
	default:
		sdma_config_ownership(sdmac, true, true, false);
		break;
	}

	sdma_get_pc(sdmac, sdmac->peripheral_type);

	if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
			(sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
		/* Handle multiple event channels differently */
		if (sdmac->event_id1) {
996 997 998 999
			if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
			    sdmac->peripheral_type == IMX_DMATYPE_ASRC)
				sdma_set_watermarklevel_for_p2p(sdmac);
		} else
1000
			__set_bit(sdmac->event_id0, sdmac->event_mask);
1001

1002 1003 1004 1005
		/* Watermark Level */
		sdmac->watermark_level |= sdmac->watermark_level;
		/* Address */
		sdmac->shp_addr = sdmac->per_address;
1006
		sdmac->per_addr = sdmac->per_address2;
1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026
	} else {
		sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
	}

	ret = sdma_load_context(sdmac);

	return ret;
}

static int sdma_set_channel_priority(struct sdma_channel *sdmac,
		unsigned int priority)
{
	struct sdma_engine *sdma = sdmac->sdma;
	int channel = sdmac->channel;

	if (priority < MXC_SDMA_MIN_PRIORITY
	    || priority > MXC_SDMA_MAX_PRIORITY) {
		return -EINVAL;
	}

1027
	writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1028 1029 1030 1031 1032 1033 1034 1035 1036 1037

	return 0;
}

static int sdma_request_channel(struct sdma_channel *sdmac)
{
	struct sdma_engine *sdma = sdmac->sdma;
	int channel = sdmac->channel;
	int ret = -EBUSY;

J
Joe Perches 已提交
1038 1039
	sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys,
					GFP_KERNEL);
1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056
	if (!sdmac->bd) {
		ret = -ENOMEM;
		goto out;
	}

	sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
	sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;

	sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
	return 0;
out:

	return ret;
}

static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
{
1057
	unsigned long flags;
1058 1059 1060
	struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
	dma_cookie_t cookie;

1061
	spin_lock_irqsave(&sdmac->lock, flags);
1062

1063
	cookie = dma_cookie_assign(tx);
1064

1065
	spin_unlock_irqrestore(&sdmac->lock, flags);
1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093

	return cookie;
}

static int sdma_alloc_chan_resources(struct dma_chan *chan)
{
	struct sdma_channel *sdmac = to_sdma_chan(chan);
	struct imx_dma_data *data = chan->private;
	int prio, ret;

	if (!data)
		return -EINVAL;

	switch (data->priority) {
	case DMA_PRIO_HIGH:
		prio = 3;
		break;
	case DMA_PRIO_MEDIUM:
		prio = 2;
		break;
	case DMA_PRIO_LOW:
	default:
		prio = 1;
		break;
	}

	sdmac->peripheral_type = data->peripheral_type;
	sdmac->event_id0 = data->dma_request;
1094
	sdmac->event_id1 = data->dma_request2;
1095

1096 1097 1098 1099 1100 1101
	ret = clk_enable(sdmac->sdma->clk_ipg);
	if (ret)
		return ret;
	ret = clk_enable(sdmac->sdma->clk_ahb);
	if (ret)
		goto disable_clk_ipg;
1102

1103
	ret = sdma_request_channel(sdmac);
1104
	if (ret)
1105
		goto disable_clk_ahb;
1106

1107
	ret = sdma_set_channel_priority(sdmac, prio);
1108
	if (ret)
1109
		goto disable_clk_ahb;
1110 1111 1112 1113 1114 1115 1116

	dma_async_tx_descriptor_init(&sdmac->desc, chan);
	sdmac->desc.tx_submit = sdma_tx_submit;
	/* txd.flags will be overwritten in prep funcs */
	sdmac->desc.flags = DMA_CTRL_ACK;

	return 0;
1117 1118 1119 1120 1121 1122

disable_clk_ahb:
	clk_disable(sdmac->sdma->clk_ahb);
disable_clk_ipg:
	clk_disable(sdmac->sdma->clk_ipg);
	return ret;
1123 1124 1125 1126 1127 1128 1129
}

static void sdma_free_chan_resources(struct dma_chan *chan)
{
	struct sdma_channel *sdmac = to_sdma_chan(chan);
	struct sdma_engine *sdma = sdmac->sdma;

1130
	sdma_disable_channel(chan);
1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143

	if (sdmac->event_id0)
		sdma_event_disable(sdmac, sdmac->event_id0);
	if (sdmac->event_id1)
		sdma_event_disable(sdmac, sdmac->event_id1);

	sdmac->event_id0 = 0;
	sdmac->event_id1 = 0;

	sdma_set_channel_priority(sdmac, 0);

	dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);

1144 1145
	clk_disable(sdma->clk_ipg);
	clk_disable(sdma->clk_ahb);
1146 1147 1148 1149
}

static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
		struct dma_chan *chan, struct scatterlist *sgl,
1150
		unsigned int sg_len, enum dma_transfer_direction direction,
1151
		unsigned long flags, void *context)
1152 1153 1154 1155
{
	struct sdma_channel *sdmac = to_sdma_chan(chan);
	struct sdma_engine *sdma = sdmac->sdma;
	int ret, i, count;
1156
	int channel = sdmac->channel;
1157 1158 1159 1160 1161 1162 1163 1164
	struct scatterlist *sg;

	if (sdmac->status == DMA_IN_PROGRESS)
		return NULL;
	sdmac->status = DMA_IN_PROGRESS;

	sdmac->flags = 0;

1165 1166
	sdmac->buf_tail = 0;

1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181
	dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
			sg_len, channel);

	sdmac->direction = direction;
	ret = sdma_load_context(sdmac);
	if (ret)
		goto err_out;

	if (sg_len > NUM_BD) {
		dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
				channel, sg_len, NUM_BD);
		ret = -EINVAL;
		goto err_out;
	}

1182
	sdmac->chn_count = 0;
1183 1184 1185 1186
	for_each_sg(sgl, sg, sg_len, i) {
		struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
		int param;

1187
		bd->buffer_addr = sg->dma_address;
1188

1189
		count = sg_dma_len(sg);
1190 1191 1192 1193 1194 1195 1196 1197 1198

		if (count > 0xffff) {
			dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
					channel, count, 0xffff);
			ret = -EINVAL;
			goto err_out;
		}

		bd->mode.count = count;
1199
		sdmac->chn_count += count;
1200 1201 1202 1203 1204

		if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
			ret =  -EINVAL;
			goto err_out;
		}
1205 1206 1207

		switch (sdmac->word_size) {
		case DMA_SLAVE_BUSWIDTH_4_BYTES:
1208
			bd->mode.command = 0;
1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222
			if (count & 3 || sg->dma_address & 3)
				return NULL;
			break;
		case DMA_SLAVE_BUSWIDTH_2_BYTES:
			bd->mode.command = 2;
			if (count & 1 || sg->dma_address & 1)
				return NULL;
			break;
		case DMA_SLAVE_BUSWIDTH_1_BYTE:
			bd->mode.command = 1;
			break;
		default:
			return NULL;
		}
1223 1224 1225

		param = BD_DONE | BD_EXTD | BD_CONT;

1226
		if (i + 1 == sg_len) {
1227
			param |= BD_INTR;
1228 1229
			param |= BD_LAST;
			param &= ~BD_CONT;
1230 1231
		}

1232 1233
		dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
				i, count, (u64)sg->dma_address,
1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244
				param & BD_WRAP ? "wrap" : "",
				param & BD_INTR ? " intr" : "");

		bd->mode.status = param;
	}

	sdmac->num_bd = sg_len;
	sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;

	return &sdmac->desc;
err_out:
1245
	sdmac->status = DMA_ERROR;
1246 1247 1248 1249 1250
	return NULL;
}

static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
		struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1251
		size_t period_len, enum dma_transfer_direction direction,
1252
		unsigned long flags)
1253 1254 1255 1256
{
	struct sdma_channel *sdmac = to_sdma_chan(chan);
	struct sdma_engine *sdma = sdmac->sdma;
	int num_periods = buf_len / period_len;
1257
	int channel = sdmac->channel;
1258 1259 1260 1261 1262 1263 1264 1265 1266
	int ret, i = 0, buf = 0;

	dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);

	if (sdmac->status == DMA_IN_PROGRESS)
		return NULL;

	sdmac->status = DMA_IN_PROGRESS;

1267
	sdmac->buf_tail = 0;
1268
	sdmac->period_len = period_len;
1269

1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306
	sdmac->flags |= IMX_DMA_SG_LOOP;
	sdmac->direction = direction;
	ret = sdma_load_context(sdmac);
	if (ret)
		goto err_out;

	if (num_periods > NUM_BD) {
		dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
				channel, num_periods, NUM_BD);
		goto err_out;
	}

	if (period_len > 0xffff) {
		dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
				channel, period_len, 0xffff);
		goto err_out;
	}

	while (buf < buf_len) {
		struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
		int param;

		bd->buffer_addr = dma_addr;

		bd->mode.count = period_len;

		if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
			goto err_out;
		if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
			bd->mode.command = 0;
		else
			bd->mode.command = sdmac->word_size;

		param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
		if (i + 1 == num_periods)
			param |= BD_WRAP;

1307 1308
		dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
				i, period_len, (u64)dma_addr,
1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328
				param & BD_WRAP ? "wrap" : "",
				param & BD_INTR ? " intr" : "");

		bd->mode.status = param;

		dma_addr += period_len;
		buf += period_len;

		i++;
	}

	sdmac->num_bd = num_periods;
	sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;

	return &sdmac->desc;
err_out:
	sdmac->status = DMA_ERROR;
	return NULL;
}

1329 1330
static int sdma_config(struct dma_chan *chan,
		       struct dma_slave_config *dmaengine_cfg)
1331 1332 1333
{
	struct sdma_channel *sdmac = to_sdma_chan(chan);

1334 1335 1336 1337 1338
	if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
		sdmac->per_address = dmaengine_cfg->src_addr;
		sdmac->watermark_level = dmaengine_cfg->src_maxburst *
			dmaengine_cfg->src_addr_width;
		sdmac->word_size = dmaengine_cfg->src_addr_width;
1339 1340 1341 1342 1343 1344 1345 1346
	} else if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) {
		sdmac->per_address2 = dmaengine_cfg->src_addr;
		sdmac->per_address = dmaengine_cfg->dst_addr;
		sdmac->watermark_level = dmaengine_cfg->src_maxburst &
			SDMA_WATERMARK_LEVEL_LWML;
		sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
			SDMA_WATERMARK_LEVEL_HWML;
		sdmac->word_size = dmaengine_cfg->dst_addr_width;
1347 1348 1349 1350 1351 1352 1353 1354
	} else {
		sdmac->per_address = dmaengine_cfg->dst_addr;
		sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
			dmaengine_cfg->dst_addr_width;
		sdmac->word_size = dmaengine_cfg->dst_addr_width;
	}
	sdmac->direction = dmaengine_cfg->direction;
	return sdma_config_channel(chan);
1355 1356 1357
}

static enum dma_status sdma_tx_status(struct dma_chan *chan,
1358 1359
				      dma_cookie_t cookie,
				      struct dma_tx_state *txstate)
1360 1361
{
	struct sdma_channel *sdmac = to_sdma_chan(chan);
1362 1363 1364 1365 1366 1367
	u32 residue;

	if (sdmac->flags & IMX_DMA_SG_LOOP)
		residue = (sdmac->num_bd - sdmac->buf_tail) * sdmac->period_len;
	else
		residue = sdmac->chn_count - sdmac->chn_real_count;
1368

1369
	dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1370
			 residue);
1371

1372
	return sdmac->status;
1373 1374 1375 1376
}

static void sdma_issue_pending(struct dma_chan *chan)
{
1377 1378 1379 1380 1381
	struct sdma_channel *sdmac = to_sdma_chan(chan);
	struct sdma_engine *sdma = sdmac->sdma;

	if (sdmac->status == DMA_IN_PROGRESS)
		sdma_enable_channel(sdma, sdmac->channel);
1382 1383
}

1384
#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1	34
1385
#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2	38
1386
#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3	41
1387 1388 1389 1390 1391 1392 1393 1394

static void sdma_add_scripts(struct sdma_engine *sdma,
		const struct sdma_script_start_addrs *addr)
{
	s32 *addr_arr = (u32 *)addr;
	s32 *saddr_arr = (u32 *)sdma->script_addrs;
	int i;

1395 1396 1397 1398
	/* use the default firmware in ROM if missing external firmware */
	if (!sdma->script_number)
		sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;

1399
	for (i = 0; i < sdma->script_number; i++)
1400 1401 1402 1403
		if (addr_arr[i] > 0)
			saddr_arr[i] = addr_arr[i];
}

1404
static void sdma_load_firmware(const struct firmware *fw, void *context)
1405
{
1406
	struct sdma_engine *sdma = context;
1407 1408 1409 1410
	const struct sdma_firmware_header *header;
	const struct sdma_script_start_addrs *addr;
	unsigned short *ram_code;

1411
	if (!fw) {
1412 1413
		dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
		/* In this case we just use the ROM firmware. */
1414 1415
		return;
	}
1416 1417 1418 1419 1420 1421 1422 1423 1424 1425

	if (fw->size < sizeof(*header))
		goto err_firmware;

	header = (struct sdma_firmware_header *)fw->data;

	if (header->magic != SDMA_FIRMWARE_MAGIC)
		goto err_firmware;
	if (header->ram_code_start + header->ram_code_size > fw->size)
		goto err_firmware;
1426
	switch (header->version_major) {
A
Asaf Vertz 已提交
1427 1428 1429 1430 1431 1432
	case 1:
		sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
		break;
	case 2:
		sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
		break;
1433 1434 1435
	case 3:
		sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
		break;
A
Asaf Vertz 已提交
1436 1437 1438
	default:
		dev_err(sdma->dev, "unknown firmware version\n");
		goto err_firmware;
1439
	}
1440 1441 1442 1443

	addr = (void *)header + header->script_addrs_start;
	ram_code = (void *)header + header->ram_code_start;

1444 1445
	clk_enable(sdma->clk_ipg);
	clk_enable(sdma->clk_ahb);
1446 1447 1448
	/* download the RAM image for SDMA */
	sdma_load_script(sdma, ram_code,
			header->ram_code_size,
1449
			addr->ram_code_start_addr);
1450 1451
	clk_disable(sdma->clk_ipg);
	clk_disable(sdma->clk_ahb);
1452 1453 1454 1455 1456 1457 1458 1459 1460

	sdma_add_scripts(sdma, addr);

	dev_info(sdma->dev, "loaded firmware %d.%d\n",
			header->version_major,
			header->version_minor);

err_firmware:
	release_firmware(fw);
1461 1462
}

1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528
#define EVENT_REMAP_CELLS 3

static int __init sdma_event_remap(struct sdma_engine *sdma)
{
	struct device_node *np = sdma->dev->of_node;
	struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
	struct property *event_remap;
	struct regmap *gpr;
	char propname[] = "fsl,sdma-event-remap";
	u32 reg, val, shift, num_map, i;
	int ret = 0;

	if (IS_ERR(np) || IS_ERR(gpr_np))
		goto out;

	event_remap = of_find_property(np, propname, NULL);
	num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
	if (!num_map) {
		dev_warn(sdma->dev, "no event needs to be remapped\n");
		goto out;
	} else if (num_map % EVENT_REMAP_CELLS) {
		dev_err(sdma->dev, "the property %s must modulo %d\n",
				propname, EVENT_REMAP_CELLS);
		ret = -EINVAL;
		goto out;
	}

	gpr = syscon_node_to_regmap(gpr_np);
	if (IS_ERR(gpr)) {
		dev_err(sdma->dev, "failed to get gpr regmap\n");
		ret = PTR_ERR(gpr);
		goto out;
	}

	for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
		ret = of_property_read_u32_index(np, propname, i, &reg);
		if (ret) {
			dev_err(sdma->dev, "failed to read property %s index %d\n",
					propname, i);
			goto out;
		}

		ret = of_property_read_u32_index(np, propname, i + 1, &shift);
		if (ret) {
			dev_err(sdma->dev, "failed to read property %s index %d\n",
					propname, i + 1);
			goto out;
		}

		ret = of_property_read_u32_index(np, propname, i + 2, &val);
		if (ret) {
			dev_err(sdma->dev, "failed to read property %s index %d\n",
					propname, i + 2);
			goto out;
		}

		regmap_update_bits(gpr, reg, BIT(shift), val << shift);
	}

out:
	if (!IS_ERR(gpr_np))
		of_node_put(gpr_np);

	return ret;
}

1529
static int sdma_get_firmware(struct sdma_engine *sdma,
1530 1531 1532 1533 1534 1535 1536
		const char *fw_name)
{
	int ret;

	ret = request_firmware_nowait(THIS_MODULE,
			FW_ACTION_HOTPLUG, fw_name, sdma->dev,
			GFP_KERNEL, sdma, sdma_load_firmware);
1537 1538 1539 1540

	return ret;
}

1541
static int sdma_init(struct sdma_engine *sdma)
1542 1543 1544 1545
{
	int i, ret;
	dma_addr_t ccb_phys;

1546 1547 1548 1549 1550 1551
	ret = clk_enable(sdma->clk_ipg);
	if (ret)
		return ret;
	ret = clk_enable(sdma->clk_ahb);
	if (ret)
		goto disable_clk_ipg;
1552 1553

	/* Be sure SDMA has not started yet */
1554
	writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575

	sdma->channel_control = dma_alloc_coherent(NULL,
			MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
			sizeof(struct sdma_context_data),
			&ccb_phys, GFP_KERNEL);

	if (!sdma->channel_control) {
		ret = -ENOMEM;
		goto err_dma_alloc;
	}

	sdma->context = (void *)sdma->channel_control +
		MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
	sdma->context_phys = ccb_phys +
		MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);

	/* Zero-out the CCB structures array just allocated */
	memset(sdma->channel_control, 0,
			MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));

	/* disable all channels */
1576
	for (i = 0; i < sdma->drvdata->num_events; i++)
1577
		writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1578 1579 1580

	/* All channels have priority 0 */
	for (i = 0; i < MAX_DMA_CHANNELS; i++)
1581
		writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1582 1583 1584 1585 1586 1587 1588 1589

	ret = sdma_request_channel(&sdma->channel[0]);
	if (ret)
		goto err_dma_alloc;

	sdma_config_ownership(&sdma->channel[0], false, true, false);

	/* Set Command Channel (Channel Zero) */
1590
	writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1591 1592 1593

	/* Set bits of CONFIG register but with static context switching */
	/* FIXME: Check whether to set ACR bit depending on clock ratios */
1594
	writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1595

1596
	writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1597 1598 1599 1600

	/* Initializes channel's priorities */
	sdma_set_channel_priority(&sdma->channel[0], 7);

1601 1602
	clk_disable(sdma->clk_ipg);
	clk_disable(sdma->clk_ahb);
1603 1604 1605 1606

	return 0;

err_dma_alloc:
1607
	clk_disable(sdma->clk_ahb);
1608 1609
disable_clk_ipg:
	clk_disable(sdma->clk_ipg);
1610 1611 1612 1613
	dev_err(sdma->dev, "initialisation failed with %d\n", ret);
	return ret;
}

1614 1615
static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
{
1616
	struct sdma_channel *sdmac = to_sdma_chan(chan);
1617 1618 1619 1620 1621
	struct imx_dma_data *data = fn_param;

	if (!imx_dma_is_general_purpose(chan))
		return false;

1622 1623
	sdmac->data = *data;
	chan->private = &sdmac->data;
1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640

	return true;
}

static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
				   struct of_dma *ofdma)
{
	struct sdma_engine *sdma = ofdma->of_dma_data;
	dma_cap_mask_t mask = sdma->dma_device.cap_mask;
	struct imx_dma_data data;

	if (dma_spec->args_count != 3)
		return NULL;

	data.dma_request = dma_spec->args[0];
	data.peripheral_type = dma_spec->args[1];
	data.priority = dma_spec->args[2];
1641 1642 1643 1644 1645 1646 1647 1648
	/*
	 * init dma_request2 to zero, which is not used by the dts.
	 * For P2P, dma_request2 is init from dma_request_channel(),
	 * chan->private will point to the imx_dma_data, and in
	 * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
	 * be set to sdmac->event_id1.
	 */
	data.dma_request2 = 0;
1649 1650 1651 1652

	return dma_request_channel(mask, sdma_filter_fn, &data);
}

1653
static int sdma_probe(struct platform_device *pdev)
1654
{
1655 1656 1657
	const struct of_device_id *of_id =
			of_match_device(sdma_dt_ids, &pdev->dev);
	struct device_node *np = pdev->dev.of_node;
1658
	struct device_node *spba_bus;
1659
	const char *fw_name;
1660 1661 1662
	int ret;
	int irq;
	struct resource *iores;
1663
	struct resource spba_res;
J
Jingoo Han 已提交
1664
	struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1665 1666
	int i;
	struct sdma_engine *sdma;
1667
	s32 *saddr_arr;
1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678
	const struct sdma_driver_data *drvdata = NULL;

	if (of_id)
		drvdata = of_id->data;
	else if (pdev->id_entry)
		drvdata = (void *)pdev->id_entry->driver_data;

	if (!drvdata) {
		dev_err(&pdev->dev, "unable to find driver data\n");
		return -EINVAL;
	}
1679

1680 1681 1682 1683
	ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
	if (ret)
		return ret;

1684
	sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
1685 1686 1687
	if (!sdma)
		return -ENOMEM;

1688
	spin_lock_init(&sdma->channel_0_lock);
1689

1690
	sdma->dev = &pdev->dev;
1691
	sdma->drvdata = drvdata;
1692 1693

	irq = platform_get_irq(pdev, 0);
1694
	if (irq < 0)
1695
		return irq;
1696

1697 1698 1699 1700
	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
	if (IS_ERR(sdma->regs))
		return PTR_ERR(sdma->regs);
1701

1702
	sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1703 1704
	if (IS_ERR(sdma->clk_ipg))
		return PTR_ERR(sdma->clk_ipg);
1705

1706
	sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1707 1708
	if (IS_ERR(sdma->clk_ahb))
		return PTR_ERR(sdma->clk_ahb);
1709 1710 1711 1712

	clk_prepare(sdma->clk_ipg);
	clk_prepare(sdma->clk_ahb);

1713 1714
	ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
			       sdma);
1715
	if (ret)
1716
		return ret;
1717

1718
	sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1719 1720
	if (!sdma->script_addrs)
		return -ENOMEM;
1721

1722 1723 1724 1725 1726
	/* initially no scripts available */
	saddr_arr = (s32 *)sdma->script_addrs;
	for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
		saddr_arr[i] = -EINVAL;

1727 1728 1729
	dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
	dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);

1730 1731 1732 1733 1734 1735 1736 1737 1738
	INIT_LIST_HEAD(&sdma->dma_device.channels);
	/* Initialize channel parameters */
	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
		struct sdma_channel *sdmac = &sdma->channel[i];

		sdmac->sdma = sdma;
		spin_lock_init(&sdmac->lock);

		sdmac->chan.device = &sdma->dma_device;
1739
		dma_cookie_init(&sdmac->chan);
1740 1741
		sdmac->channel = i;

1742 1743
		tasklet_init(&sdmac->tasklet, sdma_tasklet,
			     (unsigned long) sdmac);
1744 1745 1746 1747 1748 1749 1750 1751
		/*
		 * Add the channel to the DMAC list. Do not add channel 0 though
		 * because we need it internally in the SDMA driver. This also means
		 * that channel 0 in dmaengine counting matches sdma channel 1.
		 */
		if (i)
			list_add_tail(&sdmac->chan.device_node,
					&sdma->dma_device.channels);
1752 1753
	}

1754
	ret = sdma_init(sdma);
1755 1756 1757
	if (ret)
		goto err_init;

1758 1759 1760 1761
	ret = sdma_event_remap(sdma);
	if (ret)
		goto err_init;

1762 1763
	if (sdma->drvdata->script_addrs)
		sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
1764
	if (pdata && pdata->script_addrs)
1765 1766
		sdma_add_scripts(sdma, pdata->script_addrs);

1767
	if (pdata) {
1768 1769
		ret = sdma_get_firmware(sdma, pdata->fw_name);
		if (ret)
1770
			dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1771 1772 1773 1774 1775 1776 1777 1778
	} else {
		/*
		 * Because that device tree does not encode ROM script address,
		 * the RAM script in firmware is mandatory for device tree
		 * probe, otherwise it fails.
		 */
		ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
					      &fw_name);
1779
		if (ret)
1780
			dev_warn(&pdev->dev, "failed to get firmware name\n");
1781 1782 1783
		else {
			ret = sdma_get_firmware(sdma, fw_name);
			if (ret)
1784
				dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1785 1786
		}
	}
1787

1788 1789 1790 1791 1792 1793 1794
	sdma->dma_device.dev = &pdev->dev;

	sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
	sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
	sdma->dma_device.device_tx_status = sdma_tx_status;
	sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
	sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1795 1796
	sdma->dma_device.device_config = sdma_config;
	sdma->dma_device.device_terminate_all = sdma_disable_channel;
1797 1798 1799 1800
	sdma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
	sdma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
	sdma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
	sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1801
	sdma->dma_device.device_issue_pending = sdma_issue_pending;
1802 1803
	sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
	dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1804

1805 1806
	platform_set_drvdata(pdev, sdma);

1807 1808 1809 1810 1811 1812
	ret = dma_async_device_register(&sdma->dma_device);
	if (ret) {
		dev_err(&pdev->dev, "unable to register\n");
		goto err_init;
	}

1813 1814 1815 1816 1817 1818
	if (np) {
		ret = of_dma_controller_register(np, sdma_xlate, sdma);
		if (ret) {
			dev_err(&pdev->dev, "failed to register controller\n");
			goto err_register;
		}
1819 1820 1821 1822 1823 1824 1825 1826

		spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
		ret = of_address_to_resource(spba_bus, 0, &spba_res);
		if (!ret) {
			sdma->spba_start_addr = spba_res.start;
			sdma->spba_end_addr = spba_res.end;
		}
		of_node_put(spba_bus);
1827 1828
	}

1829
	dev_info(sdma->dev, "initialized\n");
1830 1831 1832

	return 0;

1833 1834
err_register:
	dma_async_device_unregister(&sdma->dma_device);
1835 1836
err_init:
	kfree(sdma->script_addrs);
1837
	return ret;
1838 1839
}

1840
static int sdma_remove(struct platform_device *pdev)
1841
{
1842
	struct sdma_engine *sdma = platform_get_drvdata(pdev);
1843
	int i;
1844 1845 1846

	dma_async_device_unregister(&sdma->dma_device);
	kfree(sdma->script_addrs);
1847 1848 1849 1850 1851 1852
	/* Kill the tasklet */
	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
		struct sdma_channel *sdmac = &sdma->channel[i];

		tasklet_kill(&sdmac->tasklet);
	}
1853 1854 1855 1856

	platform_set_drvdata(pdev, NULL);
	dev_info(&pdev->dev, "Removed...\n");
	return 0;
1857 1858 1859 1860 1861
}

static struct platform_driver sdma_driver = {
	.driver		= {
		.name	= "imx-sdma",
1862
		.of_match_table = sdma_dt_ids,
1863
	},
1864
	.id_table	= sdma_devtypes,
1865
	.remove		= sdma_remove,
1866
	.probe		= sdma_probe,
1867 1868
};

1869
module_platform_driver(sdma_driver);
1870 1871 1872 1873

MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION("i.MX SDMA driver");
MODULE_LICENSE("GPL");