pci.c 113.2 KB
Newer Older
L
Linus Torvalds 已提交
1 2 3 4 5 6 7 8 9 10 11 12 13
/*
 *	PCI Bus Services, see include/linux/pci.h for further explanation.
 *
 *	Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
 *	David Mosberger-Tang
 *
 *	Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
 */

#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/pci.h>
14
#include <linux/pm.h>
15
#include <linux/slab.h>
L
Linus Torvalds 已提交
16 17
#include <linux/module.h>
#include <linux/spinlock.h>
T
Tim Schmielau 已提交
18
#include <linux/string.h>
19
#include <linux/log2.h>
S
Shaohua Li 已提交
20
#include <linux/pci-aspm.h>
21
#include <linux/pm_wakeup.h>
22
#include <linux/interrupt.h>
23
#include <linux/device.h>
24
#include <linux/pm_runtime.h>
25
#include <linux/pci_hotplug.h>
26
#include <asm-generic/pci-bridge.h>
27
#include <asm/setup.h>
28
#include "pci.h"
L
Linus Torvalds 已提交
29

A
Alan Stern 已提交
30 31 32 33 34
const char *pci_power_names[] = {
	"error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
};
EXPORT_SYMBOL_GPL(pci_power_names);

35 36 37 38 39 40
int isa_dma_bridge_buggy;
EXPORT_SYMBOL(isa_dma_bridge_buggy);

int pci_pci_problems;
EXPORT_SYMBOL(pci_pci_problems);

41 42
unsigned int pci_pm_d3_delay;

43 44 45 46 47 48 49 50 51 52 53 54 55
static void pci_pme_list_scan(struct work_struct *work);

static LIST_HEAD(pci_pme_list);
static DEFINE_MUTEX(pci_pme_list_mutex);
static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);

struct pci_pme_device {
	struct list_head list;
	struct pci_dev *dev;
};

#define PME_TIMEOUT 1000 /* How long between PME checks */

56 57 58 59 60 61 62 63 64
static void pci_dev_d3_sleep(struct pci_dev *dev)
{
	unsigned int delay = dev->d3_delay;

	if (delay < pci_pm_d3_delay)
		delay = pci_pm_d3_delay;

	msleep(delay);
}
L
Linus Torvalds 已提交
65

66 67 68 69
#ifdef CONFIG_PCI_DOMAINS
int pci_domains_supported = 1;
#endif

70 71 72 73 74 75
#define DEFAULT_CARDBUS_IO_SIZE		(256)
#define DEFAULT_CARDBUS_MEM_SIZE	(64*1024*1024)
/* pci=cbmemsize=nnM,cbiosize=nn can override this */
unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;

76 77 78 79 80 81
#define DEFAULT_HOTPLUG_IO_SIZE		(256)
#define DEFAULT_HOTPLUG_MEM_SIZE	(2*1024*1024)
/* pci=hpmemsize=nnM,hpiosize=nn can override this */
unsigned long pci_hotplug_io_size  = DEFAULT_HOTPLUG_IO_SIZE;
unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;

82
enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
83

84 85 86 87 88 89
/*
 * The default CLS is used if arch didn't set CLS explicitly and not
 * all pci devices agree on the same value.  Arch can override either
 * the dfl or actual value as it sees fit.  Don't forget this is
 * measured in 32-bit words, not bytes.
 */
B
Bill Pemberton 已提交
90
u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
91 92
u8 pci_cache_line_size;

93 94 95 96 97 98
/*
 * If we set up a device for bus mastering, we need to check the latency
 * timer as certain BIOSes forget to set it properly.
 */
unsigned int pcibios_max_latency = 255;

99 100 101
/* If set, the PCIe ARI capability will not be used. */
static bool pcie_ari_disabled;

L
Linus Torvalds 已提交
102 103 104 105 106 107 108
/**
 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
 * @bus: pointer to PCI bus structure to search
 *
 * Given a PCI bus, returns the highest PCI bus number present in the set
 * including the given PCI bus and its list of child PCI buses.
 */
109
unsigned char pci_bus_max_busnr(struct pci_bus* bus)
L
Linus Torvalds 已提交
110 111 112 113
{
	struct list_head *tmp;
	unsigned char max, n;

114
	max = bus->busn_res.end;
L
Linus Torvalds 已提交
115 116 117 118 119 120 121
	list_for_each(tmp, &bus->children) {
		n = pci_bus_max_busnr(pci_bus_b(tmp));
		if(n > max)
			max = n;
	}
	return max;
}
122
EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
L
Linus Torvalds 已提交
123

A
Andrew Morton 已提交
124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139
#ifdef CONFIG_HAS_IOMEM
void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
{
	/*
	 * Make sure the BAR is actually a memory resource, not an IO resource
	 */
	if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
		WARN_ON(1);
		return NULL;
	}
	return ioremap_nocache(pci_resource_start(pdev, bar),
				     pci_resource_len(pdev, bar));
}
EXPORT_SYMBOL_GPL(pci_ioremap_bar);
#endif

140 141 142 143
#define PCI_FIND_CAP_TTL	48

static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
				   u8 pos, int cap, int *ttl)
144 145 146
{
	u8 id;

147
	while ((*ttl)--) {
148 149 150 151 152 153 154 155 156 157 158 159 160 161 162
		pci_bus_read_config_byte(bus, devfn, pos, &pos);
		if (pos < 0x40)
			break;
		pos &= ~3;
		pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
					 &id);
		if (id == 0xff)
			break;
		if (id == cap)
			return pos;
		pos += PCI_CAP_LIST_NEXT;
	}
	return 0;
}

163 164 165 166 167 168 169 170
static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
			       u8 pos, int cap)
{
	int ttl = PCI_FIND_CAP_TTL;

	return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
}

171 172 173 174 175 176 177
int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
{
	return __pci_find_next_cap(dev->bus, dev->devfn,
				   pos + PCI_CAP_LIST_NEXT, cap);
}
EXPORT_SYMBOL_GPL(pci_find_next_capability);

178 179
static int __pci_bus_find_cap_start(struct pci_bus *bus,
				    unsigned int devfn, u8 hdr_type)
L
Linus Torvalds 已提交
180 181 182 183 184 185 186 187 188 189
{
	u16 status;

	pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
	if (!(status & PCI_STATUS_CAP_LIST))
		return 0;

	switch (hdr_type) {
	case PCI_HEADER_TYPE_NORMAL:
	case PCI_HEADER_TYPE_BRIDGE:
190
		return PCI_CAPABILITY_LIST;
L
Linus Torvalds 已提交
191
	case PCI_HEADER_TYPE_CARDBUS:
192
		return PCI_CB_CAPABILITY_LIST;
L
Linus Torvalds 已提交
193 194 195
	default:
		return 0;
	}
196 197

	return 0;
L
Linus Torvalds 已提交
198 199 200
}

/**
201
 * pci_find_capability - query for devices' capabilities
L
Linus Torvalds 已提交
202 203 204 205 206 207 208 209
 * @dev: PCI device to query
 * @cap: capability code
 *
 * Tell if a device supports a given PCI capability.
 * Returns the address of the requested capability structure within the
 * device's PCI configuration space or 0 in case the device does not
 * support it.  Possible values for @cap:
 *
210 211 212 213
 *  %PCI_CAP_ID_PM           Power Management
 *  %PCI_CAP_ID_AGP          Accelerated Graphics Port
 *  %PCI_CAP_ID_VPD          Vital Product Data
 *  %PCI_CAP_ID_SLOTID       Slot Identification
L
Linus Torvalds 已提交
214
 *  %PCI_CAP_ID_MSI          Message Signalled Interrupts
215
 *  %PCI_CAP_ID_CHSWP        CompactPCI HotSwap
L
Linus Torvalds 已提交
216 217 218 219 220
 *  %PCI_CAP_ID_PCIX         PCI-X
 *  %PCI_CAP_ID_EXP          PCI Express
 */
int pci_find_capability(struct pci_dev *dev, int cap)
{
221 222 223 224 225 226 227
	int pos;

	pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
	if (pos)
		pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);

	return pos;
L
Linus Torvalds 已提交
228 229 230
}

/**
231
 * pci_bus_find_capability - query for devices' capabilities
L
Linus Torvalds 已提交
232 233 234 235 236
 * @bus:   the PCI bus to query
 * @devfn: PCI device to query
 * @cap:   capability code
 *
 * Like pci_find_capability() but works for pci devices that do not have a
237
 * pci_dev structure set up yet.
L
Linus Torvalds 已提交
238 239 240 241 242 243 244
 *
 * Returns the address of the requested capability structure within the
 * device's PCI configuration space or 0 in case the device does not
 * support it.
 */
int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
{
245
	int pos;
L
Linus Torvalds 已提交
246 247 248 249
	u8 hdr_type;

	pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);

250 251 252 253 254
	pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
	if (pos)
		pos = __pci_find_next_cap(bus, devfn, pos, cap);

	return pos;
L
Linus Torvalds 已提交
255 256 257
}

/**
258
 * pci_find_next_ext_capability - Find an extended capability
L
Linus Torvalds 已提交
259
 * @dev: PCI device to query
260
 * @start: address at which to start looking (0 to start at beginning of list)
L
Linus Torvalds 已提交
261 262
 * @cap: capability code
 *
263
 * Returns the address of the next matching extended capability structure
L
Linus Torvalds 已提交
264
 * within the device's PCI configuration space or 0 if the device does
265 266
 * not support it.  Some capabilities can occur several times, e.g., the
 * vendor-specific capability, and this provides a way to find them all.
L
Linus Torvalds 已提交
267
 */
268
int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
L
Linus Torvalds 已提交
269 270
{
	u32 header;
271 272
	int ttl;
	int pos = PCI_CFG_SPACE_SIZE;
L
Linus Torvalds 已提交
273

274 275 276 277
	/* minimum 8 bytes per capability */
	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;

	if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
L
Linus Torvalds 已提交
278 279
		return 0;

280 281 282
	if (start)
		pos = start;

L
Linus Torvalds 已提交
283 284 285 286 287 288 289 290 291 292 293
	if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
		return 0;

	/*
	 * If we have no capabilities, this is indicated by cap ID,
	 * cap version and next pointer all being 0.
	 */
	if (header == 0)
		return 0;

	while (ttl-- > 0) {
294
		if (PCI_EXT_CAP_ID(header) == cap && pos != start)
L
Linus Torvalds 已提交
295 296 297
			return pos;

		pos = PCI_EXT_CAP_NEXT(header);
298
		if (pos < PCI_CFG_SPACE_SIZE)
L
Linus Torvalds 已提交
299 300 301 302 303 304 305 306
			break;

		if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
			break;
	}

	return 0;
}
307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326
EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);

/**
 * pci_find_ext_capability - Find an extended capability
 * @dev: PCI device to query
 * @cap: capability code
 *
 * Returns the address of the requested extended capability structure
 * within the device's PCI configuration space or 0 if the device does
 * not support it.  Possible values for @cap:
 *
 *  %PCI_EXT_CAP_ID_ERR		Advanced Error Reporting
 *  %PCI_EXT_CAP_ID_VC		Virtual Channel
 *  %PCI_EXT_CAP_ID_DSN		Device Serial Number
 *  %PCI_EXT_CAP_ID_PWR		Power Budgeting
 */
int pci_find_ext_capability(struct pci_dev *dev, int cap)
{
	return pci_find_next_ext_capability(dev, 0, cap);
}
327
EXPORT_SYMBOL_GPL(pci_find_ext_capability);
L
Linus Torvalds 已提交
328

329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348
static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
{
	int rc, ttl = PCI_FIND_CAP_TTL;
	u8 cap, mask;

	if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
		mask = HT_3BIT_CAP_MASK;
	else
		mask = HT_5BIT_CAP_MASK;

	pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
				      PCI_CAP_ID_HT, &ttl);
	while (pos) {
		rc = pci_read_config_byte(dev, pos + 3, &cap);
		if (rc != PCIBIOS_SUCCESSFUL)
			return 0;

		if ((cap & mask) == ht_cap)
			return pos;

349 350
		pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
					      pos + PCI_CAP_LIST_NEXT,
351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397
					      PCI_CAP_ID_HT, &ttl);
	}

	return 0;
}
/**
 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
 * @dev: PCI device to query
 * @pos: Position from which to continue searching
 * @ht_cap: Hypertransport capability code
 *
 * To be used in conjunction with pci_find_ht_capability() to search for
 * all capabilities matching @ht_cap. @pos should always be a value returned
 * from pci_find_ht_capability().
 *
 * NB. To be 100% safe against broken PCI devices, the caller should take
 * steps to avoid an infinite loop.
 */
int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
{
	return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
}
EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);

/**
 * pci_find_ht_capability - query a device's Hypertransport capabilities
 * @dev: PCI device to query
 * @ht_cap: Hypertransport capability code
 *
 * Tell if a device supports a given Hypertransport capability.
 * Returns an address within the device's PCI configuration space
 * or 0 in case the device does not support the request capability.
 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
 * which has a Hypertransport capability matching @ht_cap.
 */
int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
{
	int pos;

	pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
	if (pos)
		pos = __pci_find_next_ht_cap(dev, pos, ht_cap);

	return pos;
}
EXPORT_SYMBOL_GPL(pci_find_ht_capability);

L
Linus Torvalds 已提交
398 399 400 401 402 403 404 405 406 407 408 409 410 411
/**
 * pci_find_parent_resource - return resource region of parent bus of given region
 * @dev: PCI device structure contains resources to be searched
 * @res: child resource record for which parent is sought
 *
 *  For given resource region of given device, return the resource
 *  region of parent bus the given region is contained in or where
 *  it should be allocated from.
 */
struct resource *
pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
{
	const struct pci_bus *bus = dev->bus;
	int i;
412
	struct resource *best = NULL, *r;
L
Linus Torvalds 已提交
413

414
	pci_bus_for_each_resource(bus, r, i) {
L
Linus Torvalds 已提交
415 416 417 418 419 420 421 422
		if (!r)
			continue;
		if (res->start && !(res->start >= r->start && res->end <= r->end))
			continue;	/* Not contained */
		if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
			continue;	/* Wrong type */
		if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
			return r;	/* Exact match */
423 424 425 426 427 428
		/* We can't insert a non-prefetch resource inside a prefetchable parent .. */
		if (r->flags & IORESOURCE_PREFETCH)
			continue;
		/* .. but we can put a prefetchable resource inside a non-prefetchable one */
		if (!best)
			best = r;
L
Linus Torvalds 已提交
429 430 431 432
	}
	return best;
}

433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458
/**
 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
 * @dev: the PCI device to operate on
 * @pos: config space offset of status word
 * @mask: mask of bit(s) to care about in status word
 *
 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
 */
int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
{
	int i;

	/* Wait for Transaction Pending bit clean */
	for (i = 0; i < 4; i++) {
		u16 status;
		if (i)
			msleep((1 << (i - 1)) * 100);

		pci_read_config_word(dev, pos, &status);
		if (!(status & mask))
			return 1;
	}

	return 0;
}

459 460 461 462 463 464 465
/**
 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
 * @dev: PCI device to have its BARs restored
 *
 * Restore the BAR values for a given device, so as to make it
 * accessible by its driver.
 */
466
static void
467 468
pci_restore_bars(struct pci_dev *dev)
{
469
	int i;
470

471
	for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
472
		pci_update_resource(dev, i);
473 474
}

475 476 477 478
static struct pci_platform_pm_ops *pci_platform_pm;

int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
{
479
	if (!ops->is_manageable || !ops->set_state || !ops->choose_state
480
	    || !ops->sleep_wake)
481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501
		return -EINVAL;
	pci_platform_pm = ops;
	return 0;
}

static inline bool platform_pci_power_manageable(struct pci_dev *dev)
{
	return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
}

static inline int platform_pci_set_power_state(struct pci_dev *dev,
                                                pci_power_t t)
{
	return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
}

static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
{
	return pci_platform_pm ?
			pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
}
R
Randy Dunlap 已提交
502

503 504 505 506 507 508
static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
{
	return pci_platform_pm ?
			pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
}

509 510 511 512 513 514
static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
{
	return pci_platform_pm ?
			pci_platform_pm->run_wake(dev, enable) : -ENODEV;
}

L
Linus Torvalds 已提交
515
/**
516 517 518 519
 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
 *                           given PCI device
 * @dev: PCI device to handle.
 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
L
Linus Torvalds 已提交
520
 *
521 522 523 524 525 526
 * RETURN VALUE:
 * -EINVAL if the requested state is invalid.
 * -EIO if device does not support PCI PM or its PM capabilities register has a
 * wrong version, or device doesn't support the requested state.
 * 0 if device already is in the requested state.
 * 0 if device's power state has been successfully changed.
L
Linus Torvalds 已提交
527
 */
528
static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
L
Linus Torvalds 已提交
529
{
530
	u16 pmcsr;
531
	bool need_restore = false;
L
Linus Torvalds 已提交
532

533 534 535 536
	/* Check if we're already there */
	if (dev->current_state == state)
		return 0;

537
	if (!dev->pm_cap)
538 539
		return -EIO;

540 541 542
	if (state < PCI_D0 || state > PCI_D3hot)
		return -EINVAL;

L
Linus Torvalds 已提交
543
	/* Validate current state:
544
	 * Can enter D0 from any state, but if we can only go deeper
L
Linus Torvalds 已提交
545 546
	 * to sleep if we're already in a low power state
	 */
547
	if (state != PCI_D0 && dev->current_state <= PCI_D3cold
548
	    && dev->current_state > state) {
549 550
		dev_err(&dev->dev, "invalid power transition "
			"(from state %d to %d)\n", dev->current_state, state);
L
Linus Torvalds 已提交
551
		return -EINVAL;
552
	}
L
Linus Torvalds 已提交
553 554

	/* check if this device supports the desired state */
555 556
	if ((state == PCI_D1 && !dev->d1_support)
	   || (state == PCI_D2 && !dev->d2_support))
557
		return -EIO;
L
Linus Torvalds 已提交
558

559
	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
560

561
	/* If we're (effectively) in D3, force entire word to 0.
L
Linus Torvalds 已提交
562 563 564
	 * This doesn't affect PME_Status, disables PME_En, and
	 * sets PowerState to 0.
	 */
565
	switch (dev->current_state) {
566 567 568 569 570 571
	case PCI_D0:
	case PCI_D1:
	case PCI_D2:
		pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
		pmcsr |= state;
		break;
572 573
	case PCI_D3hot:
	case PCI_D3cold:
574 575
	case PCI_UNKNOWN: /* Boot-up */
		if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
576
		 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
577
			need_restore = true;
578 579
		/* Fall-through: force to D0 */
	default:
580
		pmcsr = 0;
581
		break;
L
Linus Torvalds 已提交
582 583 584
	}

	/* enter specified state */
585
	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
L
Linus Torvalds 已提交
586 587 588 589

	/* Mandatory power management transition delays */
	/* see PCI PM 1.1 5.6.1 table 18 */
	if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
590
		pci_dev_d3_sleep(dev);
L
Linus Torvalds 已提交
591
	else if (state == PCI_D2 || dev->current_state == PCI_D2)
592
		udelay(PCI_PM_D2_DELAY);
L
Linus Torvalds 已提交
593

594 595 596 597 598
	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
	dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
	if (dev->current_state != state && printk_ratelimit())
		dev_info(&dev->dev, "Refused to change power state, "
			"currently in D%d\n", dev->current_state);
599

600 601
	/*
	 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
602 603 604 605 606 607 608 609 610 611 612 613 614 615
	 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
	 * from D3hot to D0 _may_ perform an internal reset, thereby
	 * going to "D0 Uninitialized" rather than "D0 Initialized".
	 * For example, at least some versions of the 3c905B and the
	 * 3c556B exhibit this behaviour.
	 *
	 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
	 * devices in a D3hot state at boot.  Consequently, we need to
	 * restore at least the BARs so that the device will be
	 * accessible to its driver.
	 */
	if (need_restore)
		pci_restore_bars(dev);

616
	if (dev->bus->self)
S
Shaohua Li 已提交
617 618
		pcie_aspm_pm_state_change(dev->bus->self);

L
Linus Torvalds 已提交
619 620 621
	return 0;
}

622 623 624 625
/**
 * pci_update_current_state - Read PCI power state of given device from its
 *                            PCI PM registers and cache it
 * @dev: PCI device to handle.
626
 * @state: State to cache in case the device doesn't have the PM capability
627
 */
628
void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
629
{
630
	if (dev->pm_cap) {
631 632
		u16 pmcsr;

633 634 635 636 637 638 639 640 641 642
		/*
		 * Configuration space is not accessible for device in
		 * D3cold, so just keep or set D3cold for safety
		 */
		if (dev->current_state == PCI_D3cold)
			return;
		if (state == PCI_D3cold) {
			dev->current_state = PCI_D3cold;
			return;
		}
643
		pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
644
		dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
645 646
	} else {
		dev->current_state = state;
647 648 649
	}
}

650 651 652 653 654 655 656 657 658 659 660 661 662
/**
 * pci_power_up - Put the given device into D0 forcibly
 * @dev: PCI device to power up
 */
void pci_power_up(struct pci_dev *dev)
{
	if (platform_pci_power_manageable(dev))
		platform_pci_set_power_state(dev, PCI_D0);

	pci_raw_set_power_state(dev, PCI_D0);
	pci_update_current_state(dev, PCI_D0);
}

663 664 665 666 667 668 669 670 671 672 673 674 675
/**
 * pci_platform_power_transition - Use platform to change device power state
 * @dev: PCI device to handle.
 * @state: State to put the device into.
 */
static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
{
	int error;

	if (platform_pci_power_manageable(dev)) {
		error = platform_pci_set_power_state(dev, state);
		if (!error)
			pci_update_current_state(dev, state);
676
	} else
677
		error = -ENODEV;
678 679 680

	if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
		dev->current_state = PCI_D0;
681 682 683 684

	return error;
}

685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706
/**
 * pci_wakeup - Wake up a PCI device
 * @pci_dev: Device to handle.
 * @ign: ignored parameter
 */
static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
{
	pci_wakeup_event(pci_dev);
	pm_request_resume(&pci_dev->dev);
	return 0;
}

/**
 * pci_wakeup_bus - Walk given bus and wake up devices on it
 * @bus: Top bus of the subtree to walk.
 */
static void pci_wakeup_bus(struct pci_bus *bus)
{
	if (bus)
		pci_walk_bus(bus, pci_wakeup, NULL);
}

707 708 709 710 711 712 713
/**
 * __pci_start_power_transition - Start power transition of a PCI device
 * @dev: PCI device to handle.
 * @state: State to put the device into.
 */
static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
{
714
	if (state == PCI_D0) {
715
		pci_platform_power_transition(dev, PCI_D0);
716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757
		/*
		 * Mandatory power management transition delays, see
		 * PCI Express Base Specification Revision 2.0 Section
		 * 6.6.1: Conventional Reset.  Do not delay for
		 * devices powered on/off by corresponding bridge,
		 * because have already delayed for the bridge.
		 */
		if (dev->runtime_d3cold) {
			msleep(dev->d3cold_delay);
			/*
			 * When powering on a bridge from D3cold, the
			 * whole hierarchy may be powered on into
			 * D0uninitialized state, resume them to give
			 * them a chance to suspend again
			 */
			pci_wakeup_bus(dev->subordinate);
		}
	}
}

/**
 * __pci_dev_set_current_state - Set current state of a PCI device
 * @dev: Device to handle
 * @data: pointer to state to be set
 */
static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
{
	pci_power_t state = *(pci_power_t *)data;

	dev->current_state = state;
	return 0;
}

/**
 * __pci_bus_set_current_state - Walk given bus and set current state of devices
 * @bus: Top bus of the subtree to walk.
 * @state: state to be set
 */
static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
{
	if (bus)
		pci_walk_bus(bus, __pci_dev_set_current_state, &state);
758 759 760 761 762 763 764 765 766 767 768
}

/**
 * __pci_complete_power_transition - Complete power transition of a PCI device
 * @dev: PCI device to handle.
 * @state: State to put the device into.
 *
 * This function should not be called directly by device drivers.
 */
int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
{
769 770
	int ret;

771
	if (state <= PCI_D0)
772 773 774 775 776 777
		return -EINVAL;
	ret = pci_platform_power_transition(dev, state);
	/* Power off the bridge may power off the whole hierarchy */
	if (!ret && state == PCI_D3cold)
		__pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
	return ret;
778 779 780
}
EXPORT_SYMBOL_GPL(__pci_complete_power_transition);

781 782 783 784 785
/**
 * pci_set_power_state - Set the power state of a PCI device
 * @dev: PCI device to handle.
 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
 *
786
 * Transition a device to a new power state, using the platform firmware and/or
787 788 789 790 791 792 793 794 795 796 797
 * the device's PCI PM registers.
 *
 * RETURN VALUE:
 * -EINVAL if the requested state is invalid.
 * -EIO if device does not support PCI PM or its PM capabilities register has a
 * wrong version, or device doesn't support the requested state.
 * 0 if device already is in the requested state.
 * 0 if device's power state has been successfully changed.
 */
int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
{
798
	int error;
799 800

	/* bound the state we're entering */
801 802
	if (state > PCI_D3cold)
		state = PCI_D3cold;
803 804 805 806 807 808 809 810 811 812
	else if (state < PCI_D0)
		state = PCI_D0;
	else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
		/*
		 * If the device or the parent bridge do not support PCI PM,
		 * ignore the request if we're doing anything other than putting
		 * it into D0 (which would only happen on boot).
		 */
		return 0;

813 814 815 816
	/* Check if we're already there */
	if (dev->current_state == state)
		return 0;

817 818
	__pci_start_power_transition(dev, state);

819 820
	/* This device is quirked not to be put into D3, so
	   don't put it in D3 */
821
	if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
822
		return 0;
823

824 825 826 827 828 829
	/*
	 * To put device in D3cold, we put device into D3hot in native
	 * way, then put device into D3cold with platform ops
	 */
	error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
					PCI_D3hot : state);
830

831 832
	if (!__pci_complete_power_transition(dev, state))
		error = 0;
833 834 835 836 837 838
	/*
	 * When aspm_policy is "powersave" this call ensures
	 * that ASPM is configured.
	 */
	if (!error && dev->bus->self)
		pcie_aspm_powersave_config_link(dev->bus->self);
839 840 841 842

	return error;
}

L
Linus Torvalds 已提交
843 844 845 846 847 848 849 850 851 852 853 854
/**
 * pci_choose_state - Choose the power state of a PCI device
 * @dev: PCI device to be suspended
 * @state: target sleep state for the whole system. This is the value
 *	that is passed to suspend() function.
 *
 * Returns PCI power state suitable for given device and given system
 * message.
 */

pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
{
855
	pci_power_t ret;
856

857
	if (!dev->pm_cap)
L
Linus Torvalds 已提交
858 859
		return PCI_D0;

860 861 862
	ret = platform_pci_choose_state(dev);
	if (ret != PCI_POWER_ERROR)
		return ret;
863 864 865 866 867

	switch (state.event) {
	case PM_EVENT_ON:
		return PCI_D0;
	case PM_EVENT_FREEZE:
868 869
	case PM_EVENT_PRETHAW:
		/* REVISIT both freeze and pre-thaw "should" use D0 */
870
	case PM_EVENT_SUSPEND:
871
	case PM_EVENT_HIBERNATE:
872
		return PCI_D3hot;
L
Linus Torvalds 已提交
873
	default:
874 875
		dev_info(&dev->dev, "unrecognized suspend event %d\n",
			 state.event);
L
Linus Torvalds 已提交
876 877 878 879 880 881 882
		BUG();
	}
	return PCI_D0;
}

EXPORT_SYMBOL(pci_choose_state);

883 884
#define PCI_EXP_SAVE_REGS	7

885

886 887
static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
						       u16 cap, bool extended)
888 889 890
{
	struct pci_cap_saved_state *tmp;

891
	hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
892
		if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
893 894 895 896 897
			return tmp;
	}
	return NULL;
}

898 899 900 901 902 903 904 905 906 907
struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
{
	return _pci_find_saved_cap(dev, cap, false);
}

struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
{
	return _pci_find_saved_cap(dev, cap, true);
}

908 909
static int pci_save_pcie_state(struct pci_dev *dev)
{
910
	int i = 0;
911 912 913
	struct pci_cap_saved_state *save_state;
	u16 *cap;

914
	if (!pci_is_pcie(dev))
915 916
		return 0;

917
	save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
918
	if (!save_state) {
919
		dev_err(&dev->dev, "buffer not found in %s\n", __func__);
920 921
		return -ENOMEM;
	}
922

923 924 925 926 927 928 929 930
	cap = (u16 *)&save_state->cap.data[0];
	pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
	pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
	pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
	pcie_capability_read_word(dev, PCI_EXP_RTCTL,  &cap[i++]);
	pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
	pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
	pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
931

932 933 934 935 936
	return 0;
}

static void pci_restore_pcie_state(struct pci_dev *dev)
{
937
	int i = 0;
938 939 940 941
	struct pci_cap_saved_state *save_state;
	u16 *cap;

	save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
942
	if (!save_state)
943 944
		return;

945 946 947 948 949 950 951 952
	cap = (u16 *)&save_state->cap.data[0];
	pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
	pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
	pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
	pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
	pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
	pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
	pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
953 954
}

S
Stephen Hemminger 已提交
955 956 957

static int pci_save_pcix_state(struct pci_dev *dev)
{
958
	int pos;
S
Stephen Hemminger 已提交
959 960 961 962 963 964
	struct pci_cap_saved_state *save_state;

	pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
	if (pos <= 0)
		return 0;

965
	save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
S
Stephen Hemminger 已提交
966
	if (!save_state) {
967
		dev_err(&dev->dev, "buffer not found in %s\n", __func__);
S
Stephen Hemminger 已提交
968 969 970
		return -ENOMEM;
	}

971 972
	pci_read_config_word(dev, pos + PCI_X_CMD,
			     (u16 *)save_state->cap.data);
973

S
Stephen Hemminger 已提交
974 975 976 977 978 979 980 981 982 983 984 985 986
	return 0;
}

static void pci_restore_pcix_state(struct pci_dev *dev)
{
	int i = 0, pos;
	struct pci_cap_saved_state *save_state;
	u16 *cap;

	save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
	pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
	if (!save_state || pos <= 0)
		return;
987
	cap = (u16 *)&save_state->cap.data[0];
S
Stephen Hemminger 已提交
988 989 990 991 992

	pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
}


L
Linus Torvalds 已提交
993 994 995 996 997 998 999 1000 1001 1002
/**
 * pci_save_state - save the PCI configuration space of a device before suspending
 * @dev: - PCI device that we're dealing with
 */
int
pci_save_state(struct pci_dev *dev)
{
	int i;
	/* XXX: 100% dword access ok here? */
	for (i = 0; i < 16; i++)
1003
		pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1004
	dev->state_saved = true;
1005 1006
	if ((i = pci_save_pcie_state(dev)) != 0)
		return i;
S
Stephen Hemminger 已提交
1007 1008
	if ((i = pci_save_pcix_state(dev)) != 0)
		return i;
1009 1010
	if ((i = pci_save_vc_state(dev)) != 0)
		return i;
L
Linus Torvalds 已提交
1011 1012 1013
	return 0;
}

1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037
static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
				     u32 saved_val, int retry)
{
	u32 val;

	pci_read_config_dword(pdev, offset, &val);
	if (val == saved_val)
		return;

	for (;;) {
		dev_dbg(&pdev->dev, "restoring config space at offset "
			"%#x (was %#x, writing %#x)\n", offset, val, saved_val);
		pci_write_config_dword(pdev, offset, saved_val);
		if (retry-- <= 0)
			return;

		pci_read_config_dword(pdev, offset, &val);
		if (val == saved_val)
			return;

		mdelay(1);
	}
}

1038 1039
static void pci_restore_config_space_range(struct pci_dev *pdev,
					   int start, int end, int retry)
1040 1041 1042 1043 1044 1045 1046 1047 1048
{
	int index;

	for (index = end; index >= start; index--)
		pci_restore_config_dword(pdev, 4 * index,
					 pdev->saved_config_space[index],
					 retry);
}

1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060
static void pci_restore_config_space(struct pci_dev *pdev)
{
	if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
		pci_restore_config_space_range(pdev, 10, 15, 0);
		/* Restore BARs before the command register. */
		pci_restore_config_space_range(pdev, 4, 9, 10);
		pci_restore_config_space_range(pdev, 0, 3, 0);
	} else {
		pci_restore_config_space_range(pdev, 0, 15, 0);
	}
}

1061
/**
L
Linus Torvalds 已提交
1062 1063 1064
 * pci_restore_state - Restore the saved state of a PCI device
 * @dev: - PCI device that we're dealing with
 */
1065
void pci_restore_state(struct pci_dev *dev)
L
Linus Torvalds 已提交
1066
{
A
Alek Du 已提交
1067
	if (!dev->state_saved)
1068
		return;
1069

1070 1071
	/* PCI Express register must be restored first */
	pci_restore_pcie_state(dev);
1072
	pci_restore_ats_state(dev);
1073
	pci_restore_vc_state(dev);
1074

1075
	pci_restore_config_space(dev);
1076

S
Stephen Hemminger 已提交
1077
	pci_restore_pcix_state(dev);
1078
	pci_restore_msi_state(dev);
Y
Yu Zhao 已提交
1079
	pci_restore_iov_state(dev);
1080

1081
	dev->state_saved = false;
L
Linus Torvalds 已提交
1082 1083
}

1084 1085 1086 1087 1088 1089 1090 1091 1092 1093
struct pci_saved_state {
	u32 config_space[16];
	struct pci_cap_saved_data cap[0];
};

/**
 * pci_store_saved_state - Allocate and return an opaque struct containing
 *			   the device saved state.
 * @dev: PCI device that we're dealing with
 *
1094
 * Return NULL if no state or error.
1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107
 */
struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
{
	struct pci_saved_state *state;
	struct pci_cap_saved_state *tmp;
	struct pci_cap_saved_data *cap;
	size_t size;

	if (!dev->state_saved)
		return NULL;

	size = sizeof(*state) + sizeof(struct pci_cap_saved_data);

1108
	hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1109 1110 1111 1112 1113 1114 1115 1116 1117 1118
		size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;

	state = kzalloc(size, GFP_KERNEL);
	if (!state)
		return NULL;

	memcpy(state->config_space, dev->saved_config_space,
	       sizeof(state->config_space));

	cap = state->cap;
1119
	hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134
		size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
		memcpy(cap, &tmp->cap, len);
		cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
	}
	/* Empty cap_save terminates list */

	return state;
}
EXPORT_SYMBOL_GPL(pci_store_saved_state);

/**
 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
 * @dev: PCI device that we're dealing with
 * @state: Saved state returned from pci_store_saved_state()
 */
1135 1136
static int pci_load_saved_state(struct pci_dev *dev,
				struct pci_saved_state *state)
1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151
{
	struct pci_cap_saved_data *cap;

	dev->state_saved = false;

	if (!state)
		return 0;

	memcpy(dev->saved_config_space, state->config_space,
	       sizeof(state->config_space));

	cap = state->cap;
	while (cap->size) {
		struct pci_cap_saved_state *tmp;

1152
		tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180
		if (!tmp || tmp->cap.size != cap->size)
			return -EINVAL;

		memcpy(tmp->cap.data, cap->data, tmp->cap.size);
		cap = (struct pci_cap_saved_data *)((u8 *)cap +
		       sizeof(struct pci_cap_saved_data) + cap->size);
	}

	dev->state_saved = true;
	return 0;
}

/**
 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
 *				   and free the memory allocated for it.
 * @dev: PCI device that we're dealing with
 * @state: Pointer to saved state returned from pci_store_saved_state()
 */
int pci_load_and_free_saved_state(struct pci_dev *dev,
				  struct pci_saved_state **state)
{
	int ret = pci_load_saved_state(dev, *state);
	kfree(*state);
	*state = NULL;
	return ret;
}
EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);

1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196
static int do_pci_enable_device(struct pci_dev *dev, int bars)
{
	int err;

	err = pci_set_power_state(dev, PCI_D0);
	if (err < 0 && err != -EIO)
		return err;
	err = pcibios_enable_device(dev, bars);
	if (err < 0)
		return err;
	pci_fixup_device(pci_fixup_enable, dev);

	return 0;
}

/**
1197
 * pci_reenable_device - Resume abandoned device
1198 1199 1200 1201 1202
 * @dev: PCI device to be resumed
 *
 *  Note this function is a backend of pci_default_resume and is not supposed
 *  to be called by normal code, write proper resume handler and use it instead.
 */
1203
int pci_reenable_device(struct pci_dev *dev)
1204
{
1205
	if (pci_is_enabled(dev))
1206 1207 1208 1209
		return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
	return 0;
}

1210 1211
static void pci_enable_bridge(struct pci_dev *dev)
{
1212
	struct pci_dev *bridge;
1213 1214
	int retval;

1215 1216 1217
	bridge = pci_upstream_bridge(dev);
	if (bridge)
		pci_enable_bridge(bridge);
1218

1219
	if (pci_is_enabled(dev)) {
1220
		if (!dev->is_busmaster)
1221
			pci_set_master(dev);
1222
		return;
1223 1224
	}

1225 1226 1227 1228 1229 1230 1231
	retval = pci_enable_device(dev);
	if (retval)
		dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
			retval);
	pci_set_master(dev);
}

1232
static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
L
Linus Torvalds 已提交
1233
{
1234
	struct pci_dev *bridge;
L
Linus Torvalds 已提交
1235
	int err;
1236
	int i, bars = 0;
L
Linus Torvalds 已提交
1237

1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249
	/*
	 * Power state could be unknown at this point, either due to a fresh
	 * boot or a device removal call.  So get the current power state
	 * so that things like MSI message writing will behave as expected
	 * (e.g. if the device really is in D0 at enable time).
	 */
	if (dev->pm_cap) {
		u16 pmcsr;
		pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
		dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
	}

1250
	if (atomic_inc_return(&dev->enable_cnt) > 1)
1251 1252
		return 0;		/* already enabled */

1253 1254 1255
	bridge = pci_upstream_bridge(dev);
	if (bridge)
		pci_enable_bridge(bridge);
1256

1257 1258 1259 1260 1261
	/* only skip sriov related */
	for (i = 0; i <= PCI_ROM_RESOURCE; i++)
		if (dev->resource[i].flags & flags)
			bars |= (1 << i);
	for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1262 1263 1264
		if (dev->resource[i].flags & flags)
			bars |= (1 << i);

1265
	err = do_pci_enable_device(dev, bars);
1266
	if (err < 0)
1267
		atomic_dec(&dev->enable_cnt);
1268
	return err;
L
Linus Torvalds 已提交
1269 1270
}

1271 1272 1273 1274 1275 1276 1277 1278 1279 1280
/**
 * pci_enable_device_io - Initialize a device for use with IO space
 * @dev: PCI device to be initialized
 *
 *  Initialize device before it's used by a driver. Ask low-level code
 *  to enable I/O resources. Wake up the device if it was suspended.
 *  Beware, this function can fail.
 */
int pci_enable_device_io(struct pci_dev *dev)
{
1281
	return pci_enable_device_flags(dev, IORESOURCE_IO);
1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293
}

/**
 * pci_enable_device_mem - Initialize a device for use with Memory space
 * @dev: PCI device to be initialized
 *
 *  Initialize device before it's used by a driver. Ask low-level code
 *  to enable Memory resources. Wake up the device if it was suspended.
 *  Beware, this function can fail.
 */
int pci_enable_device_mem(struct pci_dev *dev)
{
1294
	return pci_enable_device_flags(dev, IORESOURCE_MEM);
1295 1296
}

1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309
/**
 * pci_enable_device - Initialize device before it's used by a driver.
 * @dev: PCI device to be initialized
 *
 *  Initialize device before it's used by a driver. Ask low-level code
 *  to enable I/O and memory. Wake up the device if it was suspended.
 *  Beware, this function can fail.
 *
 *  Note we don't actually enable the device many times if we call
 *  this function repeatedly (we just increment the count).
 */
int pci_enable_device(struct pci_dev *dev)
{
1310
	return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1311 1312
}

T
Tejun Heo 已提交
1313 1314 1315 1316 1317 1318 1319
/*
 * Managed PCI resources.  This manages device on/off, intx/msi/msix
 * on/off and BAR regions.  pci_dev itself records msi/msix status, so
 * there's no need to track it separately.  pci_devres is initialized
 * when a device is enabled using managed PCI device enable interface.
 */
struct pci_devres {
1320 1321
	unsigned int enabled:1;
	unsigned int pinned:1;
T
Tejun Heo 已提交
1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344
	unsigned int orig_intx:1;
	unsigned int restore_intx:1;
	u32 region_mask;
};

static void pcim_release(struct device *gendev, void *res)
{
	struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
	struct pci_devres *this = res;
	int i;

	if (dev->msi_enabled)
		pci_disable_msi(dev);
	if (dev->msix_enabled)
		pci_disable_msix(dev);

	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
		if (this->region_mask & (1 << i))
			pci_release_region(dev, i);

	if (this->restore_intx)
		pci_intx(dev, this->orig_intx);

1345
	if (this->enabled && !this->pinned)
T
Tejun Heo 已提交
1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383
		pci_disable_device(dev);
}

static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
{
	struct pci_devres *dr, *new_dr;

	dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
	if (dr)
		return dr;

	new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
	if (!new_dr)
		return NULL;
	return devres_get(&pdev->dev, new_dr, NULL, NULL);
}

static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
{
	if (pci_is_managed(pdev))
		return devres_find(&pdev->dev, pcim_release, NULL, NULL);
	return NULL;
}

/**
 * pcim_enable_device - Managed pci_enable_device()
 * @pdev: PCI device to be initialized
 *
 * Managed pci_enable_device().
 */
int pcim_enable_device(struct pci_dev *pdev)
{
	struct pci_devres *dr;
	int rc;

	dr = get_pci_dr(pdev);
	if (unlikely(!dr))
		return -ENOMEM;
1384 1385
	if (dr->enabled)
		return 0;
T
Tejun Heo 已提交
1386 1387 1388 1389

	rc = pci_enable_device(pdev);
	if (!rc) {
		pdev->is_managed = 1;
1390
		dr->enabled = 1;
T
Tejun Heo 已提交
1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407
	}
	return rc;
}

/**
 * pcim_pin_device - Pin managed PCI device
 * @pdev: PCI device to pin
 *
 * Pin managed PCI device @pdev.  Pinned device won't be disabled on
 * driver detach.  @pdev must have been enabled with
 * pcim_enable_device().
 */
void pcim_pin_device(struct pci_dev *pdev)
{
	struct pci_devres *dr;

	dr = find_pci_dr(pdev);
1408
	WARN_ON(!dr || !dr->enabled);
T
Tejun Heo 已提交
1409
	if (dr)
1410
		dr->pinned = 1;
T
Tejun Heo 已提交
1411 1412
}

M
Matthew Garrett 已提交
1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425
/*
 * pcibios_add_device - provide arch specific hooks when adding device dev
 * @dev: the PCI device being added
 *
 * Permits the platform to provide architecture specific functionality when
 * devices are added. This is the default implementation. Architecture
 * implementations can override this.
 */
int __weak pcibios_add_device (struct pci_dev *dev)
{
	return 0;
}

1426 1427 1428 1429 1430 1431 1432 1433 1434 1435
/**
 * pcibios_release_device - provide arch specific hooks when releasing device dev
 * @dev: the PCI device being released
 *
 * Permits the platform to provide architecture specific functionality when
 * devices are released. This is the default implementation. Architecture
 * implementations can override this.
 */
void __weak pcibios_release_device(struct pci_dev *dev) {}

L
Linus Torvalds 已提交
1436 1437 1438 1439 1440 1441 1442 1443
/**
 * pcibios_disable_device - disable arch specific PCI resources for device dev
 * @dev: the PCI device to disable
 *
 * Disables architecture specific PCI resources for the device. This
 * is the default implementation. Architecture implementations can
 * override this.
 */
B
Bjorn Helgaas 已提交
1444
void __weak pcibios_disable_device (struct pci_dev *dev) {}
L
Linus Torvalds 已提交
1445

1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467
static void do_pci_disable_device(struct pci_dev *dev)
{
	u16 pci_command;

	pci_read_config_word(dev, PCI_COMMAND, &pci_command);
	if (pci_command & PCI_COMMAND_MASTER) {
		pci_command &= ~PCI_COMMAND_MASTER;
		pci_write_config_word(dev, PCI_COMMAND, pci_command);
	}

	pcibios_disable_device(dev);
}

/**
 * pci_disable_enabled_device - Disable device without updating enable_cnt
 * @dev: PCI device to disable
 *
 * NOTE: This function is a backend of PCI power management routines and is
 * not supposed to be called drivers.
 */
void pci_disable_enabled_device(struct pci_dev *dev)
{
1468
	if (pci_is_enabled(dev))
1469 1470 1471
		do_pci_disable_device(dev);
}

L
Linus Torvalds 已提交
1472 1473 1474 1475 1476 1477
/**
 * pci_disable_device - Disable PCI device after use
 * @dev: PCI device to be disabled
 *
 * Signal to the system that the PCI device is not in use by the system
 * anymore.  This only involves disabling PCI bus-mastering, if active.
1478 1479
 *
 * Note we don't actually disable the device until all callers of
1480
 * pci_enable_device() have called pci_disable_device().
L
Linus Torvalds 已提交
1481 1482 1483 1484
 */
void
pci_disable_device(struct pci_dev *dev)
{
T
Tejun Heo 已提交
1485
	struct pci_devres *dr;
1486

T
Tejun Heo 已提交
1487 1488
	dr = find_pci_dr(dev);
	if (dr)
1489
		dr->enabled = 0;
T
Tejun Heo 已提交
1490

1491 1492 1493
	dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
		      "disabling already-disabled device");

1494
	if (atomic_dec_return(&dev->enable_cnt) != 0)
1495 1496
		return;

1497
	do_pci_disable_device(dev);
L
Linus Torvalds 已提交
1498

1499
	dev->is_busmaster = 0;
L
Linus Torvalds 已提交
1500 1501
}

B
Brian King 已提交
1502 1503
/**
 * pcibios_set_pcie_reset_state - set reset state for device dev
1504
 * @dev: the PCIe device reset
B
Brian King 已提交
1505 1506 1507
 * @state: Reset state to enter into
 *
 *
1508
 * Sets the PCIe reset state for the device. This is the default
B
Brian King 已提交
1509 1510
 * implementation. Architecture implementations can override this.
 */
B
Bjorn Helgaas 已提交
1511 1512
int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
					enum pcie_reset_state state)
B
Brian King 已提交
1513 1514 1515 1516 1517 1518
{
	return -EINVAL;
}

/**
 * pci_set_pcie_reset_state - set reset state for device dev
1519
 * @dev: the PCIe device reset
B
Brian King 已提交
1520 1521 1522 1523 1524 1525 1526 1527 1528 1529
 * @state: Reset state to enter into
 *
 *
 * Sets the PCI reset state for the device.
 */
int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
{
	return pcibios_set_pcie_reset_state(dev, state);
}

1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564
/**
 * pci_check_pme_status - Check if given device has generated PME.
 * @dev: Device to check.
 *
 * Check the PME status of the device and if set, clear it and clear PME enable
 * (if set).  Return 'true' if PME status and PME enable were both set or
 * 'false' otherwise.
 */
bool pci_check_pme_status(struct pci_dev *dev)
{
	int pmcsr_pos;
	u16 pmcsr;
	bool ret = false;

	if (!dev->pm_cap)
		return false;

	pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
	pci_read_config_word(dev, pmcsr_pos, &pmcsr);
	if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
		return false;

	/* Clear PME status. */
	pmcsr |= PCI_PM_CTRL_PME_STATUS;
	if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
		/* Disable PME to avoid interrupt flood. */
		pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
		ret = true;
	}

	pci_write_config_word(dev, pmcsr_pos, pmcsr);

	return ret;
}

1565 1566 1567
/**
 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
 * @dev: Device to handle.
1568
 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1569 1570 1571 1572
 *
 * Check if @dev has generated PME and queue a resume request for it in that
 * case.
 */
1573
static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1574
{
1575 1576 1577
	if (pme_poll_reset && dev->pme_poll)
		dev->pme_poll = false;

1578 1579
	if (pci_check_pme_status(dev)) {
		pci_wakeup_event(dev);
1580
		pm_request_resume(&dev->dev);
1581
	}
1582 1583 1584 1585 1586 1587 1588 1589 1590 1591
	return 0;
}

/**
 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
 * @bus: Top bus of the subtree to walk.
 */
void pci_pme_wakeup_bus(struct pci_bus *bus)
{
	if (bus)
1592
		pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1593 1594
}

1595

1596 1597 1598 1599 1600
/**
 * pci_pme_capable - check the capability of PCI device to generate PME#
 * @dev: PCI device to handle.
 * @state: PCI state from which device will issue PME#.
 */
1601
bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1602
{
1603
	if (!dev->pm_cap)
1604 1605
		return false;

1606
	return !!(dev->pme_support & (1 << state));
1607 1608
}

1609 1610
static void pci_pme_list_scan(struct work_struct *work)
{
1611
	struct pci_pme_device *pme_dev, *n;
1612 1613 1614

	mutex_lock(&pci_pme_list_mutex);
	if (!list_empty(&pci_pme_list)) {
1615 1616
		list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
			if (pme_dev->dev->pme_poll) {
1617 1618 1619 1620 1621 1622 1623 1624 1625 1626
				struct pci_dev *bridge;

				bridge = pme_dev->dev->bus->self;
				/*
				 * If bridge is in low power state, the
				 * configuration space of subordinate devices
				 * may be not accessible
				 */
				if (bridge && bridge->current_state != PCI_D0)
					continue;
1627 1628 1629 1630 1631 1632 1633 1634 1635
				pci_pme_wakeup(pme_dev->dev, NULL);
			} else {
				list_del(&pme_dev->list);
				kfree(pme_dev);
			}
		}
		if (!list_empty(&pci_pme_list))
			schedule_delayed_work(&pci_pme_work,
					      msecs_to_jiffies(PME_TIMEOUT));
1636 1637 1638 1639
	}
	mutex_unlock(&pci_pme_list_mutex);
}

1640 1641 1642 1643 1644 1645 1646 1647
/**
 * pci_pme_active - enable or disable PCI device's PME# function
 * @dev: PCI device to handle.
 * @enable: 'true' to enable PME# generation; 'false' to disable it.
 *
 * The caller must verify that the device is capable of generating PME# before
 * calling this function with @enable equal to 'true'.
 */
1648
void pci_pme_active(struct pci_dev *dev, bool enable)
1649 1650 1651
{
	u16 pmcsr;

1652
	if (!dev->pme_support)
1653 1654
		return;

1655
	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1656 1657 1658 1659 1660
	/* Clear PME_Status by writing 1 to it and enable PME# */
	pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
	if (!enable)
		pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;

1661
	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1662

1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681
	/*
	 * PCI (as opposed to PCIe) PME requires that the device have
	 * its PME# line hooked up correctly. Not all hardware vendors
	 * do this, so the PME never gets delivered and the device
	 * remains asleep. The easiest way around this is to
	 * periodically walk the list of suspended devices and check
	 * whether any have their PME flag set. The assumption is that
	 * we'll wake up often enough anyway that this won't be a huge
	 * hit, and the power savings from the devices will still be a
	 * win.
	 *
	 * Although PCIe uses in-band PME message instead of PME# line
	 * to report PME, PME does not work for some PCIe devices in
	 * reality.  For example, there are devices that set their PME
	 * status bits, but don't really bother to send a PME message;
	 * there are PCI Express Root Ports that don't bother to
	 * trigger interrupts when they receive PME messages from the
	 * devices below.  So PME poll is used for PCIe devices too.
	 */
1682

1683
	if (dev->pme_poll) {
1684 1685 1686 1687
		struct pci_pme_device *pme_dev;
		if (enable) {
			pme_dev = kmalloc(sizeof(struct pci_pme_device),
					  GFP_KERNEL);
1688 1689 1690 1691
			if (!pme_dev) {
				dev_warn(&dev->dev, "can't enable PME#\n");
				return;
			}
1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711
			pme_dev->dev = dev;
			mutex_lock(&pci_pme_list_mutex);
			list_add(&pme_dev->list, &pci_pme_list);
			if (list_is_singular(&pci_pme_list))
				schedule_delayed_work(&pci_pme_work,
						      msecs_to_jiffies(PME_TIMEOUT));
			mutex_unlock(&pci_pme_list_mutex);
		} else {
			mutex_lock(&pci_pme_list_mutex);
			list_for_each_entry(pme_dev, &pci_pme_list, list) {
				if (pme_dev->dev == dev) {
					list_del(&pme_dev->list);
					kfree(pme_dev);
					break;
				}
			}
			mutex_unlock(&pci_pme_list_mutex);
		}
	}

1712
	dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1713 1714
}

L
Linus Torvalds 已提交
1715
/**
1716
 * __pci_enable_wake - enable PCI device as wakeup event source
1717 1718
 * @dev: PCI device affected
 * @state: PCI state from which device will issue wakeup events
1719
 * @runtime: True if the events are to be generated at run time
1720 1721 1722 1723 1724 1725 1726
 * @enable: True to enable event generation; false to disable
 *
 * This enables the device as a wakeup event source, or disables it.
 * When such events involves platform-specific hooks, those hooks are
 * called automatically by this routine.
 *
 * Devices with legacy power management (no standard PCI PM capabilities)
1727
 * always require such platform hooks.
1728
 *
1729 1730 1731 1732 1733
 * RETURN VALUE:
 * 0 is returned on success
 * -EINVAL is returned if device is not supposed to wake up the system
 * Error code depending on the platform is returned if both the platform and
 * the native mechanism fail to enable the generation of wake-up events
L
Linus Torvalds 已提交
1734
 */
1735 1736
int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
		      bool runtime, bool enable)
L
Linus Torvalds 已提交
1737
{
1738
	int ret = 0;
1739

1740
	if (enable && !runtime && !device_may_wakeup(&dev->dev))
1741
		return -EINVAL;
L
Linus Torvalds 已提交
1742

1743 1744 1745 1746
	/* Don't do the same thing twice in a row for one device. */
	if (!!enable == !!dev->wakeup_prepared)
		return 0;

1747 1748 1749 1750
	/*
	 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
	 * Anderson we should be doing PME# wake enable followed by ACPI wake
	 * enable.  To disable wake-up we call the platform first, for symmetry.
1751
	 */
L
Linus Torvalds 已提交
1752

1753 1754
	if (enable) {
		int error;
L
Linus Torvalds 已提交
1755

1756 1757 1758 1759
		if (pci_pme_capable(dev, state))
			pci_pme_active(dev, true);
		else
			ret = 1;
1760 1761
		error = runtime ? platform_pci_run_wake(dev, true) :
					platform_pci_sleep_wake(dev, true);
1762 1763
		if (ret)
			ret = error;
1764 1765
		if (!ret)
			dev->wakeup_prepared = true;
1766
	} else {
1767 1768 1769 1770
		if (runtime)
			platform_pci_run_wake(dev, false);
		else
			platform_pci_sleep_wake(dev, false);
1771
		pci_pme_active(dev, false);
1772
		dev->wakeup_prepared = false;
1773
	}
L
Linus Torvalds 已提交
1774

1775
	return ret;
1776
}
1777
EXPORT_SYMBOL(__pci_enable_wake);
L
Linus Torvalds 已提交
1778

1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799
/**
 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
 * @dev: PCI device to prepare
 * @enable: True to enable wake-up event generation; false to disable
 *
 * Many drivers want the device to wake up the system from D3_hot or D3_cold
 * and this function allows them to set that up cleanly - pci_enable_wake()
 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
 * ordering constraints.
 *
 * This function only returns error code if the device is not capable of
 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
 * enable wake-up power for it.
 */
int pci_wake_from_d3(struct pci_dev *dev, bool enable)
{
	return pci_pme_capable(dev, PCI_D3cold) ?
			pci_enable_wake(dev, PCI_D3cold, enable) :
			pci_enable_wake(dev, PCI_D3hot, enable);
}

1800
/**
J
Jesse Barnes 已提交
1801 1802 1803 1804 1805 1806
 * pci_target_state - find an appropriate low power state for a given PCI dev
 * @dev: PCI device
 *
 * Use underlying platform code to find a supported low power state for @dev.
 * If the platform can't manage @dev, return the deepest state from which it
 * can generate wake events, based on any available PME info.
1807
 */
1808
static pci_power_t pci_target_state(struct pci_dev *dev)
1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829
{
	pci_power_t target_state = PCI_D3hot;

	if (platform_pci_power_manageable(dev)) {
		/*
		 * Call the platform to choose the target state of the device
		 * and enable wake-up from this state if supported.
		 */
		pci_power_t state = platform_pci_choose_state(dev);

		switch (state) {
		case PCI_POWER_ERROR:
		case PCI_UNKNOWN:
			break;
		case PCI_D1:
		case PCI_D2:
			if (pci_no_d1d2(dev))
				break;
		default:
			target_state = state;
		}
1830 1831
	} else if (!dev->pm_cap) {
		target_state = PCI_D0;
1832 1833 1834 1835 1836 1837
	} else if (device_may_wakeup(&dev->dev)) {
		/*
		 * Find the deepest state from which the device can generate
		 * wake-up events, make it the target state and enable device
		 * to generate PME#.
		 */
1838 1839 1840 1841
		if (dev->pme_support) {
			while (target_state
			      && !(dev->pme_support & (1 << target_state)))
				target_state--;
1842 1843 1844
		}
	}

1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863
	return target_state;
}

/**
 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
 * @dev: Device to handle.
 *
 * Choose the power state appropriate for the device depending on whether
 * it can wake up the system and/or is power manageable by the platform
 * (PCI_D3hot is the default) and put the device into that state.
 */
int pci_prepare_to_sleep(struct pci_dev *dev)
{
	pci_power_t target_state = pci_target_state(dev);
	int error;

	if (target_state == PCI_POWER_ERROR)
		return -EIO;

1864 1865 1866 1867
	/* D3cold during system suspend/hibernate is not supported */
	if (target_state > PCI_D3hot)
		target_state = PCI_D3hot;

1868
	pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1869

1870 1871 1872 1873 1874 1875 1876 1877 1878
	error = pci_set_power_state(dev, target_state);

	if (error)
		pci_enable_wake(dev, target_state, false);

	return error;
}

/**
R
Randy Dunlap 已提交
1879
 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1880 1881
 * @dev: Device to handle.
 *
T
Thomas Weber 已提交
1882
 * Disable device's system wake-up capability and put it into D0.
1883 1884 1885 1886 1887 1888 1889
 */
int pci_back_from_sleep(struct pci_dev *dev)
{
	pci_enable_wake(dev, PCI_D0, false);
	return pci_set_power_state(dev, PCI_D0);
}

1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904
/**
 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
 * @dev: PCI device being suspended.
 *
 * Prepare @dev to generate wake-up events at run time and put it into a low
 * power state.
 */
int pci_finish_runtime_suspend(struct pci_dev *dev)
{
	pci_power_t target_state = pci_target_state(dev);
	int error;

	if (target_state == PCI_POWER_ERROR)
		return -EIO;

1905 1906
	dev->runtime_d3cold = target_state == PCI_D3cold;

1907 1908 1909 1910
	__pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));

	error = pci_set_power_state(dev, target_state);

1911
	if (error) {
1912
		__pci_enable_wake(dev, target_state, true, false);
1913 1914
		dev->runtime_d3cold = false;
	}
1915 1916 1917 1918

	return error;
}

1919 1920 1921 1922
/**
 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
 * @dev: Device to check.
 *
1923
 * Return true if the device itself is capable of generating wake-up events
1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953
 * (through the platform or using the native PCIe PME) or if the device supports
 * PME and one of its upstream bridges can generate wake-up events.
 */
bool pci_dev_run_wake(struct pci_dev *dev)
{
	struct pci_bus *bus = dev->bus;

	if (device_run_wake(&dev->dev))
		return true;

	if (!dev->pme_support)
		return false;

	while (bus->parent) {
		struct pci_dev *bridge = bus->self;

		if (device_run_wake(&bridge->dev))
			return true;

		bus = bus->parent;
	}

	/* We have reached the root bus. */
	if (bus->bridge)
		return device_run_wake(bus->bridge);

	return false;
}
EXPORT_SYMBOL_GPL(pci_dev_run_wake);

1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985
void pci_config_pm_runtime_get(struct pci_dev *pdev)
{
	struct device *dev = &pdev->dev;
	struct device *parent = dev->parent;

	if (parent)
		pm_runtime_get_sync(parent);
	pm_runtime_get_noresume(dev);
	/*
	 * pdev->current_state is set to PCI_D3cold during suspending,
	 * so wait until suspending completes
	 */
	pm_runtime_barrier(dev);
	/*
	 * Only need to resume devices in D3cold, because config
	 * registers are still accessible for devices suspended but
	 * not in D3cold.
	 */
	if (pdev->current_state == PCI_D3cold)
		pm_runtime_resume(dev);
}

void pci_config_pm_runtime_put(struct pci_dev *pdev)
{
	struct device *dev = &pdev->dev;
	struct device *parent = dev->parent;

	pm_runtime_put(dev);
	if (parent)
		pm_runtime_put_sync(parent);
}

1986 1987 1988 1989 1990 1991 1992 1993
/**
 * pci_pm_init - Initialize PM functions of given PCI device
 * @dev: PCI device to handle.
 */
void pci_pm_init(struct pci_dev *dev)
{
	int pm;
	u16 pmc;
L
Linus Torvalds 已提交
1994

1995
	pm_runtime_forbid(&dev->dev);
1996 1997
	pm_runtime_set_active(&dev->dev);
	pm_runtime_enable(&dev->dev);
1998
	device_enable_async_suspend(&dev->dev);
1999
	dev->wakeup_prepared = false;
2000

2001
	dev->pm_cap = 0;
2002
	dev->pme_support = 0;
2003

2004 2005 2006
	/* find PCI PM capability in list */
	pm = pci_find_capability(dev, PCI_CAP_ID_PM);
	if (!pm)
2007
		return;
2008 2009
	/* Check device's ability to generate PME# */
	pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2010

2011 2012 2013
	if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
		dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
			pmc & PCI_PM_CAP_VER_MASK);
2014
		return;
2015 2016
	}

2017
	dev->pm_cap = pm;
2018
	dev->d3_delay = PCI_PM_D3_WAIT;
2019
	dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2020
	dev->d3cold_allowed = true;
2021 2022 2023 2024

	dev->d1_support = false;
	dev->d2_support = false;
	if (!pci_no_d1d2(dev)) {
B
Bjorn Helgaas 已提交
2025
		if (pmc & PCI_PM_CAP_D1)
2026
			dev->d1_support = true;
B
Bjorn Helgaas 已提交
2027
		if (pmc & PCI_PM_CAP_D2)
2028
			dev->d2_support = true;
B
Bjorn Helgaas 已提交
2029 2030 2031

		if (dev->d1_support || dev->d2_support)
			dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
2032 2033
				   dev->d1_support ? " D1" : "",
				   dev->d2_support ? " D2" : "");
2034 2035 2036 2037
	}

	pmc &= PCI_PM_CAP_PME_MASK;
	if (pmc) {
B
Bjorn Helgaas 已提交
2038 2039
		dev_printk(KERN_DEBUG, &dev->dev,
			 "PME# supported from%s%s%s%s%s\n",
B
Bjorn Helgaas 已提交
2040 2041 2042 2043 2044
			 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
			 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
			 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
			 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
			 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2045
		dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2046
		dev->pme_poll = true;
2047 2048 2049 2050 2051 2052
		/*
		 * Make device's PM flags reflect the wake-up capability, but
		 * let the user space enable it to wake up the system as needed.
		 */
		device_set_wakeup_capable(&dev->dev, true);
		/* Disable the PME# generation functionality */
2053
		pci_pme_active(dev, false);
2054
	}
L
Linus Torvalds 已提交
2055 2056
}

2057 2058 2059 2060 2061 2062
static void pci_add_saved_cap(struct pci_dev *pci_dev,
	struct pci_cap_saved_state *new_cap)
{
	hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
}

2063
/**
2064 2065
 * _pci_add_cap_save_buffer - allocate buffer for saving given
 *                            capability registers
2066 2067
 * @dev: the PCI device
 * @cap: the capability to allocate the buffer for
2068
 * @extended: Standard or Extended capability ID
2069 2070
 * @size: requested size of the buffer
 */
2071 2072
static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
				    bool extended, unsigned int size)
2073 2074 2075 2076
{
	int pos;
	struct pci_cap_saved_state *save_state;

2077 2078 2079 2080 2081
	if (extended)
		pos = pci_find_ext_capability(dev, cap);
	else
		pos = pci_find_capability(dev, cap);

2082 2083 2084 2085 2086 2087 2088
	if (pos <= 0)
		return 0;

	save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
	if (!save_state)
		return -ENOMEM;

2089
	save_state->cap.cap_nr = cap;
2090
	save_state->cap.cap_extended = extended;
2091
	save_state->cap.size = size;
2092 2093 2094 2095 2096
	pci_add_saved_cap(dev, save_state);

	return 0;
}

2097 2098 2099 2100 2101 2102 2103 2104 2105 2106
int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
{
	return _pci_add_cap_save_buffer(dev, cap, false, size);
}

int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
{
	return _pci_add_cap_save_buffer(dev, cap, true, size);
}

2107 2108 2109 2110 2111 2112 2113 2114
/**
 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
 * @dev: the PCI device
 */
void pci_allocate_cap_save_buffers(struct pci_dev *dev)
{
	int error;

2115 2116
	error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
					PCI_EXP_SAVE_REGS * sizeof(u16));
2117 2118 2119 2120 2121 2122 2123 2124
	if (error)
		dev_err(&dev->dev,
			"unable to preallocate PCI Express save buffer\n");

	error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
	if (error)
		dev_err(&dev->dev,
			"unable to preallocate PCI-X save buffer\n");
2125 2126

	pci_allocate_vc_save_buffers(dev);
2127 2128
}

2129 2130 2131
void pci_free_cap_save_buffers(struct pci_dev *dev)
{
	struct pci_cap_saved_state *tmp;
2132
	struct hlist_node *n;
2133

2134
	hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2135 2136 2137
		kfree(tmp);
}

Y
Yu Zhao 已提交
2138
/**
2139
 * pci_configure_ari - enable or disable ARI forwarding
Y
Yu Zhao 已提交
2140
 * @dev: the PCI device
2141 2142 2143
 *
 * If @dev and its upstream bridge both support ARI, enable ARI in the
 * bridge.  Otherwise, disable ARI in the bridge.
Y
Yu Zhao 已提交
2144
 */
2145
void pci_configure_ari(struct pci_dev *dev)
Y
Yu Zhao 已提交
2146 2147
{
	u32 cap;
2148
	struct pci_dev *bridge;
Y
Yu Zhao 已提交
2149

2150
	if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
Y
Yu Zhao 已提交
2151 2152
		return;

2153
	bridge = dev->bus->self;
2154
	if (!bridge)
2155 2156
		return;

2157
	pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
Y
Yu Zhao 已提交
2158 2159 2160
	if (!(cap & PCI_EXP_DEVCAP2_ARI))
		return;

2161 2162 2163 2164 2165 2166 2167 2168 2169
	if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
		pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
					 PCI_EXP_DEVCTL2_ARI);
		bridge->ari_enabled = 1;
	} else {
		pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
					   PCI_EXP_DEVCTL2_ARI);
		bridge->ari_enabled = 0;
	}
Y
Yu Zhao 已提交
2170 2171
}

C
Chris Wright 已提交
2172 2173 2174 2175 2176 2177 2178 2179 2180 2181
static int pci_acs_enable;

/**
 * pci_request_acs - ask for ACS to be enabled if supported
 */
void pci_request_acs(void)
{
	pci_acs_enable = 1;
}

2182 2183 2184 2185 2186 2187 2188 2189 2190 2191
/**
 * pci_enable_acs - enable ACS if hardware support it
 * @dev: the PCI device
 */
void pci_enable_acs(struct pci_dev *dev)
{
	int pos;
	u16 cap;
	u16 ctrl;

C
Chris Wright 已提交
2192 2193 2194
	if (!pci_acs_enable)
		return;

2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216
	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
	if (!pos)
		return;

	pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
	pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);

	/* Source Validation */
	ctrl |= (cap & PCI_ACS_SV);

	/* P2P Request Redirect */
	ctrl |= (cap & PCI_ACS_RR);

	/* P2P Completion Redirect */
	ctrl |= (cap & PCI_ACS_CR);

	/* Upstream Forwarding */
	ctrl |= (cap & PCI_ACS_UF);

	pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
}

2217 2218 2219
static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
{
	int pos;
2220
	u16 cap, ctrl;
2221 2222 2223 2224 2225

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
	if (!pos)
		return false;

2226 2227 2228 2229 2230 2231 2232 2233
	/*
	 * Except for egress control, capabilities are either required
	 * or only required if controllable.  Features missing from the
	 * capability field can therefore be assumed as hard-wired enabled.
	 */
	pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
	acs_flags &= (cap | PCI_ACS_EC);

2234 2235 2236 2237
	pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
	return (ctrl & acs_flags) == acs_flags;
}

2238 2239 2240 2241 2242 2243 2244
/**
 * pci_acs_enabled - test ACS against required flags for a given device
 * @pdev: device to test
 * @acs_flags: required PCI ACS flags
 *
 * Return true if the device supports the provided flags.  Automatically
 * filters out flags that are not implemented on multifunction devices.
2245 2246 2247 2248 2249 2250 2251 2252
 *
 * Note that this interface checks the effective ACS capabilities of the
 * device rather than the actual capabilities.  For instance, most single
 * function endpoints are not required to support ACS because they have no
 * opportunity for peer-to-peer access.  We therefore return 'true'
 * regardless of whether the device exposes an ACS capability.  This makes
 * it much easier for callers of this function to ignore the actual type
 * or topology of the device when testing ACS support.
2253 2254 2255
 */
bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
{
2256
	int ret;
2257 2258 2259 2260 2261

	ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
	if (ret >= 0)
		return ret > 0;

2262 2263 2264 2265 2266
	/*
	 * Conventional PCI and PCI-X devices never support ACS, either
	 * effectively or actually.  The shared bus topology implies that
	 * any device on the bus can receive or snoop DMA.
	 */
2267 2268 2269
	if (!pci_is_pcie(pdev))
		return false;

2270 2271 2272
	switch (pci_pcie_type(pdev)) {
	/*
	 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2273
	 * but since their primary interface is PCI/X, we conservatively
2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296
	 * handle them as we would a non-PCIe device.
	 */
	case PCI_EXP_TYPE_PCIE_BRIDGE:
	/*
	 * PCIe 3.0, 6.12.1 excludes ACS on these devices.  "ACS is never
	 * applicable... must never implement an ACS Extended Capability...".
	 * This seems arbitrary, but we take a conservative interpretation
	 * of this statement.
	 */
	case PCI_EXP_TYPE_PCI_BRIDGE:
	case PCI_EXP_TYPE_RC_EC:
		return false;
	/*
	 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
	 * implement ACS in order to indicate their peer-to-peer capabilities,
	 * regardless of whether they are single- or multi-function devices.
	 */
	case PCI_EXP_TYPE_DOWNSTREAM:
	case PCI_EXP_TYPE_ROOT_PORT:
		return pci_acs_flags_enabled(pdev, acs_flags);
	/*
	 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
	 * implemented by the remaining PCIe types to indicate peer-to-peer
2297
	 * capabilities, but only when they are part of a multifunction
2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308
	 * device.  The footnote for section 6.12 indicates the specific
	 * PCIe types included here.
	 */
	case PCI_EXP_TYPE_ENDPOINT:
	case PCI_EXP_TYPE_UPSTREAM:
	case PCI_EXP_TYPE_LEG_END:
	case PCI_EXP_TYPE_RC_END:
		if (!pdev->multifunction)
			break;

		return pci_acs_flags_enabled(pdev, acs_flags);
2309 2310
	}

2311
	/*
2312
	 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2313 2314
	 * to single function devices with the exception of downstream ports.
	 */
2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346
	return true;
}

/**
 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
 * @start: starting downstream device
 * @end: ending upstream device or NULL to search to the root bus
 * @acs_flags: required flags
 *
 * Walk up a device tree from start to end testing PCI ACS support.  If
 * any step along the way does not support the required flags, return false.
 */
bool pci_acs_path_enabled(struct pci_dev *start,
			  struct pci_dev *end, u16 acs_flags)
{
	struct pci_dev *pdev, *parent = start;

	do {
		pdev = parent;

		if (!pci_acs_enabled(pdev, acs_flags))
			return false;

		if (pci_is_root_bus(pdev->bus))
			return (end == NULL);

		parent = pdev->bus->self;
	} while (pdev != end);

	return true;
}

2347 2348 2349
/**
 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
 * @dev: the PCI device
2350
 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2351 2352 2353
 *
 * Perform INTx swizzling for a device behind one level of bridge.  This is
 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2354 2355 2356
 * behind bridges on add-in cards.  For devices with ARI enabled, the slot
 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
 * the PCI Express Base Specification, Revision 2.1)
2357
 */
2358
u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2359
{
2360 2361 2362 2363 2364 2365 2366 2367
	int slot;

	if (pci_ari_enabled(dev->bus))
		slot = 0;
	else
		slot = PCI_SLOT(dev->devfn);

	return (((pin - 1) + slot) % 4) + 1;
2368 2369
}

L
Linus Torvalds 已提交
2370 2371 2372 2373 2374
int
pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
{
	u8 pin;

2375
	pin = dev->pin;
L
Linus Torvalds 已提交
2376 2377
	if (!pin)
		return -1;
2378

2379
	while (!pci_is_root_bus(dev->bus)) {
2380
		pin = pci_swizzle_interrupt_pin(dev, pin);
L
Linus Torvalds 已提交
2381 2382 2383 2384 2385 2386
		dev = dev->bus->self;
	}
	*bridge = dev;
	return pin;
}

2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398
/**
 * pci_common_swizzle - swizzle INTx all the way to root bridge
 * @dev: the PCI device
 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
 *
 * Perform INTx swizzling for a device.  This traverses through all PCI-to-PCI
 * bridges all the way up to a PCI root bus.
 */
u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
{
	u8 pin = *pinp;

2399
	while (!pci_is_root_bus(dev->bus)) {
2400 2401 2402 2403 2404 2405 2406
		pin = pci_swizzle_interrupt_pin(dev, pin);
		dev = dev->bus->self;
	}
	*pinp = pin;
	return PCI_SLOT(dev->devfn);
}

L
Linus Torvalds 已提交
2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417
/**
 *	pci_release_region - Release a PCI bar
 *	@pdev: PCI device whose resources were previously reserved by pci_request_region
 *	@bar: BAR to release
 *
 *	Releases the PCI I/O and memory resources previously reserved by a
 *	successful call to pci_request_region.  Call this function only
 *	after all use of the PCI regions has ceased.
 */
void pci_release_region(struct pci_dev *pdev, int bar)
{
T
Tejun Heo 已提交
2418 2419
	struct pci_devres *dr;

L
Linus Torvalds 已提交
2420 2421 2422 2423 2424 2425 2426 2427
	if (pci_resource_len(pdev, bar) == 0)
		return;
	if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
		release_region(pci_resource_start(pdev, bar),
				pci_resource_len(pdev, bar));
	else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
		release_mem_region(pci_resource_start(pdev, bar),
				pci_resource_len(pdev, bar));
T
Tejun Heo 已提交
2428 2429 2430 2431

	dr = find_pci_dr(pdev);
	if (dr)
		dr->region_mask &= ~(1 << bar);
L
Linus Torvalds 已提交
2432 2433 2434
}

/**
2435
 *	__pci_request_region - Reserved PCI I/O and memory resource
L
Linus Torvalds 已提交
2436 2437 2438
 *	@pdev: PCI device whose resources are to be reserved
 *	@bar: BAR to be reserved
 *	@res_name: Name to be associated with resource.
2439
 *	@exclusive: whether the region access is exclusive or not
L
Linus Torvalds 已提交
2440 2441 2442 2443 2444 2445
 *
 *	Mark the PCI region associated with PCI device @pdev BR @bar as
 *	being reserved by owner @res_name.  Do not access any
 *	address inside the PCI regions unless this call returns
 *	successfully.
 *
2446 2447
 *	If @exclusive is set, then the region is marked so that userspace
 *	is explicitly not allowed to map the resource via /dev/mem or
2448
 *	sysfs MMIO access.
2449
 *
L
Linus Torvalds 已提交
2450 2451 2452
 *	Returns 0 on success, or %EBUSY on error.  A warning
 *	message is also printed on failure.
 */
2453 2454
static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
									int exclusive)
L
Linus Torvalds 已提交
2455
{
T
Tejun Heo 已提交
2456 2457
	struct pci_devres *dr;

L
Linus Torvalds 已提交
2458 2459
	if (pci_resource_len(pdev, bar) == 0)
		return 0;
2460

L
Linus Torvalds 已提交
2461 2462 2463 2464 2465 2466
	if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
		if (!request_region(pci_resource_start(pdev, bar),
			    pci_resource_len(pdev, bar), res_name))
			goto err_out;
	}
	else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2467 2468 2469
		if (!__request_mem_region(pci_resource_start(pdev, bar),
					pci_resource_len(pdev, bar), res_name,
					exclusive))
L
Linus Torvalds 已提交
2470 2471
			goto err_out;
	}
T
Tejun Heo 已提交
2472 2473 2474 2475 2476

	dr = find_pci_dr(pdev);
	if (dr)
		dr->region_mask |= 1 << bar;

L
Linus Torvalds 已提交
2477 2478 2479
	return 0;

err_out:
2480
	dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2481
		 &pdev->resource[bar]);
L
Linus Torvalds 已提交
2482 2483 2484
	return -EBUSY;
}

2485
/**
2486
 *	pci_request_region - Reserve PCI I/O and memory resource
2487 2488
 *	@pdev: PCI device whose resources are to be reserved
 *	@bar: BAR to be reserved
2489
 *	@res_name: Name to be associated with resource
2490
 *
2491
 *	Mark the PCI region associated with PCI device @pdev BAR @bar as
2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519
 *	being reserved by owner @res_name.  Do not access any
 *	address inside the PCI regions unless this call returns
 *	successfully.
 *
 *	Returns 0 on success, or %EBUSY on error.  A warning
 *	message is also printed on failure.
 */
int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
{
	return __pci_request_region(pdev, bar, res_name, 0);
}

/**
 *	pci_request_region_exclusive - Reserved PCI I/O and memory resource
 *	@pdev: PCI device whose resources are to be reserved
 *	@bar: BAR to be reserved
 *	@res_name: Name to be associated with resource.
 *
 *	Mark the PCI region associated with PCI device @pdev BR @bar as
 *	being reserved by owner @res_name.  Do not access any
 *	address inside the PCI regions unless this call returns
 *	successfully.
 *
 *	Returns 0 on success, or %EBUSY on error.  A warning
 *	message is also printed on failure.
 *
 *	The key difference that _exclusive makes it that userspace is
 *	explicitly not allowed to map the resource via /dev/mem or
2520
 *	sysfs.
2521 2522 2523 2524 2525
 */
int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
{
	return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
}
2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542
/**
 * pci_release_selected_regions - Release selected PCI I/O and memory resources
 * @pdev: PCI device whose resources were previously reserved
 * @bars: Bitmask of BARs to be released
 *
 * Release selected PCI I/O and memory resources previously reserved.
 * Call this function only after all use of the PCI regions has ceased.
 */
void pci_release_selected_regions(struct pci_dev *pdev, int bars)
{
	int i;

	for (i = 0; i < 6; i++)
		if (bars & (1 << i))
			pci_release_region(pdev, i);
}

2543
static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2544
				 const char *res_name, int excl)
2545 2546 2547 2548 2549
{
	int i;

	for (i = 0; i < 6; i++)
		if (bars & (1 << i))
2550
			if (__pci_request_region(pdev, i, res_name, excl))
2551 2552 2553 2554 2555 2556 2557 2558 2559 2560
				goto err_out;
	return 0;

err_out:
	while(--i >= 0)
		if (bars & (1 << i))
			pci_release_region(pdev, i);

	return -EBUSY;
}
L
Linus Torvalds 已提交
2561

2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581

/**
 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
 * @pdev: PCI device whose resources are to be reserved
 * @bars: Bitmask of BARs to be requested
 * @res_name: Name to be associated with resource
 */
int pci_request_selected_regions(struct pci_dev *pdev, int bars,
				 const char *res_name)
{
	return __pci_request_selected_regions(pdev, bars, res_name, 0);
}

int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
				 int bars, const char *res_name)
{
	return __pci_request_selected_regions(pdev, bars, res_name,
			IORESOURCE_EXCLUSIVE);
}

L
Linus Torvalds 已提交
2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592
/**
 *	pci_release_regions - Release reserved PCI I/O and memory resources
 *	@pdev: PCI device whose resources were previously reserved by pci_request_regions
 *
 *	Releases all PCI I/O and memory resources previously reserved by a
 *	successful call to pci_request_regions.  Call this function only
 *	after all use of the PCI regions has ceased.
 */

void pci_release_regions(struct pci_dev *pdev)
{
2593
	pci_release_selected_regions(pdev, (1 << 6) - 1);
L
Linus Torvalds 已提交
2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608
}

/**
 *	pci_request_regions - Reserved PCI I/O and memory resources
 *	@pdev: PCI device whose resources are to be reserved
 *	@res_name: Name to be associated with resource.
 *
 *	Mark all PCI regions associated with PCI device @pdev as
 *	being reserved by owner @res_name.  Do not access any
 *	address inside the PCI regions unless this call returns
 *	successfully.
 *
 *	Returns 0 on success, or %EBUSY on error.  A warning
 *	message is also printed on failure.
 */
2609
int pci_request_regions(struct pci_dev *pdev, const char *res_name)
L
Linus Torvalds 已提交
2610
{
2611
	return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
L
Linus Torvalds 已提交
2612 2613
}

2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624
/**
 *	pci_request_regions_exclusive - Reserved PCI I/O and memory resources
 *	@pdev: PCI device whose resources are to be reserved
 *	@res_name: Name to be associated with resource.
 *
 *	Mark all PCI regions associated with PCI device @pdev as
 *	being reserved by owner @res_name.  Do not access any
 *	address inside the PCI regions unless this call returns
 *	successfully.
 *
 *	pci_request_regions_exclusive() will mark the region so that
2625
 *	/dev/mem and the sysfs MMIO access will not be allowed.
2626 2627 2628 2629 2630 2631 2632 2633 2634 2635
 *
 *	Returns 0 on success, or %EBUSY on error.  A warning
 *	message is also printed on failure.
 */
int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
{
	return pci_request_selected_regions_exclusive(pdev,
					((1 << 6) - 1), res_name);
}

2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651
static void __pci_set_master(struct pci_dev *dev, bool enable)
{
	u16 old_cmd, cmd;

	pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
	if (enable)
		cmd = old_cmd | PCI_COMMAND_MASTER;
	else
		cmd = old_cmd & ~PCI_COMMAND_MASTER;
	if (cmd != old_cmd) {
		dev_dbg(&dev->dev, "%s bus mastering\n",
			enable ? "enabling" : "disabling");
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	dev->is_busmaster = enable;
}
2652

2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664
/**
 * pcibios_setup - process "pci=" kernel boot arguments
 * @str: string used to pass in "pci=" kernel boot arguments
 *
 * Process kernel boot arguments.  This is the default implementation.
 * Architecture specific implementations can override this as necessary.
 */
char * __weak __init pcibios_setup(char *str)
{
	return str;
}

2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676
/**
 * pcibios_set_master - enable PCI bus-mastering for device dev
 * @dev: the PCI device to enable
 *
 * Enables PCI bus-mastering for the device.  This is the default
 * implementation.  Architecture specific implementations can override
 * this if necessary.
 */
void __weak pcibios_set_master(struct pci_dev *dev)
{
	u8 lat;

2677 2678 2679 2680
	/* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
	if (pci_is_pcie(dev))
		return;

2681 2682 2683 2684 2685 2686 2687
	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	if (lat < 16)
		lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	else if (lat > pcibios_max_latency)
		lat = pcibios_max_latency;
	else
		return;
2688

2689 2690 2691
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
}

L
Linus Torvalds 已提交
2692 2693 2694 2695 2696 2697 2698
/**
 * pci_set_master - enables bus-mastering for device dev
 * @dev: the PCI device to enable
 *
 * Enables bus-mastering on the device and calls pcibios_set_master()
 * to do the needed arch specific settings.
 */
2699
void pci_set_master(struct pci_dev *dev)
L
Linus Torvalds 已提交
2700
{
2701
	__pci_set_master(dev, true);
L
Linus Torvalds 已提交
2702 2703 2704
	pcibios_set_master(dev);
}

2705 2706 2707 2708 2709 2710 2711 2712 2713
/**
 * pci_clear_master - disables bus-mastering for device dev
 * @dev: the PCI device to disable
 */
void pci_clear_master(struct pci_dev *dev)
{
	__pci_set_master(dev, false);
}

L
Linus Torvalds 已提交
2714
/**
2715 2716
 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
 * @dev: the PCI device for which MWI is to be enabled
L
Linus Torvalds 已提交
2717
 *
2718 2719
 * Helper function for pci_set_mwi.
 * Originally copied from drivers/net/acenic.c.
L
Linus Torvalds 已提交
2720 2721 2722 2723
 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
 *
 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 */
T
Tejun Heo 已提交
2724
int pci_set_cacheline_size(struct pci_dev *dev)
L
Linus Torvalds 已提交
2725 2726 2727 2728
{
	u8 cacheline_size;

	if (!pci_cache_line_size)
T
Tejun Heo 已提交
2729
		return -EINVAL;
L
Linus Torvalds 已提交
2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744

	/* Validate current setting: the PCI_CACHE_LINE_SIZE must be
	   equal to or multiple of the right value. */
	pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
	if (cacheline_size >= pci_cache_line_size &&
	    (cacheline_size % pci_cache_line_size) == 0)
		return 0;

	/* Write the correct value. */
	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
	/* Read it back. */
	pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
	if (cacheline_size == pci_cache_line_size)
		return 0;

2745 2746
	dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
		   "supported\n", pci_cache_line_size << 2);
L
Linus Torvalds 已提交
2747 2748 2749

	return -EINVAL;
}
T
Tejun Heo 已提交
2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767
EXPORT_SYMBOL_GPL(pci_set_cacheline_size);

#ifdef PCI_DISABLE_MWI
int pci_set_mwi(struct pci_dev *dev)
{
	return 0;
}

int pci_try_set_mwi(struct pci_dev *dev)
{
	return 0;
}

void pci_clear_mwi(struct pci_dev *dev)
{
}

#else
L
Linus Torvalds 已提交
2768 2769 2770 2771 2772

/**
 * pci_set_mwi - enables memory-write-invalidate PCI transaction
 * @dev: the PCI device for which MWI is enabled
 *
R
Randy Dunlap 已提交
2773
 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
L
Linus Torvalds 已提交
2774 2775 2776 2777 2778 2779 2780 2781 2782
 *
 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 */
int
pci_set_mwi(struct pci_dev *dev)
{
	int rc;
	u16 cmd;

2783
	rc = pci_set_cacheline_size(dev);
L
Linus Torvalds 已提交
2784 2785 2786 2787 2788
	if (rc)
		return rc;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2789
		dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
L
Linus Torvalds 已提交
2790 2791 2792
		cmd |= PCI_COMMAND_INVALIDATE;
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
2793

L
Linus Torvalds 已提交
2794 2795 2796
	return 0;
}

R
Randy Dunlap 已提交
2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811
/**
 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
 * @dev: the PCI device for which MWI is enabled
 *
 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
 * Callers are not required to check the return value.
 *
 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 */
int pci_try_set_mwi(struct pci_dev *dev)
{
	int rc = pci_set_mwi(dev);
	return rc;
}

L
Linus Torvalds 已提交
2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828
/**
 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
 * @dev: the PCI device to disable
 *
 * Disables PCI Memory-Write-Invalidate transaction on the device
 */
void
pci_clear_mwi(struct pci_dev *dev)
{
	u16 cmd;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	if (cmd & PCI_COMMAND_INVALIDATE) {
		cmd &= ~PCI_COMMAND_INVALIDATE;
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
}
2829
#endif /* ! PCI_DISABLE_MWI */
L
Linus Torvalds 已提交
2830

B
Brett M Russ 已提交
2831 2832
/**
 * pci_intx - enables/disables PCI INTx for device dev
R
Randy Dunlap 已提交
2833 2834
 * @pdev: the PCI device to operate on
 * @enable: boolean: whether to enable or disable PCI INTx
B
Brett M Russ 已提交
2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851
 *
 * Enables/disables PCI INTx for device dev
 */
void
pci_intx(struct pci_dev *pdev, int enable)
{
	u16 pci_command, new;

	pci_read_config_word(pdev, PCI_COMMAND, &pci_command);

	if (enable) {
		new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
	} else {
		new = pci_command | PCI_COMMAND_INTX_DISABLE;
	}

	if (new != pci_command) {
T
Tejun Heo 已提交
2852 2853
		struct pci_devres *dr;

2854
		pci_write_config_word(pdev, PCI_COMMAND, new);
T
Tejun Heo 已提交
2855 2856 2857 2858 2859 2860

		dr = find_pci_dr(pdev);
		if (dr && !dr->restore_intx) {
			dr->restore_intx = 1;
			dr->orig_intx = !enable;
		}
B
Brett M Russ 已提交
2861 2862 2863
	}
}

2864 2865
/**
 * pci_intx_mask_supported - probe for INTx masking support
2866
 * @dev: the PCI device to operate on
2867 2868 2869 2870 2871 2872 2873 2874 2875
 *
 * Check if the device dev support INTx masking via the config space
 * command word.
 */
bool pci_intx_mask_supported(struct pci_dev *dev)
{
	bool mask_supported = false;
	u16 orig, new;

2876 2877 2878
	if (dev->broken_intx_masking)
		return false;

2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950
	pci_cfg_access_lock(dev);

	pci_read_config_word(dev, PCI_COMMAND, &orig);
	pci_write_config_word(dev, PCI_COMMAND,
			      orig ^ PCI_COMMAND_INTX_DISABLE);
	pci_read_config_word(dev, PCI_COMMAND, &new);

	/*
	 * There's no way to protect against hardware bugs or detect them
	 * reliably, but as long as we know what the value should be, let's
	 * go ahead and check it.
	 */
	if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
		dev_err(&dev->dev, "Command register changed from "
			"0x%x to 0x%x: driver or hardware bug?\n", orig, new);
	} else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
		mask_supported = true;
		pci_write_config_word(dev, PCI_COMMAND, orig);
	}

	pci_cfg_access_unlock(dev);
	return mask_supported;
}
EXPORT_SYMBOL_GPL(pci_intx_mask_supported);

static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
{
	struct pci_bus *bus = dev->bus;
	bool mask_updated = true;
	u32 cmd_status_dword;
	u16 origcmd, newcmd;
	unsigned long flags;
	bool irq_pending;

	/*
	 * We do a single dword read to retrieve both command and status.
	 * Document assumptions that make this possible.
	 */
	BUILD_BUG_ON(PCI_COMMAND % 4);
	BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);

	raw_spin_lock_irqsave(&pci_lock, flags);

	bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);

	irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;

	/*
	 * Check interrupt status register to see whether our device
	 * triggered the interrupt (when masking) or the next IRQ is
	 * already pending (when unmasking).
	 */
	if (mask != irq_pending) {
		mask_updated = false;
		goto done;
	}

	origcmd = cmd_status_dword;
	newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
	if (mask)
		newcmd |= PCI_COMMAND_INTX_DISABLE;
	if (newcmd != origcmd)
		bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);

done:
	raw_spin_unlock_irqrestore(&pci_lock, flags);

	return mask_updated;
}

/**
 * pci_check_and_mask_intx - mask INTx on pending interrupt
2951
 * @dev: the PCI device to operate on
2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963
 *
 * Check if the device dev has its INTx line asserted, mask it and
 * return true in that case. False is returned if not interrupt was
 * pending.
 */
bool pci_check_and_mask_intx(struct pci_dev *dev)
{
	return pci_check_and_set_intx_mask(dev, true);
}
EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);

/**
2964
 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
2965
 * @dev: the PCI device to operate on
2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976
 *
 * Check if the device dev has its INTx line asserted, unmask it if not
 * and return true. False is returned and the mask remains active if
 * there was still an interrupt pending.
 */
bool pci_check_and_unmask_intx(struct pci_dev *dev)
{
	return pci_check_and_set_intx_mask(dev, false);
}
EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);

2977
/**
2978
 * pci_msi_off - disables any MSI or MSI-X capabilities
R
Randy Dunlap 已提交
2979
 * @dev: the PCI device to operate on
2980
 *
2981 2982 2983
 * If you want to use MSI, see pci_enable_msi() and friends.
 * This is a lower-level primitive that allows us to disable
 * MSI operation at the device level.
2984 2985 2986 2987 2988 2989
 */
void pci_msi_off(struct pci_dev *dev)
{
	int pos;
	u16 control;

2990 2991 2992 2993 2994
	/*
	 * This looks like it could go in msi.c, but we need it even when
	 * CONFIG_PCI_MSI=n.  For the same reason, we can't use
	 * dev->msi_cap or dev->msix_cap here.
	 */
2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007
	pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
	if (pos) {
		pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
		control &= ~PCI_MSI_FLAGS_ENABLE;
		pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
	}
	pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
	if (pos) {
		pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
		control &= ~PCI_MSIX_FLAGS_ENABLE;
		pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
	}
}
3008
EXPORT_SYMBOL_GPL(pci_msi_off);
3009

3010 3011 3012 3013 3014 3015
int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
{
	return dma_set_max_seg_size(&dev->dev, size);
}
EXPORT_SYMBOL(pci_set_dma_max_seg_size);

3016 3017 3018 3019 3020 3021
int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
{
	return dma_set_seg_boundary(&dev->dev, mask);
}
EXPORT_SYMBOL(pci_set_dma_seg_boundary);

3022 3023 3024 3025 3026 3027 3028
/**
 * pci_wait_for_pending_transaction - waits for pending transaction
 * @dev: the PCI device to operate on
 *
 * Return 0 if transaction is pending 1 otherwise.
 */
int pci_wait_for_pending_transaction(struct pci_dev *dev)
3029
{
3030 3031
	if (!pci_is_pcie(dev))
		return 1;
Y
Yu Zhao 已提交
3032

3033
	return pci_wait_for_pending(dev, PCI_EXP_DEVSTA, PCI_EXP_DEVSTA_TRPND);
3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049
}
EXPORT_SYMBOL(pci_wait_for_pending_transaction);

static int pcie_flr(struct pci_dev *dev, int probe)
{
	u32 cap;

	pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
	if (!(cap & PCI_EXP_DEVCAP_FLR))
		return -ENOTTY;

	if (probe)
		return 0;

	if (!pci_wait_for_pending_transaction(dev))
		dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
Y
Yu Zhao 已提交
3050

3051
	pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3052

Y
Yu Zhao 已提交
3053
	msleep(100);
3054 3055 3056

	return 0;
}
S
Sheng Yang 已提交
3057

Y
Yu Zhao 已提交
3058
static int pci_af_flr(struct pci_dev *dev, int probe)
3059
{
Y
Yu Zhao 已提交
3060
	int pos;
3061 3062
	u8 cap;

Y
Yu Zhao 已提交
3063 3064
	pos = pci_find_capability(dev, PCI_CAP_ID_AF);
	if (!pos)
3065
		return -ENOTTY;
Y
Yu Zhao 已提交
3066 3067

	pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3068 3069 3070 3071 3072 3073 3074
	if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
		return -ENOTTY;

	if (probe)
		return 0;

	/* Wait for Transaction Pending bit clean */
3075 3076
	if (pci_wait_for_pending(dev, PCI_AF_STATUS, PCI_AF_STATUS_TP))
		goto clear;
S
Sheng Yang 已提交
3077

Y
Yu Zhao 已提交
3078 3079
	dev_err(&dev->dev, "transaction is not cleared; "
			"proceeding with reset anyway\n");
S
Sheng Yang 已提交
3080

Y
Yu Zhao 已提交
3081 3082
clear:
	pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3083
	msleep(100);
Y
Yu Zhao 已提交
3084

3085 3086 3087
	return 0;
}

3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099
/**
 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
 * @dev: Device to reset.
 * @probe: If set, only check if the device can be reset this way.
 *
 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
 * unset, it will be reinitialized internally when going from PCI_D3hot to
 * PCI_D0.  If that's the case and the device is not in a low-power state
 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
 *
 * NOTE: This causes the caller to sleep for twice the device power transition
 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3100
 * by default (i.e. unless the @dev's d3_delay field has a different value).
3101 3102
 * Moreover, only devices in D0 can be reset by this function.
 */
3103
static int pci_pm_reset(struct pci_dev *dev, int probe)
S
Sheng Yang 已提交
3104
{
3105 3106 3107 3108
	u16 csr;

	if (!dev->pm_cap)
		return -ENOTTY;
S
Sheng Yang 已提交
3109

3110 3111 3112
	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
	if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
		return -ENOTTY;
S
Sheng Yang 已提交
3113

3114 3115
	if (probe)
		return 0;
3116

3117 3118 3119 3120 3121 3122
	if (dev->current_state != PCI_D0)
		return -EINVAL;

	csr &= ~PCI_PM_CTRL_STATE_MASK;
	csr |= PCI_D3hot;
	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3123
	pci_dev_d3_sleep(dev);
3124 3125 3126 3127

	csr &= ~PCI_PM_CTRL_STATE_MASK;
	csr |= PCI_D0;
	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3128
	pci_dev_d3_sleep(dev);
3129 3130 3131 3132

	return 0;
}

3133 3134 3135 3136 3137 3138 3139 3140
/**
 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
 * @dev: Bridge device
 *
 * Use the bridge control register to assert reset on the secondary bus.
 * Devices on the secondary bus are left in power-on state.
 */
void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
Y
Yu Zhao 已提交
3141 3142
{
	u16 ctrl;
3143 3144 3145 3146

	pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
	ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3147 3148
	/*
	 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms.  Double
3149
	 * this to 2ms to ensure that we meet the minimum requirement.
3150 3151
	 */
	msleep(2);
3152 3153 3154

	ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3155 3156 3157 3158 3159 3160 3161 3162 3163

	/*
	 * Trhfa for conventional PCI is 2^25 clock cycles.
	 * Assuming a minimum 33MHz clock this results in a 1s
	 * delay before we can consider subordinate devices to
	 * be re-initialized.  PCIe has some ways to shorten this,
	 * but we don't make use of them yet.
	 */
	ssleep(1);
3164 3165 3166 3167 3168
}
EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);

static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
{
Y
Yu Zhao 已提交
3169 3170
	struct pci_dev *pdev;

3171
	if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
Y
Yu Zhao 已提交
3172 3173 3174 3175 3176 3177 3178 3179 3180
		return -ENOTTY;

	list_for_each_entry(pdev, &dev->bus->devices, bus_list)
		if (pdev != dev)
			return -ENOTTY;

	if (probe)
		return 0;

3181
	pci_reset_bridge_secondary_bus(dev->bus->self);
Y
Yu Zhao 已提交
3182 3183 3184 3185

	return 0;
}

3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214
static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
{
	int rc = -ENOTTY;

	if (!hotplug || !try_module_get(hotplug->ops->owner))
		return rc;

	if (hotplug->ops->reset_slot)
		rc = hotplug->ops->reset_slot(hotplug, probe);

	module_put(hotplug->ops->owner);

	return rc;
}

static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
{
	struct pci_dev *pdev;

	if (dev->subordinate || !dev->slot)
		return -ENOTTY;

	list_for_each_entry(pdev, &dev->bus->devices, bus_list)
		if (pdev != dev && pdev->slot == dev->slot)
			return -ENOTTY;

	return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
}

3215
static int __pci_dev_reset(struct pci_dev *dev, int probe)
S
Sheng Yang 已提交
3216
{
Y
Yu Zhao 已提交
3217 3218 3219 3220
	int rc;

	might_sleep();

3221 3222 3223 3224
	rc = pci_dev_specific_reset(dev, probe);
	if (rc != -ENOTTY)
		goto done;

Y
Yu Zhao 已提交
3225 3226 3227
	rc = pcie_flr(dev, probe);
	if (rc != -ENOTTY)
		goto done;
S
Sheng Yang 已提交
3228

Y
Yu Zhao 已提交
3229
	rc = pci_af_flr(dev, probe);
3230 3231 3232 3233
	if (rc != -ENOTTY)
		goto done;

	rc = pci_pm_reset(dev, probe);
Y
Yu Zhao 已提交
3234 3235 3236
	if (rc != -ENOTTY)
		goto done;

3237 3238 3239 3240
	rc = pci_dev_reset_slot_function(dev, probe);
	if (rc != -ENOTTY)
		goto done;

Y
Yu Zhao 已提交
3241
	rc = pci_parent_bus_reset(dev, probe);
Y
Yu Zhao 已提交
3242
done:
3243 3244 3245
	return rc;
}

3246 3247 3248 3249 3250 3251 3252
static void pci_dev_lock(struct pci_dev *dev)
{
	pci_cfg_access_lock(dev);
	/* block PM suspend, driver probe, etc. */
	device_lock(&dev->dev);
}

3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264
/* Return 1 on successful lock, 0 on contention */
static int pci_dev_trylock(struct pci_dev *dev)
{
	if (pci_cfg_access_trylock(dev)) {
		if (device_trylock(&dev->dev))
			return 1;
		pci_cfg_access_unlock(dev);
	}

	return 0;
}

3265 3266 3267 3268 3269 3270 3271 3272
static void pci_dev_unlock(struct pci_dev *dev)
{
	device_unlock(&dev->dev);
	pci_cfg_access_unlock(dev);
}

static void pci_dev_save_and_disable(struct pci_dev *dev)
{
3273 3274 3275 3276 3277 3278 3279
	/*
	 * Wake-up device prior to save.  PM registers default to D0 after
	 * reset and a simple register restore doesn't reliably return
	 * to a non-D0 state anyway.
	 */
	pci_set_power_state(dev, PCI_D0);

3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295
	pci_save_state(dev);
	/*
	 * Disable the device by clearing the Command register, except for
	 * INTx-disable which is set.  This not only disables MMIO and I/O port
	 * BARs, but also prevents the device from being Bus Master, preventing
	 * DMA from the device including MSI/MSI-X interrupts.  For PCI 2.3
	 * compliant devices, INTx-disable prevents legacy interrupts.
	 */
	pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
}

static void pci_dev_restore(struct pci_dev *dev)
{
	pci_restore_state(dev);
}

3296 3297 3298 3299
static int pci_dev_reset(struct pci_dev *dev, int probe)
{
	int rc;

3300 3301
	if (!probe)
		pci_dev_lock(dev);
3302 3303 3304

	rc = __pci_dev_reset(dev, probe);

3305 3306 3307
	if (!probe)
		pci_dev_unlock(dev);

Y
Yu Zhao 已提交
3308
	return rc;
S
Sheng Yang 已提交
3309 3310
}
/**
Y
Yu Zhao 已提交
3311 3312
 * __pci_reset_function - reset a PCI device function
 * @dev: PCI device to reset
S
Sheng Yang 已提交
3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323
 *
 * Some devices allow an individual function to be reset without affecting
 * other functions in the same device.  The PCI device must be responsive
 * to PCI config space in order to use this function.
 *
 * The device function is presumed to be unused when this function is called.
 * Resetting the device will make the contents of PCI configuration space
 * random, so any caller of this must be prepared to reinitialise the
 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
 * etc.
 *
Y
Yu Zhao 已提交
3324
 * Returns 0 if the device function was successfully reset or negative if the
S
Sheng Yang 已提交
3325 3326
 * device doesn't support resetting a single function.
 */
Y
Yu Zhao 已提交
3327
int __pci_reset_function(struct pci_dev *dev)
S
Sheng Yang 已提交
3328
{
Y
Yu Zhao 已提交
3329
	return pci_dev_reset(dev, 0);
S
Sheng Yang 已提交
3330
}
Y
Yu Zhao 已提交
3331
EXPORT_SYMBOL_GPL(__pci_reset_function);
3332

3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353
/**
 * __pci_reset_function_locked - reset a PCI device function while holding
 * the @dev mutex lock.
 * @dev: PCI device to reset
 *
 * Some devices allow an individual function to be reset without affecting
 * other functions in the same device.  The PCI device must be responsive
 * to PCI config space in order to use this function.
 *
 * The device function is presumed to be unused and the caller is holding
 * the device mutex lock when this function is called.
 * Resetting the device will make the contents of PCI configuration space
 * random, so any caller of this must be prepared to reinitialise the
 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
 * etc.
 *
 * Returns 0 if the device function was successfully reset or negative if the
 * device doesn't support resetting a single function.
 */
int __pci_reset_function_locked(struct pci_dev *dev)
{
3354
	return __pci_dev_reset(dev, 0);
3355 3356 3357
}
EXPORT_SYMBOL_GPL(__pci_reset_function_locked);

3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373
/**
 * pci_probe_reset_function - check whether the device can be safely reset
 * @dev: PCI device to reset
 *
 * Some devices allow an individual function to be reset without affecting
 * other functions in the same device.  The PCI device must be responsive
 * to PCI config space in order to use this function.
 *
 * Returns 0 if the device function can be reset or negative if the
 * device doesn't support resetting a single function.
 */
int pci_probe_reset_function(struct pci_dev *dev)
{
	return pci_dev_reset(dev, 1);
}

3374
/**
Y
Yu Zhao 已提交
3375 3376
 * pci_reset_function - quiesce and reset a PCI device function
 * @dev: PCI device to reset
3377 3378 3379 3380 3381 3382 3383
 *
 * Some devices allow an individual function to be reset without affecting
 * other functions in the same device.  The PCI device must be responsive
 * to PCI config space in order to use this function.
 *
 * This function does not just reset the PCI portion of a device, but
 * clears all the state associated with the device.  This function differs
Y
Yu Zhao 已提交
3384
 * from __pci_reset_function in that it saves and restores device state
3385 3386
 * over the reset.
 *
Y
Yu Zhao 已提交
3387
 * Returns 0 if the device function was successfully reset or negative if the
3388 3389 3390 3391
 * device doesn't support resetting a single function.
 */
int pci_reset_function(struct pci_dev *dev)
{
Y
Yu Zhao 已提交
3392
	int rc;
3393

Y
Yu Zhao 已提交
3394 3395 3396
	rc = pci_dev_reset(dev, 1);
	if (rc)
		return rc;
3397

3398
	pci_dev_save_and_disable(dev);
3399

Y
Yu Zhao 已提交
3400
	rc = pci_dev_reset(dev, 0);
3401

3402
	pci_dev_restore(dev);
3403

Y
Yu Zhao 已提交
3404
	return rc;
3405 3406 3407
}
EXPORT_SYMBOL_GPL(pci_reset_function);

3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435
/**
 * pci_try_reset_function - quiesce and reset a PCI device function
 * @dev: PCI device to reset
 *
 * Same as above, except return -EAGAIN if unable to lock device.
 */
int pci_try_reset_function(struct pci_dev *dev)
{
	int rc;

	rc = pci_dev_reset(dev, 1);
	if (rc)
		return rc;

	pci_dev_save_and_disable(dev);

	if (pci_dev_trylock(dev)) {
		rc = __pci_dev_reset(dev, 0);
		pci_dev_unlock(dev);
	} else
		rc = -EAGAIN;

	pci_dev_restore(dev);

	return rc;
}
EXPORT_SYMBOL_GPL(pci_try_reset_function);

3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459
/* Lock devices from the top of the tree down */
static void pci_bus_lock(struct pci_bus *bus)
{
	struct pci_dev *dev;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		pci_dev_lock(dev);
		if (dev->subordinate)
			pci_bus_lock(dev->subordinate);
	}
}

/* Unlock devices from the bottom of the tree up */
static void pci_bus_unlock(struct pci_bus *bus)
{
	struct pci_dev *dev;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		if (dev->subordinate)
			pci_bus_unlock(dev->subordinate);
		pci_dev_unlock(dev);
	}
}

3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485
/* Return 1 on successful lock, 0 on contention */
static int pci_bus_trylock(struct pci_bus *bus)
{
	struct pci_dev *dev;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		if (!pci_dev_trylock(dev))
			goto unlock;
		if (dev->subordinate) {
			if (!pci_bus_trylock(dev->subordinate)) {
				pci_dev_unlock(dev);
				goto unlock;
			}
		}
	}
	return 1;

unlock:
	list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
		if (dev->subordinate)
			pci_bus_unlock(dev->subordinate);
		pci_dev_unlock(dev);
	}
	return 0;
}

3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513
/* Lock devices from the top of the tree down */
static void pci_slot_lock(struct pci_slot *slot)
{
	struct pci_dev *dev;

	list_for_each_entry(dev, &slot->bus->devices, bus_list) {
		if (!dev->slot || dev->slot != slot)
			continue;
		pci_dev_lock(dev);
		if (dev->subordinate)
			pci_bus_lock(dev->subordinate);
	}
}

/* Unlock devices from the bottom of the tree up */
static void pci_slot_unlock(struct pci_slot *slot)
{
	struct pci_dev *dev;

	list_for_each_entry(dev, &slot->bus->devices, bus_list) {
		if (!dev->slot || dev->slot != slot)
			continue;
		if (dev->subordinate)
			pci_bus_unlock(dev->subordinate);
		pci_dev_unlock(dev);
	}
}

3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544
/* Return 1 on successful lock, 0 on contention */
static int pci_slot_trylock(struct pci_slot *slot)
{
	struct pci_dev *dev;

	list_for_each_entry(dev, &slot->bus->devices, bus_list) {
		if (!dev->slot || dev->slot != slot)
			continue;
		if (!pci_dev_trylock(dev))
			goto unlock;
		if (dev->subordinate) {
			if (!pci_bus_trylock(dev->subordinate)) {
				pci_dev_unlock(dev);
				goto unlock;
			}
		}
	}
	return 1;

unlock:
	list_for_each_entry_continue_reverse(dev,
					     &slot->bus->devices, bus_list) {
		if (!dev->slot || dev->slot != slot)
			continue;
		if (dev->subordinate)
			pci_bus_unlock(dev->subordinate);
		pci_dev_unlock(dev);
	}
	return 0;
}

3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622
/* Save and disable devices from the top of the tree down */
static void pci_bus_save_and_disable(struct pci_bus *bus)
{
	struct pci_dev *dev;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		pci_dev_save_and_disable(dev);
		if (dev->subordinate)
			pci_bus_save_and_disable(dev->subordinate);
	}
}

/*
 * Restore devices from top of the tree down - parent bridges need to be
 * restored before we can get to subordinate devices.
 */
static void pci_bus_restore(struct pci_bus *bus)
{
	struct pci_dev *dev;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		pci_dev_restore(dev);
		if (dev->subordinate)
			pci_bus_restore(dev->subordinate);
	}
}

/* Save and disable devices from the top of the tree down */
static void pci_slot_save_and_disable(struct pci_slot *slot)
{
	struct pci_dev *dev;

	list_for_each_entry(dev, &slot->bus->devices, bus_list) {
		if (!dev->slot || dev->slot != slot)
			continue;
		pci_dev_save_and_disable(dev);
		if (dev->subordinate)
			pci_bus_save_and_disable(dev->subordinate);
	}
}

/*
 * Restore devices from top of the tree down - parent bridges need to be
 * restored before we can get to subordinate devices.
 */
static void pci_slot_restore(struct pci_slot *slot)
{
	struct pci_dev *dev;

	list_for_each_entry(dev, &slot->bus->devices, bus_list) {
		if (!dev->slot || dev->slot != slot)
			continue;
		pci_dev_restore(dev);
		if (dev->subordinate)
			pci_bus_restore(dev->subordinate);
	}
}

static int pci_slot_reset(struct pci_slot *slot, int probe)
{
	int rc;

	if (!slot)
		return -ENOTTY;

	if (!probe)
		pci_slot_lock(slot);

	might_sleep();

	rc = pci_reset_hotplug_slot(slot->hotplug, probe);

	if (!probe)
		pci_slot_unlock(slot);

	return rc;
}

3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634
/**
 * pci_probe_reset_slot - probe whether a PCI slot can be reset
 * @slot: PCI slot to probe
 *
 * Return 0 if slot can be reset, negative if a slot reset is not supported.
 */
int pci_probe_reset_slot(struct pci_slot *slot)
{
	return pci_slot_reset(slot, 1);
}
EXPORT_SYMBOL_GPL(pci_probe_reset_slot);

3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667
/**
 * pci_reset_slot - reset a PCI slot
 * @slot: PCI slot to reset
 *
 * A PCI bus may host multiple slots, each slot may support a reset mechanism
 * independent of other slots.  For instance, some slots may support slot power
 * control.  In the case of a 1:1 bus to slot architecture, this function may
 * wrap the bus reset to avoid spurious slot related events such as hotplug.
 * Generally a slot reset should be attempted before a bus reset.  All of the
 * function of the slot and any subordinate buses behind the slot are reset
 * through this function.  PCI config space of all devices in the slot and
 * behind the slot is saved before and restored after reset.
 *
 * Return 0 on success, non-zero on error.
 */
int pci_reset_slot(struct pci_slot *slot)
{
	int rc;

	rc = pci_slot_reset(slot, 1);
	if (rc)
		return rc;

	pci_slot_save_and_disable(slot);

	rc = pci_slot_reset(slot, 0);

	pci_slot_restore(slot);

	return rc;
}
EXPORT_SYMBOL_GPL(pci_reset_slot);

3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696
/**
 * pci_try_reset_slot - Try to reset a PCI slot
 * @slot: PCI slot to reset
 *
 * Same as above except return -EAGAIN if the slot cannot be locked
 */
int pci_try_reset_slot(struct pci_slot *slot)
{
	int rc;

	rc = pci_slot_reset(slot, 1);
	if (rc)
		return rc;

	pci_slot_save_and_disable(slot);

	if (pci_slot_trylock(slot)) {
		might_sleep();
		rc = pci_reset_hotplug_slot(slot->hotplug, 0);
		pci_slot_unlock(slot);
	} else
		rc = -EAGAIN;

	pci_slot_restore(slot);

	return rc;
}
EXPORT_SYMBOL_GPL(pci_try_reset_slot);

3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715
static int pci_bus_reset(struct pci_bus *bus, int probe)
{
	if (!bus->self)
		return -ENOTTY;

	if (probe)
		return 0;

	pci_bus_lock(bus);

	might_sleep();

	pci_reset_bridge_secondary_bus(bus->self);

	pci_bus_unlock(bus);

	return 0;
}

3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727
/**
 * pci_probe_reset_bus - probe whether a PCI bus can be reset
 * @bus: PCI bus to probe
 *
 * Return 0 if bus can be reset, negative if a bus reset is not supported.
 */
int pci_probe_reset_bus(struct pci_bus *bus)
{
	return pci_bus_reset(bus, 1);
}
EXPORT_SYMBOL_GPL(pci_probe_reset_bus);

3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754
/**
 * pci_reset_bus - reset a PCI bus
 * @bus: top level PCI bus to reset
 *
 * Do a bus reset on the given bus and any subordinate buses, saving
 * and restoring state of all devices.
 *
 * Return 0 on success, non-zero on error.
 */
int pci_reset_bus(struct pci_bus *bus)
{
	int rc;

	rc = pci_bus_reset(bus, 1);
	if (rc)
		return rc;

	pci_bus_save_and_disable(bus);

	rc = pci_bus_reset(bus, 0);

	pci_bus_restore(bus);

	return rc;
}
EXPORT_SYMBOL_GPL(pci_reset_bus);

3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783
/**
 * pci_try_reset_bus - Try to reset a PCI bus
 * @bus: top level PCI bus to reset
 *
 * Same as above except return -EAGAIN if the bus cannot be locked
 */
int pci_try_reset_bus(struct pci_bus *bus)
{
	int rc;

	rc = pci_bus_reset(bus, 1);
	if (rc)
		return rc;

	pci_bus_save_and_disable(bus);

	if (pci_bus_trylock(bus)) {
		might_sleep();
		pci_reset_bridge_secondary_bus(bus->self);
		pci_bus_unlock(bus);
	} else
		rc = -EAGAIN;

	pci_bus_restore(bus);

	return rc;
}
EXPORT_SYMBOL_GPL(pci_try_reset_bus);

3784 3785 3786 3787 3788 3789 3790 3791 3792
/**
 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
 * @dev: PCI device to query
 *
 * Returns mmrbc: maximum designed memory read count in bytes
 *    or appropriate error value.
 */
int pcix_get_max_mmrbc(struct pci_dev *dev)
{
3793
	int cap;
3794 3795 3796 3797 3798 3799
	u32 stat;

	cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
	if (!cap)
		return -EINVAL;

3800
	if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3801 3802
		return -EINVAL;

3803
	return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815
}
EXPORT_SYMBOL(pcix_get_max_mmrbc);

/**
 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
 * @dev: PCI device to query
 *
 * Returns mmrbc: maximum memory read count in bytes
 *    or appropriate error value.
 */
int pcix_get_mmrbc(struct pci_dev *dev)
{
3816
	int cap;
3817
	u16 cmd;
3818 3819 3820 3821 3822

	cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
	if (!cap)
		return -EINVAL;

3823 3824
	if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
		return -EINVAL;
3825

3826
	return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840
}
EXPORT_SYMBOL(pcix_get_mmrbc);

/**
 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
 * @dev: PCI device to query
 * @mmrbc: maximum memory read count in bytes
 *    valid values are 512, 1024, 2048, 4096
 *
 * If possible sets maximum memory read byte count, some bridges have erratas
 * that prevent this.
 */
int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
{
3841
	int cap;
3842 3843
	u32 stat, v, o;
	u16 cmd;
3844

3845
	if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3846
		return -EINVAL;
3847 3848 3849 3850 3851

	v = ffs(mmrbc) - 10;

	cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
	if (!cap)
3852
		return -EINVAL;
3853

3854 3855
	if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
		return -EINVAL;
3856 3857 3858 3859

	if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
		return -E2BIG;

3860 3861
	if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
		return -EINVAL;
3862 3863 3864

	o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
	if (o != v) {
3865
		if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3866 3867 3868 3869
			return -EIO;

		cmd &= ~PCI_X_CMD_MAX_READ;
		cmd |= v << 2;
3870 3871
		if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
			return -EIO;
3872
	}
3873
	return 0;
3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887
}
EXPORT_SYMBOL(pcix_set_mmrbc);

/**
 * pcie_get_readrq - get PCI Express read request size
 * @dev: PCI device to query
 *
 * Returns maximum memory read request in bytes
 *    or appropriate error value.
 */
int pcie_get_readrq(struct pci_dev *dev)
{
	u16 ctl;

3888
	pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3889

3890
	return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3891 3892 3893 3894 3895 3896
}
EXPORT_SYMBOL(pcie_get_readrq);

/**
 * pcie_set_readrq - set PCI Express maximum memory read request
 * @dev: PCI device to query
3897
 * @rq: maximum memory read count in bytes
3898 3899
 *    valid values are 128, 256, 512, 1024, 2048, 4096
 *
3900
 * If possible sets maximum memory read request in bytes
3901 3902 3903
 */
int pcie_set_readrq(struct pci_dev *dev, int rq)
{
3904
	u16 v;
3905

3906
	if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3907
		return -EINVAL;
3908

3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922
	/*
	 * If using the "performance" PCIe config, we clamp the
	 * read rq size to the max packet size to prevent the
	 * host bridge generating requests larger than we can
	 * cope with
	 */
	if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
		int mps = pcie_get_mps(dev);

		if (mps < rq)
			rq = mps;
	}

	v = (ffs(rq) - 8) << 12;
3923

3924 3925
	return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
						  PCI_EXP_DEVCTL_READRQ, v);
3926 3927 3928
}
EXPORT_SYMBOL(pcie_set_readrq);

3929 3930 3931 3932 3933 3934 3935 3936 3937 3938
/**
 * pcie_get_mps - get PCI Express maximum payload size
 * @dev: PCI device to query
 *
 * Returns maximum payload size in bytes
 */
int pcie_get_mps(struct pci_dev *dev)
{
	u16 ctl;

3939
	pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3940

3941
	return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3942
}
3943
EXPORT_SYMBOL(pcie_get_mps);
3944 3945 3946 3947

/**
 * pcie_set_mps - set PCI Express maximum payload size
 * @dev: PCI device to query
3948
 * @mps: maximum payload size in bytes
3949 3950 3951 3952 3953 3954
 *    valid values are 128, 256, 512, 1024, 2048, 4096
 *
 * If possible sets maximum payload size
 */
int pcie_set_mps(struct pci_dev *dev, int mps)
{
3955
	u16 v;
3956 3957

	if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3958
		return -EINVAL;
3959 3960

	v = ffs(mps) - 8;
3961
	if (v > dev->pcie_mpss)
3962
		return -EINVAL;
3963 3964
	v <<= 5;

3965 3966
	return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
						  PCI_EXP_DEVCTL_PAYLOAD, v);
3967
}
3968
EXPORT_SYMBOL(pcie_set_mps);
3969

3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012
/**
 * pcie_get_minimum_link - determine minimum link settings of a PCI device
 * @dev: PCI device to query
 * @speed: storage for minimum speed
 * @width: storage for minimum width
 *
 * This function will walk up the PCI device chain and determine the minimum
 * link width and speed of the device.
 */
int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
			  enum pcie_link_width *width)
{
	int ret;

	*speed = PCI_SPEED_UNKNOWN;
	*width = PCIE_LNK_WIDTH_UNKNOWN;

	while (dev) {
		u16 lnksta;
		enum pci_bus_speed next_speed;
		enum pcie_link_width next_width;

		ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
		if (ret)
			return ret;

		next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
		next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
			PCI_EXP_LNKSTA_NLW_SHIFT;

		if (next_speed < *speed)
			*speed = next_speed;

		if (next_width < *width)
			*width = next_width;

		dev = dev->bus->self;
	}

	return 0;
}
EXPORT_SYMBOL(pcie_get_minimum_link);

4013 4014
/**
 * pci_select_bars - Make BAR mask from the type of resource
4015
 * @dev: the PCI device for which BAR mask is made
4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028
 * @flags: resource type mask to be selected
 *
 * This helper routine makes bar mask from the type of resource.
 */
int pci_select_bars(struct pci_dev *dev, unsigned long flags)
{
	int i, bars = 0;
	for (i = 0; i < PCI_NUM_RESOURCES; i++)
		if (pci_resource_flags(dev, i) & flags)
			bars |= (1 << i);
	return bars;
}

4029 4030 4031 4032 4033 4034 4035 4036 4037 4038
/**
 * pci_resource_bar - get position of the BAR associated with a resource
 * @dev: the PCI device
 * @resno: the resource number
 * @type: the BAR type to be filled in
 *
 * Returns BAR position in config space, or 0 if the BAR is invalid.
 */
int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
{
4039 4040
	int reg;

4041 4042 4043 4044 4045 4046
	if (resno < PCI_ROM_RESOURCE) {
		*type = pci_bar_unknown;
		return PCI_BASE_ADDRESS_0 + 4 * resno;
	} else if (resno == PCI_ROM_RESOURCE) {
		*type = pci_bar_mem32;
		return dev->rom_base_reg;
4047 4048 4049 4050 4051
	} else if (resno < PCI_BRIDGE_RESOURCES) {
		/* device specific resource */
		reg = pci_iov_resource_bar(dev, resno, type);
		if (reg)
			return reg;
4052 4053
	}

4054
	dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
4055 4056 4057
	return 0;
}

4058 4059 4060 4061 4062 4063 4064 4065 4066
/* Some architectures require additional programming to enable VGA */
static arch_set_vga_state_t arch_set_vga_state;

void __init pci_register_set_vga_state(arch_set_vga_state_t func)
{
	arch_set_vga_state = func;	/* NULL disables */
}

static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
4067
		      unsigned int command_bits, u32 flags)
4068 4069 4070
{
	if (arch_set_vga_state)
		return arch_set_vga_state(dev, decode, command_bits,
4071
						flags);
4072 4073 4074
	return 0;
}

4075 4076
/**
 * pci_set_vga_state - set VGA decode state on device and parents if requested
R
Randy Dunlap 已提交
4077 4078 4079
 * @dev: the PCI device
 * @decode: true = enable decoding, false = disable decoding
 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
R
Randy Dunlap 已提交
4080
 * @flags: traverse ancestors and change bridges
4081
 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4082 4083
 */
int pci_set_vga_state(struct pci_dev *dev, bool decode,
4084
		      unsigned int command_bits, u32 flags)
4085 4086 4087 4088
{
	struct pci_bus *bus;
	struct pci_dev *bridge;
	u16 cmd;
4089
	int rc;
4090

4091
	WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4092

4093
	/* ARCH specific VGA enables */
4094
	rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4095 4096 4097
	if (rc)
		return rc;

4098 4099 4100 4101 4102 4103 4104 4105
	if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
		pci_read_config_word(dev, PCI_COMMAND, &cmd);
		if (decode == true)
			cmd |= command_bits;
		else
			cmd &= ~command_bits;
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
4106

4107
	if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127
		return 0;

	bus = dev->bus;
	while (bus) {
		bridge = bus->self;
		if (bridge) {
			pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
					     &cmd);
			if (decode == true)
				cmd |= PCI_BRIDGE_CTL_VGA;
			else
				cmd &= ~PCI_BRIDGE_CTL_VGA;
			pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
					      cmd);
		}
		bus = bus->parent;
	}
	return 0;
}

4128 4129 4130 4131 4132 4133 4134 4135
bool pci_device_is_present(struct pci_dev *pdev)
{
	u32 v;

	return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
}
EXPORT_SYMBOL_GPL(pci_device_is_present);

4136 4137
#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
4138
static DEFINE_SPINLOCK(resource_alignment_lock);
4139 4140 4141 4142 4143 4144 4145 4146

/**
 * pci_specified_resource_alignment - get resource alignment specified by user.
 * @dev: the PCI device to get
 *
 * RETURNS: Resource alignment if it is specified.
 *          Zero if it is not specified.
 */
4147
static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196
{
	int seg, bus, slot, func, align_order, count;
	resource_size_t align = 0;
	char *p;

	spin_lock(&resource_alignment_lock);
	p = resource_alignment_param;
	while (*p) {
		count = 0;
		if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
							p[count] == '@') {
			p += count + 1;
		} else {
			align_order = -1;
		}
		if (sscanf(p, "%x:%x:%x.%x%n",
			&seg, &bus, &slot, &func, &count) != 4) {
			seg = 0;
			if (sscanf(p, "%x:%x.%x%n",
					&bus, &slot, &func, &count) != 3) {
				/* Invalid format */
				printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
					p);
				break;
			}
		}
		p += count;
		if (seg == pci_domain_nr(dev->bus) &&
			bus == dev->bus->number &&
			slot == PCI_SLOT(dev->devfn) &&
			func == PCI_FUNC(dev->devfn)) {
			if (align_order == -1) {
				align = PAGE_SIZE;
			} else {
				align = 1 << align_order;
			}
			/* Found */
			break;
		}
		if (*p != ';' && *p != ',') {
			/* End of param or invalid format */
			break;
		}
		p++;
	}
	spin_unlock(&resource_alignment_lock);
	return align;
}

4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210
/*
 * This function disables memory decoding and releases memory resources
 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
 * It also rounds up size to specified alignment.
 * Later on, the kernel will assign page-aligned memory resource back
 * to the device.
 */
void pci_reassigndev_resource_alignment(struct pci_dev *dev)
{
	int i;
	struct resource *r;
	resource_size_t align, size;
	u16 command;

Y
Yinghai Lu 已提交
4211 4212 4213
	/* check if specified PCI is target device to reassign */
	align = pci_specified_resource_alignment(dev);
	if (!align)
4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259
		return;

	if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
	    (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
		dev_warn(&dev->dev,
			"Can't reassign resources to host bridge.\n");
		return;
	}

	dev_info(&dev->dev,
		"Disabling memory decoding and releasing memory resources.\n");
	pci_read_config_word(dev, PCI_COMMAND, &command);
	command &= ~PCI_COMMAND_MEMORY;
	pci_write_config_word(dev, PCI_COMMAND, command);

	for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
		r = &dev->resource[i];
		if (!(r->flags & IORESOURCE_MEM))
			continue;
		size = resource_size(r);
		if (size < align) {
			size = align;
			dev_info(&dev->dev,
				"Rounding up size of resource #%d to %#llx.\n",
				i, (unsigned long long)size);
		}
		r->end = size - 1;
		r->start = 0;
	}
	/* Need to disable bridge's resource window,
	 * to enable the kernel to reassign new resource
	 * window later on.
	 */
	if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
	    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
		for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
			r = &dev->resource[i];
			if (!(r->flags & IORESOURCE_MEM))
				continue;
			r->end = resource_size(r) - 1;
			r->start = 0;
		}
		pci_disable_bridge_window(dev);
	}
}

4260
static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
4261 4262 4263 4264 4265 4266 4267 4268 4269 4270
{
	if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
		count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
	spin_lock(&resource_alignment_lock);
	strncpy(resource_alignment_param, buf, count);
	resource_alignment_param[count] = '\0';
	spin_unlock(&resource_alignment_lock);
	return count;
}

4271
static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301
{
	size_t count;
	spin_lock(&resource_alignment_lock);
	count = snprintf(buf, size, "%s", resource_alignment_param);
	spin_unlock(&resource_alignment_lock);
	return count;
}

static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
{
	return pci_get_resource_alignment_param(buf, PAGE_SIZE);
}

static ssize_t pci_resource_alignment_store(struct bus_type *bus,
					const char *buf, size_t count)
{
	return pci_set_resource_alignment_param(buf, count);
}

BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
					pci_resource_alignment_store);

static int __init pci_resource_alignment_sysfs_init(void)
{
	return bus_create_file(&pci_bus_type,
					&bus_attr_resource_alignment);
}

late_initcall(pci_resource_alignment_sysfs_init);

B
Bill Pemberton 已提交
4302
static void pci_no_domains(void)
4303 4304 4305 4306 4307 4308
{
#ifdef CONFIG_PCI_DOMAINS
	pci_domains_supported = 0;
#endif
}

4309
/**
4310
 * pci_ext_cfg_avail - can we access extended PCI config space?
4311 4312 4313 4314 4315
 *
 * Returns 1 if we can access PCI extended config space (offsets
 * greater than 0xff). This is the default implementation. Architecture
 * implementations can override this.
 */
4316
int __weak pci_ext_cfg_avail(void)
4317 4318 4319 4320
{
	return 1;
}

4321 4322 4323 4324 4325
void __weak pci_fixup_cardbus(struct pci_bus *bus)
{
}
EXPORT_SYMBOL(pci_fixup_cardbus);

A
Al Viro 已提交
4326
static int __init pci_setup(char *str)
L
Linus Torvalds 已提交
4327 4328 4329 4330 4331 4332
{
	while (str) {
		char *k = strchr(str, ',');
		if (k)
			*k++ = 0;
		if (*str && (str = pcibios_setup(str)) && *str) {
4333 4334
			if (!strcmp(str, "nomsi")) {
				pci_no_msi();
R
Randy Dunlap 已提交
4335 4336
			} else if (!strcmp(str, "noaer")) {
				pci_no_aer();
4337 4338
			} else if (!strncmp(str, "realloc=", 8)) {
				pci_realloc_get_opt(str + 8);
4339
			} else if (!strncmp(str, "realloc", 7)) {
4340
				pci_realloc_get_opt("on");
4341 4342
			} else if (!strcmp(str, "nodomains")) {
				pci_no_domains();
4343 4344
			} else if (!strncmp(str, "noari", 5)) {
				pcie_ari_disabled = true;
4345 4346 4347 4348
			} else if (!strncmp(str, "cbiosize=", 9)) {
				pci_cardbus_io_size = memparse(str + 9, &str);
			} else if (!strncmp(str, "cbmemsize=", 10)) {
				pci_cardbus_mem_size = memparse(str + 10, &str);
4349 4350 4351
			} else if (!strncmp(str, "resource_alignment=", 19)) {
				pci_set_resource_alignment_param(str + 19,
							strlen(str + 19));
4352 4353
			} else if (!strncmp(str, "ecrc=", 5)) {
				pcie_ecrc_get_policy(str + 5);
4354 4355 4356 4357
			} else if (!strncmp(str, "hpiosize=", 9)) {
				pci_hotplug_io_size = memparse(str + 9, &str);
			} else if (!strncmp(str, "hpmemsize=", 10)) {
				pci_hotplug_mem_size = memparse(str + 10, &str);
4358 4359
			} else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
				pcie_bus_config = PCIE_BUS_TUNE_OFF;
4360 4361 4362 4363
			} else if (!strncmp(str, "pcie_bus_safe", 13)) {
				pcie_bus_config = PCIE_BUS_SAFE;
			} else if (!strncmp(str, "pcie_bus_perf", 13)) {
				pcie_bus_config = PCIE_BUS_PERFORMANCE;
4364 4365
			} else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
				pcie_bus_config = PCIE_BUS_PEER2PEER;
4366 4367
			} else if (!strncmp(str, "pcie_scan_all", 13)) {
				pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
4368 4369 4370 4371
			} else {
				printk(KERN_ERR "PCI: Unknown option `%s'\n",
						str);
			}
L
Linus Torvalds 已提交
4372 4373 4374
		}
		str = k;
	}
4375
	return 0;
L
Linus Torvalds 已提交
4376
}
4377
early_param("pci", pci_setup);
L
Linus Torvalds 已提交
4378

4379
EXPORT_SYMBOL(pci_reenable_device);
4380 4381
EXPORT_SYMBOL(pci_enable_device_io);
EXPORT_SYMBOL(pci_enable_device_mem);
L
Linus Torvalds 已提交
4382
EXPORT_SYMBOL(pci_enable_device);
T
Tejun Heo 已提交
4383 4384
EXPORT_SYMBOL(pcim_enable_device);
EXPORT_SYMBOL(pcim_pin_device);
L
Linus Torvalds 已提交
4385 4386 4387 4388 4389
EXPORT_SYMBOL(pci_disable_device);
EXPORT_SYMBOL(pci_find_capability);
EXPORT_SYMBOL(pci_bus_find_capability);
EXPORT_SYMBOL(pci_release_regions);
EXPORT_SYMBOL(pci_request_regions);
4390
EXPORT_SYMBOL(pci_request_regions_exclusive);
L
Linus Torvalds 已提交
4391 4392
EXPORT_SYMBOL(pci_release_region);
EXPORT_SYMBOL(pci_request_region);
4393
EXPORT_SYMBOL(pci_request_region_exclusive);
4394 4395
EXPORT_SYMBOL(pci_release_selected_regions);
EXPORT_SYMBOL(pci_request_selected_regions);
4396
EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
L
Linus Torvalds 已提交
4397
EXPORT_SYMBOL(pci_set_master);
4398
EXPORT_SYMBOL(pci_clear_master);
L
Linus Torvalds 已提交
4399
EXPORT_SYMBOL(pci_set_mwi);
R
Randy Dunlap 已提交
4400
EXPORT_SYMBOL(pci_try_set_mwi);
L
Linus Torvalds 已提交
4401
EXPORT_SYMBOL(pci_clear_mwi);
B
Brett M Russ 已提交
4402
EXPORT_SYMBOL_GPL(pci_intx);
L
Linus Torvalds 已提交
4403 4404
EXPORT_SYMBOL(pci_assign_resource);
EXPORT_SYMBOL(pci_find_parent_resource);
4405
EXPORT_SYMBOL(pci_select_bars);
L
Linus Torvalds 已提交
4406 4407 4408 4409

EXPORT_SYMBOL(pci_set_power_state);
EXPORT_SYMBOL(pci_save_state);
EXPORT_SYMBOL(pci_restore_state);
4410
EXPORT_SYMBOL(pci_pme_capable);
4411
EXPORT_SYMBOL(pci_pme_active);
4412
EXPORT_SYMBOL(pci_wake_from_d3);
4413 4414
EXPORT_SYMBOL(pci_prepare_to_sleep);
EXPORT_SYMBOL(pci_back_from_sleep);
B
Brian King 已提交
4415
EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);