sh_eth.c 78.5 KB
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Sergei Shtylyov 已提交
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/*  SuperH Ethernet device driver
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 *
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 *  Copyright (C) 2014 Renesas Electronics Corporation
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 *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
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 *  Copyright (C) 2008-2014 Renesas Solutions Corp.
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 *  Copyright (C) 2013-2017 Cogent Embedded, Inc.
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Ben Dooks 已提交
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 *  Copyright (C) 2014 Codethink Limited
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 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms and conditions of the GNU General Public License,
 *  version 2, as published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 *  more details.
 *
 *  The full GNU General Public License is included in this distribution in
 *  the file called "COPYING".
 */

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Yoshihiro Shimoda 已提交
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#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/mdio-bitbang.h>
#include <linux/netdevice.h>
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#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/of_net.h>
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#include <linux/phy.h>
#include <linux/cache.h>
#include <linux/io.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/ethtool.h>
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#include <linux/if_vlan.h>
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#include <linux/clk.h>
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#include <linux/sh_eth.h>
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#include <linux/of_mdio.h>
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#include "sh_eth.h"

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#define SH_ETH_DEF_MSG_ENABLE \
		(NETIF_MSG_LINK	| \
		NETIF_MSG_TIMER	| \
		NETIF_MSG_RX_ERR| \
		NETIF_MSG_TX_ERR)

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#define SH_ETH_OFFSET_INVALID	((u16)~0)

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#define SH_ETH_OFFSET_DEFAULTS			\
	[0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID

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static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
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	SH_ETH_OFFSET_DEFAULTS,

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	[EDSR]		= 0x0000,
	[EDMR]		= 0x0400,
	[EDTRR]		= 0x0408,
	[EDRRR]		= 0x0410,
	[EESR]		= 0x0428,
	[EESIPR]	= 0x0430,
	[TDLAR]		= 0x0010,
	[TDFAR]		= 0x0014,
	[TDFXR]		= 0x0018,
	[TDFFR]		= 0x001c,
	[RDLAR]		= 0x0030,
	[RDFAR]		= 0x0034,
	[RDFXR]		= 0x0038,
	[RDFFR]		= 0x003c,
	[TRSCER]	= 0x0438,
	[RMFCR]		= 0x0440,
	[TFTR]		= 0x0448,
	[FDR]		= 0x0450,
	[RMCR]		= 0x0458,
	[RPADIR]	= 0x0460,
	[FCFTR]		= 0x0468,
	[CSMR]		= 0x04E4,

	[ECMR]		= 0x0500,
	[ECSR]		= 0x0510,
	[ECSIPR]	= 0x0518,
	[PIR]		= 0x0520,
	[PSR]		= 0x0528,
	[PIPR]		= 0x052c,
	[RFLR]		= 0x0508,
	[APR]		= 0x0554,
	[MPR]		= 0x0558,
	[PFTCR]		= 0x055c,
	[PFRCR]		= 0x0560,
	[TPAUSER]	= 0x0564,
	[GECMR]		= 0x05b0,
	[BCULR]		= 0x05b4,
	[MAHR]		= 0x05c0,
	[MALR]		= 0x05c8,
	[TROCR]		= 0x0700,
	[CDCR]		= 0x0708,
	[LCCR]		= 0x0710,
	[CEFCR]		= 0x0740,
	[FRECR]		= 0x0748,
	[TSFRCR]	= 0x0750,
	[TLFRCR]	= 0x0758,
	[RFCR]		= 0x0760,
	[CERCR]		= 0x0768,
	[CEECR]		= 0x0770,
	[MAFCR]		= 0x0778,
	[RMII_MII]	= 0x0790,

	[ARSTR]		= 0x0000,
	[TSU_CTRST]	= 0x0004,
	[TSU_FWEN0]	= 0x0010,
	[TSU_FWEN1]	= 0x0014,
	[TSU_FCM]	= 0x0018,
	[TSU_BSYSL0]	= 0x0020,
	[TSU_BSYSL1]	= 0x0024,
	[TSU_PRISL0]	= 0x0028,
	[TSU_PRISL1]	= 0x002c,
	[TSU_FWSL0]	= 0x0030,
	[TSU_FWSL1]	= 0x0034,
	[TSU_FWSLC]	= 0x0038,
	[TSU_QTAG0]	= 0x0040,
	[TSU_QTAG1]	= 0x0044,
	[TSU_FWSR]	= 0x0050,
	[TSU_FWINMK]	= 0x0054,
	[TSU_ADQT0]	= 0x0048,
	[TSU_ADQT1]	= 0x004c,
	[TSU_VTAG0]	= 0x0058,
	[TSU_VTAG1]	= 0x005c,
	[TSU_ADSBSY]	= 0x0060,
	[TSU_TEN]	= 0x0064,
	[TSU_POST1]	= 0x0070,
	[TSU_POST2]	= 0x0074,
	[TSU_POST3]	= 0x0078,
	[TSU_POST4]	= 0x007c,
	[TSU_ADRH0]	= 0x0100,

	[TXNLCR0]	= 0x0080,
	[TXALCR0]	= 0x0084,
	[RXNLCR0]	= 0x0088,
	[RXALCR0]	= 0x008c,
	[FWNLCR0]	= 0x0090,
	[FWALCR0]	= 0x0094,
	[TXNLCR1]	= 0x00a0,
	[TXALCR1]	= 0x00a0,
	[RXNLCR1]	= 0x00a8,
	[RXALCR1]	= 0x00ac,
	[FWNLCR1]	= 0x00b0,
	[FWALCR1]	= 0x00b4,
};

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static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
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	SH_ETH_OFFSET_DEFAULTS,

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	[EDSR]		= 0x0000,
	[EDMR]		= 0x0400,
	[EDTRR]		= 0x0408,
	[EDRRR]		= 0x0410,
	[EESR]		= 0x0428,
	[EESIPR]	= 0x0430,
	[TDLAR]		= 0x0010,
	[TDFAR]		= 0x0014,
	[TDFXR]		= 0x0018,
	[TDFFR]		= 0x001c,
	[RDLAR]		= 0x0030,
	[RDFAR]		= 0x0034,
	[RDFXR]		= 0x0038,
	[RDFFR]		= 0x003c,
	[TRSCER]	= 0x0438,
	[RMFCR]		= 0x0440,
	[TFTR]		= 0x0448,
	[FDR]		= 0x0450,
	[RMCR]		= 0x0458,
	[RPADIR]	= 0x0460,
	[FCFTR]		= 0x0468,
	[CSMR]		= 0x04E4,

	[ECMR]		= 0x0500,
	[RFLR]		= 0x0508,
	[ECSR]		= 0x0510,
	[ECSIPR]	= 0x0518,
	[PIR]		= 0x0520,
	[APR]		= 0x0554,
	[MPR]		= 0x0558,
	[PFTCR]		= 0x055c,
	[PFRCR]		= 0x0560,
	[TPAUSER]	= 0x0564,
	[MAHR]		= 0x05c0,
	[MALR]		= 0x05c8,
	[CEFCR]		= 0x0740,
	[FRECR]		= 0x0748,
	[TSFRCR]	= 0x0750,
	[TLFRCR]	= 0x0758,
	[RFCR]		= 0x0760,
	[MAFCR]		= 0x0778,

	[ARSTR]		= 0x0000,
	[TSU_CTRST]	= 0x0004,
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	[TSU_FWSLC]	= 0x0038,
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	[TSU_VTAG0]	= 0x0058,
	[TSU_ADSBSY]	= 0x0060,
	[TSU_TEN]	= 0x0064,
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	[TSU_POST1]	= 0x0070,
	[TSU_POST2]	= 0x0074,
	[TSU_POST3]	= 0x0078,
	[TSU_POST4]	= 0x007c,
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	[TSU_ADRH0]	= 0x0100,

	[TXNLCR0]	= 0x0080,
	[TXALCR0]	= 0x0084,
	[RXNLCR0]	= 0x0088,
	[RXALCR0]	= 0x008C,
};

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static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
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	SH_ETH_OFFSET_DEFAULTS,

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	[ECMR]		= 0x0300,
	[RFLR]		= 0x0308,
	[ECSR]		= 0x0310,
	[ECSIPR]	= 0x0318,
	[PIR]		= 0x0320,
	[PSR]		= 0x0328,
	[RDMLR]		= 0x0340,
	[IPGR]		= 0x0350,
	[APR]		= 0x0354,
	[MPR]		= 0x0358,
	[RFCF]		= 0x0360,
	[TPAUSER]	= 0x0364,
	[TPAUSECR]	= 0x0368,
	[MAHR]		= 0x03c0,
	[MALR]		= 0x03c8,
	[TROCR]		= 0x03d0,
	[CDCR]		= 0x03d4,
	[LCCR]		= 0x03d8,
	[CNDCR]		= 0x03dc,
	[CEFCR]		= 0x03e4,
	[FRECR]		= 0x03e8,
	[TSFRCR]	= 0x03ec,
	[TLFRCR]	= 0x03f0,
	[RFCR]		= 0x03f4,
	[MAFCR]		= 0x03f8,

	[EDMR]		= 0x0200,
	[EDTRR]		= 0x0208,
	[EDRRR]		= 0x0210,
	[TDLAR]		= 0x0218,
	[RDLAR]		= 0x0220,
	[EESR]		= 0x0228,
	[EESIPR]	= 0x0230,
	[TRSCER]	= 0x0238,
	[RMFCR]		= 0x0240,
	[TFTR]		= 0x0248,
	[FDR]		= 0x0250,
	[RMCR]		= 0x0258,
	[TFUCR]		= 0x0264,
	[RFOCR]		= 0x0268,
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	[RMIIMODE]      = 0x026c,
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	[FCFTR]		= 0x0270,
	[TRIMD]		= 0x027c,
};

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static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
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	SH_ETH_OFFSET_DEFAULTS,

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	[ECMR]		= 0x0100,
	[RFLR]		= 0x0108,
	[ECSR]		= 0x0110,
	[ECSIPR]	= 0x0118,
	[PIR]		= 0x0120,
	[PSR]		= 0x0128,
	[RDMLR]		= 0x0140,
	[IPGR]		= 0x0150,
	[APR]		= 0x0154,
	[MPR]		= 0x0158,
	[TPAUSER]	= 0x0164,
	[RFCF]		= 0x0160,
	[TPAUSECR]	= 0x0168,
	[BCFRR]		= 0x016c,
	[MAHR]		= 0x01c0,
	[MALR]		= 0x01c8,
	[TROCR]		= 0x01d0,
	[CDCR]		= 0x01d4,
	[LCCR]		= 0x01d8,
	[CNDCR]		= 0x01dc,
	[CEFCR]		= 0x01e4,
	[FRECR]		= 0x01e8,
	[TSFRCR]	= 0x01ec,
	[TLFRCR]	= 0x01f0,
	[RFCR]		= 0x01f4,
	[MAFCR]		= 0x01f8,
	[RTRATE]	= 0x01fc,

	[EDMR]		= 0x0000,
	[EDTRR]		= 0x0008,
	[EDRRR]		= 0x0010,
	[TDLAR]		= 0x0018,
	[RDLAR]		= 0x0020,
	[EESR]		= 0x0028,
	[EESIPR]	= 0x0030,
	[TRSCER]	= 0x0038,
	[RMFCR]		= 0x0040,
	[TFTR]		= 0x0048,
	[FDR]		= 0x0050,
	[RMCR]		= 0x0058,
	[TFUCR]		= 0x0064,
	[RFOCR]		= 0x0068,
	[FCFTR]		= 0x0070,
	[RPADIR]	= 0x0078,
	[TRIMD]		= 0x007c,
	[RBWAR]		= 0x00c8,
	[RDFAR]		= 0x00cc,
	[TBRAR]		= 0x00d4,
	[TDFAR]		= 0x00d8,
};

static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
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	SH_ETH_OFFSET_DEFAULTS,

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	[EDMR]		= 0x0000,
	[EDTRR]		= 0x0004,
	[EDRRR]		= 0x0008,
	[TDLAR]		= 0x000c,
	[RDLAR]		= 0x0010,
	[EESR]		= 0x0014,
	[EESIPR]	= 0x0018,
	[TRSCER]	= 0x001c,
	[RMFCR]		= 0x0020,
	[TFTR]		= 0x0024,
	[FDR]		= 0x0028,
	[RMCR]		= 0x002c,
	[EDOCR]		= 0x0030,
	[FCFTR]		= 0x0034,
	[RPADIR]	= 0x0038,
	[TRIMD]		= 0x003c,
	[RBWAR]		= 0x0040,
	[RDFAR]		= 0x0044,
	[TBRAR]		= 0x004c,
	[TDFAR]		= 0x0050,

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	[ECMR]		= 0x0160,
	[ECSR]		= 0x0164,
	[ECSIPR]	= 0x0168,
	[PIR]		= 0x016c,
	[MAHR]		= 0x0170,
	[MALR]		= 0x0174,
	[RFLR]		= 0x0178,
	[PSR]		= 0x017c,
	[TROCR]		= 0x0180,
	[CDCR]		= 0x0184,
	[LCCR]		= 0x0188,
	[CNDCR]		= 0x018c,
	[CEFCR]		= 0x0194,
	[FRECR]		= 0x0198,
	[TSFRCR]	= 0x019c,
	[TLFRCR]	= 0x01a0,
	[RFCR]		= 0x01a4,
	[MAFCR]		= 0x01a8,
	[IPGR]		= 0x01b4,
	[APR]		= 0x01b8,
	[MPR]		= 0x01bc,
	[TPAUSER]	= 0x01c4,
	[BCFR]		= 0x01cc,

	[ARSTR]		= 0x0000,
	[TSU_CTRST]	= 0x0004,
	[TSU_FWEN0]	= 0x0010,
	[TSU_FWEN1]	= 0x0014,
	[TSU_FCM]	= 0x0018,
	[TSU_BSYSL0]	= 0x0020,
	[TSU_BSYSL1]	= 0x0024,
	[TSU_PRISL0]	= 0x0028,
	[TSU_PRISL1]	= 0x002c,
	[TSU_FWSL0]	= 0x0030,
	[TSU_FWSL1]	= 0x0034,
	[TSU_FWSLC]	= 0x0038,
	[TSU_QTAGM0]	= 0x0040,
	[TSU_QTAGM1]	= 0x0044,
	[TSU_ADQT0]	= 0x0048,
	[TSU_ADQT1]	= 0x004c,
	[TSU_FWSR]	= 0x0050,
	[TSU_FWINMK]	= 0x0054,
	[TSU_ADSBSY]	= 0x0060,
	[TSU_TEN]	= 0x0064,
	[TSU_POST1]	= 0x0070,
	[TSU_POST2]	= 0x0074,
	[TSU_POST3]	= 0x0078,
	[TSU_POST4]	= 0x007c,

	[TXNLCR0]	= 0x0080,
	[TXALCR0]	= 0x0084,
	[RXNLCR0]	= 0x0088,
	[RXALCR0]	= 0x008c,
	[FWNLCR0]	= 0x0090,
	[FWALCR0]	= 0x0094,
	[TXNLCR1]	= 0x00a0,
	[TXALCR1]	= 0x00a0,
	[RXNLCR1]	= 0x00a8,
	[RXALCR1]	= 0x00ac,
	[FWNLCR1]	= 0x00b0,
	[FWALCR1]	= 0x00b4,

	[TSU_ADRH0]	= 0x0100,
};

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static void sh_eth_rcv_snd_disable(struct net_device *ndev);
static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);

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static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u16 offset = mdp->reg_offset[enum_index];

	if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
		return;

	iowrite32(data, mdp->addr + offset);
}

static u32 sh_eth_read(struct net_device *ndev, int enum_index)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u16 offset = mdp->reg_offset[enum_index];

	if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
		return ~0U;

	return ioread32(mdp->addr + offset);
}

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static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
			  u32 set)
{
	sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
		     enum_index);
}

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static bool sh_eth_is_gether(struct sh_eth_private *mdp)
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{
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	return mdp->reg_offset == sh_eth_offset_gigabit;
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}

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static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
{
	return mdp->reg_offset == sh_eth_offset_fast_rz;
}

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static void sh_eth_select_mii(struct net_device *ndev)
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{
	struct sh_eth_private *mdp = netdev_priv(ndev);
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	u32 value;
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	switch (mdp->phy_interface) {
	case PHY_INTERFACE_MODE_GMII:
		value = 0x2;
		break;
	case PHY_INTERFACE_MODE_MII:
		value = 0x1;
		break;
	case PHY_INTERFACE_MODE_RMII:
		value = 0x0;
		break;
	default:
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		netdev_warn(ndev,
			    "PHY interface mode was not setup. Set to MII.\n");
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		value = 0x1;
		break;
	}

	sh_eth_write(ndev, value, RMII_MII);
}

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static void sh_eth_set_duplex(struct net_device *ndev)
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{
	struct sh_eth_private *mdp = netdev_priv(ndev);

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	sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
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}

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static void sh_eth_chip_reset(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	/* reset device */
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	sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
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	mdelay(1);
}

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static void sh_eth_set_rate_gether(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	switch (mdp->speed) {
	case 10: /* 10BASE */
		sh_eth_write(ndev, GECMR_10, GECMR);
		break;
	case 100:/* 100BASE */
		sh_eth_write(ndev, GECMR_100, GECMR);
		break;
	case 1000: /* 1000BASE */
		sh_eth_write(ndev, GECMR_1000, GECMR);
		break;
	}
}

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#ifdef CONFIG_OF
/* R7S72100 */
static struct sh_eth_cpu_data r7s72100_data = {
	.chip_reset	= sh_eth_chip_reset,
	.set_duplex	= sh_eth_set_duplex,

	.register_type	= SH_ETH_REG_FAST_RZ,

	.ecsr_value	= ECSR_ICD,
	.ecsipr_value	= ECSIPR_ICDIP,
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	.eesipr_value	= 0xe77f009f,
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	.tx_check	= EESR_TC1 | EESR_FTC,
	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
			  EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
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			  EESR_TDE,
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	.fdr_value	= 0x0000070f,

	.no_psr		= 1,
	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
	.rpadir		= 1,
	.rpadir_value   = 2 << 16,
	.no_trimd	= 1,
	.no_ade		= 1,
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	.hw_checksum	= 1,
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	.tsu		= 1,
};
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static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
{
544
	sh_eth_chip_reset(ndev);
545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563

	sh_eth_select_mii(ndev);
}

/* R8A7740 */
static struct sh_eth_cpu_data r8a7740_data = {
	.chip_reset	= sh_eth_chip_reset_r8a7740,
	.set_duplex	= sh_eth_set_duplex,
	.set_rate	= sh_eth_set_rate_gether,

	.register_type	= SH_ETH_REG_GIGABIT,

	.ecsr_value	= ECSR_ICD | ECSR_MPD,
	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.tx_check	= EESR_TC1 | EESR_FTC,
	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
			  EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
564
			  EESR_TDE,
565 566 567 568 569 570 571 572 573 574 575
	.fdr_value	= 0x0000070f,

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.bculr		= 1,
	.hw_swap	= 1,
	.rpadir		= 1,
	.rpadir_value   = 2 << 16,
	.no_trimd	= 1,
	.no_ade		= 1,
576
	.hw_checksum	= 1,
577 578
	.tsu		= 1,
	.select_mii	= 1,
579
	.magic		= 1,
580
};
581

582
/* There is CPU dependent code */
583
static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
584 585
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
586

587 588
	switch (mdp->speed) {
	case 10: /* 10BASE */
589
		sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
590 591
		break;
	case 100:/* 100BASE */
592
		sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
593 594 595 596
		break;
	}
}

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597
/* R8A7778/9 */
598
static struct sh_eth_cpu_data r8a777x_data = {
599
	.set_duplex	= sh_eth_set_duplex,
600
	.set_rate	= sh_eth_set_rate_r8a777x,
601

602 603
	.register_type	= SH_ETH_REG_FAST_RCAR,

604 605 606 607 608
	.ecsr_value	= ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
	.ecsipr_value	= ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
	.eesipr_value	= 0x01ff009f,

	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
609
	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
610
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
611
	.fdr_value	= 0x00000f0f,
612 613 614 615 616 617 618

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
};

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619 620
/* R8A7790/1 */
static struct sh_eth_cpu_data r8a779x_data = {
621 622 623
	.set_duplex	= sh_eth_set_duplex,
	.set_rate	= sh_eth_set_rate_r8a777x,

624 625
	.register_type	= SH_ETH_REG_FAST_RCAR,

626 627 628
	.ecsr_value	= ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
	.ecsipr_value	= ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
			  ECSIPR_MPDIP,
629 630 631
	.eesipr_value	= 0x01ff009f,

	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
632
	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
633
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
634
	.fdr_value	= 0x00000f0f,
635

636 637
	.trscer_err_mask = DESC_I_RINT8,

638 639 640 641 642
	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
	.rmiimode	= 1,
643
	.magic		= 1,
644
};
645
#endif /* CONFIG_OF */
646

647
static void sh_eth_set_rate_sh7724(struct net_device *ndev)
648 649
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
650 651 652

	switch (mdp->speed) {
	case 10: /* 10BASE */
653
		sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
654 655
		break;
	case 100:/* 100BASE */
656
		sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
657 658 659 660 661
		break;
	}
}

/* SH7724 */
662
static struct sh_eth_cpu_data sh7724_data = {
663
	.set_duplex	= sh_eth_set_duplex,
664
	.set_rate	= sh_eth_set_rate_sh7724,
665

666 667
	.register_type	= SH_ETH_REG_FAST_SH4,

668 669
	.ecsr_value	= ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
	.ecsipr_value	= ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
670
	.eesipr_value	= 0x01ff009f,
671 672

	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
673
	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
674
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
675 676 677 678 679

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
680 681
	.rpadir		= 1,
	.rpadir_value	= 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
682
};
683

684
static void sh_eth_set_rate_sh7757(struct net_device *ndev)
685 686 687 688 689
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	switch (mdp->speed) {
	case 10: /* 10BASE */
690
		sh_eth_write(ndev, 0, RTRATE);
691 692
		break;
	case 100:/* 100BASE */
693
		sh_eth_write(ndev, 1, RTRATE);
694 695 696 697 698
		break;
	}
}

/* SH7757 */
699 700 701
static struct sh_eth_cpu_data sh7757_data = {
	.set_duplex	= sh_eth_set_duplex,
	.set_rate	= sh_eth_set_rate_sh7757,
702

703 704
	.register_type	= SH_ETH_REG_FAST_SH4,

705 706 707
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
708
	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
709
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
710

711
	.irq_flags	= IRQF_SHARED,
712 713 714 715 716
	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
	.no_ade		= 1,
717 718
	.rpadir		= 1,
	.rpadir_value   = 2 << 16,
719
	.rtrate		= 1,
720
};
721

722
#define SH_GIGA_ETH_BASE	0xfee00000UL
723 724 725 726
#define GIGA_MALR(port)		(SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
#define GIGA_MAHR(port)		(SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
static void sh_eth_chip_reset_giga(struct net_device *ndev)
{
727
	u32 mahr[2], malr[2];
728
	int i;
729 730 731

	/* save MAHR and MALR */
	for (i = 0; i < 2; i++) {
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Yoshihiro Shimoda 已提交
732 733
		malr[i] = ioread32((void *)GIGA_MALR(i));
		mahr[i] = ioread32((void *)GIGA_MAHR(i));
734 735
	}

736
	sh_eth_chip_reset(ndev);
737 738 739

	/* restore MAHR and MALR */
	for (i = 0; i < 2; i++) {
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740 741
		iowrite32(malr[i], (void *)GIGA_MALR(i));
		iowrite32(mahr[i], (void *)GIGA_MAHR(i));
742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762
	}
}

static void sh_eth_set_rate_giga(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	switch (mdp->speed) {
	case 10: /* 10BASE */
		sh_eth_write(ndev, 0x00000000, GECMR);
		break;
	case 100:/* 100BASE */
		sh_eth_write(ndev, 0x00000010, GECMR);
		break;
	case 1000: /* 1000BASE */
		sh_eth_write(ndev, 0x00000020, GECMR);
		break;
	}
}

/* SH7757(GETHERC) */
763
static struct sh_eth_cpu_data sh7757_data_giga = {
764
	.chip_reset	= sh_eth_chip_reset_giga,
765
	.set_duplex	= sh_eth_set_duplex,
766 767
	.set_rate	= sh_eth_set_rate_giga,

768 769
	.register_type	= SH_ETH_REG_GIGABIT,

770 771 772 773 774
	.ecsr_value	= ECSR_ICD | ECSR_MPD,
	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.tx_check	= EESR_TC1 | EESR_FTC,
775 776
	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
			  EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
777
			  EESR_TDE,
778 779
	.fdr_value	= 0x0000072f,

780
	.irq_flags	= IRQF_SHARED,
781 782 783 784 785 786 787 788 789
	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.bculr		= 1,
	.hw_swap	= 1,
	.rpadir		= 1,
	.rpadir_value   = 2 << 16,
	.no_trimd	= 1,
	.no_ade		= 1,
790
	.tsu		= 1,
791 792
};

793 794
/* SH7734 */
static struct sh_eth_cpu_data sh7734_data = {
795 796
	.chip_reset	= sh_eth_chip_reset,
	.set_duplex	= sh_eth_set_duplex,
797 798
	.set_rate	= sh_eth_set_rate_gether,

799 800
	.register_type	= SH_ETH_REG_GIGABIT,

801 802
	.ecsr_value	= ECSR_ICD | ECSR_MPD,
	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
803
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff,
804 805

	.tx_check	= EESR_TC1 | EESR_FTC,
806 807
	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
			  EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
808
			  EESR_TDE,
809 810 811 812 813 814 815 816 817

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.bculr		= 1,
	.hw_swap	= 1,
	.no_trimd	= 1,
	.no_ade		= 1,
	.tsu		= 1,
818
	.hw_checksum	= 1,
819
	.select_mii	= 1,
820
	.magic		= 1,
821 822 823 824 825 826 827
};

/* SH7763 */
static struct sh_eth_cpu_data sh7763_data = {
	.chip_reset	= sh_eth_chip_reset,
	.set_duplex	= sh_eth_set_duplex,
	.set_rate	= sh_eth_set_rate_gether,
828

829 830
	.register_type	= SH_ETH_REG_GIGABIT,

831 832
	.ecsr_value	= ECSR_ICD | ECSR_MPD,
	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
833
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff,
834 835

	.tx_check	= EESR_TC1 | EESR_FTC,
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Sergei Shtylyov 已提交
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	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
837
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
838 839 840 841 842 843 844 845

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.bculr		= 1,
	.hw_swap	= 1,
	.no_trimd	= 1,
	.no_ade		= 1,
846
	.tsu		= 1,
847
	.irq_flags	= IRQF_SHARED,
848 849
};

850
static struct sh_eth_cpu_data sh7619_data = {
851 852
	.register_type	= SH_ETH_REG_FAST_SH3_SH2,

853 854 855 856 857 858 859
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
};
860 861

static struct sh_eth_cpu_data sh771x_data = {
862 863
	.register_type	= SH_ETH_REG_FAST_SH3_SH2,

864
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
865
	.tsu		= 1,
866 867 868 869 870 871 872 873 874 875 876
};

static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
{
	if (!cd->ecsr_value)
		cd->ecsr_value = DEFAULT_ECSR_INIT;

	if (!cd->ecsipr_value)
		cd->ecsipr_value = DEFAULT_ECSIPR_INIT;

	if (!cd->fcftr_value)
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877
		cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
878 879 880 881 882 883 884 885 886 887
				  DEFAULT_FIFO_F_D_RFD;

	if (!cd->fdr_value)
		cd->fdr_value = DEFAULT_FDR_INIT;

	if (!cd->tx_check)
		cd->tx_check = DEFAULT_TX_CHECK;

	if (!cd->eesr_err_check)
		cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
888 889 890

	if (!cd->trscer_err_mask)
		cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
891 892
}

893 894 895 896 897 898
static int sh_eth_check_reset(struct net_device *ndev)
{
	int ret = 0;
	int cnt = 100;

	while (cnt > 0) {
899
		if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
900 901 902 903
			break;
		mdelay(1);
		cnt--;
	}
904
	if (cnt <= 0) {
905
		netdev_err(ndev, "Device reset failed\n");
906 907 908
		ret = -ETIMEDOUT;
	}
	return ret;
909
}
910 911 912 913 914 915

static int sh_eth_reset(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int ret = 0;

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Simon Horman 已提交
916
	if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
917
		sh_eth_write(ndev, EDSR_ENALL, EDSR);
918
		sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
919 920 921

		ret = sh_eth_check_reset(ndev);
		if (ret)
922
			return ret;
923 924 925 926 927 928 929 930 931 932 933 934

		/* Table Init */
		sh_eth_write(ndev, 0x0, TDLAR);
		sh_eth_write(ndev, 0x0, TDFAR);
		sh_eth_write(ndev, 0x0, TDFXR);
		sh_eth_write(ndev, 0x0, TDFFR);
		sh_eth_write(ndev, 0x0, RDLAR);
		sh_eth_write(ndev, 0x0, RDFAR);
		sh_eth_write(ndev, 0x0, RDFXR);
		sh_eth_write(ndev, 0x0, RDFFR);

		/* Reset HW CRC register */
935
		if (mdp->cd->hw_checksum)
936 937 938 939 940 941
			sh_eth_write(ndev, 0x0, CSMR);

		/* Select MII mode */
		if (mdp->cd->select_mii)
			sh_eth_select_mii(ndev);
	} else {
942
		sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
943
		mdelay(3);
944
		sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
945 946 947 948
	}

	return ret;
}
949 950 951

static void sh_eth_set_receive_align(struct sk_buff *skb)
{
952
	uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
953 954

	if (reserve)
955
		skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
956 957
}

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958
/* Program the hardware MAC address from dev->dev_addr. */
959 960
static void update_mac_address(struct net_device *ndev)
{
961
	sh_eth_write(ndev,
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962 963
		     (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
		     (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
964
	sh_eth_write(ndev,
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965
		     (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
966 967
}

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968
/* Get MAC address from SuperH MAC address register
969 970 971 972 973 974
 *
 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 * When you want use this device, you must set MAC address in bootloader.
 *
 */
975
static void read_mac_address(struct net_device *ndev, unsigned char *mac)
976
{
977
	if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
978
		memcpy(ndev->dev_addr, mac, ETH_ALEN);
979
	} else {
980 981 982 983 984 985 986 987 988
		u32 mahr = sh_eth_read(ndev, MAHR);
		u32 malr = sh_eth_read(ndev, MALR);

		ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
		ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
		ndev->dev_addr[2] = (mahr >>  8) & 0xFF;
		ndev->dev_addr[3] = (mahr >>  0) & 0xFF;
		ndev->dev_addr[4] = (malr >>  8) & 0xFF;
		ndev->dev_addr[5] = (malr >>  0) & 0xFF;
989
	}
990 991
}

992
static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
993
{
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Simon Horman 已提交
994
	if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
995 996 997 998 999
		return EDTRR_TRNS_GETHER;
	else
		return EDTRR_TRNS_ETHER;
}

1000
struct bb_info {
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Yoshihiro Shimoda 已提交
1001
	void (*set_gate)(void *addr);
1002
	struct mdiobb_ctrl ctrl;
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Yoshihiro Shimoda 已提交
1003
	void *addr;
1004 1005
};

1006
static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1007 1008
{
	struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1009
	u32 pir;
1010 1011 1012 1013

	if (bitbang->set_gate)
		bitbang->set_gate(bitbang->addr);

1014
	pir = ioread32(bitbang->addr);
1015
	if (set)
1016
		pir |=  mask;
1017
	else
1018 1019
		pir &= ~mask;
	iowrite32(pir, bitbang->addr);
1020 1021 1022 1023 1024 1025
}

/* Data I/O pin control */
static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
{
	sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1026 1027 1028 1029 1030
}

/* Set bit data*/
static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
{
1031
	sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1032 1033 1034 1035 1036 1037
}

/* Get bit data*/
static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
{
	struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1038 1039 1040 1041

	if (bitbang->set_gate)
		bitbang->set_gate(bitbang->addr);

1042
	return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1043 1044 1045 1046 1047
}

/* MDC pin control */
static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
{
1048
	sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063
}

/* mdio bus control struct */
static struct mdiobb_ops bb_ops = {
	.owner = THIS_MODULE,
	.set_mdc = sh_mdc_ctrl,
	.set_mdio_dir = sh_mmd_ctrl,
	.set_mdio_data = sh_set_mdio,
	.get_mdio_data = sh_get_mdio,
};

/* free skb and descriptor buffer */
static void sh_eth_ring_free(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
1064
	int ringsize, i;
1065 1066 1067

	/* Free Rx skb ringbuffer */
	if (mdp->rx_skbuff) {
1068 1069
		for (i = 0; i < mdp->num_rx_ring; i++)
			dev_kfree_skb(mdp->rx_skbuff[i]);
1070 1071
	}
	kfree(mdp->rx_skbuff);
1072
	mdp->rx_skbuff = NULL;
1073 1074 1075

	/* Free Tx skb ringbuffer */
	if (mdp->tx_skbuff) {
1076 1077
		for (i = 0; i < mdp->num_tx_ring; i++)
			dev_kfree_skb(mdp->tx_skbuff[i]);
1078 1079
	}
	kfree(mdp->tx_skbuff);
1080
	mdp->tx_skbuff = NULL;
1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094

	if (mdp->rx_ring) {
		ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
		dma_free_coherent(NULL, ringsize, mdp->rx_ring,
				  mdp->rx_desc_dma);
		mdp->rx_ring = NULL;
	}

	if (mdp->tx_ring) {
		ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
		dma_free_coherent(NULL, ringsize, mdp->tx_ring,
				  mdp->tx_desc_dma);
		mdp->tx_ring = NULL;
	}
1095 1096 1097 1098 1099 1100 1101 1102 1103 1104
}

/* format skb and descriptor buffer */
static void sh_eth_ring_format(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i;
	struct sk_buff *skb;
	struct sh_eth_rxdesc *rxdesc = NULL;
	struct sh_eth_txdesc *txdesc = NULL;
1105 1106
	int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
	int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1107
	int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1108
	dma_addr_t dma_addr;
1109
	u32 buf_len;
1110

S
Sergei Shtylyov 已提交
1111 1112 1113 1114
	mdp->cur_rx = 0;
	mdp->cur_tx = 0;
	mdp->dirty_rx = 0;
	mdp->dirty_tx = 0;
1115 1116 1117 1118

	memset(mdp->rx_ring, 0, rx_ringsize);

	/* build Rx ring buffer */
1119
	for (i = 0; i < mdp->num_rx_ring; i++) {
1120 1121
		/* skb */
		mdp->rx_skbuff[i] = NULL;
1122
		skb = netdev_alloc_skb(ndev, skbuff_size);
1123 1124
		if (skb == NULL)
			break;
1125 1126
		sh_eth_set_receive_align(skb);

1127
		/* The size of the buffer is a multiple of 32 bytes. */
1128 1129
		buf_len = ALIGN(mdp->rx_buf_sz, 32);
		dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1130 1131 1132 1133 1134 1135
					  DMA_FROM_DEVICE);
		if (dma_mapping_error(&ndev->dev, dma_addr)) {
			kfree_skb(skb);
			break;
		}
		mdp->rx_skbuff[i] = skb;
1136 1137 1138 1139

		/* RX descriptor */
		rxdesc = &mdp->rx_ring[i];
		rxdesc->len = cpu_to_le32(buf_len << 16);
1140 1141
		rxdesc->addr = cpu_to_le32(dma_addr);
		rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1142

1143 1144
		/* Rx descriptor address set */
		if (i == 0) {
1145
			sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
S
Simon Horman 已提交
1146 1147
			if (sh_eth_is_gether(mdp) ||
			    sh_eth_is_rz_fast_ether(mdp))
1148
				sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1149
		}
1150 1151
	}

1152
	mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1153 1154

	/* Mark the last entry as wrapping the ring. */
1155 1156
	if (rxdesc)
		rxdesc->status |= cpu_to_le32(RD_RDLE);
1157 1158 1159 1160

	memset(mdp->tx_ring, 0, tx_ringsize);

	/* build Tx ring buffer */
1161
	for (i = 0; i < mdp->num_tx_ring; i++) {
1162 1163
		mdp->tx_skbuff[i] = NULL;
		txdesc = &mdp->tx_ring[i];
1164 1165
		txdesc->status = cpu_to_le32(TD_TFP);
		txdesc->len = cpu_to_le32(0);
1166
		if (i == 0) {
1167
			/* Tx descriptor address set */
1168
			sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
S
Simon Horman 已提交
1169 1170
			if (sh_eth_is_gether(mdp) ||
			    sh_eth_is_rz_fast_ether(mdp))
1171
				sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1172
		}
1173 1174
	}

1175
	txdesc->status |= cpu_to_le32(TD_TDLE);
1176 1177 1178 1179 1180 1181
}

/* Get skb and descriptor buffer */
static int sh_eth_ring_init(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
1182
	int rx_ringsize, tx_ringsize;
1183

S
Sergei Shtylyov 已提交
1184
	/* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1185 1186 1187 1188 1189 1190
	 * card needs room to do 8 byte alignment, +2 so we can reserve
	 * the first 2 bytes, and +16 gets room for the status word from the
	 * card.
	 */
	mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
			  (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1191 1192
	if (mdp->cd->rpadir)
		mdp->rx_buf_sz += NET_IP_ALIGN;
1193 1194

	/* Allocate RX and TX skb rings */
1195 1196
	mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
				 GFP_KERNEL);
1197 1198
	if (!mdp->rx_skbuff)
		return -ENOMEM;
1199

1200 1201
	mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
				 GFP_KERNEL);
1202
	if (!mdp->tx_skbuff)
1203
		goto ring_free;
1204 1205

	/* Allocate all Rx descriptors. */
1206
	rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1207
	mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1208
					  GFP_KERNEL);
1209
	if (!mdp->rx_ring)
1210
		goto ring_free;
1211 1212 1213 1214

	mdp->dirty_rx = 0;

	/* Allocate all Tx descriptors. */
1215
	tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1216
	mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1217
					  GFP_KERNEL);
1218
	if (!mdp->tx_ring)
1219
		goto ring_free;
1220
	return 0;
1221

1222 1223
ring_free:
	/* Free Rx and Tx skb ring buffer and DMA buffer */
1224 1225
	sh_eth_ring_free(ndev);

1226
	return -ENOMEM;
1227 1228
}

1229
static int sh_eth_dev_init(struct net_device *ndev)
1230 1231
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
1232
	int ret;
1233 1234

	/* Soft Reset */
1235 1236
	ret = sh_eth_reset(ndev);
	if (ret)
1237
		return ret;
1238

1239 1240 1241
	if (mdp->cd->rmiimode)
		sh_eth_write(ndev, 0x1, RMIIMODE);

1242 1243
	/* Descriptor format */
	sh_eth_ring_format(ndev);
1244
	if (mdp->cd->rpadir)
1245
		sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1246 1247

	/* all sh_eth int mask */
1248
	sh_eth_write(ndev, 0, EESIPR);
1249

1250
#if defined(__LITTLE_ENDIAN)
1251
	if (mdp->cd->hw_swap)
1252
		sh_eth_write(ndev, EDMR_EL, EDMR);
1253
	else
1254
#endif
1255
		sh_eth_write(ndev, 0, EDMR);
1256

1257
	/* FIFO size set */
1258 1259
	sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
	sh_eth_write(ndev, 0, TFTR);
1260

1261 1262
	/* Frame recv control (enable multiple-packets per rx irq) */
	sh_eth_write(ndev, RMCR_RNC, RMCR);
1263

1264
	sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1265

1266
	if (mdp->cd->bculr)
1267
		sh_eth_write(ndev, 0x800, BCULR);	/* Burst sycle set */
1268

1269
	sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1270

1271
	if (!mdp->cd->no_trimd)
1272
		sh_eth_write(ndev, 0, TRIMD);
1273

1274
	/* Recv frame limit set register */
1275 1276
	sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
		     RFLR);
1277

1278
	sh_eth_modify(ndev, EESR, 0, 0);
1279 1280
	mdp->irq_enabled = true;
	sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1281 1282

	/* PAUSE Prohibition */
1283 1284
	sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
		     ECMR_TE | ECMR_RE, ECMR);
1285

1286 1287 1288
	if (mdp->cd->set_rate)
		mdp->cd->set_rate(ndev);

1289
	/* E-MAC Status Register clear */
1290
	sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1291 1292

	/* E-MAC Interrupt Enable register */
1293
	sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1294 1295 1296 1297 1298

	/* Set MAC address */
	update_mac_address(ndev);

	/* mask reset */
1299
	if (mdp->cd->apr)
1300
		sh_eth_write(ndev, APR_AP, APR);
1301
	if (mdp->cd->mpr)
1302
		sh_eth_write(ndev, MPR_MP, MPR);
1303
	if (mdp->cd->tpauser)
1304
		sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1305

1306 1307
	/* Setting the Rx mode will start the Rx process. */
	sh_eth_write(ndev, EDRRR_R, EDRRR);
1308 1309 1310 1311

	return ret;
}

1312 1313 1314 1315 1316 1317 1318 1319 1320
static void sh_eth_dev_exit(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i;

	/* Deactivate all TX descriptors, so DMA should stop at next
	 * packet boundary if it's currently running
	 */
	for (i = 0; i < mdp->num_tx_ring; i++)
1321
		mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336

	/* Disable TX FIFO egress to MAC */
	sh_eth_rcv_snd_disable(ndev);

	/* Stop RX DMA at next packet boundary */
	sh_eth_write(ndev, 0, EDRRR);

	/* Aside from TX DMA, we can't tell when the hardware is
	 * really stopped, so we need to reset to make sure.
	 * Before doing that, wait for long enough to *probably*
	 * finish transmitting the last packet and poll stats.
	 */
	msleep(2); /* max frame time at 10 Mbps < 1250 us */
	sh_eth_get_stats(ndev);
	sh_eth_reset(ndev);
1337 1338 1339

	/* Set MAC address again */
	update_mac_address(ndev);
1340 1341
}

1342 1343 1344 1345 1346
/* free Tx skb function */
static int sh_eth_txfree(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_txdesc *txdesc;
S
Sergei Shtylyov 已提交
1347
	int free_num = 0;
1348
	int entry;
1349 1350

	for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1351
		entry = mdp->dirty_tx % mdp->num_tx_ring;
1352
		txdesc = &mdp->tx_ring[entry];
1353
		if (txdesc->status & cpu_to_le32(TD_TACT))
1354
			break;
1355
		/* TACT bit must be checked before all the following reads */
S
Sergei Shtylyov 已提交
1356
		dma_rmb();
1357 1358
		netif_info(mdp, tx_done, ndev,
			   "tx entry %d status 0x%08x\n",
1359
			   entry, le32_to_cpu(txdesc->status));
1360 1361
		/* Free the original skb. */
		if (mdp->tx_skbuff[entry]) {
1362 1363
			dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
					 le32_to_cpu(txdesc->len) >> 16,
1364
					 DMA_TO_DEVICE);
1365 1366
			dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
			mdp->tx_skbuff[entry] = NULL;
S
Sergei Shtylyov 已提交
1367
			free_num++;
1368
		}
1369
		txdesc->status = cpu_to_le32(TD_TFP);
1370
		if (entry >= mdp->num_tx_ring - 1)
1371
			txdesc->status |= cpu_to_le32(TD_TDLE);
1372

1373
		ndev->stats.tx_packets++;
1374
		ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1375
	}
S
Sergei Shtylyov 已提交
1376
	return free_num;
1377 1378 1379
}

/* Packet receive function */
S
Sergei Shtylyov 已提交
1380
static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1381 1382 1383 1384
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_rxdesc *rxdesc;

1385 1386
	int entry = mdp->cur_rx % mdp->num_rx_ring;
	int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1387
	int limit;
1388
	struct sk_buff *skb;
1389
	u32 desc_status;
1390
	int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1391
	dma_addr_t dma_addr;
1392
	u16 pkt_len;
1393
	u32 buf_len;
1394

1395 1396
	boguscnt = min(boguscnt, *quota);
	limit = boguscnt;
1397
	rxdesc = &mdp->rx_ring[entry];
1398
	while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1399
		/* RACT bit must be checked before all the following reads */
S
Sergei Shtylyov 已提交
1400
		dma_rmb();
1401 1402
		desc_status = le32_to_cpu(rxdesc->status);
		pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1403 1404 1405 1406

		if (--boguscnt < 0)
			break;

1407 1408 1409 1410
		netif_info(mdp, rx_status, ndev,
			   "rx entry %d status 0x%08x len %d\n",
			   entry, desc_status, pkt_len);

1411
		if (!(desc_status & RDFEND))
1412
			ndev->stats.rx_length_errors++;
1413

S
Sergei Shtylyov 已提交
1414
		/* In case of almost all GETHER/ETHERs, the Receive Frame State
1415
		 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1416 1417
		 * bit 0. However, in case of the R8A7740 and R7S72100
		 * the RFS bits are from bit 25 to bit 16. So, the
S
Simon Horman 已提交
1418
		 * driver needs right shifting by 16.
1419
		 */
1420
		if (mdp->cd->hw_checksum)
1421
			desc_status >>= 16;
1422

1423
		skb = mdp->rx_skbuff[entry];
1424 1425
		if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
				   RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1426
			ndev->stats.rx_errors++;
1427
			if (desc_status & RD_RFS1)
1428
				ndev->stats.rx_crc_errors++;
1429
			if (desc_status & RD_RFS2)
1430
				ndev->stats.rx_frame_errors++;
1431
			if (desc_status & RD_RFS3)
1432
				ndev->stats.rx_length_errors++;
1433
			if (desc_status & RD_RFS4)
1434
				ndev->stats.rx_length_errors++;
1435
			if (desc_status & RD_RFS6)
1436
				ndev->stats.rx_missed_errors++;
1437
			if (desc_status & RD_RFS10)
1438
				ndev->stats.rx_over_errors++;
1439
		} else	if (skb) {
1440
			dma_addr = le32_to_cpu(rxdesc->addr);
1441 1442
			if (!mdp->cd->hw_swap)
				sh_eth_soft_swap(
1443
					phys_to_virt(ALIGN(dma_addr, 4)),
1444
					pkt_len + 2);
1445
			mdp->rx_skbuff[entry] = NULL;
1446 1447
			if (mdp->cd->rpadir)
				skb_reserve(skb, NET_IP_ALIGN);
1448
			dma_unmap_single(&ndev->dev, dma_addr,
1449
					 ALIGN(mdp->rx_buf_sz, 32),
1450
					 DMA_FROM_DEVICE);
1451 1452
			skb_put(skb, pkt_len);
			skb->protocol = eth_type_trans(skb, ndev);
1453
			netif_receive_skb(skb);
1454 1455
			ndev->stats.rx_packets++;
			ndev->stats.rx_bytes += pkt_len;
1456 1457
			if (desc_status & RD_RFS8)
				ndev->stats.multicast++;
1458
		}
1459
		entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1460
		rxdesc = &mdp->rx_ring[entry];
1461 1462 1463 1464
	}

	/* Refill the Rx ring buffers. */
	for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1465
		entry = mdp->dirty_rx % mdp->num_rx_ring;
1466
		rxdesc = &mdp->rx_ring[entry];
1467
		/* The size of the buffer is 32 byte boundary. */
1468
		buf_len = ALIGN(mdp->rx_buf_sz, 32);
1469
		rxdesc->len = cpu_to_le32(buf_len << 16);
1470

1471
		if (mdp->rx_skbuff[entry] == NULL) {
1472
			skb = netdev_alloc_skb(ndev, skbuff_size);
1473 1474
			if (skb == NULL)
				break;	/* Better luck next round. */
1475
			sh_eth_set_receive_align(skb);
1476
			dma_addr = dma_map_single(&ndev->dev, skb->data,
1477
						  buf_len, DMA_FROM_DEVICE);
1478 1479 1480 1481 1482
			if (dma_mapping_error(&ndev->dev, dma_addr)) {
				kfree_skb(skb);
				break;
			}
			mdp->rx_skbuff[entry] = skb;
1483

1484
			skb_checksum_none_assert(skb);
1485
			rxdesc->addr = cpu_to_le32(dma_addr);
1486
		}
S
Sergei Shtylyov 已提交
1487
		dma_wmb(); /* RACT bit must be set after all the above writes */
1488
		if (entry >= mdp->num_rx_ring - 1)
1489
			rxdesc->status |=
1490
				cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1491
		else
1492
			rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1493 1494 1495 1496
	}

	/* Restart Rx engine if stopped. */
	/* If we don't need to check status, don't. -KDU */
1497
	if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1498
		/* fix the values for the next receiving if RDE is set */
1499 1500
		if (intr_status & EESR_RDE &&
		    mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
S
Sergei Shtylyov 已提交
1501 1502 1503 1504 1505 1506
			u32 count = (sh_eth_read(ndev, RDFAR) -
				     sh_eth_read(ndev, RDLAR)) >> 4;

			mdp->cur_rx = count;
			mdp->dirty_rx = count;
		}
1507
		sh_eth_write(ndev, EDRRR_R, EDRRR);
1508
	}
1509

1510 1511
	*quota -= limit - boguscnt - 1;

1512
	return *quota <= 0;
1513 1514
}

1515
static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1516 1517
{
	/* disable tx and rx */
1518
	sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1519 1520
}

1521
static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1522 1523
{
	/* enable tx and rx */
1524
	sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1525 1526
}

1527 1528
/* E-MAC interrupt handler */
static void sh_eth_emac_interrupt(struct net_device *ndev)
1529 1530 1531
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 felic_stat;
1532
	u32 link_stat;
1533

1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554
	felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
	sh_eth_write(ndev, felic_stat, ECSR);	/* clear int */
	if (felic_stat & ECSR_ICD)
		ndev->stats.tx_carrier_errors++;
	if (felic_stat & ECSR_LCHNG) {
		/* Link Changed */
		if (mdp->cd->no_psr || mdp->no_ether_link)
			return;
		link_stat = sh_eth_read(ndev, PSR);
		if (mdp->ether_link_active_low)
			link_stat = ~link_stat;
		if (!(link_stat & PHY_ST_LINK)) {
			sh_eth_rcv_snd_disable(ndev);
		} else {
			/* Link Up */
			sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
			/* clear int */
			sh_eth_modify(ndev, ECSR, 0, 0);
			sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, DMAC_M_ECI);
			/* enable tx and rx */
			sh_eth_rcv_snd_enable(ndev);
1555 1556
		}
	}
1557 1558
	if (felic_stat & ECSR_MPD)
		pm_wakeup_event(&mdp->pdev->dev, 0);
1559 1560 1561 1562 1563 1564 1565
}

/* error control function */
static void sh_eth_error(struct net_device *ndev, u32 intr_status)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 mask;
1566 1567

	if (intr_status & EESR_TWB) {
1568 1569
		/* Unused write back interrupt */
		if (intr_status & EESR_TABT) {	/* Transmit Abort int */
1570
			ndev->stats.tx_aborted_errors++;
1571
			netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1572
		}
1573 1574 1575 1576 1577 1578
	}

	if (intr_status & EESR_RABT) {
		/* Receive Abort int */
		if (intr_status & EESR_RFRMER) {
			/* Receive Frame Overflow int */
1579
			ndev->stats.rx_frame_errors++;
1580 1581
		}
	}
1582

1583 1584
	if (intr_status & EESR_TDE) {
		/* Transmit Descriptor Empty int */
1585
		ndev->stats.tx_fifo_errors++;
1586
		netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1587 1588 1589 1590
	}

	if (intr_status & EESR_TFE) {
		/* FIFO under flow */
1591
		ndev->stats.tx_fifo_errors++;
1592
		netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1593 1594 1595 1596
	}

	if (intr_status & EESR_RDE) {
		/* Receive Descriptor Empty int */
1597
		ndev->stats.rx_over_errors++;
1598
	}
1599

1600 1601
	if (intr_status & EESR_RFE) {
		/* Receive FIFO Overflow int */
1602
		ndev->stats.rx_fifo_errors++;
1603 1604 1605 1606
	}

	if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
		/* Address Error */
1607
		ndev->stats.tx_fifo_errors++;
1608
		netif_err(mdp, tx_err, ndev, "Address Error\n");
1609
	}
1610 1611 1612 1613 1614

	mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
	if (mdp->cd->no_ade)
		mask &= ~EESR_ADE;
	if (intr_status & mask) {
1615
		/* Tx error */
1616
		u32 edtrr = sh_eth_read(ndev, EDTRR);
1617

1618
		/* dmesg */
1619 1620 1621
		netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
			   intr_status, mdp->cur_tx, mdp->dirty_tx,
			   (u32)ndev->state, edtrr);
1622 1623 1624 1625
		/* dirty buffer free */
		sh_eth_txfree(ndev);

		/* SH7712 BUG */
1626
		if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1627
			/* tx dma start */
1628
			sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1629 1630 1631 1632 1633 1634 1635 1636 1637 1638
		}
		/* wakeup */
		netif_wake_queue(ndev);
	}
}

static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
{
	struct net_device *ndev = netdev;
	struct sh_eth_private *mdp = netdev_priv(ndev);
1639
	struct sh_eth_cpu_data *cd = mdp->cd;
1640
	irqreturn_t ret = IRQ_NONE;
1641
	u32 intr_status, intr_enable;
1642 1643 1644

	spin_lock(&mdp->lock);

1645
	/* Get interrupt status */
1646
	intr_status = sh_eth_read(ndev, EESR);
1647 1648 1649 1650 1651
	/* Mask it with the interrupt mask, forcing ECI interrupt  to be always
	 * enabled since it's the one that  comes  thru regardless of the mask,
	 * and  we need to fully handle it  in sh_eth_emac_interrupt() in order
	 * to quench it as it doesn't get cleared by just writing 1 to the  ECI
	 * bit...
1652
	 */
S
Sergei Shtylyov 已提交
1653 1654
	intr_enable = sh_eth_read(ndev, EESIPR);
	intr_status &= intr_enable | DMAC_M_ECI;
1655 1656
	if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
			   cd->eesr_err_check))
1657
		ret = IRQ_HANDLED;
S
Sergei Shtylyov 已提交
1658
	else
1659 1660
		goto out;

1661
	if (unlikely(!mdp->irq_enabled)) {
1662 1663 1664
		sh_eth_write(ndev, 0, EESIPR);
		goto out;
	}
1665

S
Sergei Shtylyov 已提交
1666 1667 1668 1669 1670 1671 1672
	if (intr_status & EESR_RX_CHECK) {
		if (napi_schedule_prep(&mdp->napi)) {
			/* Mask Rx interrupts */
			sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
				     EESIPR);
			__napi_schedule(&mdp->napi);
		} else {
1673
			netdev_warn(ndev,
1674
				    "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1675
				    intr_status, intr_enable);
S
Sergei Shtylyov 已提交
1676 1677
		}
	}
1678

1679
	/* Tx Check */
1680
	if (intr_status & cd->tx_check) {
S
Sergei Shtylyov 已提交
1681 1682 1683
		/* Clear Tx interrupts */
		sh_eth_write(ndev, intr_status & cd->tx_check, EESR);

1684 1685 1686 1687
		sh_eth_txfree(ndev);
		netif_wake_queue(ndev);
	}

1688 1689 1690 1691
	/* E-MAC interrupt */
	if (intr_status & EESR_ECI)
		sh_eth_emac_interrupt(ndev);

S
Sergei Shtylyov 已提交
1692 1693 1694 1695
	if (intr_status & cd->eesr_err_check) {
		/* Clear error interrupts */
		sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);

1696
		sh_eth_error(ndev, intr_status);
S
Sergei Shtylyov 已提交
1697
	}
1698

1699
out:
1700 1701
	spin_unlock(&mdp->lock);

1702
	return ret;
1703 1704
}

S
Sergei Shtylyov 已提交
1705 1706 1707 1708 1709 1710
static int sh_eth_poll(struct napi_struct *napi, int budget)
{
	struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
						  napi);
	struct net_device *ndev = napi->dev;
	int quota = budget;
1711
	u32 intr_status;
S
Sergei Shtylyov 已提交
1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726

	for (;;) {
		intr_status = sh_eth_read(ndev, EESR);
		if (!(intr_status & EESR_RX_CHECK))
			break;
		/* Clear Rx interrupts */
		sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);

		if (sh_eth_rx(ndev, intr_status, &quota))
			goto out;
	}

	napi_complete(napi);

	/* Reenable Rx interrupts */
1727 1728
	if (mdp->irq_enabled)
		sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
S
Sergei Shtylyov 已提交
1729 1730 1731 1732
out:
	return budget - quota;
}

1733 1734 1735 1736
/* PHY state control function */
static void sh_eth_adjust_link(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
1737
	struct phy_device *phydev = ndev->phydev;
1738 1739
	int new_state = 0;

1740
	if (phydev->link) {
1741 1742 1743
		if (phydev->duplex != mdp->duplex) {
			new_state = 1;
			mdp->duplex = phydev->duplex;
1744 1745
			if (mdp->cd->set_duplex)
				mdp->cd->set_duplex(ndev);
1746 1747 1748 1749 1750
		}

		if (phydev->speed != mdp->speed) {
			new_state = 1;
			mdp->speed = phydev->speed;
1751 1752
			if (mdp->cd->set_rate)
				mdp->cd->set_rate(ndev);
1753
		}
1754
		if (!mdp->link) {
1755
			sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1756 1757
			new_state = 1;
			mdp->link = phydev->link;
1758 1759
			if (mdp->cd->no_psr || mdp->no_ether_link)
				sh_eth_rcv_snd_enable(ndev);
1760 1761 1762
		}
	} else if (mdp->link) {
		new_state = 1;
1763
		mdp->link = 0;
1764 1765
		mdp->speed = 0;
		mdp->duplex = -1;
1766 1767
		if (mdp->cd->no_psr || mdp->no_ether_link)
			sh_eth_rcv_snd_disable(ndev);
1768 1769
	}

1770
	if (new_state && netif_msg_link(mdp))
1771 1772 1773 1774 1775 1776
		phy_print_status(phydev);
}

/* PHY init function */
static int sh_eth_phy_init(struct net_device *ndev)
{
B
Ben Dooks 已提交
1777
	struct device_node *np = ndev->dev.parent->of_node;
1778
	struct sh_eth_private *mdp = netdev_priv(ndev);
1779
	struct phy_device *phydev;
1780

1781
	mdp->link = 0;
1782 1783 1784 1785
	mdp->speed = 0;
	mdp->duplex = -1;

	/* Try connect to PHY */
B
Ben Dooks 已提交
1786 1787 1788 1789 1790 1791 1792 1793
	if (np) {
		struct device_node *pn;

		pn = of_parse_phandle(np, "phy-handle", 0);
		phydev = of_phy_connect(ndev, pn,
					sh_eth_adjust_link, 0,
					mdp->phy_interface);

1794
		of_node_put(pn);
B
Ben Dooks 已提交
1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806
		if (!phydev)
			phydev = ERR_PTR(-ENOENT);
	} else {
		char phy_id[MII_BUS_ID_SIZE + 3];

		snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
			 mdp->mii_bus->id, mdp->phy_id);

		phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
				     mdp->phy_interface);
	}

1807
	if (IS_ERR(phydev)) {
1808
		netdev_err(ndev, "failed to connect PHY\n");
1809 1810
		return PTR_ERR(phydev);
	}
1811

1812
	phy_attached_info(phydev);
1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825

	return 0;
}

/* PHY control start function */
static int sh_eth_phy_start(struct net_device *ndev)
{
	int ret;

	ret = sh_eth_phy_init(ndev);
	if (ret)
		return ret;

1826
	phy_start(ndev->phydev);
1827 1828 1829 1830

	return 0;
}

1831 1832
static int sh_eth_get_link_ksettings(struct net_device *ndev,
				     struct ethtool_link_ksettings *cmd)
1833 1834 1835 1836 1837
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	unsigned long flags;
	int ret;

1838
	if (!ndev->phydev)
1839 1840
		return -ENODEV;

1841
	spin_lock_irqsave(&mdp->lock, flags);
1842
	ret = phy_ethtool_ksettings_get(ndev->phydev, cmd);
1843 1844 1845 1846 1847
	spin_unlock_irqrestore(&mdp->lock, flags);

	return ret;
}

1848 1849
static int sh_eth_set_link_ksettings(struct net_device *ndev,
				     const struct ethtool_link_ksettings *cmd)
1850 1851 1852 1853 1854
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	unsigned long flags;
	int ret;

1855
	if (!ndev->phydev)
1856 1857
		return -ENODEV;

1858 1859 1860
	spin_lock_irqsave(&mdp->lock, flags);

	/* disable tx and rx */
1861
	sh_eth_rcv_snd_disable(ndev);
1862

1863
	ret = phy_ethtool_ksettings_set(ndev->phydev, cmd);
1864 1865 1866
	if (ret)
		goto error_exit;

1867
	if (cmd->base.duplex == DUPLEX_FULL)
1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878
		mdp->duplex = 1;
	else
		mdp->duplex = 0;

	if (mdp->cd->set_duplex)
		mdp->cd->set_duplex(ndev);

error_exit:
	mdelay(1);

	/* enable tx and rx */
1879
	sh_eth_rcv_snd_enable(ndev);
1880 1881 1882 1883 1884 1885

	spin_unlock_irqrestore(&mdp->lock, flags);

	return ret;
}

1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995
/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
 * version must be bumped as well.  Just adding registers up to that
 * limit is fine, as long as the existing register indices don't
 * change.
 */
#define SH_ETH_REG_DUMP_VERSION		1
#define SH_ETH_REG_DUMP_MAX_REGS	256

static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_cpu_data *cd = mdp->cd;
	u32 *valid_map;
	size_t len;

	BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);

	/* Dump starts with a bitmap that tells ethtool which
	 * registers are defined for this chip.
	 */
	len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
	if (buf) {
		valid_map = buf;
		buf += len;
	} else {
		valid_map = NULL;
	}

	/* Add a register to the dump, if it has a defined offset.
	 * This automatically skips most undefined registers, but for
	 * some it is also necessary to check a capability flag in
	 * struct sh_eth_cpu_data.
	 */
#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
#define add_reg_from(reg, read_expr) do {				\
		if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) {	\
			if (buf) {					\
				mark_reg_valid(reg);			\
				*buf++ = read_expr;			\
			}						\
			++len;						\
		}							\
	} while (0)
#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))

	add_reg(EDSR);
	add_reg(EDMR);
	add_reg(EDTRR);
	add_reg(EDRRR);
	add_reg(EESR);
	add_reg(EESIPR);
	add_reg(TDLAR);
	add_reg(TDFAR);
	add_reg(TDFXR);
	add_reg(TDFFR);
	add_reg(RDLAR);
	add_reg(RDFAR);
	add_reg(RDFXR);
	add_reg(RDFFR);
	add_reg(TRSCER);
	add_reg(RMFCR);
	add_reg(TFTR);
	add_reg(FDR);
	add_reg(RMCR);
	add_reg(TFUCR);
	add_reg(RFOCR);
	if (cd->rmiimode)
		add_reg(RMIIMODE);
	add_reg(FCFTR);
	if (cd->rpadir)
		add_reg(RPADIR);
	if (!cd->no_trimd)
		add_reg(TRIMD);
	add_reg(ECMR);
	add_reg(ECSR);
	add_reg(ECSIPR);
	add_reg(PIR);
	if (!cd->no_psr)
		add_reg(PSR);
	add_reg(RDMLR);
	add_reg(RFLR);
	add_reg(IPGR);
	if (cd->apr)
		add_reg(APR);
	if (cd->mpr)
		add_reg(MPR);
	add_reg(RFCR);
	add_reg(RFCF);
	if (cd->tpauser)
		add_reg(TPAUSER);
	add_reg(TPAUSECR);
	add_reg(GECMR);
	if (cd->bculr)
		add_reg(BCULR);
	add_reg(MAHR);
	add_reg(MALR);
	add_reg(TROCR);
	add_reg(CDCR);
	add_reg(LCCR);
	add_reg(CNDCR);
	add_reg(CEFCR);
	add_reg(FRECR);
	add_reg(TSFRCR);
	add_reg(TLFRCR);
	add_reg(CERCR);
	add_reg(CEECR);
	add_reg(MAFCR);
	if (cd->rtrate)
		add_reg(RTRATE);
1996
	if (cd->hw_checksum)
1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071
		add_reg(CSMR);
	if (cd->select_mii)
		add_reg(RMII_MII);
	add_reg(ARSTR);
	if (cd->tsu) {
		add_tsu_reg(TSU_CTRST);
		add_tsu_reg(TSU_FWEN0);
		add_tsu_reg(TSU_FWEN1);
		add_tsu_reg(TSU_FCM);
		add_tsu_reg(TSU_BSYSL0);
		add_tsu_reg(TSU_BSYSL1);
		add_tsu_reg(TSU_PRISL0);
		add_tsu_reg(TSU_PRISL1);
		add_tsu_reg(TSU_FWSL0);
		add_tsu_reg(TSU_FWSL1);
		add_tsu_reg(TSU_FWSLC);
		add_tsu_reg(TSU_QTAG0);
		add_tsu_reg(TSU_QTAG1);
		add_tsu_reg(TSU_QTAGM0);
		add_tsu_reg(TSU_QTAGM1);
		add_tsu_reg(TSU_FWSR);
		add_tsu_reg(TSU_FWINMK);
		add_tsu_reg(TSU_ADQT0);
		add_tsu_reg(TSU_ADQT1);
		add_tsu_reg(TSU_VTAG0);
		add_tsu_reg(TSU_VTAG1);
		add_tsu_reg(TSU_ADSBSY);
		add_tsu_reg(TSU_TEN);
		add_tsu_reg(TSU_POST1);
		add_tsu_reg(TSU_POST2);
		add_tsu_reg(TSU_POST3);
		add_tsu_reg(TSU_POST4);
		if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
			/* This is the start of a table, not just a single
			 * register.
			 */
			if (buf) {
				unsigned int i;

				mark_reg_valid(TSU_ADRH0);
				for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
					*buf++ = ioread32(
						mdp->tsu_addr +
						mdp->reg_offset[TSU_ADRH0] +
						i * 4);
			}
			len += SH_ETH_TSU_CAM_ENTRIES * 2;
		}
	}

#undef mark_reg_valid
#undef add_reg_from
#undef add_reg
#undef add_tsu_reg

	return len * 4;
}

static int sh_eth_get_regs_len(struct net_device *ndev)
{
	return __sh_eth_get_regs(ndev, NULL);
}

static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
			    void *buf)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	regs->version = SH_ETH_REG_DUMP_VERSION;

	pm_runtime_get_sync(&mdp->pdev->dev);
	__sh_eth_get_regs(ndev, buf);
	pm_runtime_put_sync(&mdp->pdev->dev);
}

2072 2073 2074 2075 2076 2077
static int sh_eth_nway_reset(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	unsigned long flags;
	int ret;

2078
	if (!ndev->phydev)
2079 2080
		return -ENODEV;

2081
	spin_lock_irqsave(&mdp->lock, flags);
2082
	ret = phy_start_aneg(ndev->phydev);
2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116
	spin_unlock_irqrestore(&mdp->lock, flags);

	return ret;
}

static u32 sh_eth_get_msglevel(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	return mdp->msg_enable;
}

static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	mdp->msg_enable = value;
}

static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
	"rx_current", "tx_current",
	"rx_dirty", "tx_dirty",
};
#define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)

static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
{
	switch (sset) {
	case ETH_SS_STATS:
		return SH_ETH_STATS_LEN;
	default:
		return -EOPNOTSUPP;
	}
}

static void sh_eth_get_ethtool_stats(struct net_device *ndev,
S
Sergei Shtylyov 已提交
2117
				     struct ethtool_stats *stats, u64 *data)
2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i = 0;

	/* device-specific stats */
	data[i++] = mdp->cur_rx;
	data[i++] = mdp->cur_tx;
	data[i++] = mdp->dirty_rx;
	data[i++] = mdp->dirty_tx;
}

static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
{
	switch (stringset) {
	case ETH_SS_STATS:
		memcpy(data, *sh_eth_gstrings_stats,
S
Sergei Shtylyov 已提交
2134
		       sizeof(sh_eth_gstrings_stats));
2135 2136 2137 2138
		break;
	}
}

2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164
static void sh_eth_get_ringparam(struct net_device *ndev,
				 struct ethtool_ringparam *ring)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	ring->rx_max_pending = RX_RING_MAX;
	ring->tx_max_pending = TX_RING_MAX;
	ring->rx_pending = mdp->num_rx_ring;
	ring->tx_pending = mdp->num_tx_ring;
}

static int sh_eth_set_ringparam(struct net_device *ndev,
				struct ethtool_ringparam *ring)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int ret;

	if (ring->tx_pending > TX_RING_MAX ||
	    ring->rx_pending > RX_RING_MAX ||
	    ring->tx_pending < TX_RING_MIN ||
	    ring->rx_pending < RX_RING_MIN)
		return -EINVAL;
	if (ring->rx_mini_pending || ring->rx_jumbo_pending)
		return -EINVAL;

	if (netif_running(ndev)) {
2165
		netif_device_detach(ndev);
2166
		netif_tx_disable(ndev);
2167 2168 2169 2170 2171 2172 2173

		/* Serialise with the interrupt handler and NAPI, then
		 * disable interrupts.  We have to clear the
		 * irq_enabled flag first to ensure that interrupts
		 * won't be re-enabled.
		 */
		mdp->irq_enabled = false;
2174
		synchronize_irq(ndev->irq);
2175
		napi_synchronize(&mdp->napi);
2176 2177
		sh_eth_write(ndev, 0x0000, EESIPR);

2178
		sh_eth_dev_exit(ndev);
2179

2180
		/* Free all the skbuffs in the Rx queue and the DMA buffers. */
2181 2182
		sh_eth_ring_free(ndev);
	}
2183 2184 2185 2186 2187 2188

	/* Set new parameters */
	mdp->num_rx_ring = ring->rx_pending;
	mdp->num_tx_ring = ring->tx_pending;

	if (netif_running(ndev)) {
2189 2190 2191 2192 2193 2194
		ret = sh_eth_ring_init(ndev);
		if (ret < 0) {
			netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
				   __func__);
			return ret;
		}
2195
		ret = sh_eth_dev_init(ndev);
2196 2197 2198 2199 2200 2201
		if (ret < 0) {
			netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
				   __func__);
			return ret;
		}

2202
		netif_device_attach(ndev);
2203 2204 2205 2206 2207
	}

	return 0;
}

2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234
static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	wol->supported = 0;
	wol->wolopts = 0;

	if (mdp->cd->magic && mdp->clk) {
		wol->supported = WAKE_MAGIC;
		wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
	}
}

static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	if (!mdp->cd->magic || !mdp->clk || wol->wolopts & ~WAKE_MAGIC)
		return -EOPNOTSUPP;

	mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);

	device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);

	return 0;
}

S
stephen hemminger 已提交
2235
static const struct ethtool_ops sh_eth_ethtool_ops = {
2236 2237
	.get_regs_len	= sh_eth_get_regs_len,
	.get_regs	= sh_eth_get_regs,
S
stephen hemminger 已提交
2238
	.nway_reset	= sh_eth_nway_reset,
2239 2240
	.get_msglevel	= sh_eth_get_msglevel,
	.set_msglevel	= sh_eth_set_msglevel,
S
stephen hemminger 已提交
2241
	.get_link	= ethtool_op_get_link,
2242 2243 2244
	.get_strings	= sh_eth_get_strings,
	.get_ethtool_stats  = sh_eth_get_ethtool_stats,
	.get_sset_count     = sh_eth_get_sset_count,
2245 2246
	.get_ringparam	= sh_eth_get_ringparam,
	.set_ringparam	= sh_eth_set_ringparam,
2247 2248
	.get_link_ksettings = sh_eth_get_link_ksettings,
	.set_link_ksettings = sh_eth_set_link_ksettings,
2249 2250
	.get_wol	= sh_eth_get_wol,
	.set_wol	= sh_eth_set_wol,
2251 2252
};

2253 2254 2255 2256
/* network device open function */
static int sh_eth_open(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
2257
	int ret;
2258

2259 2260
	pm_runtime_get_sync(&mdp->pdev->dev);

2261 2262
	napi_enable(&mdp->napi);

2263
	ret = request_irq(ndev->irq, sh_eth_interrupt,
2264
			  mdp->cd->irq_flags, ndev->name, ndev);
2265
	if (ret) {
2266
		netdev_err(ndev, "Can not assign IRQ number\n");
2267
		goto out_napi_off;
2268 2269 2270 2271 2272 2273 2274 2275
	}

	/* Descriptor set */
	ret = sh_eth_ring_init(ndev);
	if (ret)
		goto out_free_irq;

	/* device init */
2276
	ret = sh_eth_dev_init(ndev);
2277 2278 2279 2280 2281 2282 2283 2284
	if (ret)
		goto out_free_irq;

	/* PHY control start*/
	ret = sh_eth_phy_start(ndev);
	if (ret)
		goto out_free_irq;

2285 2286
	netif_start_queue(ndev);

2287 2288
	mdp->is_opened = 1;

2289 2290 2291 2292
	return ret;

out_free_irq:
	free_irq(ndev->irq, ndev);
2293 2294
out_napi_off:
	napi_disable(&mdp->napi);
2295
	pm_runtime_put_sync(&mdp->pdev->dev);
2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307
	return ret;
}

/* Timeout function */
static void sh_eth_tx_timeout(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_rxdesc *rxdesc;
	int i;

	netif_stop_queue(ndev);

2308 2309
	netif_err(mdp, timer, ndev,
		  "transmit timed out, status %8.8x, resetting...\n",
2310
		  sh_eth_read(ndev, EESR));
2311 2312

	/* tx_errors count up */
2313
	ndev->stats.tx_errors++;
2314 2315

	/* Free all the skbuffs in the Rx queue. */
2316
	for (i = 0; i < mdp->num_rx_ring; i++) {
2317
		rxdesc = &mdp->rx_ring[i];
2318 2319
		rxdesc->status = cpu_to_le32(0);
		rxdesc->addr = cpu_to_le32(0xBADF00D0);
2320
		dev_kfree_skb(mdp->rx_skbuff[i]);
2321 2322
		mdp->rx_skbuff[i] = NULL;
	}
2323
	for (i = 0; i < mdp->num_tx_ring; i++) {
2324
		dev_kfree_skb(mdp->tx_skbuff[i]);
2325 2326 2327 2328
		mdp->tx_skbuff[i] = NULL;
	}

	/* device init */
2329
	sh_eth_dev_init(ndev);
2330 2331

	netif_start_queue(ndev);
2332 2333 2334 2335 2336 2337 2338
}

/* Packet transmit function */
static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_txdesc *txdesc;
2339
	dma_addr_t dma_addr;
2340
	u32 entry;
2341
	unsigned long flags;
2342 2343

	spin_lock_irqsave(&mdp->lock, flags);
2344
	if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2345
		if (!sh_eth_txfree(ndev)) {
2346
			netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2347 2348
			netif_stop_queue(ndev);
			spin_unlock_irqrestore(&mdp->lock, flags);
2349
			return NETDEV_TX_BUSY;
2350 2351 2352 2353
		}
	}
	spin_unlock_irqrestore(&mdp->lock, flags);

2354
	if (skb_put_padto(skb, ETH_ZLEN))
2355 2356
		return NETDEV_TX_OK;

2357
	entry = mdp->cur_tx % mdp->num_tx_ring;
2358 2359 2360
	mdp->tx_skbuff[entry] = skb;
	txdesc = &mdp->tx_ring[entry];
	/* soft swap. */
2361
	if (!mdp->cd->hw_swap)
2362
		sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2363 2364 2365
	dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
				  DMA_TO_DEVICE);
	if (dma_mapping_error(&ndev->dev, dma_addr)) {
2366 2367 2368
		kfree_skb(skb);
		return NETDEV_TX_OK;
	}
2369 2370
	txdesc->addr = cpu_to_le32(dma_addr);
	txdesc->len  = cpu_to_le32(skb->len << 16);
2371

S
Sergei Shtylyov 已提交
2372
	dma_wmb(); /* TACT bit must be set after all the above writes */
2373
	if (entry >= mdp->num_tx_ring - 1)
2374
		txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2375
	else
2376
		txdesc->status |= cpu_to_le32(TD_TACT);
2377 2378 2379

	mdp->cur_tx++;

2380 2381
	if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
		sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2382

2383
	return NETDEV_TX_OK;
2384 2385
}

2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401
/* The statistics registers have write-clear behaviour, which means we
 * will lose any increment between the read and write.  We mitigate
 * this by only clearing when we read a non-zero value, so we will
 * never falsely report a total of zero.
 */
static void
sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
{
	u32 delta = sh_eth_read(ndev, reg);

	if (delta) {
		*stat += delta;
		sh_eth_write(ndev, 0, reg);
	}
}

2402 2403 2404 2405 2406 2407 2408 2409 2410 2411
static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	if (sh_eth_is_rz_fast_ether(mdp))
		return &ndev->stats;

	if (!mdp->is_opened)
		return &ndev->stats;

2412 2413 2414
	sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
	sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
	sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2415 2416

	if (sh_eth_is_gether(mdp)) {
2417 2418 2419 2420
		sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
				   CERCR);
		sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
				   CEECR);
2421
	} else {
2422 2423
		sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
				   CNDCR);
2424 2425 2426 2427 2428
	}

	return &ndev->stats;
}

2429 2430 2431 2432 2433 2434 2435
/* device close function */
static int sh_eth_close(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	netif_stop_queue(ndev);

2436 2437 2438 2439 2440 2441 2442
	/* Serialise with the interrupt handler and NAPI, then disable
	 * interrupts.  We have to clear the irq_enabled flag first to
	 * ensure that interrupts won't be re-enabled.
	 */
	mdp->irq_enabled = false;
	synchronize_irq(ndev->irq);
	napi_disable(&mdp->napi);
2443
	sh_eth_write(ndev, 0x0000, EESIPR);
2444

2445
	sh_eth_dev_exit(ndev);
2446 2447

	/* PHY Disconnect */
2448 2449 2450
	if (ndev->phydev) {
		phy_stop(ndev->phydev);
		phy_disconnect(ndev->phydev);
2451 2452 2453 2454
	}

	free_irq(ndev->irq, ndev);

2455
	/* Free all the skbuffs in the Rx queue and the DMA buffer. */
2456 2457
	sh_eth_ring_free(ndev);

2458 2459
	pm_runtime_put_sync(&mdp->pdev->dev);

2460
	mdp->is_opened = 0;
2461

2462
	return 0;
2463 2464
}

2465
/* ioctl to device function */
S
Sergei Shtylyov 已提交
2466
static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2467
{
2468
	struct phy_device *phydev = ndev->phydev;
2469 2470 2471 2472 2473 2474 2475

	if (!netif_running(ndev))
		return -EINVAL;

	if (!phydev)
		return -ENODEV;

2476
	return phy_mii_ioctl(phydev, rq, cmd);
2477 2478
}

2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534
/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
					    int entry)
{
	return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
}

static u32 sh_eth_tsu_get_post_mask(int entry)
{
	return 0x0f << (28 - ((entry % 8) * 4));
}

static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
{
	return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
}

static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
					     int entry)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 tmp;
	void *reg_offset;

	reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
	tmp = ioread32(reg_offset);
	iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
}

static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
					      int entry)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 post_mask, ref_mask, tmp;
	void *reg_offset;

	reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
	post_mask = sh_eth_tsu_get_post_mask(entry);
	ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;

	tmp = ioread32(reg_offset);
	iowrite32(tmp & ~post_mask, reg_offset);

	/* If other port enables, the function returns "true" */
	return tmp & ref_mask;
}

static int sh_eth_tsu_busy(struct net_device *ndev)
{
	int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
	struct sh_eth_private *mdp = netdev_priv(ndev);

	while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
		udelay(10);
		timeout--;
		if (timeout <= 0) {
2535
			netdev_err(ndev, "%s: timeout\n", __func__);
2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584
			return -ETIMEDOUT;
		}
	}

	return 0;
}

static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
				  const u8 *addr)
{
	u32 val;

	val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
	iowrite32(val, reg);
	if (sh_eth_tsu_busy(ndev) < 0)
		return -EBUSY;

	val = addr[4] << 8 | addr[5];
	iowrite32(val, reg + 4);
	if (sh_eth_tsu_busy(ndev) < 0)
		return -EBUSY;

	return 0;
}

static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
{
	u32 val;

	val = ioread32(reg);
	addr[0] = (val >> 24) & 0xff;
	addr[1] = (val >> 16) & 0xff;
	addr[2] = (val >> 8) & 0xff;
	addr[3] = val & 0xff;
	val = ioread32(reg + 4);
	addr[4] = (val >> 8) & 0xff;
	addr[5] = val & 0xff;
}


static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
	int i;
	u8 c_addr[ETH_ALEN];

	for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
		sh_eth_tsu_read_entry(reg_offset, c_addr);
2585
		if (ether_addr_equal(addr, c_addr))
2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677
			return i;
	}

	return -ENOENT;
}

static int sh_eth_tsu_find_empty(struct net_device *ndev)
{
	u8 blank[ETH_ALEN];
	int entry;

	memset(blank, 0, sizeof(blank));
	entry = sh_eth_tsu_find_entry(ndev, blank);
	return (entry < 0) ? -ENOMEM : entry;
}

static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
					      int entry)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
	int ret;
	u8 blank[ETH_ALEN];

	sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
			 ~(1 << (31 - entry)), TSU_TEN);

	memset(blank, 0, sizeof(blank));
	ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
	if (ret < 0)
		return ret;
	return 0;
}

static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
	int i, ret;

	if (!mdp->cd->tsu)
		return 0;

	i = sh_eth_tsu_find_entry(ndev, addr);
	if (i < 0) {
		/* No entry found, create one */
		i = sh_eth_tsu_find_empty(ndev);
		if (i < 0)
			return -ENOMEM;
		ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
		if (ret < 0)
			return ret;

		/* Enable the entry */
		sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
				 (1 << (31 - i)), TSU_TEN);
	}

	/* Entry found or created, enable POST */
	sh_eth_tsu_enable_cam_entry_post(ndev, i);

	return 0;
}

static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i, ret;

	if (!mdp->cd->tsu)
		return 0;

	i = sh_eth_tsu_find_entry(ndev, addr);
	if (i) {
		/* Entry found */
		if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
			goto done;

		/* Disable the entry if both ports was disabled */
		ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
		if (ret < 0)
			return ret;
	}
done:
	return 0;
}

static int sh_eth_tsu_purge_all(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i, ret;

2678
	if (!mdp->cd->tsu)
2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700
		return 0;

	for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
		if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
			continue;

		/* Disable the entry if both ports was disabled */
		ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u8 addr[ETH_ALEN];
	void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
	int i;

2701
	if (!mdp->cd->tsu)
2702 2703 2704 2705 2706 2707 2708 2709 2710
		return;

	for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
		sh_eth_tsu_read_entry(reg_offset, addr);
		if (is_multicast_ether_addr(addr))
			sh_eth_tsu_del_entry(ndev, addr);
	}
}

2711 2712
/* Update promiscuous flag and multicast filter */
static void sh_eth_set_rx_mode(struct net_device *ndev)
2713
{
2714 2715 2716 2717 2718 2719
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 ecmr_bits;
	int mcast_all = 0;
	unsigned long flags;

	spin_lock_irqsave(&mdp->lock, flags);
S
Sergei Shtylyov 已提交
2720
	/* Initial condition is MCT = 1, PRM = 0.
2721 2722
	 * Depending on ndev->flags, set PRM or clear MCT
	 */
2723 2724 2725
	ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
	if (mdp->cd->tsu)
		ecmr_bits |= ECMR_MCT;
2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736

	if (!(ndev->flags & IFF_MULTICAST)) {
		sh_eth_tsu_purge_mcast(ndev);
		mcast_all = 1;
	}
	if (ndev->flags & IFF_ALLMULTI) {
		sh_eth_tsu_purge_mcast(ndev);
		ecmr_bits &= ~ECMR_MCT;
		mcast_all = 1;
	}

2737
	if (ndev->flags & IFF_PROMISC) {
2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753
		sh_eth_tsu_purge_all(ndev);
		ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
	} else if (mdp->cd->tsu) {
		struct netdev_hw_addr *ha;
		netdev_for_each_mc_addr(ha, ndev) {
			if (mcast_all && is_multicast_ether_addr(ha->addr))
				continue;

			if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
				if (!mcast_all) {
					sh_eth_tsu_purge_mcast(ndev);
					ecmr_bits &= ~ECMR_MCT;
					mcast_all = 1;
				}
			}
		}
2754
	}
2755 2756 2757 2758 2759

	/* update the ethernet mode */
	sh_eth_write(ndev, ecmr_bits, ECMR);

	spin_unlock_irqrestore(&mdp->lock, flags);
2760
}
2761 2762 2763 2764 2765 2766 2767 2768 2769

static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
{
	if (!mdp->port)
		return TSU_VTAG0;
	else
		return TSU_VTAG1;
}

2770 2771
static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
				  __be16 proto, u16 vid)
2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int vtag_reg_index = sh_eth_get_vtag_index(mdp);

	if (unlikely(!mdp->cd->tsu))
		return -EPERM;

	/* No filtering if vid = 0 */
	if (!vid)
		return 0;

	mdp->vlan_num_ids++;

S
Sergei Shtylyov 已提交
2785
	/* The controller has one VLAN tag HW filter. So, if the filter is
2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799
	 * already enabled, the driver disables it and the filte
	 */
	if (mdp->vlan_num_ids > 1) {
		/* disable VLAN filter */
		sh_eth_tsu_write(mdp, 0, vtag_reg_index);
		return 0;
	}

	sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
			 vtag_reg_index);

	return 0;
}

2800 2801
static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
				   __be16 proto, u16 vid)
2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int vtag_reg_index = sh_eth_get_vtag_index(mdp);

	if (unlikely(!mdp->cd->tsu))
		return -EPERM;

	/* No filtering if vid = 0 */
	if (!vid)
		return 0;

	mdp->vlan_num_ids--;
	sh_eth_tsu_write(mdp, 0, vtag_reg_index);

	return 0;
}
2818 2819

/* SuperH's TSU register init function */
2820
static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2821
{
S
Simon Horman 已提交
2822 2823
	if (sh_eth_is_rz_fast_ether(mdp)) {
		sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2824 2825
		sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
				 TSU_FWSLC);	/* Enable POST registers */
S
Simon Horman 已提交
2826 2827 2828
		return;
	}

2829 2830 2831 2832 2833 2834 2835 2836 2837 2838
	sh_eth_tsu_write(mdp, 0, TSU_FWEN0);	/* Disable forward(0->1) */
	sh_eth_tsu_write(mdp, 0, TSU_FWEN1);	/* Disable forward(1->0) */
	sh_eth_tsu_write(mdp, 0, TSU_FCM);	/* forward fifo 3k-3k */
	sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
	sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
	sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
	sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
	sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
	sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
	sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2839 2840 2841 2842 2843 2844 2845
	if (sh_eth_is_gether(mdp)) {
		sh_eth_tsu_write(mdp, 0, TSU_QTAG0);	/* Disable QTAG(0->1) */
		sh_eth_tsu_write(mdp, 0, TSU_QTAG1);	/* Disable QTAG(1->0) */
	} else {
		sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);	/* Disable QTAG(0->1) */
		sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);	/* Disable QTAG(1->0) */
	}
2846 2847 2848 2849 2850 2851 2852
	sh_eth_tsu_write(mdp, 0, TSU_FWSR);	/* all interrupt status clear */
	sh_eth_tsu_write(mdp, 0, TSU_FWINMK);	/* Disable all interrupt */
	sh_eth_tsu_write(mdp, 0, TSU_TEN);	/* Disable all CAM entry */
	sh_eth_tsu_write(mdp, 0, TSU_POST1);	/* Disable CAM entry [ 0- 7] */
	sh_eth_tsu_write(mdp, 0, TSU_POST2);	/* Disable CAM entry [ 8-15] */
	sh_eth_tsu_write(mdp, 0, TSU_POST3);	/* Disable CAM entry [16-23] */
	sh_eth_tsu_write(mdp, 0, TSU_POST4);	/* Disable CAM entry [24-31] */
2853 2854 2855
}

/* MDIO bus release function */
2856
static int sh_mdio_release(struct sh_eth_private *mdp)
2857 2858
{
	/* unregister mdio bus */
2859
	mdiobus_unregister(mdp->mii_bus);
2860 2861

	/* free bitbang info */
2862
	free_mdio_bitbang(mdp->mii_bus);
2863 2864 2865 2866 2867

	return 0;
}

/* MDIO bus init function */
2868
static int sh_mdio_init(struct sh_eth_private *mdp,
2869
			struct sh_eth_plat_data *pd)
2870
{
2871
	int ret;
2872
	struct bb_info *bitbang;
2873
	struct platform_device *pdev = mdp->pdev;
2874
	struct device *dev = &mdp->pdev->dev;
2875 2876

	/* create bit control struct for PHY */
2877
	bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2878 2879
	if (!bitbang)
		return -ENOMEM;
2880 2881

	/* bitbang init */
Y
Yoshihiro Shimoda 已提交
2882
	bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2883
	bitbang->set_gate = pd->set_mdio_gate;
2884 2885
	bitbang->ctrl.ops = &bb_ops;

2886
	/* MII controller setting */
2887
	mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2888 2889
	if (!mdp->mii_bus)
		return -ENOMEM;
2890 2891 2892

	/* Hook up MII support for ethtool */
	mdp->mii_bus->name = "sh_mii";
2893
	mdp->mii_bus->parent = dev;
2894
	snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2895
		 pdev->name, pdev->id);
2896

2897 2898 2899
	/* register MDIO bus */
	if (dev->of_node) {
		ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
B
Ben Dooks 已提交
2900 2901 2902 2903 2904 2905 2906
	} else {
		if (pd->phy_irq > 0)
			mdp->mii_bus->irq[pd->phy] = pd->phy_irq;

		ret = mdiobus_register(mdp->mii_bus);
	}

2907
	if (ret)
S
Sergei Shtylyov 已提交
2908
		goto out_free_bus;
2909 2910 2911 2912

	return 0;

out_free_bus:
2913
	free_mdio_bitbang(mdp->mii_bus);
2914 2915 2916
	return ret;
}

2917 2918 2919 2920 2921 2922 2923 2924
static const u16 *sh_eth_get_register_offset(int register_type)
{
	const u16 *reg_offset = NULL;

	switch (register_type) {
	case SH_ETH_REG_GIGABIT:
		reg_offset = sh_eth_offset_gigabit;
		break;
S
Simon Horman 已提交
2925 2926 2927
	case SH_ETH_REG_FAST_RZ:
		reg_offset = sh_eth_offset_fast_rz;
		break;
2928 2929 2930
	case SH_ETH_REG_FAST_RCAR:
		reg_offset = sh_eth_offset_fast_rcar;
		break;
2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941
	case SH_ETH_REG_FAST_SH4:
		reg_offset = sh_eth_offset_fast_sh4;
		break;
	case SH_ETH_REG_FAST_SH3_SH2:
		reg_offset = sh_eth_offset_fast_sh3_sh2;
		break;
	}

	return reg_offset;
}

2942
static const struct net_device_ops sh_eth_netdev_ops = {
2943 2944 2945 2946
	.ndo_open		= sh_eth_open,
	.ndo_stop		= sh_eth_close,
	.ndo_start_xmit		= sh_eth_start_xmit,
	.ndo_get_stats		= sh_eth_get_stats,
2947
	.ndo_set_rx_mode	= sh_eth_set_rx_mode,
2948 2949 2950 2951 2952 2953
	.ndo_tx_timeout		= sh_eth_tx_timeout,
	.ndo_do_ioctl		= sh_eth_do_ioctl,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_set_mac_address	= eth_mac_addr,
};

2954 2955 2956 2957 2958
static const struct net_device_ops sh_eth_netdev_ops_tsu = {
	.ndo_open		= sh_eth_open,
	.ndo_stop		= sh_eth_close,
	.ndo_start_xmit		= sh_eth_start_xmit,
	.ndo_get_stats		= sh_eth_get_stats,
2959
	.ndo_set_rx_mode	= sh_eth_set_rx_mode,
2960 2961 2962 2963 2964 2965 2966 2967
	.ndo_vlan_rx_add_vid	= sh_eth_vlan_rx_add_vid,
	.ndo_vlan_rx_kill_vid	= sh_eth_vlan_rx_kill_vid,
	.ndo_tx_timeout		= sh_eth_tx_timeout,
	.ndo_do_ioctl		= sh_eth_do_ioctl,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_set_mac_address	= eth_mac_addr,
};

2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994
#ifdef CONFIG_OF
static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
{
	struct device_node *np = dev->of_node;
	struct sh_eth_plat_data *pdata;
	const char *mac_addr;

	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return NULL;

	pdata->phy_interface = of_get_phy_mode(np);

	mac_addr = of_get_mac_address(np);
	if (mac_addr)
		memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);

	pdata->no_ether_link =
		of_property_read_bool(np, "renesas,no-ether-link");
	pdata->ether_link_active_low =
		of_property_read_bool(np, "renesas,ether-link-active-low");

	return pdata;
}

static const struct of_device_id sh_eth_match_table[] = {
	{ .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
S
Sergei Shtylyov 已提交
2995 2996
	{ .compatible = "renesas,ether-r8a7743", .data = &r8a779x_data },
	{ .compatible = "renesas,ether-r8a7745", .data = &r8a779x_data },
2997 2998 2999 3000
	{ .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
	{ .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
	{ .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
	{ .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
3001
	{ .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
3002
	{ .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013
	{ .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
	{ }
};
MODULE_DEVICE_TABLE(of, sh_eth_match_table);
#else
static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
{
	return NULL;
}
#endif

3014 3015 3016
static int sh_eth_drv_probe(struct platform_device *pdev)
{
	struct resource *res;
J
Jingoo Han 已提交
3017
	struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3018
	const struct platform_device_id *id = platform_get_device_id(pdev);
3019 3020 3021
	struct sh_eth_private *mdp;
	struct net_device *ndev;
	int ret, devno;
3022 3023 3024 3025 3026

	/* get base addr */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3027 3028
	if (!ndev)
		return -ENOMEM;
3029

3030 3031 3032
	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);

3033 3034 3035 3036
	devno = pdev->id;
	if (devno < 0)
		devno = 0;

3037
	ret = platform_get_irq(pdev, 0);
3038
	if (ret < 0)
3039
		goto out_release;
3040
	ndev->irq = ret;
3041 3042 3043 3044

	SET_NETDEV_DEV(ndev, &pdev->dev);

	mdp = netdev_priv(ndev);
3045 3046
	mdp->num_tx_ring = TX_RING_SIZE;
	mdp->num_rx_ring = RX_RING_SIZE;
S
Sergei Shtylyov 已提交
3047 3048 3049
	mdp->addr = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mdp->addr)) {
		ret = PTR_ERR(mdp->addr);
Y
Yoshihiro Shimoda 已提交
3050 3051 3052
		goto out_release;
	}

3053 3054 3055 3056 3057
	/* Get clock, if not found that's OK but Wake-On-Lan is unavailable */
	mdp->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(mdp->clk))
		mdp->clk = NULL;

3058 3059
	ndev->base_addr = res->start;

3060
	spin_lock_init(&mdp->lock);
3061
	mdp->pdev = pdev;
3062

3063 3064
	if (pdev->dev.of_node)
		pd = sh_eth_parse_dt(&pdev->dev);
3065 3066 3067 3068 3069 3070
	if (!pd) {
		dev_err(&pdev->dev, "no platform data\n");
		ret = -EINVAL;
		goto out_release;
	}

3071
	/* get PHY ID */
3072
	mdp->phy_id = pd->phy;
3073
	mdp->phy_interface = pd->phy_interface;
3074 3075
	mdp->no_ether_link = pd->no_ether_link;
	mdp->ether_link_active_low = pd->ether_link_active_low;
3076

3077
	/* set cpu data */
3078
	if (id)
3079
		mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3080 3081
	else
		mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3082

3083
	mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3084 3085 3086 3087 3088 3089
	if (!mdp->reg_offset) {
		dev_err(&pdev->dev, "Unknown register type (%d)\n",
			mdp->cd->register_type);
		ret = -EINVAL;
		goto out_release;
	}
3090 3091
	sh_eth_set_default_cpu_data(mdp->cd);

3092
	/* set function */
3093 3094 3095 3096
	if (mdp->cd->tsu)
		ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
	else
		ndev->netdev_ops = &sh_eth_netdev_ops;
3097
	ndev->ethtool_ops = &sh_eth_ethtool_ops;
3098 3099
	ndev->watchdog_timeo = TX_TIMEOUT;

3100 3101
	/* debug message level */
	mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3102 3103

	/* read and set MAC address */
3104
	read_mac_address(ndev, pd->mac_addr);
3105 3106 3107 3108 3109
	if (!is_valid_ether_addr(ndev->dev_addr)) {
		dev_warn(&pdev->dev,
			 "no valid MAC address supplied, using a random one.\n");
		eth_hw_addr_random(ndev);
	}
3110

3111 3112 3113 3114
	/* ioremap the TSU registers */
	if (mdp->cd->tsu) {
		struct resource *rtsu;
		rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
S
Sergei Shtylyov 已提交
3115 3116 3117
		mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
		if (IS_ERR(mdp->tsu_addr)) {
			ret = PTR_ERR(mdp->tsu_addr);
3118 3119
			goto out_release;
		}
3120
		mdp->port = devno % 2;
3121
		ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3122 3123
	}

3124 3125
	/* initialize first or needed device */
	if (!devno || pd->needs_init) {
3126 3127
		if (mdp->cd->chip_reset)
			mdp->cd->chip_reset(ndev);
3128

3129 3130 3131 3132
		if (mdp->cd->tsu) {
			/* TSU init (Init only)*/
			sh_eth_tsu_init(mdp);
		}
3133 3134
	}

3135 3136 3137
	if (mdp->cd->rmiimode)
		sh_eth_write(ndev, 0x1, RMIIMODE);

3138 3139 3140 3141 3142 3143 3144
	/* MDIO bus init */
	ret = sh_mdio_init(mdp, pd);
	if (ret) {
		dev_err(&ndev->dev, "failed to initialise MDIO\n");
		goto out_release;
	}

S
Sergei Shtylyov 已提交
3145 3146
	netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);

3147 3148 3149
	/* network device register */
	ret = register_netdev(ndev);
	if (ret)
S
Sergei Shtylyov 已提交
3150
		goto out_napi_del;
3151

3152 3153 3154
	if (mdp->cd->magic && mdp->clk)
		device_set_wakeup_capable(&pdev->dev, 1);

L
Lucas De Marchi 已提交
3155
	/* print device information */
3156 3157
	netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
		    (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3158

3159
	pm_runtime_put(&pdev->dev);
3160 3161 3162 3163
	platform_set_drvdata(pdev, ndev);

	return ret;

S
Sergei Shtylyov 已提交
3164 3165
out_napi_del:
	netif_napi_del(&mdp->napi);
3166
	sh_mdio_release(mdp);
S
Sergei Shtylyov 已提交
3167

3168 3169 3170 3171 3172
out_release:
	/* net_dev free */
	if (ndev)
		free_netdev(ndev);

3173 3174
	pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
3175 3176 3177 3178 3179 3180
	return ret;
}

static int sh_eth_drv_remove(struct platform_device *pdev)
{
	struct net_device *ndev = platform_get_drvdata(pdev);
S
Sergei Shtylyov 已提交
3181
	struct sh_eth_private *mdp = netdev_priv(ndev);
3182 3183

	unregister_netdev(ndev);
S
Sergei Shtylyov 已提交
3184
	netif_napi_del(&mdp->napi);
3185
	sh_mdio_release(mdp);
3186
	pm_runtime_disable(&pdev->dev);
3187 3188 3189 3190 3191
	free_netdev(ndev);

	return 0;
}

3192
#ifdef CONFIG_PM
M
Mikhail Ulyanov 已提交
3193
#ifdef CONFIG_PM_SLEEP
3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239
static int sh_eth_wol_setup(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	/* Only allow ECI interrupts */
	synchronize_irq(ndev->irq);
	napi_disable(&mdp->napi);
	sh_eth_write(ndev, DMAC_M_ECI, EESIPR);

	/* Enable MagicPacket */
	sh_eth_modify(ndev, ECMR, 0, ECMR_MPDE);

	/* Increased clock usage so device won't be suspended */
	clk_enable(mdp->clk);

	return enable_irq_wake(ndev->irq);
}

static int sh_eth_wol_restore(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int ret;

	napi_enable(&mdp->napi);

	/* Disable MagicPacket */
	sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);

	/* The device needs to be reset to restore MagicPacket logic
	 * for next wakeup. If we close and open the device it will
	 * both be reset and all registers restored. This is what
	 * happens during suspend and resume without WoL enabled.
	 */
	ret = sh_eth_close(ndev);
	if (ret < 0)
		return ret;
	ret = sh_eth_open(ndev);
	if (ret < 0)
		return ret;

	/* Restore clock usage count */
	clk_disable(mdp->clk);

	return disable_irq_wake(ndev->irq);
}

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Mikhail Ulyanov 已提交
3240 3241 3242
static int sh_eth_suspend(struct device *dev)
{
	struct net_device *ndev = dev_get_drvdata(dev);
3243
	struct sh_eth_private *mdp = netdev_priv(ndev);
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Mikhail Ulyanov 已提交
3244 3245
	int ret = 0;

3246 3247 3248 3249 3250 3251 3252 3253
	if (!netif_running(ndev))
		return 0;

	netif_device_detach(ndev);

	if (mdp->wol_enabled)
		ret = sh_eth_wol_setup(ndev);
	else
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Mikhail Ulyanov 已提交
3254 3255 3256 3257 3258 3259 3260 3261
		ret = sh_eth_close(ndev);

	return ret;
}

static int sh_eth_resume(struct device *dev)
{
	struct net_device *ndev = dev_get_drvdata(dev);
3262
	struct sh_eth_private *mdp = netdev_priv(ndev);
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Mikhail Ulyanov 已提交
3263 3264
	int ret = 0;

3265 3266 3267 3268 3269 3270
	if (!netif_running(ndev))
		return 0;

	if (mdp->wol_enabled)
		ret = sh_eth_wol_restore(ndev);
	else
M
Mikhail Ulyanov 已提交
3271
		ret = sh_eth_open(ndev);
3272 3273 3274 3275 3276

	if (ret < 0)
		return ret;

	netif_device_attach(ndev);
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Mikhail Ulyanov 已提交
3277 3278 3279 3280 3281

	return ret;
}
#endif

3282 3283
static int sh_eth_runtime_nop(struct device *dev)
{
S
Sergei Shtylyov 已提交
3284
	/* Runtime PM callback shared between ->runtime_suspend()
3285 3286 3287 3288 3289 3290 3291 3292 3293
	 * and ->runtime_resume(). Simply returns success.
	 *
	 * This driver re-initializes all registers after
	 * pm_runtime_get_sync() anyway so there is no need
	 * to save and restore registers here.
	 */
	return 0;
}

3294
static const struct dev_pm_ops sh_eth_dev_pm_ops = {
M
Mikhail Ulyanov 已提交
3295
	SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3296
	SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3297
};
3298 3299 3300 3301
#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
#else
#define SH_ETH_PM_OPS NULL
#endif
3302

3303
static struct platform_device_id sh_eth_id_table[] = {
3304
	{ "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3305
	{ "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3306
	{ "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3307
	{ "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3308 3309
	{ "sh7757-ether", (kernel_ulong_t)&sh7757_data },
	{ "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3310
	{ "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3311 3312 3313 3314
	{ }
};
MODULE_DEVICE_TABLE(platform, sh_eth_id_table);

3315 3316 3317
static struct platform_driver sh_eth_driver = {
	.probe = sh_eth_drv_probe,
	.remove = sh_eth_drv_remove,
3318
	.id_table = sh_eth_id_table,
3319 3320
	.driver = {
		   .name = CARDNAME,
3321
		   .pm = SH_ETH_PM_OPS,
3322
		   .of_match_table = of_match_ptr(sh_eth_match_table),
3323 3324 3325
	},
};

3326
module_platform_driver(sh_eth_driver);
3327 3328 3329 3330

MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
MODULE_LICENSE("GPL v2");