sh_eth.c 71.2 KB
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Sergei Shtylyov 已提交
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/*  SuperH Ethernet device driver
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 *
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 *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
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 *  Copyright (C) 2008-2014 Renesas Solutions Corp.
 *  Copyright (C) 2013-2014 Cogent Embedded, Inc.
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Ben Dooks 已提交
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 *  Copyright (C) 2014 Codethink Limited
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 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms and conditions of the GNU General Public License,
 *  version 2, as published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 *  more details.
 *
 *  The full GNU General Public License is included in this distribution in
 *  the file called "COPYING".
 */

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Yoshihiro Shimoda 已提交
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#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/mdio-bitbang.h>
#include <linux/netdevice.h>
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#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/of_net.h>
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#include <linux/phy.h>
#include <linux/cache.h>
#include <linux/io.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/ethtool.h>
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#include <linux/if_vlan.h>
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#include <linux/clk.h>
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#include <linux/sh_eth.h>
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Ben Dooks 已提交
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#include <linux/of_mdio.h>
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#include "sh_eth.h"

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#define SH_ETH_DEF_MSG_ENABLE \
		(NETIF_MSG_LINK	| \
		NETIF_MSG_TIMER	| \
		NETIF_MSG_RX_ERR| \
		NETIF_MSG_TX_ERR)

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static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
	[EDSR]		= 0x0000,
	[EDMR]		= 0x0400,
	[EDTRR]		= 0x0408,
	[EDRRR]		= 0x0410,
	[EESR]		= 0x0428,
	[EESIPR]	= 0x0430,
	[TDLAR]		= 0x0010,
	[TDFAR]		= 0x0014,
	[TDFXR]		= 0x0018,
	[TDFFR]		= 0x001c,
	[RDLAR]		= 0x0030,
	[RDFAR]		= 0x0034,
	[RDFXR]		= 0x0038,
	[RDFFR]		= 0x003c,
	[TRSCER]	= 0x0438,
	[RMFCR]		= 0x0440,
	[TFTR]		= 0x0448,
	[FDR]		= 0x0450,
	[RMCR]		= 0x0458,
	[RPADIR]	= 0x0460,
	[FCFTR]		= 0x0468,
	[CSMR]		= 0x04E4,

	[ECMR]		= 0x0500,
	[ECSR]		= 0x0510,
	[ECSIPR]	= 0x0518,
	[PIR]		= 0x0520,
	[PSR]		= 0x0528,
	[PIPR]		= 0x052c,
	[RFLR]		= 0x0508,
	[APR]		= 0x0554,
	[MPR]		= 0x0558,
	[PFTCR]		= 0x055c,
	[PFRCR]		= 0x0560,
	[TPAUSER]	= 0x0564,
	[GECMR]		= 0x05b0,
	[BCULR]		= 0x05b4,
	[MAHR]		= 0x05c0,
	[MALR]		= 0x05c8,
	[TROCR]		= 0x0700,
	[CDCR]		= 0x0708,
	[LCCR]		= 0x0710,
	[CEFCR]		= 0x0740,
	[FRECR]		= 0x0748,
	[TSFRCR]	= 0x0750,
	[TLFRCR]	= 0x0758,
	[RFCR]		= 0x0760,
	[CERCR]		= 0x0768,
	[CEECR]		= 0x0770,
	[MAFCR]		= 0x0778,
	[RMII_MII]	= 0x0790,

	[ARSTR]		= 0x0000,
	[TSU_CTRST]	= 0x0004,
	[TSU_FWEN0]	= 0x0010,
	[TSU_FWEN1]	= 0x0014,
	[TSU_FCM]	= 0x0018,
	[TSU_BSYSL0]	= 0x0020,
	[TSU_BSYSL1]	= 0x0024,
	[TSU_PRISL0]	= 0x0028,
	[TSU_PRISL1]	= 0x002c,
	[TSU_FWSL0]	= 0x0030,
	[TSU_FWSL1]	= 0x0034,
	[TSU_FWSLC]	= 0x0038,
	[TSU_QTAG0]	= 0x0040,
	[TSU_QTAG1]	= 0x0044,
	[TSU_FWSR]	= 0x0050,
	[TSU_FWINMK]	= 0x0054,
	[TSU_ADQT0]	= 0x0048,
	[TSU_ADQT1]	= 0x004c,
	[TSU_VTAG0]	= 0x0058,
	[TSU_VTAG1]	= 0x005c,
	[TSU_ADSBSY]	= 0x0060,
	[TSU_TEN]	= 0x0064,
	[TSU_POST1]	= 0x0070,
	[TSU_POST2]	= 0x0074,
	[TSU_POST3]	= 0x0078,
	[TSU_POST4]	= 0x007c,
	[TSU_ADRH0]	= 0x0100,
	[TSU_ADRL0]	= 0x0104,
	[TSU_ADRH31]	= 0x01f8,
	[TSU_ADRL31]	= 0x01fc,

	[TXNLCR0]	= 0x0080,
	[TXALCR0]	= 0x0084,
	[RXNLCR0]	= 0x0088,
	[RXALCR0]	= 0x008c,
	[FWNLCR0]	= 0x0090,
	[FWALCR0]	= 0x0094,
	[TXNLCR1]	= 0x00a0,
	[TXALCR1]	= 0x00a0,
	[RXNLCR1]	= 0x00a8,
	[RXALCR1]	= 0x00ac,
	[FWNLCR1]	= 0x00b0,
	[FWALCR1]	= 0x00b4,
};

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Simon Horman 已提交
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static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
	[EDSR]		= 0x0000,
	[EDMR]		= 0x0400,
	[EDTRR]		= 0x0408,
	[EDRRR]		= 0x0410,
	[EESR]		= 0x0428,
	[EESIPR]	= 0x0430,
	[TDLAR]		= 0x0010,
	[TDFAR]		= 0x0014,
	[TDFXR]		= 0x0018,
	[TDFFR]		= 0x001c,
	[RDLAR]		= 0x0030,
	[RDFAR]		= 0x0034,
	[RDFXR]		= 0x0038,
	[RDFFR]		= 0x003c,
	[TRSCER]	= 0x0438,
	[RMFCR]		= 0x0440,
	[TFTR]		= 0x0448,
	[FDR]		= 0x0450,
	[RMCR]		= 0x0458,
	[RPADIR]	= 0x0460,
	[FCFTR]		= 0x0468,
	[CSMR]		= 0x04E4,

	[ECMR]		= 0x0500,
	[RFLR]		= 0x0508,
	[ECSR]		= 0x0510,
	[ECSIPR]	= 0x0518,
	[PIR]		= 0x0520,
	[APR]		= 0x0554,
	[MPR]		= 0x0558,
	[PFTCR]		= 0x055c,
	[PFRCR]		= 0x0560,
	[TPAUSER]	= 0x0564,
	[MAHR]		= 0x05c0,
	[MALR]		= 0x05c8,
	[CEFCR]		= 0x0740,
	[FRECR]		= 0x0748,
	[TSFRCR]	= 0x0750,
	[TLFRCR]	= 0x0758,
	[RFCR]		= 0x0760,
	[MAFCR]		= 0x0778,

	[ARSTR]		= 0x0000,
	[TSU_CTRST]	= 0x0004,
	[TSU_VTAG0]	= 0x0058,
	[TSU_ADSBSY]	= 0x0060,
	[TSU_TEN]	= 0x0064,
	[TSU_ADRH0]	= 0x0100,
	[TSU_ADRL0]	= 0x0104,
	[TSU_ADRH31]	= 0x01f8,
	[TSU_ADRL31]	= 0x01fc,

	[TXNLCR0]	= 0x0080,
	[TXALCR0]	= 0x0084,
	[RXNLCR0]	= 0x0088,
	[RXALCR0]	= 0x008C,
};

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static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
	[ECMR]		= 0x0300,
	[RFLR]		= 0x0308,
	[ECSR]		= 0x0310,
	[ECSIPR]	= 0x0318,
	[PIR]		= 0x0320,
	[PSR]		= 0x0328,
	[RDMLR]		= 0x0340,
	[IPGR]		= 0x0350,
	[APR]		= 0x0354,
	[MPR]		= 0x0358,
	[RFCF]		= 0x0360,
	[TPAUSER]	= 0x0364,
	[TPAUSECR]	= 0x0368,
	[MAHR]		= 0x03c0,
	[MALR]		= 0x03c8,
	[TROCR]		= 0x03d0,
	[CDCR]		= 0x03d4,
	[LCCR]		= 0x03d8,
	[CNDCR]		= 0x03dc,
	[CEFCR]		= 0x03e4,
	[FRECR]		= 0x03e8,
	[TSFRCR]	= 0x03ec,
	[TLFRCR]	= 0x03f0,
	[RFCR]		= 0x03f4,
	[MAFCR]		= 0x03f8,

	[EDMR]		= 0x0200,
	[EDTRR]		= 0x0208,
	[EDRRR]		= 0x0210,
	[TDLAR]		= 0x0218,
	[RDLAR]		= 0x0220,
	[EESR]		= 0x0228,
	[EESIPR]	= 0x0230,
	[TRSCER]	= 0x0238,
	[RMFCR]		= 0x0240,
	[TFTR]		= 0x0248,
	[FDR]		= 0x0250,
	[RMCR]		= 0x0258,
	[TFUCR]		= 0x0264,
	[RFOCR]		= 0x0268,
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	[RMIIMODE]      = 0x026c,
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	[FCFTR]		= 0x0270,
	[TRIMD]		= 0x027c,
};

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static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
	[ECMR]		= 0x0100,
	[RFLR]		= 0x0108,
	[ECSR]		= 0x0110,
	[ECSIPR]	= 0x0118,
	[PIR]		= 0x0120,
	[PSR]		= 0x0128,
	[RDMLR]		= 0x0140,
	[IPGR]		= 0x0150,
	[APR]		= 0x0154,
	[MPR]		= 0x0158,
	[TPAUSER]	= 0x0164,
	[RFCF]		= 0x0160,
	[TPAUSECR]	= 0x0168,
	[BCFRR]		= 0x016c,
	[MAHR]		= 0x01c0,
	[MALR]		= 0x01c8,
	[TROCR]		= 0x01d0,
	[CDCR]		= 0x01d4,
	[LCCR]		= 0x01d8,
	[CNDCR]		= 0x01dc,
	[CEFCR]		= 0x01e4,
	[FRECR]		= 0x01e8,
	[TSFRCR]	= 0x01ec,
	[TLFRCR]	= 0x01f0,
	[RFCR]		= 0x01f4,
	[MAFCR]		= 0x01f8,
	[RTRATE]	= 0x01fc,

	[EDMR]		= 0x0000,
	[EDTRR]		= 0x0008,
	[EDRRR]		= 0x0010,
	[TDLAR]		= 0x0018,
	[RDLAR]		= 0x0020,
	[EESR]		= 0x0028,
	[EESIPR]	= 0x0030,
	[TRSCER]	= 0x0038,
	[RMFCR]		= 0x0040,
	[TFTR]		= 0x0048,
	[FDR]		= 0x0050,
	[RMCR]		= 0x0058,
	[TFUCR]		= 0x0064,
	[RFOCR]		= 0x0068,
	[FCFTR]		= 0x0070,
	[RPADIR]	= 0x0078,
	[TRIMD]		= 0x007c,
	[RBWAR]		= 0x00c8,
	[RDFAR]		= 0x00cc,
	[TBRAR]		= 0x00d4,
	[TDFAR]		= 0x00d8,
};

static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
	[ECMR]		= 0x0160,
	[ECSR]		= 0x0164,
	[ECSIPR]	= 0x0168,
	[PIR]		= 0x016c,
	[MAHR]		= 0x0170,
	[MALR]		= 0x0174,
	[RFLR]		= 0x0178,
	[PSR]		= 0x017c,
	[TROCR]		= 0x0180,
	[CDCR]		= 0x0184,
	[LCCR]		= 0x0188,
	[CNDCR]		= 0x018c,
	[CEFCR]		= 0x0194,
	[FRECR]		= 0x0198,
	[TSFRCR]	= 0x019c,
	[TLFRCR]	= 0x01a0,
	[RFCR]		= 0x01a4,
	[MAFCR]		= 0x01a8,
	[IPGR]		= 0x01b4,
	[APR]		= 0x01b8,
	[MPR]		= 0x01bc,
	[TPAUSER]	= 0x01c4,
	[BCFR]		= 0x01cc,

	[ARSTR]		= 0x0000,
	[TSU_CTRST]	= 0x0004,
	[TSU_FWEN0]	= 0x0010,
	[TSU_FWEN1]	= 0x0014,
	[TSU_FCM]	= 0x0018,
	[TSU_BSYSL0]	= 0x0020,
	[TSU_BSYSL1]	= 0x0024,
	[TSU_PRISL0]	= 0x0028,
	[TSU_PRISL1]	= 0x002c,
	[TSU_FWSL0]	= 0x0030,
	[TSU_FWSL1]	= 0x0034,
	[TSU_FWSLC]	= 0x0038,
	[TSU_QTAGM0]	= 0x0040,
	[TSU_QTAGM1]	= 0x0044,
	[TSU_ADQT0]	= 0x0048,
	[TSU_ADQT1]	= 0x004c,
	[TSU_FWSR]	= 0x0050,
	[TSU_FWINMK]	= 0x0054,
	[TSU_ADSBSY]	= 0x0060,
	[TSU_TEN]	= 0x0064,
	[TSU_POST1]	= 0x0070,
	[TSU_POST2]	= 0x0074,
	[TSU_POST3]	= 0x0078,
	[TSU_POST4]	= 0x007c,

	[TXNLCR0]	= 0x0080,
	[TXALCR0]	= 0x0084,
	[RXNLCR0]	= 0x0088,
	[RXALCR0]	= 0x008c,
	[FWNLCR0]	= 0x0090,
	[FWALCR0]	= 0x0094,
	[TXNLCR1]	= 0x00a0,
	[TXALCR1]	= 0x00a0,
	[RXNLCR1]	= 0x00a8,
	[RXALCR1]	= 0x00ac,
	[FWNLCR1]	= 0x00b0,
	[FWALCR1]	= 0x00b4,

	[TSU_ADRH0]	= 0x0100,
	[TSU_ADRL0]	= 0x0104,
	[TSU_ADRL31]	= 0x01fc,
};

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static bool sh_eth_is_gether(struct sh_eth_private *mdp)
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{
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	return mdp->reg_offset == sh_eth_offset_gigabit;
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}

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static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
{
	return mdp->reg_offset == sh_eth_offset_fast_rz;
}

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static void sh_eth_select_mii(struct net_device *ndev)
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{
	u32 value = 0x0;
	struct sh_eth_private *mdp = netdev_priv(ndev);

	switch (mdp->phy_interface) {
	case PHY_INTERFACE_MODE_GMII:
		value = 0x2;
		break;
	case PHY_INTERFACE_MODE_MII:
		value = 0x1;
		break;
	case PHY_INTERFACE_MODE_RMII:
		value = 0x0;
		break;
	default:
		pr_warn("PHY interface mode was not setup. Set to MII.\n");
		value = 0x1;
		break;
	}

	sh_eth_write(ndev, value, RMII_MII);
}

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static void sh_eth_set_duplex(struct net_device *ndev)
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{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	if (mdp->duplex) /* Full */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
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	else		/* Half */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
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}

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/* There is CPU dependent code */
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static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
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{
	struct sh_eth_private *mdp = netdev_priv(ndev);
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	switch (mdp->speed) {
	case 10: /* 10BASE */
		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
		break;
	case 100:/* 100BASE */
		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
		break;
	default:
		break;
	}
}

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/* R8A7778/9 */
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static struct sh_eth_cpu_data r8a777x_data = {
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	.set_duplex	= sh_eth_set_duplex,
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	.set_rate	= sh_eth_set_rate_r8a777x,
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	.register_type	= SH_ETH_REG_FAST_RCAR,

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	.ecsr_value	= ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
	.ecsipr_value	= ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
	.eesipr_value	= 0x01ff009f,

	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
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	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
			  EESR_ECI,
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	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
};

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/* R8A7790/1 */
static struct sh_eth_cpu_data r8a779x_data = {
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	.set_duplex	= sh_eth_set_duplex,
	.set_rate	= sh_eth_set_rate_r8a777x,

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	.register_type	= SH_ETH_REG_FAST_RCAR,

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	.ecsr_value	= ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
	.ecsipr_value	= ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
	.eesipr_value	= 0x01ff009f,

	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
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	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
			  EESR_ECI,
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	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
	.rmiimode	= 1,
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	.shift_rd0	= 1,
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};

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static void sh_eth_set_rate_sh7724(struct net_device *ndev)
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{
	struct sh_eth_private *mdp = netdev_priv(ndev);
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	switch (mdp->speed) {
	case 10: /* 10BASE */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
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		break;
	case 100:/* 100BASE */
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		sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
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		break;
	default:
		break;
	}
}

/* SH7724 */
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static struct sh_eth_cpu_data sh7724_data = {
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	.set_duplex	= sh_eth_set_duplex,
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	.set_rate	= sh_eth_set_rate_sh7724,
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	.register_type	= SH_ETH_REG_FAST_SH4,

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	.ecsr_value	= ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
	.ecsipr_value	= ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
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	.eesipr_value	= 0x01ff009f,
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	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
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	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
			  EESR_ECI,
515 516 517 518 519

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
520 521
	.rpadir		= 1,
	.rpadir_value	= 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
522
};
523

524
static void sh_eth_set_rate_sh7757(struct net_device *ndev)
525 526 527 528 529
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	switch (mdp->speed) {
	case 10: /* 10BASE */
530
		sh_eth_write(ndev, 0, RTRATE);
531 532
		break;
	case 100:/* 100BASE */
533
		sh_eth_write(ndev, 1, RTRATE);
534 535 536 537 538 539 540
		break;
	default:
		break;
	}
}

/* SH7757 */
541 542 543
static struct sh_eth_cpu_data sh7757_data = {
	.set_duplex	= sh_eth_set_duplex,
	.set_rate	= sh_eth_set_rate_sh7757,
544

545 546
	.register_type	= SH_ETH_REG_FAST_SH4,

547
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
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548
	.rmcr_value	= RMCR_RNC,
549 550

	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
551 552 553
	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
			  EESR_ECI,
554

555
	.irq_flags	= IRQF_SHARED,
556 557 558 559 560
	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
	.no_ade		= 1,
561 562
	.rpadir		= 1,
	.rpadir_value   = 2 << 16,
563
};
564

565
#define SH_GIGA_ETH_BASE	0xfee00000UL
566 567 568 569 570 571 572 573 574
#define GIGA_MALR(port)		(SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
#define GIGA_MAHR(port)		(SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
static void sh_eth_chip_reset_giga(struct net_device *ndev)
{
	int i;
	unsigned long mahr[2], malr[2];

	/* save MAHR and MALR */
	for (i = 0; i < 2; i++) {
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		malr[i] = ioread32((void *)GIGA_MALR(i));
		mahr[i] = ioread32((void *)GIGA_MAHR(i));
577 578 579
	}

	/* reset device */
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580
	iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
581 582 583 584
	mdelay(1);

	/* restore MAHR and MALR */
	for (i = 0; i < 2; i++) {
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Yoshihiro Shimoda 已提交
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		iowrite32(malr[i], (void *)GIGA_MALR(i));
		iowrite32(mahr[i], (void *)GIGA_MAHR(i));
587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609
	}
}

static void sh_eth_set_rate_giga(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	switch (mdp->speed) {
	case 10: /* 10BASE */
		sh_eth_write(ndev, 0x00000000, GECMR);
		break;
	case 100:/* 100BASE */
		sh_eth_write(ndev, 0x00000010, GECMR);
		break;
	case 1000: /* 1000BASE */
		sh_eth_write(ndev, 0x00000020, GECMR);
		break;
	default:
		break;
	}
}

/* SH7757(GETHERC) */
610
static struct sh_eth_cpu_data sh7757_data_giga = {
611
	.chip_reset	= sh_eth_chip_reset_giga,
612
	.set_duplex	= sh_eth_set_duplex,
613 614
	.set_rate	= sh_eth_set_rate_giga,

615 616
	.register_type	= SH_ETH_REG_GIGABIT,

617 618 619 620 621
	.ecsr_value	= ECSR_ICD | ECSR_MPD,
	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.tx_check	= EESR_TC1 | EESR_FTC,
622 623 624
	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
			  EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
			  EESR_TDE | EESR_ECI,
625
	.fdr_value	= 0x0000072f,
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	.rmcr_value	= RMCR_RNC,
627

628
	.irq_flags	= IRQF_SHARED,
629 630 631 632 633 634 635 636 637
	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.bculr		= 1,
	.hw_swap	= 1,
	.rpadir		= 1,
	.rpadir_value   = 2 << 16,
	.no_trimd	= 1,
	.no_ade		= 1,
638
	.tsu		= 1,
639 640
};

641 642
static void sh_eth_chip_reset(struct net_device *ndev)
{
643 644
	struct sh_eth_private *mdp = netdev_priv(ndev);

645
	/* reset device */
646
	sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
647 648 649
	mdelay(1);
}

650
static void sh_eth_set_rate_gether(struct net_device *ndev)
651 652 653 654 655
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	switch (mdp->speed) {
	case 10: /* 10BASE */
656
		sh_eth_write(ndev, GECMR_10, GECMR);
657 658
		break;
	case 100:/* 100BASE */
659
		sh_eth_write(ndev, GECMR_100, GECMR);
660 661
		break;
	case 1000: /* 1000BASE */
662
		sh_eth_write(ndev, GECMR_1000, GECMR);
663 664 665 666 667 668
		break;
	default:
		break;
	}
}

669 670
/* SH7734 */
static struct sh_eth_cpu_data sh7734_data = {
671 672
	.chip_reset	= sh_eth_chip_reset,
	.set_duplex	= sh_eth_set_duplex,
673 674
	.set_rate	= sh_eth_set_rate_gether,

675 676
	.register_type	= SH_ETH_REG_GIGABIT,

677 678 679 680 681
	.ecsr_value	= ECSR_ICD | ECSR_MPD,
	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.tx_check	= EESR_TC1 | EESR_FTC,
682 683 684
	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
			  EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
			  EESR_TDE | EESR_ECI,
685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.bculr		= 1,
	.hw_swap	= 1,
	.no_trimd	= 1,
	.no_ade		= 1,
	.tsu		= 1,
	.hw_crc		= 1,
	.select_mii	= 1,
};

/* SH7763 */
static struct sh_eth_cpu_data sh7763_data = {
	.chip_reset	= sh_eth_chip_reset,
	.set_duplex	= sh_eth_set_duplex,
	.set_rate	= sh_eth_set_rate_gether,
703

704 705
	.register_type	= SH_ETH_REG_GIGABIT,

706 707 708 709 710
	.ecsr_value	= ECSR_ICD | ECSR_MPD,
	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.tx_check	= EESR_TC1 | EESR_FTC,
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	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
			  EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
713 714 715 716 717 718 719 720 721
			  EESR_ECI,

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.bculr		= 1,
	.hw_swap	= 1,
	.no_trimd	= 1,
	.no_ade		= 1,
722
	.tsu		= 1,
723
	.irq_flags	= IRQF_SHARED,
724 725
};

726
static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
727 728 729 730 731 732 733
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	/* reset device */
	sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
	mdelay(1);

734
	sh_eth_select_mii(ndev);
735 736 737
}

/* R8A7740 */
738 739
static struct sh_eth_cpu_data r8a7740_data = {
	.chip_reset	= sh_eth_chip_reset_r8a7740,
740
	.set_duplex	= sh_eth_set_duplex,
741
	.set_rate	= sh_eth_set_rate_gether,
742

743 744
	.register_type	= SH_ETH_REG_GIGABIT,

745 746 747 748 749
	.ecsr_value	= ECSR_ICD | ECSR_MPD,
	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.tx_check	= EESR_TC1 | EESR_FTC,
750 751 752
	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
			  EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
			  EESR_TDE | EESR_ECI,
753
	.fdr_value	= 0x0000070f,
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Sergei Shtylyov 已提交
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	.rmcr_value	= RMCR_RNC,
755 756 757 758 759 760

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.bculr		= 1,
	.hw_swap	= 1,
761 762
	.rpadir		= 1,
	.rpadir_value   = 2 << 16,
763 764 765
	.no_trimd	= 1,
	.no_ade		= 1,
	.tsu		= 1,
766
	.select_mii	= 1,
767
	.shift_rd0	= 1,
768 769
};

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770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801
/* R7S72100 */
static struct sh_eth_cpu_data r7s72100_data = {
	.chip_reset	= sh_eth_chip_reset,
	.set_duplex	= sh_eth_set_duplex,

	.register_type	= SH_ETH_REG_FAST_RZ,

	.ecsr_value	= ECSR_ICD,
	.ecsipr_value	= ECSIPR_ICDIP,
	.eesipr_value	= 0xff7f009f,

	.tx_check	= EESR_TC1 | EESR_FTC,
	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
			  EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
			  EESR_TDE | EESR_ECI,
	.fdr_value	= 0x0000070f,
	.rmcr_value	= RMCR_RNC,

	.no_psr		= 1,
	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
	.rpadir		= 1,
	.rpadir_value   = 2 << 16,
	.no_trimd	= 1,
	.no_ade		= 1,
	.hw_crc		= 1,
	.tsu		= 1,
	.shift_rd0	= 1,
};

802
static struct sh_eth_cpu_data sh7619_data = {
803 804
	.register_type	= SH_ETH_REG_FAST_SH3_SH2,

805 806 807 808 809 810 811
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,

	.apr		= 1,
	.mpr		= 1,
	.tpauser	= 1,
	.hw_swap	= 1,
};
812 813

static struct sh_eth_cpu_data sh771x_data = {
814 815
	.register_type	= SH_ETH_REG_FAST_SH3_SH2,

816
	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
817
	.tsu		= 1,
818 819 820 821 822 823 824 825 826 827 828
};

static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
{
	if (!cd->ecsr_value)
		cd->ecsr_value = DEFAULT_ECSR_INIT;

	if (!cd->ecsipr_value)
		cd->ecsipr_value = DEFAULT_ECSIPR_INIT;

	if (!cd->fcftr_value)
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Sergei Shtylyov 已提交
829
		cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
830 831 832 833 834 835 836 837 838 839 840 841 842 843 844
				  DEFAULT_FIFO_F_D_RFD;

	if (!cd->fdr_value)
		cd->fdr_value = DEFAULT_FDR_INIT;

	if (!cd->rmcr_value)
		cd->rmcr_value = DEFAULT_RMCR_VALUE;

	if (!cd->tx_check)
		cd->tx_check = DEFAULT_TX_CHECK;

	if (!cd->eesr_err_check)
		cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
}

845 846 847 848 849 850 851 852 853 854 855
static int sh_eth_check_reset(struct net_device *ndev)
{
	int ret = 0;
	int cnt = 100;

	while (cnt > 0) {
		if (!(sh_eth_read(ndev, EDMR) & 0x3))
			break;
		mdelay(1);
		cnt--;
	}
856 857
	if (cnt <= 0) {
		pr_err("Device reset failed\n");
858 859 860
		ret = -ETIMEDOUT;
	}
	return ret;
861
}
862 863 864 865 866 867

static int sh_eth_reset(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int ret = 0;

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Simon Horman 已提交
868
	if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904
		sh_eth_write(ndev, EDSR_ENALL, EDSR);
		sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
			     EDMR);

		ret = sh_eth_check_reset(ndev);
		if (ret)
			goto out;

		/* Table Init */
		sh_eth_write(ndev, 0x0, TDLAR);
		sh_eth_write(ndev, 0x0, TDFAR);
		sh_eth_write(ndev, 0x0, TDFXR);
		sh_eth_write(ndev, 0x0, TDFFR);
		sh_eth_write(ndev, 0x0, RDLAR);
		sh_eth_write(ndev, 0x0, RDFAR);
		sh_eth_write(ndev, 0x0, RDFXR);
		sh_eth_write(ndev, 0x0, RDFFR);

		/* Reset HW CRC register */
		if (mdp->cd->hw_crc)
			sh_eth_write(ndev, 0x0, CSMR);

		/* Select MII mode */
		if (mdp->cd->select_mii)
			sh_eth_select_mii(ndev);
	} else {
		sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
			     EDMR);
		mdelay(3);
		sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
			     EDMR);
	}

out:
	return ret;
}
905

906
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922
static void sh_eth_set_receive_align(struct sk_buff *skb)
{
	int reserve;

	reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
	if (reserve)
		skb_reserve(skb, reserve);
}
#else
static void sh_eth_set_receive_align(struct sk_buff *skb)
{
	skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
}
#endif


923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945
/* CPU <-> EDMAC endian convert */
static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
{
	switch (mdp->edmac_endian) {
	case EDMAC_LITTLE_ENDIAN:
		return cpu_to_le32(x);
	case EDMAC_BIG_ENDIAN:
		return cpu_to_be32(x);
	}
	return x;
}

static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
{
	switch (mdp->edmac_endian) {
	case EDMAC_LITTLE_ENDIAN:
		return le32_to_cpu(x);
	case EDMAC_BIG_ENDIAN:
		return be32_to_cpu(x);
	}
	return x;
}

S
Sergei Shtylyov 已提交
946
/* Program the hardware MAC address from dev->dev_addr. */
947 948
static void update_mac_address(struct net_device *ndev)
{
949
	sh_eth_write(ndev,
S
Sergei Shtylyov 已提交
950 951
		     (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
		     (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
952
	sh_eth_write(ndev,
S
Sergei Shtylyov 已提交
953
		     (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
954 955
}

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956
/* Get MAC address from SuperH MAC address register
957 958 959 960 961 962
 *
 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 * When you want use this device, you must set MAC address in bootloader.
 *
 */
963
static void read_mac_address(struct net_device *ndev, unsigned char *mac)
964
{
965
	if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
966
		memcpy(ndev->dev_addr, mac, ETH_ALEN);
967
	} else {
968 969 970 971 972 973
		ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
		ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
		ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
		ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
		ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
		ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
974
	}
975 976
}

977 978
static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
{
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Simon Horman 已提交
979
	if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
980 981 982 983 984
		return EDTRR_TRNS_GETHER;
	else
		return EDTRR_TRNS_ETHER;
}

985
struct bb_info {
Y
Yoshihiro Shimoda 已提交
986
	void (*set_gate)(void *addr);
987
	struct mdiobb_ctrl ctrl;
Y
Yoshihiro Shimoda 已提交
988
	void *addr;
989 990 991 992 993 994 995
	u32 mmd_msk;/* MMD */
	u32 mdo_msk;
	u32 mdi_msk;
	u32 mdc_msk;
};

/* PHY bit set */
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Yoshihiro Shimoda 已提交
996
static void bb_set(void *addr, u32 msk)
997
{
Y
Yoshihiro Shimoda 已提交
998
	iowrite32(ioread32(addr) | msk, addr);
999 1000 1001
}

/* PHY bit clear */
Y
Yoshihiro Shimoda 已提交
1002
static void bb_clr(void *addr, u32 msk)
1003
{
Y
Yoshihiro Shimoda 已提交
1004
	iowrite32((ioread32(addr) & ~msk), addr);
1005 1006 1007
}

/* PHY bit read */
Y
Yoshihiro Shimoda 已提交
1008
static int bb_read(void *addr, u32 msk)
1009
{
Y
Yoshihiro Shimoda 已提交
1010
	return (ioread32(addr) & msk) != 0;
1011 1012 1013 1014 1015 1016
}

/* Data I/O pin control */
static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
{
	struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1017 1018 1019 1020

	if (bitbang->set_gate)
		bitbang->set_gate(bitbang->addr);

1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031
	if (bit)
		bb_set(bitbang->addr, bitbang->mmd_msk);
	else
		bb_clr(bitbang->addr, bitbang->mmd_msk);
}

/* Set bit data*/
static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
{
	struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);

1032 1033 1034
	if (bitbang->set_gate)
		bitbang->set_gate(bitbang->addr);

1035 1036 1037 1038 1039 1040 1041 1042 1043 1044
	if (bit)
		bb_set(bitbang->addr, bitbang->mdo_msk);
	else
		bb_clr(bitbang->addr, bitbang->mdo_msk);
}

/* Get bit data*/
static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
{
	struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1045 1046 1047 1048

	if (bitbang->set_gate)
		bitbang->set_gate(bitbang->addr);

1049 1050 1051 1052 1053 1054 1055 1056
	return bb_read(bitbang->addr, bitbang->mdi_msk);
}

/* MDC pin control */
static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
{
	struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);

1057 1058 1059
	if (bitbang->set_gate)
		bitbang->set_gate(bitbang->addr);

1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082
	if (bit)
		bb_set(bitbang->addr, bitbang->mdc_msk);
	else
		bb_clr(bitbang->addr, bitbang->mdc_msk);
}

/* mdio bus control struct */
static struct mdiobb_ops bb_ops = {
	.owner = THIS_MODULE,
	.set_mdc = sh_mdc_ctrl,
	.set_mdio_dir = sh_mmd_ctrl,
	.set_mdio_data = sh_set_mdio,
	.get_mdio_data = sh_get_mdio,
};

/* free skb and descriptor buffer */
static void sh_eth_ring_free(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i;

	/* Free Rx skb ringbuffer */
	if (mdp->rx_skbuff) {
1083
		for (i = 0; i < mdp->num_rx_ring; i++) {
1084 1085 1086 1087 1088
			if (mdp->rx_skbuff[i])
				dev_kfree_skb(mdp->rx_skbuff[i]);
		}
	}
	kfree(mdp->rx_skbuff);
1089
	mdp->rx_skbuff = NULL;
1090 1091 1092

	/* Free Tx skb ringbuffer */
	if (mdp->tx_skbuff) {
1093
		for (i = 0; i < mdp->num_tx_ring; i++) {
1094 1095 1096 1097 1098
			if (mdp->tx_skbuff[i])
				dev_kfree_skb(mdp->tx_skbuff[i]);
		}
	}
	kfree(mdp->tx_skbuff);
1099
	mdp->tx_skbuff = NULL;
1100 1101 1102 1103 1104 1105 1106 1107 1108 1109
}

/* format skb and descriptor buffer */
static void sh_eth_ring_format(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i;
	struct sk_buff *skb;
	struct sh_eth_rxdesc *rxdesc = NULL;
	struct sh_eth_txdesc *txdesc = NULL;
1110 1111
	int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
	int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1112

S
Sergei Shtylyov 已提交
1113 1114 1115 1116
	mdp->cur_rx = 0;
	mdp->cur_tx = 0;
	mdp->dirty_rx = 0;
	mdp->dirty_tx = 0;
1117 1118 1119 1120

	memset(mdp->rx_ring, 0, rx_ringsize);

	/* build Rx ring buffer */
1121
	for (i = 0; i < mdp->num_rx_ring; i++) {
1122 1123
		/* skb */
		mdp->rx_skbuff[i] = NULL;
1124
		skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1125 1126 1127
		mdp->rx_skbuff[i] = skb;
		if (skb == NULL)
			break;
1128
		dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
S
Sergei Shtylyov 已提交
1129
			       DMA_FROM_DEVICE);
1130 1131
		sh_eth_set_receive_align(skb);

1132 1133
		/* RX descriptor */
		rxdesc = &mdp->rx_ring[i];
1134
		rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1135
		rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1136 1137

		/* The size of the buffer is 16 byte boundary. */
1138
		rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1139 1140
		/* Rx descriptor address set */
		if (i == 0) {
1141
			sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
S
Simon Horman 已提交
1142 1143
			if (sh_eth_is_gether(mdp) ||
			    sh_eth_is_rz_fast_ether(mdp))
1144
				sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1145
		}
1146 1147
	}

1148
	mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1149 1150

	/* Mark the last entry as wrapping the ring. */
1151
	rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1152 1153 1154 1155

	memset(mdp->tx_ring, 0, tx_ringsize);

	/* build Tx ring buffer */
1156
	for (i = 0; i < mdp->num_tx_ring; i++) {
1157 1158
		mdp->tx_skbuff[i] = NULL;
		txdesc = &mdp->tx_ring[i];
1159
		txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1160
		txdesc->buffer_length = 0;
1161
		if (i == 0) {
1162
			/* Tx descriptor address set */
1163
			sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
S
Simon Horman 已提交
1164 1165
			if (sh_eth_is_gether(mdp) ||
			    sh_eth_is_rz_fast_ether(mdp))
1166
				sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1167
		}
1168 1169
	}

1170
	txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1171 1172 1173 1174 1175 1176 1177 1178
}

/* Get skb and descriptor buffer */
static int sh_eth_ring_init(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int rx_ringsize, tx_ringsize, ret = 0;

S
Sergei Shtylyov 已提交
1179
	/* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1180 1181 1182 1183 1184 1185
	 * card needs room to do 8 byte alignment, +2 so we can reserve
	 * the first 2 bytes, and +16 gets room for the status word from the
	 * card.
	 */
	mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
			  (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1186 1187
	if (mdp->cd->rpadir)
		mdp->rx_buf_sz += NET_IP_ALIGN;
1188 1189

	/* Allocate RX and TX skb rings */
1190 1191
	mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
				       sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1192 1193 1194 1195 1196
	if (!mdp->rx_skbuff) {
		ret = -ENOMEM;
		return ret;
	}

1197 1198
	mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
				       sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1199 1200 1201 1202 1203 1204
	if (!mdp->tx_skbuff) {
		ret = -ENOMEM;
		goto skb_ring_free;
	}

	/* Allocate all Rx descriptors. */
1205
	rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1206
	mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1207
					  GFP_KERNEL);
1208 1209 1210 1211 1212 1213 1214 1215
	if (!mdp->rx_ring) {
		ret = -ENOMEM;
		goto desc_ring_free;
	}

	mdp->dirty_rx = 0;

	/* Allocate all Tx descriptors. */
1216
	tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1217
	mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1218
					  GFP_KERNEL);
1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231
	if (!mdp->tx_ring) {
		ret = -ENOMEM;
		goto desc_ring_free;
	}
	return ret;

desc_ring_free:
	/* free DMA buffer */
	dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);

skb_ring_free:
	/* Free Rx and Tx skb ring buffer */
	sh_eth_ring_free(ndev);
1232 1233
	mdp->tx_ring = NULL;
	mdp->rx_ring = NULL;
1234 1235 1236 1237

	return ret;
}

1238 1239 1240 1241 1242
static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
{
	int ringsize;

	if (mdp->rx_ring) {
1243
		ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1244 1245 1246 1247 1248 1249
		dma_free_coherent(NULL, ringsize, mdp->rx_ring,
				  mdp->rx_desc_dma);
		mdp->rx_ring = NULL;
	}

	if (mdp->tx_ring) {
1250
		ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1251 1252 1253 1254 1255 1256
		dma_free_coherent(NULL, ringsize, mdp->tx_ring,
				  mdp->tx_desc_dma);
		mdp->tx_ring = NULL;
	}
}

1257
static int sh_eth_dev_init(struct net_device *ndev, bool start)
1258 1259 1260 1261 1262 1263
{
	int ret = 0;
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 val;

	/* Soft Reset */
1264 1265 1266
	ret = sh_eth_reset(ndev);
	if (ret)
		goto out;
1267

1268 1269 1270
	if (mdp->cd->rmiimode)
		sh_eth_write(ndev, 0x1, RMIIMODE);

1271 1272
	/* Descriptor format */
	sh_eth_ring_format(ndev);
1273
	if (mdp->cd->rpadir)
1274
		sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1275 1276

	/* all sh_eth int mask */
1277
	sh_eth_write(ndev, 0, EESIPR);
1278

1279
#if defined(__LITTLE_ENDIAN)
1280
	if (mdp->cd->hw_swap)
1281
		sh_eth_write(ndev, EDMR_EL, EDMR);
1282
	else
1283
#endif
1284
		sh_eth_write(ndev, 0, EDMR);
1285

1286
	/* FIFO size set */
1287 1288
	sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
	sh_eth_write(ndev, 0, TFTR);
1289

1290
	/* Frame recv control */
1291
	sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
1292

1293
	sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1294

1295
	if (mdp->cd->bculr)
1296
		sh_eth_write(ndev, 0x800, BCULR);	/* Burst sycle set */
1297

1298
	sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1299

1300
	if (!mdp->cd->no_trimd)
1301
		sh_eth_write(ndev, 0, TRIMD);
1302

1303
	/* Recv frame limit set register */
1304 1305
	sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
		     RFLR);
1306

1307
	sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1308 1309
	if (start)
		sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1310 1311

	/* PAUSE Prohibition */
1312
	val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1313 1314
		ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;

1315
	sh_eth_write(ndev, val, ECMR);
1316

1317 1318 1319
	if (mdp->cd->set_rate)
		mdp->cd->set_rate(ndev);

1320
	/* E-MAC Status Register clear */
1321
	sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1322 1323

	/* E-MAC Interrupt Enable register */
1324 1325
	if (start)
		sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1326 1327 1328 1329 1330

	/* Set MAC address */
	update_mac_address(ndev);

	/* mask reset */
1331
	if (mdp->cd->apr)
1332
		sh_eth_write(ndev, APR_AP, APR);
1333
	if (mdp->cd->mpr)
1334
		sh_eth_write(ndev, MPR_MP, MPR);
1335
	if (mdp->cd->tpauser)
1336
		sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1337

1338 1339 1340
	if (start) {
		/* Setting the Rx mode will start the Rx process. */
		sh_eth_write(ndev, EDRRR_R, EDRRR);
1341

1342 1343
		netif_start_queue(ndev);
	}
1344

1345
out:
1346 1347 1348 1349 1350 1351 1352 1353
	return ret;
}

/* free Tx skb function */
static int sh_eth_txfree(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_txdesc *txdesc;
S
Sergei Shtylyov 已提交
1354
	int free_num = 0;
1355 1356 1357
	int entry = 0;

	for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1358
		entry = mdp->dirty_tx % mdp->num_tx_ring;
1359
		txdesc = &mdp->tx_ring[entry];
1360
		if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1361 1362 1363
			break;
		/* Free the original skb. */
		if (mdp->tx_skbuff[entry]) {
1364 1365
			dma_unmap_single(&ndev->dev, txdesc->addr,
					 txdesc->buffer_length, DMA_TO_DEVICE);
1366 1367
			dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
			mdp->tx_skbuff[entry] = NULL;
S
Sergei Shtylyov 已提交
1368
			free_num++;
1369
		}
1370
		txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1371
		if (entry >= mdp->num_tx_ring - 1)
1372
			txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1373

1374 1375
		ndev->stats.tx_packets++;
		ndev->stats.tx_bytes += txdesc->buffer_length;
1376
	}
S
Sergei Shtylyov 已提交
1377
	return free_num;
1378 1379 1380
}

/* Packet receive function */
S
Sergei Shtylyov 已提交
1381
static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1382 1383 1384 1385
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_rxdesc *rxdesc;

1386 1387
	int entry = mdp->cur_rx % mdp->num_rx_ring;
	int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1388
	struct sk_buff *skb;
S
Sergei Shtylyov 已提交
1389
	int exceeded = 0;
1390
	u16 pkt_len = 0;
1391
	u32 desc_status;
1392 1393

	rxdesc = &mdp->rx_ring[entry];
1394 1395
	while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
		desc_status = edmac_to_cpu(mdp, rxdesc->status);
1396 1397 1398 1399 1400
		pkt_len = rxdesc->frame_length;

		if (--boguscnt < 0)
			break;

S
Sergei Shtylyov 已提交
1401 1402 1403 1404 1405 1406
		if (*quota <= 0) {
			exceeded = 1;
			break;
		}
		(*quota)--;

1407
		if (!(desc_status & RDFEND))
1408
			ndev->stats.rx_length_errors++;
1409

S
Sergei Shtylyov 已提交
1410
		/* In case of almost all GETHER/ETHERs, the Receive Frame State
1411
		 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
S
Simon Horman 已提交
1412 1413 1414
		 * bit 0. However, in case of the R8A7740, R8A779x, and
		 * R7S72100 the RFS bits are from bit 25 to bit 16. So, the
		 * driver needs right shifting by 16.
1415
		 */
1416 1417
		if (mdp->cd->shift_rd0)
			desc_status >>= 16;
1418

1419 1420
		if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
				   RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1421
			ndev->stats.rx_errors++;
1422
			if (desc_status & RD_RFS1)
1423
				ndev->stats.rx_crc_errors++;
1424
			if (desc_status & RD_RFS2)
1425
				ndev->stats.rx_frame_errors++;
1426
			if (desc_status & RD_RFS3)
1427
				ndev->stats.rx_length_errors++;
1428
			if (desc_status & RD_RFS4)
1429
				ndev->stats.rx_length_errors++;
1430
			if (desc_status & RD_RFS6)
1431
				ndev->stats.rx_missed_errors++;
1432
			if (desc_status & RD_RFS10)
1433
				ndev->stats.rx_over_errors++;
1434
		} else {
1435 1436 1437 1438
			if (!mdp->cd->hw_swap)
				sh_eth_soft_swap(
					phys_to_virt(ALIGN(rxdesc->addr, 4)),
					pkt_len + 2);
1439 1440
			skb = mdp->rx_skbuff[entry];
			mdp->rx_skbuff[entry] = NULL;
1441 1442
			if (mdp->cd->rpadir)
				skb_reserve(skb, NET_IP_ALIGN);
1443 1444 1445
			dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,
						mdp->rx_buf_sz,
						DMA_FROM_DEVICE);
1446 1447
			skb_put(skb, pkt_len);
			skb->protocol = eth_type_trans(skb, ndev);
1448
			netif_receive_skb(skb);
1449 1450
			ndev->stats.rx_packets++;
			ndev->stats.rx_bytes += pkt_len;
1451
		}
1452
		rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1453
		entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1454
		rxdesc = &mdp->rx_ring[entry];
1455 1456 1457 1458
	}

	/* Refill the Rx ring buffers. */
	for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1459
		entry = mdp->dirty_rx % mdp->num_rx_ring;
1460
		rxdesc = &mdp->rx_ring[entry];
1461
		/* The size of the buffer is 16 byte boundary. */
1462
		rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1463

1464
		if (mdp->rx_skbuff[entry] == NULL) {
1465
			skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1466 1467 1468
			mdp->rx_skbuff[entry] = skb;
			if (skb == NULL)
				break;	/* Better luck next round. */
1469
			dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
S
Sergei Shtylyov 已提交
1470
				       DMA_FROM_DEVICE);
1471 1472
			sh_eth_set_receive_align(skb);

1473
			skb_checksum_none_assert(skb);
1474
			rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1475
		}
1476
		if (entry >= mdp->num_rx_ring - 1)
1477
			rxdesc->status |=
1478
				cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1479 1480
		else
			rxdesc->status |=
1481
				cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1482 1483 1484 1485
	}

	/* Restart Rx engine if stopped. */
	/* If we don't need to check status, don't. -KDU */
1486
	if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1487
		/* fix the values for the next receiving if RDE is set */
S
Sergei Shtylyov 已提交
1488 1489 1490 1491 1492 1493 1494
		if (intr_status & EESR_RDE) {
			u32 count = (sh_eth_read(ndev, RDFAR) -
				     sh_eth_read(ndev, RDLAR)) >> 4;

			mdp->cur_rx = count;
			mdp->dirty_rx = count;
		}
1495
		sh_eth_write(ndev, EDRRR_R, EDRRR);
1496
	}
1497

S
Sergei Shtylyov 已提交
1498
	return exceeded;
1499 1500
}

1501
static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1502 1503
{
	/* disable tx and rx */
1504 1505
	sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
		~(ECMR_RE | ECMR_TE), ECMR);
1506 1507
}

1508
static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1509 1510
{
	/* enable tx and rx */
1511 1512
	sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
		(ECMR_RE | ECMR_TE), ECMR);
1513 1514
}

1515 1516 1517 1518 1519
/* error control function */
static void sh_eth_error(struct net_device *ndev, int intr_status)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 felic_stat;
1520 1521
	u32 link_stat;
	u32 mask;
1522 1523

	if (intr_status & EESR_ECI) {
1524 1525
		felic_stat = sh_eth_read(ndev, ECSR);
		sh_eth_write(ndev, felic_stat, ECSR);	/* clear int */
1526
		if (felic_stat & ECSR_ICD)
1527
			ndev->stats.tx_carrier_errors++;
1528 1529
		if (felic_stat & ECSR_LCHNG) {
			/* Link Changed */
1530
			if (mdp->cd->no_psr || mdp->no_ether_link) {
1531
				goto ignore_link;
1532
			} else {
1533
				link_stat = (sh_eth_read(ndev, PSR));
1534 1535
				if (mdp->ether_link_active_low)
					link_stat = ~link_stat;
1536
			}
S
Sergei Shtylyov 已提交
1537
			if (!(link_stat & PHY_ST_LINK)) {
1538
				sh_eth_rcv_snd_disable(ndev);
S
Sergei Shtylyov 已提交
1539
			} else {
1540
				/* Link Up */
1541
				sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
S
Sergei Shtylyov 已提交
1542 1543
						   ~DMAC_M_ECI, EESIPR);
				/* clear int */
1544
				sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
S
Sergei Shtylyov 已提交
1545
					     ECSR);
1546
				sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
S
Sergei Shtylyov 已提交
1547
						   DMAC_M_ECI, EESIPR);
1548
				/* enable tx and rx */
1549
				sh_eth_rcv_snd_enable(ndev);
1550 1551 1552 1553
			}
		}
	}

1554
ignore_link:
1555
	if (intr_status & EESR_TWB) {
1556 1557
		/* Unused write back interrupt */
		if (intr_status & EESR_TABT) {	/* Transmit Abort int */
1558
			ndev->stats.tx_aborted_errors++;
1559 1560
			if (netif_msg_tx_err(mdp))
				dev_err(&ndev->dev, "Transmit Abort\n");
1561
		}
1562 1563 1564 1565 1566 1567
	}

	if (intr_status & EESR_RABT) {
		/* Receive Abort int */
		if (intr_status & EESR_RFRMER) {
			/* Receive Frame Overflow int */
1568
			ndev->stats.rx_frame_errors++;
1569 1570
			if (netif_msg_rx_err(mdp))
				dev_err(&ndev->dev, "Receive Abort\n");
1571 1572
		}
	}
1573

1574 1575
	if (intr_status & EESR_TDE) {
		/* Transmit Descriptor Empty int */
1576
		ndev->stats.tx_fifo_errors++;
1577 1578 1579 1580 1581 1582
		if (netif_msg_tx_err(mdp))
			dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
	}

	if (intr_status & EESR_TFE) {
		/* FIFO under flow */
1583
		ndev->stats.tx_fifo_errors++;
1584 1585
		if (netif_msg_tx_err(mdp))
			dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1586 1587 1588 1589
	}

	if (intr_status & EESR_RDE) {
		/* Receive Descriptor Empty int */
1590
		ndev->stats.rx_over_errors++;
1591

1592 1593
		if (netif_msg_rx_err(mdp))
			dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1594
	}
1595

1596 1597
	if (intr_status & EESR_RFE) {
		/* Receive FIFO Overflow int */
1598
		ndev->stats.rx_fifo_errors++;
1599 1600 1601 1602 1603 1604
		if (netif_msg_rx_err(mdp))
			dev_err(&ndev->dev, "Receive FIFO Overflow\n");
	}

	if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
		/* Address Error */
1605
		ndev->stats.tx_fifo_errors++;
1606 1607
		if (netif_msg_tx_err(mdp))
			dev_err(&ndev->dev, "Address Error\n");
1608
	}
1609 1610 1611 1612 1613

	mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
	if (mdp->cd->no_ade)
		mask &= ~EESR_ADE;
	if (intr_status & mask) {
1614
		/* Tx error */
1615
		u32 edtrr = sh_eth_read(ndev, EDTRR);
1616

1617
		/* dmesg */
1618 1619 1620
		dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
			intr_status, mdp->cur_tx, mdp->dirty_tx,
			(u32)ndev->state, edtrr);
1621 1622 1623 1624
		/* dirty buffer free */
		sh_eth_txfree(ndev);

		/* SH7712 BUG */
1625
		if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1626
			/* tx dma start */
1627
			sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1628 1629 1630 1631 1632 1633 1634 1635 1636 1637
		}
		/* wakeup */
		netif_wake_queue(ndev);
	}
}

static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
{
	struct net_device *ndev = netdev;
	struct sh_eth_private *mdp = netdev_priv(ndev);
1638
	struct sh_eth_cpu_data *cd = mdp->cd;
1639
	irqreturn_t ret = IRQ_NONE;
S
Sergei Shtylyov 已提交
1640
	unsigned long intr_status, intr_enable;
1641 1642 1643

	spin_lock(&mdp->lock);

1644
	/* Get interrupt status */
1645
	intr_status = sh_eth_read(ndev, EESR);
1646 1647 1648 1649 1650
	/* Mask it with the interrupt mask, forcing ECI interrupt to be always
	 * enabled since it's the one that  comes thru regardless of the mask,
	 * and we need to fully handle it in sh_eth_error() in order to quench
	 * it as it doesn't get cleared by just writing 1 to the ECI bit...
	 */
S
Sergei Shtylyov 已提交
1651 1652 1653
	intr_enable = sh_eth_read(ndev, EESIPR);
	intr_status &= intr_enable | DMAC_M_ECI;
	if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1654
		ret = IRQ_HANDLED;
S
Sergei Shtylyov 已提交
1655
	else
1656
		goto other_irq;
1657

S
Sergei Shtylyov 已提交
1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669
	if (intr_status & EESR_RX_CHECK) {
		if (napi_schedule_prep(&mdp->napi)) {
			/* Mask Rx interrupts */
			sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
				     EESIPR);
			__napi_schedule(&mdp->napi);
		} else {
			dev_warn(&ndev->dev,
				 "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
				 intr_status, intr_enable);
		}
	}
1670

1671
	/* Tx Check */
1672
	if (intr_status & cd->tx_check) {
S
Sergei Shtylyov 已提交
1673 1674 1675
		/* Clear Tx interrupts */
		sh_eth_write(ndev, intr_status & cd->tx_check, EESR);

1676 1677 1678 1679
		sh_eth_txfree(ndev);
		netif_wake_queue(ndev);
	}

S
Sergei Shtylyov 已提交
1680 1681 1682 1683
	if (intr_status & cd->eesr_err_check) {
		/* Clear error interrupts */
		sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);

1684
		sh_eth_error(ndev, intr_status);
S
Sergei Shtylyov 已提交
1685
	}
1686

1687
other_irq:
1688 1689
	spin_unlock(&mdp->lock);

1690
	return ret;
1691 1692
}

S
Sergei Shtylyov 已提交
1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719
static int sh_eth_poll(struct napi_struct *napi, int budget)
{
	struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
						  napi);
	struct net_device *ndev = napi->dev;
	int quota = budget;
	unsigned long intr_status;

	for (;;) {
		intr_status = sh_eth_read(ndev, EESR);
		if (!(intr_status & EESR_RX_CHECK))
			break;
		/* Clear Rx interrupts */
		sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);

		if (sh_eth_rx(ndev, intr_status, &quota))
			goto out;
	}

	napi_complete(napi);

	/* Reenable Rx interrupts */
	sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
out:
	return budget - quota;
}

1720 1721 1722 1723 1724 1725 1726
/* PHY state control function */
static void sh_eth_adjust_link(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct phy_device *phydev = mdp->phydev;
	int new_state = 0;

1727
	if (phydev->link) {
1728 1729 1730
		if (phydev->duplex != mdp->duplex) {
			new_state = 1;
			mdp->duplex = phydev->duplex;
1731 1732
			if (mdp->cd->set_duplex)
				mdp->cd->set_duplex(ndev);
1733 1734 1735 1736 1737
		}

		if (phydev->speed != mdp->speed) {
			new_state = 1;
			mdp->speed = phydev->speed;
1738 1739
			if (mdp->cd->set_rate)
				mdp->cd->set_rate(ndev);
1740
		}
1741
		if (!mdp->link) {
1742
			sh_eth_write(ndev,
S
Sergei Shtylyov 已提交
1743 1744
				     sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
				     ECMR);
1745 1746
			new_state = 1;
			mdp->link = phydev->link;
1747 1748
			if (mdp->cd->no_psr || mdp->no_ether_link)
				sh_eth_rcv_snd_enable(ndev);
1749 1750 1751
		}
	} else if (mdp->link) {
		new_state = 1;
1752
		mdp->link = 0;
1753 1754
		mdp->speed = 0;
		mdp->duplex = -1;
1755 1756
		if (mdp->cd->no_psr || mdp->no_ether_link)
			sh_eth_rcv_snd_disable(ndev);
1757 1758
	}

1759
	if (new_state && netif_msg_link(mdp))
1760 1761 1762 1763 1764 1765
		phy_print_status(phydev);
}

/* PHY init function */
static int sh_eth_phy_init(struct net_device *ndev)
{
B
Ben Dooks 已提交
1766
	struct device_node *np = ndev->dev.parent->of_node;
1767 1768 1769
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct phy_device *phydev = NULL;

1770
	mdp->link = 0;
1771 1772 1773 1774
	mdp->speed = 0;
	mdp->duplex = -1;

	/* Try connect to PHY */
B
Ben Dooks 已提交
1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794
	if (np) {
		struct device_node *pn;

		pn = of_parse_phandle(np, "phy-handle", 0);
		phydev = of_phy_connect(ndev, pn,
					sh_eth_adjust_link, 0,
					mdp->phy_interface);

		if (!phydev)
			phydev = ERR_PTR(-ENOENT);
	} else {
		char phy_id[MII_BUS_ID_SIZE + 3];

		snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
			 mdp->mii_bus->id, mdp->phy_id);

		phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
				     mdp->phy_interface);
	}

1795
	if (IS_ERR(phydev)) {
B
Ben Dooks 已提交
1796
		dev_err(&ndev->dev, "failed to connect PHY\n");
1797 1798
		return PTR_ERR(phydev);
	}
1799

1800 1801
	dev_info(&ndev->dev, "attached PHY %d (IRQ %d) to driver %s\n",
		 phydev->addr, phydev->irq, phydev->drv->name);
1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822

	mdp->phydev = phydev;

	return 0;
}

/* PHY control start function */
static int sh_eth_phy_start(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int ret;

	ret = sh_eth_phy_init(ndev);
	if (ret)
		return ret;

	phy_start(mdp->phydev);

	return 0;
}

1823
static int sh_eth_get_settings(struct net_device *ndev,
S
Sergei Shtylyov 已提交
1824
			       struct ethtool_cmd *ecmd)
1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&mdp->lock, flags);
	ret = phy_ethtool_gset(mdp->phydev, ecmd);
	spin_unlock_irqrestore(&mdp->lock, flags);

	return ret;
}

static int sh_eth_set_settings(struct net_device *ndev,
S
Sergei Shtylyov 已提交
1838
			       struct ethtool_cmd *ecmd)
1839 1840 1841 1842 1843 1844 1845 1846
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&mdp->lock, flags);

	/* disable tx and rx */
1847
	sh_eth_rcv_snd_disable(ndev);
1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864

	ret = phy_ethtool_sset(mdp->phydev, ecmd);
	if (ret)
		goto error_exit;

	if (ecmd->duplex == DUPLEX_FULL)
		mdp->duplex = 1;
	else
		mdp->duplex = 0;

	if (mdp->cd->set_duplex)
		mdp->cd->set_duplex(ndev);

error_exit:
	mdelay(1);

	/* enable tx and rx */
1865
	sh_eth_rcv_snd_enable(ndev);
1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913

	spin_unlock_irqrestore(&mdp->lock, flags);

	return ret;
}

static int sh_eth_nway_reset(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&mdp->lock, flags);
	ret = phy_start_aneg(mdp->phydev);
	spin_unlock_irqrestore(&mdp->lock, flags);

	return ret;
}

static u32 sh_eth_get_msglevel(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	return mdp->msg_enable;
}

static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	mdp->msg_enable = value;
}

static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
	"rx_current", "tx_current",
	"rx_dirty", "tx_dirty",
};
#define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)

static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
{
	switch (sset) {
	case ETH_SS_STATS:
		return SH_ETH_STATS_LEN;
	default:
		return -EOPNOTSUPP;
	}
}

static void sh_eth_get_ethtool_stats(struct net_device *ndev,
S
Sergei Shtylyov 已提交
1914
				     struct ethtool_stats *stats, u64 *data)
1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i = 0;

	/* device-specific stats */
	data[i++] = mdp->cur_rx;
	data[i++] = mdp->cur_tx;
	data[i++] = mdp->dirty_rx;
	data[i++] = mdp->dirty_tx;
}

static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
{
	switch (stringset) {
	case ETH_SS_STATS:
		memcpy(data, *sh_eth_gstrings_stats,
S
Sergei Shtylyov 已提交
1931
		       sizeof(sh_eth_gstrings_stats));
1932 1933 1934 1935
		break;
	}
}

1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000
static void sh_eth_get_ringparam(struct net_device *ndev,
				 struct ethtool_ringparam *ring)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	ring->rx_max_pending = RX_RING_MAX;
	ring->tx_max_pending = TX_RING_MAX;
	ring->rx_pending = mdp->num_rx_ring;
	ring->tx_pending = mdp->num_tx_ring;
}

static int sh_eth_set_ringparam(struct net_device *ndev,
				struct ethtool_ringparam *ring)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int ret;

	if (ring->tx_pending > TX_RING_MAX ||
	    ring->rx_pending > RX_RING_MAX ||
	    ring->tx_pending < TX_RING_MIN ||
	    ring->rx_pending < RX_RING_MIN)
		return -EINVAL;
	if (ring->rx_mini_pending || ring->rx_jumbo_pending)
		return -EINVAL;

	if (netif_running(ndev)) {
		netif_tx_disable(ndev);
		/* Disable interrupts by clearing the interrupt mask. */
		sh_eth_write(ndev, 0x0000, EESIPR);
		/* Stop the chip's Tx and Rx processes. */
		sh_eth_write(ndev, 0, EDTRR);
		sh_eth_write(ndev, 0, EDRRR);
		synchronize_irq(ndev->irq);
	}

	/* Free all the skbuffs in the Rx queue. */
	sh_eth_ring_free(ndev);
	/* Free DMA buffer */
	sh_eth_free_dma_buffer(mdp);

	/* Set new parameters */
	mdp->num_rx_ring = ring->rx_pending;
	mdp->num_tx_ring = ring->tx_pending;

	ret = sh_eth_ring_init(ndev);
	if (ret < 0) {
		dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
		return ret;
	}
	ret = sh_eth_dev_init(ndev, false);
	if (ret < 0) {
		dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
		return ret;
	}

	if (netif_running(ndev)) {
		sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
		/* Setting the Rx mode will start the Rx process. */
		sh_eth_write(ndev, EDRRR_R, EDRRR);
		netif_wake_queue(ndev);
	}

	return 0;
}

S
stephen hemminger 已提交
2001
static const struct ethtool_ops sh_eth_ethtool_ops = {
2002 2003
	.get_settings	= sh_eth_get_settings,
	.set_settings	= sh_eth_set_settings,
S
stephen hemminger 已提交
2004
	.nway_reset	= sh_eth_nway_reset,
2005 2006
	.get_msglevel	= sh_eth_get_msglevel,
	.set_msglevel	= sh_eth_set_msglevel,
S
stephen hemminger 已提交
2007
	.get_link	= ethtool_op_get_link,
2008 2009 2010
	.get_strings	= sh_eth_get_strings,
	.get_ethtool_stats  = sh_eth_get_ethtool_stats,
	.get_sset_count     = sh_eth_get_sset_count,
2011 2012
	.get_ringparam	= sh_eth_get_ringparam,
	.set_ringparam	= sh_eth_set_ringparam,
2013 2014
};

2015 2016 2017 2018 2019 2020
/* network device open function */
static int sh_eth_open(struct net_device *ndev)
{
	int ret = 0;
	struct sh_eth_private *mdp = netdev_priv(ndev);

2021 2022
	pm_runtime_get_sync(&mdp->pdev->dev);

2023 2024
	napi_enable(&mdp->napi);

2025
	ret = request_irq(ndev->irq, sh_eth_interrupt,
2026
			  mdp->cd->irq_flags, ndev->name, ndev);
2027
	if (ret) {
2028
		dev_err(&ndev->dev, "Can not assign IRQ number\n");
2029
		goto out_napi_off;
2030 2031 2032 2033 2034 2035 2036 2037
	}

	/* Descriptor set */
	ret = sh_eth_ring_init(ndev);
	if (ret)
		goto out_free_irq;

	/* device init */
2038
	ret = sh_eth_dev_init(ndev, true);
2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050
	if (ret)
		goto out_free_irq;

	/* PHY control start*/
	ret = sh_eth_phy_start(ndev);
	if (ret)
		goto out_free_irq;

	return ret;

out_free_irq:
	free_irq(ndev->irq, ndev);
2051 2052
out_napi_off:
	napi_disable(&mdp->napi);
2053
	pm_runtime_put_sync(&mdp->pdev->dev);
2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065
	return ret;
}

/* Timeout function */
static void sh_eth_tx_timeout(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_rxdesc *rxdesc;
	int i;

	netif_stop_queue(ndev);

S
Sergei Shtylyov 已提交
2066 2067 2068 2069
	if (netif_msg_timer(mdp)) {
		dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x, resetting...\n",
			ndev->name, (int)sh_eth_read(ndev, EESR));
	}
2070 2071

	/* tx_errors count up */
2072
	ndev->stats.tx_errors++;
2073 2074

	/* Free all the skbuffs in the Rx queue. */
2075
	for (i = 0; i < mdp->num_rx_ring; i++) {
2076 2077 2078 2079 2080 2081 2082
		rxdesc = &mdp->rx_ring[i];
		rxdesc->status = 0;
		rxdesc->addr = 0xBADF00D0;
		if (mdp->rx_skbuff[i])
			dev_kfree_skb(mdp->rx_skbuff[i]);
		mdp->rx_skbuff[i] = NULL;
	}
2083
	for (i = 0; i < mdp->num_tx_ring; i++) {
2084 2085 2086 2087 2088 2089
		if (mdp->tx_skbuff[i])
			dev_kfree_skb(mdp->tx_skbuff[i]);
		mdp->tx_skbuff[i] = NULL;
	}

	/* device init */
2090
	sh_eth_dev_init(ndev, true);
2091 2092 2093 2094 2095 2096 2097 2098
}

/* Packet transmit function */
static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct sh_eth_txdesc *txdesc;
	u32 entry;
2099
	unsigned long flags;
2100 2101

	spin_lock_irqsave(&mdp->lock, flags);
2102
	if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2103
		if (!sh_eth_txfree(ndev)) {
2104 2105
			if (netif_msg_tx_queued(mdp))
				dev_warn(&ndev->dev, "TxFD exhausted.\n");
2106 2107
			netif_stop_queue(ndev);
			spin_unlock_irqrestore(&mdp->lock, flags);
2108
			return NETDEV_TX_BUSY;
2109 2110 2111 2112
		}
	}
	spin_unlock_irqrestore(&mdp->lock, flags);

2113
	entry = mdp->cur_tx % mdp->num_tx_ring;
2114 2115 2116
	mdp->tx_skbuff[entry] = skb;
	txdesc = &mdp->tx_ring[entry];
	/* soft swap. */
2117 2118 2119
	if (!mdp->cd->hw_swap)
		sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
				 skb->len + 2);
2120 2121
	txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
				      DMA_TO_DEVICE);
2122 2123
	if (skb->len < ETH_ZLEN)
		txdesc->buffer_length = ETH_ZLEN;
2124 2125 2126
	else
		txdesc->buffer_length = skb->len;

2127
	if (entry >= mdp->num_tx_ring - 1)
2128
		txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2129
	else
2130
		txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2131 2132 2133

	mdp->cur_tx++;

2134 2135
	if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
		sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2136

2137
	return NETDEV_TX_OK;
2138 2139 2140 2141 2142 2143 2144 2145 2146 2147
}

/* device close function */
static int sh_eth_close(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

	netif_stop_queue(ndev);

	/* Disable interrupts by clearing the interrupt mask. */
2148
	sh_eth_write(ndev, 0x0000, EESIPR);
2149 2150

	/* Stop the chip's Tx and Rx processes. */
2151 2152
	sh_eth_write(ndev, 0, EDTRR);
	sh_eth_write(ndev, 0, EDRRR);
2153 2154 2155 2156 2157 2158 2159 2160 2161

	/* PHY Disconnect */
	if (mdp->phydev) {
		phy_stop(mdp->phydev);
		phy_disconnect(mdp->phydev);
	}

	free_irq(ndev->irq, ndev);

2162 2163
	napi_disable(&mdp->napi);

2164 2165 2166 2167
	/* Free all the skbuffs in the Rx queue. */
	sh_eth_ring_free(ndev);

	/* free DMA buffer */
2168
	sh_eth_free_dma_buffer(mdp);
2169

2170 2171
	pm_runtime_put_sync(&mdp->pdev->dev);

2172 2173 2174 2175 2176 2177 2178
	return 0;
}

static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);

S
Simon Horman 已提交
2179 2180 2181
	if (sh_eth_is_rz_fast_ether(mdp))
		return &ndev->stats;

2182 2183
	pm_runtime_get_sync(&mdp->pdev->dev);

2184
	ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2185
	sh_eth_write(ndev, 0, TROCR);	/* (write clear) */
2186
	ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2187
	sh_eth_write(ndev, 0, CDCR);	/* (write clear) */
2188
	ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2189
	sh_eth_write(ndev, 0, LCCR);	/* (write clear) */
2190
	if (sh_eth_is_gether(mdp)) {
2191
		ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2192
		sh_eth_write(ndev, 0, CERCR);	/* (write clear) */
2193
		ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2194 2195
		sh_eth_write(ndev, 0, CEECR);	/* (write clear) */
	} else {
2196
		ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2197 2198
		sh_eth_write(ndev, 0, CNDCR);	/* (write clear) */
	}
2199 2200
	pm_runtime_put_sync(&mdp->pdev->dev);

2201
	return &ndev->stats;
2202 2203
}

2204
/* ioctl to device function */
S
Sergei Shtylyov 已提交
2205
static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2206 2207 2208 2209 2210 2211 2212 2213 2214 2215
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	struct phy_device *phydev = mdp->phydev;

	if (!netif_running(ndev))
		return -EINVAL;

	if (!phydev)
		return -ENODEV;

2216
	return phy_mii_ioctl(phydev, rq, cmd);
2217 2218
}

2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324
/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
					    int entry)
{
	return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
}

static u32 sh_eth_tsu_get_post_mask(int entry)
{
	return 0x0f << (28 - ((entry % 8) * 4));
}

static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
{
	return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
}

static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
					     int entry)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 tmp;
	void *reg_offset;

	reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
	tmp = ioread32(reg_offset);
	iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
}

static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
					      int entry)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 post_mask, ref_mask, tmp;
	void *reg_offset;

	reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
	post_mask = sh_eth_tsu_get_post_mask(entry);
	ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;

	tmp = ioread32(reg_offset);
	iowrite32(tmp & ~post_mask, reg_offset);

	/* If other port enables, the function returns "true" */
	return tmp & ref_mask;
}

static int sh_eth_tsu_busy(struct net_device *ndev)
{
	int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
	struct sh_eth_private *mdp = netdev_priv(ndev);

	while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
		udelay(10);
		timeout--;
		if (timeout <= 0) {
			dev_err(&ndev->dev, "%s: timeout\n", __func__);
			return -ETIMEDOUT;
		}
	}

	return 0;
}

static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
				  const u8 *addr)
{
	u32 val;

	val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
	iowrite32(val, reg);
	if (sh_eth_tsu_busy(ndev) < 0)
		return -EBUSY;

	val = addr[4] << 8 | addr[5];
	iowrite32(val, reg + 4);
	if (sh_eth_tsu_busy(ndev) < 0)
		return -EBUSY;

	return 0;
}

static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
{
	u32 val;

	val = ioread32(reg);
	addr[0] = (val >> 24) & 0xff;
	addr[1] = (val >> 16) & 0xff;
	addr[2] = (val >> 8) & 0xff;
	addr[3] = val & 0xff;
	val = ioread32(reg + 4);
	addr[4] = (val >> 8) & 0xff;
	addr[5] = val & 0xff;
}


static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
	int i;
	u8 c_addr[ETH_ALEN];

	for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
		sh_eth_tsu_read_entry(reg_offset, c_addr);
2325
		if (ether_addr_equal(addr, c_addr))
2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450
			return i;
	}

	return -ENOENT;
}

static int sh_eth_tsu_find_empty(struct net_device *ndev)
{
	u8 blank[ETH_ALEN];
	int entry;

	memset(blank, 0, sizeof(blank));
	entry = sh_eth_tsu_find_entry(ndev, blank);
	return (entry < 0) ? -ENOMEM : entry;
}

static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
					      int entry)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
	int ret;
	u8 blank[ETH_ALEN];

	sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
			 ~(1 << (31 - entry)), TSU_TEN);

	memset(blank, 0, sizeof(blank));
	ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
	if (ret < 0)
		return ret;
	return 0;
}

static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
	int i, ret;

	if (!mdp->cd->tsu)
		return 0;

	i = sh_eth_tsu_find_entry(ndev, addr);
	if (i < 0) {
		/* No entry found, create one */
		i = sh_eth_tsu_find_empty(ndev);
		if (i < 0)
			return -ENOMEM;
		ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
		if (ret < 0)
			return ret;

		/* Enable the entry */
		sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
				 (1 << (31 - i)), TSU_TEN);
	}

	/* Entry found or created, enable POST */
	sh_eth_tsu_enable_cam_entry_post(ndev, i);

	return 0;
}

static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i, ret;

	if (!mdp->cd->tsu)
		return 0;

	i = sh_eth_tsu_find_entry(ndev, addr);
	if (i) {
		/* Entry found */
		if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
			goto done;

		/* Disable the entry if both ports was disabled */
		ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
		if (ret < 0)
			return ret;
	}
done:
	return 0;
}

static int sh_eth_tsu_purge_all(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int i, ret;

	if (unlikely(!mdp->cd->tsu))
		return 0;

	for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
		if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
			continue;

		/* Disable the entry if both ports was disabled */
		ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u8 addr[ETH_ALEN];
	void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
	int i;

	if (unlikely(!mdp->cd->tsu))
		return;

	for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
		sh_eth_tsu_read_entry(reg_offset, addr);
		if (is_multicast_ether_addr(addr))
			sh_eth_tsu_del_entry(ndev, addr);
	}
}

2451 2452 2453
/* Multicast reception directions set */
static void sh_eth_set_multicast_list(struct net_device *ndev)
{
2454 2455 2456 2457 2458 2459
	struct sh_eth_private *mdp = netdev_priv(ndev);
	u32 ecmr_bits;
	int mcast_all = 0;
	unsigned long flags;

	spin_lock_irqsave(&mdp->lock, flags);
S
Sergei Shtylyov 已提交
2460
	/* Initial condition is MCT = 1, PRM = 0.
2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474
	 * Depending on ndev->flags, set PRM or clear MCT
	 */
	ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;

	if (!(ndev->flags & IFF_MULTICAST)) {
		sh_eth_tsu_purge_mcast(ndev);
		mcast_all = 1;
	}
	if (ndev->flags & IFF_ALLMULTI) {
		sh_eth_tsu_purge_mcast(ndev);
		ecmr_bits &= ~ECMR_MCT;
		mcast_all = 1;
	}

2475
	if (ndev->flags & IFF_PROMISC) {
2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491
		sh_eth_tsu_purge_all(ndev);
		ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
	} else if (mdp->cd->tsu) {
		struct netdev_hw_addr *ha;
		netdev_for_each_mc_addr(ha, ndev) {
			if (mcast_all && is_multicast_ether_addr(ha->addr))
				continue;

			if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
				if (!mcast_all) {
					sh_eth_tsu_purge_mcast(ndev);
					ecmr_bits &= ~ECMR_MCT;
					mcast_all = 1;
				}
			}
		}
2492 2493
	} else {
		/* Normal, unicast/broadcast-only mode. */
2494
		ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2495
	}
2496 2497 2498 2499 2500

	/* update the ethernet mode */
	sh_eth_write(ndev, ecmr_bits, ECMR);

	spin_unlock_irqrestore(&mdp->lock, flags);
2501
}
2502 2503 2504 2505 2506 2507 2508 2509 2510

static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
{
	if (!mdp->port)
		return TSU_VTAG0;
	else
		return TSU_VTAG1;
}

2511 2512
static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
				  __be16 proto, u16 vid)
2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int vtag_reg_index = sh_eth_get_vtag_index(mdp);

	if (unlikely(!mdp->cd->tsu))
		return -EPERM;

	/* No filtering if vid = 0 */
	if (!vid)
		return 0;

	mdp->vlan_num_ids++;

S
Sergei Shtylyov 已提交
2526
	/* The controller has one VLAN tag HW filter. So, if the filter is
2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540
	 * already enabled, the driver disables it and the filte
	 */
	if (mdp->vlan_num_ids > 1) {
		/* disable VLAN filter */
		sh_eth_tsu_write(mdp, 0, vtag_reg_index);
		return 0;
	}

	sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
			 vtag_reg_index);

	return 0;
}

2541 2542
static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
				   __be16 proto, u16 vid)
2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558
{
	struct sh_eth_private *mdp = netdev_priv(ndev);
	int vtag_reg_index = sh_eth_get_vtag_index(mdp);

	if (unlikely(!mdp->cd->tsu))
		return -EPERM;

	/* No filtering if vid = 0 */
	if (!vid)
		return 0;

	mdp->vlan_num_ids--;
	sh_eth_tsu_write(mdp, 0, vtag_reg_index);

	return 0;
}
2559 2560

/* SuperH's TSU register init function */
2561
static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2562
{
S
Simon Horman 已提交
2563 2564 2565 2566 2567
	if (sh_eth_is_rz_fast_ether(mdp)) {
		sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
		return;
	}

2568 2569 2570 2571 2572 2573 2574 2575 2576 2577
	sh_eth_tsu_write(mdp, 0, TSU_FWEN0);	/* Disable forward(0->1) */
	sh_eth_tsu_write(mdp, 0, TSU_FWEN1);	/* Disable forward(1->0) */
	sh_eth_tsu_write(mdp, 0, TSU_FCM);	/* forward fifo 3k-3k */
	sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
	sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
	sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
	sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
	sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
	sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
	sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2578 2579 2580 2581 2582 2583 2584
	if (sh_eth_is_gether(mdp)) {
		sh_eth_tsu_write(mdp, 0, TSU_QTAG0);	/* Disable QTAG(0->1) */
		sh_eth_tsu_write(mdp, 0, TSU_QTAG1);	/* Disable QTAG(1->0) */
	} else {
		sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);	/* Disable QTAG(0->1) */
		sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);	/* Disable QTAG(1->0) */
	}
2585 2586 2587 2588 2589 2590 2591
	sh_eth_tsu_write(mdp, 0, TSU_FWSR);	/* all interrupt status clear */
	sh_eth_tsu_write(mdp, 0, TSU_FWINMK);	/* Disable all interrupt */
	sh_eth_tsu_write(mdp, 0, TSU_TEN);	/* Disable all CAM entry */
	sh_eth_tsu_write(mdp, 0, TSU_POST1);	/* Disable CAM entry [ 0- 7] */
	sh_eth_tsu_write(mdp, 0, TSU_POST2);	/* Disable CAM entry [ 8-15] */
	sh_eth_tsu_write(mdp, 0, TSU_POST3);	/* Disable CAM entry [16-23] */
	sh_eth_tsu_write(mdp, 0, TSU_POST4);	/* Disable CAM entry [24-31] */
2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611
}

/* MDIO bus release function */
static int sh_mdio_release(struct net_device *ndev)
{
	struct mii_bus *bus = dev_get_drvdata(&ndev->dev);

	/* unregister mdio bus */
	mdiobus_unregister(bus);

	/* remove mdio bus info from net_device */
	dev_set_drvdata(&ndev->dev, NULL);

	/* free bitbang info */
	free_mdio_bitbang(bus);

	return 0;
}

/* MDIO bus init function */
2612 2613
static int sh_mdio_init(struct net_device *ndev, int id,
			struct sh_eth_plat_data *pd)
2614 2615 2616 2617 2618 2619
{
	int ret, i;
	struct bb_info *bitbang;
	struct sh_eth_private *mdp = netdev_priv(ndev);

	/* create bit control struct for PHY */
S
Sergei Shtylyov 已提交
2620 2621
	bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
			       GFP_KERNEL);
2622 2623 2624 2625 2626 2627
	if (!bitbang) {
		ret = -ENOMEM;
		goto out;
	}

	/* bitbang init */
Y
Yoshihiro Shimoda 已提交
2628
	bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2629
	bitbang->set_gate = pd->set_mdio_gate;
S
Sergei Shtylyov 已提交
2630 2631 2632 2633
	bitbang->mdi_msk = PIR_MDI;
	bitbang->mdo_msk = PIR_MDO;
	bitbang->mmd_msk = PIR_MMD;
	bitbang->mdc_msk = PIR_MDC;
2634 2635
	bitbang->ctrl.ops = &bb_ops;

2636
	/* MII controller setting */
2637 2638 2639
	mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
	if (!mdp->mii_bus) {
		ret = -ENOMEM;
S
Sergei Shtylyov 已提交
2640
		goto out;
2641 2642 2643 2644
	}

	/* Hook up MII support for ethtool */
	mdp->mii_bus->name = "sh_mii";
2645
	mdp->mii_bus->parent = &ndev->dev;
2646
	snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
S
Sergei Shtylyov 已提交
2647
		 mdp->pdev->name, id);
2648 2649

	/* PHY IRQ */
S
Sergei Shtylyov 已提交
2650 2651 2652
	mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
					 sizeof(int) * PHY_MAX_ADDR,
					 GFP_KERNEL);
2653 2654 2655 2656 2657
	if (!mdp->mii_bus->irq) {
		ret = -ENOMEM;
		goto out_free_bus;
	}

2658
	/* register mdio bus */
B
Ben Dooks 已提交
2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670
	if (ndev->dev.parent->of_node) {
		ret = of_mdiobus_register(mdp->mii_bus,
					  ndev->dev.parent->of_node);
	} else {
		for (i = 0; i < PHY_MAX_ADDR; i++)
			mdp->mii_bus->irq[i] = PHY_POLL;
		if (pd->phy_irq > 0)
			mdp->mii_bus->irq[pd->phy] = pd->phy_irq;

		ret = mdiobus_register(mdp->mii_bus);
	}

2671
	if (ret)
S
Sergei Shtylyov 已提交
2672
		goto out_free_bus;
2673 2674 2675 2676 2677 2678

	dev_set_drvdata(&ndev->dev, mdp->mii_bus);

	return 0;

out_free_bus:
2679
	free_mdio_bitbang(mdp->mii_bus);
2680 2681 2682 2683 2684

out:
	return ret;
}

2685 2686 2687 2688 2689 2690 2691 2692
static const u16 *sh_eth_get_register_offset(int register_type)
{
	const u16 *reg_offset = NULL;

	switch (register_type) {
	case SH_ETH_REG_GIGABIT:
		reg_offset = sh_eth_offset_gigabit;
		break;
S
Simon Horman 已提交
2693 2694 2695
	case SH_ETH_REG_FAST_RZ:
		reg_offset = sh_eth_offset_fast_rz;
		break;
2696 2697 2698
	case SH_ETH_REG_FAST_RCAR:
		reg_offset = sh_eth_offset_fast_rcar;
		break;
2699 2700 2701 2702 2703 2704 2705
	case SH_ETH_REG_FAST_SH4:
		reg_offset = sh_eth_offset_fast_sh4;
		break;
	case SH_ETH_REG_FAST_SH3_SH2:
		reg_offset = sh_eth_offset_fast_sh3_sh2;
		break;
	default:
2706
		pr_err("Unknown register type (%d)\n", register_type);
2707 2708 2709 2710 2711 2712
		break;
	}

	return reg_offset;
}

2713
static const struct net_device_ops sh_eth_netdev_ops = {
2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724
	.ndo_open		= sh_eth_open,
	.ndo_stop		= sh_eth_close,
	.ndo_start_xmit		= sh_eth_start_xmit,
	.ndo_get_stats		= sh_eth_get_stats,
	.ndo_tx_timeout		= sh_eth_tx_timeout,
	.ndo_do_ioctl		= sh_eth_do_ioctl,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_set_mac_address	= eth_mac_addr,
	.ndo_change_mtu		= eth_change_mtu,
};

2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739
static const struct net_device_ops sh_eth_netdev_ops_tsu = {
	.ndo_open		= sh_eth_open,
	.ndo_stop		= sh_eth_close,
	.ndo_start_xmit		= sh_eth_start_xmit,
	.ndo_get_stats		= sh_eth_get_stats,
	.ndo_set_rx_mode	= sh_eth_set_multicast_list,
	.ndo_vlan_rx_add_vid	= sh_eth_vlan_rx_add_vid,
	.ndo_vlan_rx_kill_vid	= sh_eth_vlan_rx_kill_vid,
	.ndo_tx_timeout		= sh_eth_tx_timeout,
	.ndo_do_ioctl		= sh_eth_do_ioctl,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_set_mac_address	= eth_mac_addr,
	.ndo_change_mtu		= eth_change_mtu,
};

2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781
#ifdef CONFIG_OF
static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
{
	struct device_node *np = dev->of_node;
	struct sh_eth_plat_data *pdata;
	const char *mac_addr;

	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return NULL;

	pdata->phy_interface = of_get_phy_mode(np);

	mac_addr = of_get_mac_address(np);
	if (mac_addr)
		memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);

	pdata->no_ether_link =
		of_property_read_bool(np, "renesas,no-ether-link");
	pdata->ether_link_active_low =
		of_property_read_bool(np, "renesas,ether-link-active-low");

	return pdata;
}

static const struct of_device_id sh_eth_match_table[] = {
	{ .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
	{ .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
	{ .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
	{ .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
	{ .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
	{ .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
	{ }
};
MODULE_DEVICE_TABLE(of, sh_eth_match_table);
#else
static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
{
	return NULL;
}
#endif

2782 2783
static int sh_eth_drv_probe(struct platform_device *pdev)
{
2784
	int ret, devno = 0;
2785 2786
	struct resource *res;
	struct net_device *ndev = NULL;
2787
	struct sh_eth_private *mdp = NULL;
J
Jingoo Han 已提交
2788
	struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2789
	const struct platform_device_id *id = platform_get_device_id(pdev);
2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811

	/* get base addr */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (unlikely(res == NULL)) {
		dev_err(&pdev->dev, "invalid resource\n");
		ret = -EINVAL;
		goto out;
	}

	ndev = alloc_etherdev(sizeof(struct sh_eth_private));
	if (!ndev) {
		ret = -ENOMEM;
		goto out;
	}

	/* The sh Ether-specific entries in the device structure. */
	ndev->base_addr = res->start;
	devno = pdev->id;
	if (devno < 0)
		devno = 0;

	ndev->dma = -1;
2812 2813
	ret = platform_get_irq(pdev, 0);
	if (ret < 0) {
2814 2815 2816
		ret = -ENODEV;
		goto out_release;
	}
2817
	ndev->irq = ret;
2818 2819 2820 2821

	SET_NETDEV_DEV(ndev, &pdev->dev);

	mdp = netdev_priv(ndev);
2822 2823
	mdp->num_tx_ring = TX_RING_SIZE;
	mdp->num_rx_ring = RX_RING_SIZE;
S
Sergei Shtylyov 已提交
2824 2825 2826
	mdp->addr = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mdp->addr)) {
		ret = PTR_ERR(mdp->addr);
Y
Yoshihiro Shimoda 已提交
2827 2828 2829
		goto out_release;
	}

2830
	spin_lock_init(&mdp->lock);
2831 2832 2833
	mdp->pdev = pdev;
	pm_runtime_enable(&pdev->dev);
	pm_runtime_resume(&pdev->dev);
2834

2835 2836
	if (pdev->dev.of_node)
		pd = sh_eth_parse_dt(&pdev->dev);
2837 2838 2839 2840 2841 2842
	if (!pd) {
		dev_err(&pdev->dev, "no platform data\n");
		ret = -EINVAL;
		goto out_release;
	}

2843
	/* get PHY ID */
2844
	mdp->phy_id = pd->phy;
2845
	mdp->phy_interface = pd->phy_interface;
2846 2847
	/* EDMAC endian */
	mdp->edmac_endian = pd->edmac_endian;
2848 2849
	mdp->no_ether_link = pd->no_ether_link;
	mdp->ether_link_active_low = pd->ether_link_active_low;
2850

2851
	/* set cpu data */
2852 2853 2854 2855 2856 2857 2858 2859 2860
	if (id) {
		mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
	} else	{
		const struct of_device_id *match;

		match = of_match_device(of_match_ptr(sh_eth_match_table),
					&pdev->dev);
		mdp->cd = (struct sh_eth_cpu_data *)match->data;
	}
2861
	mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
2862 2863
	sh_eth_set_default_cpu_data(mdp->cd);

2864
	/* set function */
2865 2866 2867 2868
	if (mdp->cd->tsu)
		ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
	else
		ndev->netdev_ops = &sh_eth_netdev_ops;
2869
	SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2870 2871
	ndev->watchdog_timeo = TX_TIMEOUT;

2872 2873
	/* debug message level */
	mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2874 2875

	/* read and set MAC address */
2876
	read_mac_address(ndev, pd->mac_addr);
2877 2878 2879 2880 2881
	if (!is_valid_ether_addr(ndev->dev_addr)) {
		dev_warn(&pdev->dev,
			 "no valid MAC address supplied, using a random one.\n");
		eth_hw_addr_random(ndev);
	}
2882

2883 2884 2885 2886
	/* ioremap the TSU registers */
	if (mdp->cd->tsu) {
		struct resource *rtsu;
		rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
S
Sergei Shtylyov 已提交
2887 2888 2889
		mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
		if (IS_ERR(mdp->tsu_addr)) {
			ret = PTR_ERR(mdp->tsu_addr);
2890 2891
			goto out_release;
		}
2892
		mdp->port = devno % 2;
2893
		ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2894 2895
	}

2896 2897
	/* initialize first or needed device */
	if (!devno || pd->needs_init) {
2898 2899
		if (mdp->cd->chip_reset)
			mdp->cd->chip_reset(ndev);
2900

2901 2902 2903 2904
		if (mdp->cd->tsu) {
			/* TSU init (Init only)*/
			sh_eth_tsu_init(mdp);
		}
2905 2906
	}

S
Sergei Shtylyov 已提交
2907 2908
	netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);

2909 2910 2911
	/* network device register */
	ret = register_netdev(ndev);
	if (ret)
S
Sergei Shtylyov 已提交
2912
		goto out_napi_del;
2913 2914

	/* mdio bus init */
2915
	ret = sh_mdio_init(ndev, pdev->id, pd);
B
Ben Dooks 已提交
2916 2917
	if (ret) {
		dev_err(&ndev->dev, "failed to initialise MDIO\n");
2918
		goto out_unregister;
B
Ben Dooks 已提交
2919
	}
2920

L
Lucas De Marchi 已提交
2921
	/* print device information */
2922
	pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
S
Sergei Shtylyov 已提交
2923
		(u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2924 2925 2926 2927 2928 2929 2930 2931

	platform_set_drvdata(pdev, ndev);

	return ret;

out_unregister:
	unregister_netdev(ndev);

S
Sergei Shtylyov 已提交
2932 2933 2934
out_napi_del:
	netif_napi_del(&mdp->napi);

2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946
out_release:
	/* net_dev free */
	if (ndev)
		free_netdev(ndev);

out:
	return ret;
}

static int sh_eth_drv_remove(struct platform_device *pdev)
{
	struct net_device *ndev = platform_get_drvdata(pdev);
S
Sergei Shtylyov 已提交
2947
	struct sh_eth_private *mdp = netdev_priv(ndev);
2948 2949 2950

	sh_mdio_release(ndev);
	unregister_netdev(ndev);
S
Sergei Shtylyov 已提交
2951
	netif_napi_del(&mdp->napi);
2952
	pm_runtime_disable(&pdev->dev);
2953 2954 2955 2956 2957
	free_netdev(ndev);

	return 0;
}

2958
#ifdef CONFIG_PM
2959 2960
static int sh_eth_runtime_nop(struct device *dev)
{
S
Sergei Shtylyov 已提交
2961
	/* Runtime PM callback shared between ->runtime_suspend()
2962 2963 2964 2965 2966 2967 2968 2969 2970
	 * and ->runtime_resume(). Simply returns success.
	 *
	 * This driver re-initializes all registers after
	 * pm_runtime_get_sync() anyway so there is no need
	 * to save and restore registers here.
	 */
	return 0;
}

2971
static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2972 2973 2974
	.runtime_suspend = sh_eth_runtime_nop,
	.runtime_resume = sh_eth_runtime_nop,
};
2975 2976 2977 2978
#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
#else
#define SH_ETH_PM_OPS NULL
#endif
2979

2980
static struct platform_device_id sh_eth_id_table[] = {
2981
	{ "sh7619-ether", (kernel_ulong_t)&sh7619_data },
2982
	{ "sh771x-ether", (kernel_ulong_t)&sh771x_data },
2983
	{ "sh7724-ether", (kernel_ulong_t)&sh7724_data },
2984
	{ "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2985 2986
	{ "sh7757-ether", (kernel_ulong_t)&sh7757_data },
	{ "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
2987
	{ "sh7763-gether", (kernel_ulong_t)&sh7763_data },
S
Simon Horman 已提交
2988
	{ "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
2989
	{ "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
2990
	{ "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
S
Sergei Shtylyov 已提交
2991 2992
	{ "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
	{ "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
2993 2994 2995 2996
	{ }
};
MODULE_DEVICE_TABLE(platform, sh_eth_id_table);

2997 2998 2999
static struct platform_driver sh_eth_driver = {
	.probe = sh_eth_drv_probe,
	.remove = sh_eth_drv_remove,
3000
	.id_table = sh_eth_id_table,
3001 3002
	.driver = {
		   .name = CARDNAME,
3003
		   .pm = SH_ETH_PM_OPS,
3004
		   .of_match_table = of_match_ptr(sh_eth_match_table),
3005 3006 3007
	},
};

3008
module_platform_driver(sh_eth_driver);
3009 3010 3011 3012

MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
MODULE_LICENSE("GPL v2");