sdhci.c 82.3 KB
Newer Older
1
/*
P
Pierre Ossman 已提交
2
 *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3
 *
4
 *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 6
 *
 * This program is free software; you can redistribute it and/or modify
7 8 9
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
10 11 12 13
 *
 * Thanks to the following companies for their support:
 *
 *     - JMicron (hardware and technical support)
14 15 16 17
 */

#include <linux/delay.h>
#include <linux/highmem.h>
18
#include <linux/io.h>
19
#include <linux/module.h>
20
#include <linux/dma-mapping.h>
21
#include <linux/slab.h>
22
#include <linux/scatterlist.h>
M
Marek Szyprowski 已提交
23
#include <linux/regulator/consumer.h>
24
#include <linux/pm_runtime.h>
25

26 27
#include <linux/leds.h>

28
#include <linux/mmc/mmc.h>
29
#include <linux/mmc/host.h>
30
#include <linux/mmc/card.h>
31
#include <linux/mmc/slot-gpio.h>
32 33 34 35 36 37

#include "sdhci.h"

#define DRIVER_NAME "sdhci"

#define DBG(f, x...) \
38
	pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
39

40 41 42 43 44
#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
	defined(CONFIG_MMC_SDHCI_MODULE))
#define SDHCI_USE_LEDS_CLASS
#endif

45 46
#define MAX_TUNING_LOOP 40

47
static unsigned int debug_quirks = 0;
48
static unsigned int debug_quirks2;
49

50 51 52 53
static void sdhci_finish_data(struct sdhci_host *);

static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
static void sdhci_finish_command(struct sdhci_host *);
54
static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
55
static void sdhci_tuning_timer(unsigned long data);
56

57 58 59 60 61 62 63 64 65 66 67 68 69 70
#ifdef CONFIG_PM_RUNTIME
static int sdhci_runtime_pm_get(struct sdhci_host *host);
static int sdhci_runtime_pm_put(struct sdhci_host *host);
#else
static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
{
	return 0;
}
static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
{
	return 0;
}
#endif

71 72
static void sdhci_dumpregs(struct sdhci_host *host)
{
73
	pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
74
		mmc_hostname(host->mmc));
75

76
	pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
77 78
		sdhci_readl(host, SDHCI_DMA_ADDRESS),
		sdhci_readw(host, SDHCI_HOST_VERSION));
79
	pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
80 81
		sdhci_readw(host, SDHCI_BLOCK_SIZE),
		sdhci_readw(host, SDHCI_BLOCK_COUNT));
82
	pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
83 84
		sdhci_readl(host, SDHCI_ARGUMENT),
		sdhci_readw(host, SDHCI_TRANSFER_MODE));
85
	pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
86 87
		sdhci_readl(host, SDHCI_PRESENT_STATE),
		sdhci_readb(host, SDHCI_HOST_CONTROL));
88
	pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
89 90
		sdhci_readb(host, SDHCI_POWER_CONTROL),
		sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
91
	pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
92 93
		sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
		sdhci_readw(host, SDHCI_CLOCK_CONTROL));
94
	pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
95 96
		sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
		sdhci_readl(host, SDHCI_INT_STATUS));
97
	pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
98 99
		sdhci_readl(host, SDHCI_INT_ENABLE),
		sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
100
	pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
101 102
		sdhci_readw(host, SDHCI_ACMD12_ERR),
		sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
103
	pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
104
		sdhci_readl(host, SDHCI_CAPABILITIES),
105
		sdhci_readl(host, SDHCI_CAPABILITIES_1));
106
	pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
107
		sdhci_readw(host, SDHCI_COMMAND),
108
		sdhci_readl(host, SDHCI_MAX_CURRENT));
109
	pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
110
		sdhci_readw(host, SDHCI_HOST_CONTROL2));
111

112
	if (host->flags & SDHCI_USE_ADMA)
113
		pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
114 115 116
		       readl(host->ioaddr + SDHCI_ADMA_ERROR),
		       readl(host->ioaddr + SDHCI_ADMA_ADDRESS));

117
	pr_debug(DRIVER_NAME ": ===========================================\n");
118 119 120 121 122 123 124 125
}

/*****************************************************************************\
 *                                                                           *
 * Low level functions                                                       *
 *                                                                           *
\*****************************************************************************/

126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148
static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
{
	u32 ier;

	ier = sdhci_readl(host, SDHCI_INT_ENABLE);
	ier &= ~clear;
	ier |= set;
	sdhci_writel(host, ier, SDHCI_INT_ENABLE);
	sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
}

static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
{
	sdhci_clear_set_irqs(host, 0, irqs);
}

static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
{
	sdhci_clear_set_irqs(host, irqs, 0);
}

static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
{
149
	u32 present, irqs;
150

151
	if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
152
	    (host->mmc->caps & MMC_CAP_NONREMOVABLE))
153 154
		return;

155 156 157 158
	present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
			      SDHCI_CARD_PRESENT;
	irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;

159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174
	if (enable)
		sdhci_unmask_irqs(host, irqs);
	else
		sdhci_mask_irqs(host, irqs);
}

static void sdhci_enable_card_detection(struct sdhci_host *host)
{
	sdhci_set_card_detection(host, true);
}

static void sdhci_disable_card_detection(struct sdhci_host *host)
{
	sdhci_set_card_detection(host, false);
}

175 176
static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
177
	unsigned long timeout;
178
	u32 uninitialized_var(ier);
179

180
	if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
181
		if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
182 183 184 185
			SDHCI_CARD_PRESENT))
			return;
	}

186 187 188
	if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
		ier = sdhci_readl(host, SDHCI_INT_ENABLE);

189 190 191
	if (host->ops->platform_reset_enter)
		host->ops->platform_reset_enter(host, mask);

192
	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
193

194
	if (mask & SDHCI_RESET_ALL)
195 196
		host->clock = 0;

197 198 199 200
	/* Wait max 100 ms */
	timeout = 100;

	/* hw clears the bit when it's done */
201
	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
202
		if (timeout == 0) {
203
			pr_err("%s: Reset 0x%x never completed.\n",
204 205 206 207 208 209
				mmc_hostname(host->mmc), (int)mask);
			sdhci_dumpregs(host);
			return;
		}
		timeout--;
		mdelay(1);
210
	}
211

212 213 214
	if (host->ops->platform_reset_exit)
		host->ops->platform_reset_exit(host, mask);

215 216
	if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
		sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
217 218 219 220 221

	if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
		if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
			host->ops->enable_dma(host);
	}
222 223
}

224 225 226
static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);

static void sdhci_init(struct sdhci_host *host, int soft)
227
{
228 229 230 231
	if (soft)
		sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
	else
		sdhci_reset(host, SDHCI_RESET_ALL);
232

233 234
	sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
		SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
235 236
		SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
		SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
237
		SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
238 239 240 241 242 243

	if (soft) {
		/* force clock reconfiguration */
		host->clock = 0;
		sdhci_set_ios(host->mmc, &host->mmc->ios);
	}
244
}
245

246 247
static void sdhci_reinit(struct sdhci_host *host)
{
248
	sdhci_init(host, 0);
249 250 251 252 253
	/*
	 * Retuning stuffs are affected by different cards inserted and only
	 * applicable to UHS-I cards. So reset these fields to their initial
	 * value when card is removed.
	 */
254 255 256
	if (host->flags & SDHCI_USING_RETUNING_TIMER) {
		host->flags &= ~SDHCI_USING_RETUNING_TIMER;

257 258 259 260 261
		del_timer_sync(&host->tuning_timer);
		host->flags &= ~SDHCI_NEEDS_RETUNING;
		host->mmc->max_blk_count =
			(host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
	}
262
	sdhci_enable_card_detection(host);
263 264 265 266 267 268
}

static void sdhci_activate_led(struct sdhci_host *host)
{
	u8 ctrl;

269
	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
270
	ctrl |= SDHCI_CTRL_LED;
271
	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
272 273 274 275 276 277
}

static void sdhci_deactivate_led(struct sdhci_host *host)
{
	u8 ctrl;

278
	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
279
	ctrl &= ~SDHCI_CTRL_LED;
280
	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
281 282
}

283
#ifdef SDHCI_USE_LEDS_CLASS
284 285 286 287 288 289 290 291
static void sdhci_led_control(struct led_classdev *led,
	enum led_brightness brightness)
{
	struct sdhci_host *host = container_of(led, struct sdhci_host, led);
	unsigned long flags;

	spin_lock_irqsave(&host->lock, flags);

292 293 294
	if (host->runtime_suspended)
		goto out;

295 296 297 298
	if (brightness == LED_OFF)
		sdhci_deactivate_led(host);
	else
		sdhci_activate_led(host);
299
out:
300 301 302 303
	spin_unlock_irqrestore(&host->lock, flags);
}
#endif

304 305 306 307 308 309
/*****************************************************************************\
 *                                                                           *
 * Core functions                                                            *
 *                                                                           *
\*****************************************************************************/

P
Pierre Ossman 已提交
310
static void sdhci_read_block_pio(struct sdhci_host *host)
311
{
312 313
	unsigned long flags;
	size_t blksize, len, chunk;
314
	u32 uninitialized_var(scratch);
315
	u8 *buf;
316

P
Pierre Ossman 已提交
317
	DBG("PIO reading\n");
318

P
Pierre Ossman 已提交
319
	blksize = host->data->blksz;
320
	chunk = 0;
321

322
	local_irq_save(flags);
323

P
Pierre Ossman 已提交
324
	while (blksize) {
325 326
		if (!sg_miter_next(&host->sg_miter))
			BUG();
327

328
		len = min(host->sg_miter.length, blksize);
329

330 331
		blksize -= len;
		host->sg_miter.consumed = len;
332

333
		buf = host->sg_miter.addr;
334

335 336
		while (len) {
			if (chunk == 0) {
337
				scratch = sdhci_readl(host, SDHCI_BUFFER);
338
				chunk = 4;
P
Pierre Ossman 已提交
339
			}
340 341 342 343 344 345 346

			*buf = scratch & 0xFF;

			buf++;
			scratch >>= 8;
			chunk--;
			len--;
347
		}
P
Pierre Ossman 已提交
348
	}
349 350 351 352

	sg_miter_stop(&host->sg_miter);

	local_irq_restore(flags);
P
Pierre Ossman 已提交
353
}
354

P
Pierre Ossman 已提交
355 356
static void sdhci_write_block_pio(struct sdhci_host *host)
{
357 358 359 360
	unsigned long flags;
	size_t blksize, len, chunk;
	u32 scratch;
	u8 *buf;
361

P
Pierre Ossman 已提交
362 363 364
	DBG("PIO writing\n");

	blksize = host->data->blksz;
365 366
	chunk = 0;
	scratch = 0;
367

368
	local_irq_save(flags);
369

P
Pierre Ossman 已提交
370
	while (blksize) {
371 372
		if (!sg_miter_next(&host->sg_miter))
			BUG();
P
Pierre Ossman 已提交
373

374 375 376 377 378 379
		len = min(host->sg_miter.length, blksize);

		blksize -= len;
		host->sg_miter.consumed = len;

		buf = host->sg_miter.addr;
380

381 382 383 384 385 386 387 388
		while (len) {
			scratch |= (u32)*buf << (chunk * 8);

			buf++;
			chunk++;
			len--;

			if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
389
				sdhci_writel(host, scratch, SDHCI_BUFFER);
390 391
				chunk = 0;
				scratch = 0;
392 393 394
			}
		}
	}
395 396 397 398

	sg_miter_stop(&host->sg_miter);

	local_irq_restore(flags);
P
Pierre Ossman 已提交
399 400 401 402 403 404 405 406
}

static void sdhci_transfer_pio(struct sdhci_host *host)
{
	u32 mask;

	BUG_ON(!host->data);

407
	if (host->blocks == 0)
P
Pierre Ossman 已提交
408 409 410 411 412 413 414
		return;

	if (host->data->flags & MMC_DATA_READ)
		mask = SDHCI_DATA_AVAILABLE;
	else
		mask = SDHCI_SPACE_AVAILABLE;

415 416 417 418 419 420 421 422 423
	/*
	 * Some controllers (JMicron JMB38x) mess up the buffer bits
	 * for transfers < 4 bytes. As long as it is just one block,
	 * we can ignore the bits.
	 */
	if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
		(host->data->blocks == 1))
		mask = ~0;

424
	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
425 426 427
		if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
			udelay(100);

P
Pierre Ossman 已提交
428 429 430 431
		if (host->data->flags & MMC_DATA_READ)
			sdhci_read_block_pio(host);
		else
			sdhci_write_block_pio(host);
432

433 434
		host->blocks--;
		if (host->blocks == 0)
P
Pierre Ossman 已提交
435 436
			break;
	}
437

P
Pierre Ossman 已提交
438
	DBG("PIO transfer complete.\n");
439 440
}

441 442 443
static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
{
	local_irq_save(*flags);
444
	return kmap_atomic(sg_page(sg)) + sg->offset;
445 446 447 448
}

static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
{
449
	kunmap_atomic(buffer);
450 451 452
	local_irq_restore(*flags);
}

B
Ben Dooks 已提交
453 454
static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
{
455 456
	__le32 *dataddr = (__le32 __force *)(desc + 4);
	__le16 *cmdlen = (__le16 __force *)desc;
B
Ben Dooks 已提交
457

458 459
	/* SDHCI specification says ADMA descriptors should be 4 byte
	 * aligned, so using 16 or 32bit operations should be safe. */
B
Ben Dooks 已提交
460

461 462 463 464
	cmdlen[0] = cpu_to_le16(cmd);
	cmdlen[1] = cpu_to_le16(len);

	dataddr[0] = cpu_to_le32(addr);
B
Ben Dooks 已提交
465 466
}

467
static int sdhci_adma_table_pre(struct sdhci_host *host,
468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499
	struct mmc_data *data)
{
	int direction;

	u8 *desc;
	u8 *align;
	dma_addr_t addr;
	dma_addr_t align_addr;
	int len, offset;

	struct scatterlist *sg;
	int i;
	char *buffer;
	unsigned long flags;

	/*
	 * The spec does not specify endianness of descriptor table.
	 * We currently guess that it is LE.
	 */

	if (data->flags & MMC_DATA_READ)
		direction = DMA_FROM_DEVICE;
	else
		direction = DMA_TO_DEVICE;

	/*
	 * The ADMA descriptor table is mapped further down as we
	 * need to fill it with data first.
	 */

	host->align_addr = dma_map_single(mmc_dev(host->mmc),
		host->align_buffer, 128 * 4, direction);
500
	if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
501
		goto fail;
502 503 504 505
	BUG_ON(host->align_addr & 0x3);

	host->sg_count = dma_map_sg(mmc_dev(host->mmc),
		data->sg, data->sg_len, direction);
506 507
	if (host->sg_count == 0)
		goto unmap_align;
508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528

	desc = host->adma_desc;
	align = host->align_buffer;

	align_addr = host->align_addr;

	for_each_sg(data->sg, sg, host->sg_count, i) {
		addr = sg_dma_address(sg);
		len = sg_dma_len(sg);

		/*
		 * The SDHCI specification states that ADMA
		 * addresses must be 32-bit aligned. If they
		 * aren't, then we use a bounce buffer for
		 * the (up to three) bytes that screw up the
		 * alignment.
		 */
		offset = (4 - (addr & 0x3)) & 0x3;
		if (offset) {
			if (data->flags & MMC_DATA_WRITE) {
				buffer = sdhci_kmap_atomic(sg, &flags);
529
				WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
530 531 532 533
				memcpy(align, buffer, offset);
				sdhci_kunmap_atomic(buffer, &flags);
			}

B
Ben Dooks 已提交
534 535
			/* tran, valid */
			sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
536 537 538 539 540 541 542 543 544 545 546 547 548 549

			BUG_ON(offset > 65536);

			align += 4;
			align_addr += 4;

			desc += 8;

			addr += offset;
			len -= offset;
		}

		BUG_ON(len > 65536);

B
Ben Dooks 已提交
550 551
		/* tran, valid */
		sdhci_set_adma_desc(desc, addr, len, 0x21);
552 553 554 555 556 557 558 559 560
		desc += 8;

		/*
		 * If this triggers then we have a calculation bug
		 * somewhere. :/
		 */
		WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
	}

561 562 563 564 565 566 567 568 569 570 571 572
	if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
		/*
		* Mark the last descriptor as the terminating descriptor
		*/
		if (desc != host->adma_desc) {
			desc -= 8;
			desc[0] |= 0x2; /* end */
		}
	} else {
		/*
		* Add a terminating entry.
		*/
573

574 575 576
		/* nop, end, valid */
		sdhci_set_adma_desc(desc, 0, 0, 0x3);
	}
577 578 579 580 581 582 583 584 585 586 587

	/*
	 * Resync align buffer as we might have changed it.
	 */
	if (data->flags & MMC_DATA_WRITE) {
		dma_sync_single_for_device(mmc_dev(host->mmc),
			host->align_addr, 128 * 4, direction);
	}

	host->adma_addr = dma_map_single(mmc_dev(host->mmc),
		host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
588
	if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
589
		goto unmap_entries;
590
	BUG_ON(host->adma_addr & 0x3);
591 592 593 594 595 596 597 598 599 600 601

	return 0;

unmap_entries:
	dma_unmap_sg(mmc_dev(host->mmc), data->sg,
		data->sg_len, direction);
unmap_align:
	dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
		128 * 4, direction);
fail:
	return -EINVAL;
602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636
}

static void sdhci_adma_table_post(struct sdhci_host *host,
	struct mmc_data *data)
{
	int direction;

	struct scatterlist *sg;
	int i, size;
	u8 *align;
	char *buffer;
	unsigned long flags;

	if (data->flags & MMC_DATA_READ)
		direction = DMA_FROM_DEVICE;
	else
		direction = DMA_TO_DEVICE;

	dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
		(128 * 2 + 1) * 4, DMA_TO_DEVICE);

	dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
		128 * 4, direction);

	if (data->flags & MMC_DATA_READ) {
		dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
			data->sg_len, direction);

		align = host->align_buffer;

		for_each_sg(data->sg, sg, host->sg_count, i) {
			if (sg_dma_address(sg) & 0x3) {
				size = 4 - (sg_dma_address(sg) & 0x3);

				buffer = sdhci_kmap_atomic(sg, &flags);
637
				WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
638 639 640 641 642 643 644 645 646 647 648 649
				memcpy(buffer, align, size);
				sdhci_kunmap_atomic(buffer, &flags);

				align += 4;
			}
		}
	}

	dma_unmap_sg(mmc_dev(host->mmc), data->sg,
		data->sg_len, direction);
}

650
static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
651
{
652
	u8 count;
653
	struct mmc_data *data = cmd->data;
654
	unsigned target_timeout, current_timeout;
655

656 657 658 659 660 661
	/*
	 * If the host controller provides us with an incorrect timeout
	 * value, just skip the check and use 0xE.  The hardware may take
	 * longer to time out, but that's much better than having a too-short
	 * timeout value.
	 */
662
	if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
663
		return 0xE;
664

665 666 667
	/* Unspecified timeout, assume max */
	if (!data && !cmd->cmd_timeout_ms)
		return 0xE;
668

669 670 671
	/* timeout in us */
	if (!data)
		target_timeout = cmd->cmd_timeout_ms * 1000;
672 673 674 675 676
	else {
		target_timeout = data->timeout_ns / 1000;
		if (host->clock)
			target_timeout += data->timeout_clks / host->clock;
	}
677

678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697
	/*
	 * Figure out needed cycles.
	 * We do this in steps in order to fit inside a 32 bit int.
	 * The first step is the minimum timeout, which will have a
	 * minimum resolution of 6 bits:
	 * (1) 2^13*1000 > 2^22,
	 * (2) host->timeout_clk < 2^16
	 *     =>
	 *     (1) / (2) > 2^6
	 */
	count = 0;
	current_timeout = (1 << 13) * 1000 / host->timeout_clk;
	while (current_timeout < target_timeout) {
		count++;
		current_timeout <<= 1;
		if (count >= 0xF)
			break;
	}

	if (count >= 0xF) {
698 699
		DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
		    mmc_hostname(host->mmc), count, cmd->opcode);
700 701 702
		count = 0xE;
	}

703 704 705
	return count;
}

706 707 708 709 710 711 712 713 714 715 716
static void sdhci_set_transfer_irqs(struct sdhci_host *host)
{
	u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
	u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;

	if (host->flags & SDHCI_REQ_USE_DMA)
		sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
	else
		sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
}

717
static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
718 719
{
	u8 count;
720
	u8 ctrl;
721
	struct mmc_data *data = cmd->data;
722
	int ret;
723 724 725

	WARN_ON(host->data);

726 727 728 729 730 731
	if (data || (cmd->flags & MMC_RSP_BUSY)) {
		count = sdhci_calc_timeout(host, cmd);
		sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
	}

	if (!data)
732 733 734 735 736 737 738 739 740
		return;

	/* Sanity checks */
	BUG_ON(data->blksz * data->blocks > 524288);
	BUG_ON(data->blksz > host->mmc->max_blk_size);
	BUG_ON(data->blocks > 65535);

	host->data = data;
	host->data_early = 0;
741
	host->data->bytes_xfered = 0;
742

743
	if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
744 745
		host->flags |= SDHCI_REQ_USE_DMA;

746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773
	/*
	 * FIXME: This doesn't account for merging when mapping the
	 * scatterlist.
	 */
	if (host->flags & SDHCI_REQ_USE_DMA) {
		int broken, i;
		struct scatterlist *sg;

		broken = 0;
		if (host->flags & SDHCI_USE_ADMA) {
			if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
				broken = 1;
		} else {
			if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
				broken = 1;
		}

		if (unlikely(broken)) {
			for_each_sg(data->sg, sg, data->sg_len, i) {
				if (sg->length & 0x3) {
					DBG("Reverting to PIO because of "
						"transfer size (%d)\n",
						sg->length);
					host->flags &= ~SDHCI_REQ_USE_DMA;
					break;
				}
			}
		}
774 775 776 777 778 779
	}

	/*
	 * The assumption here being that alignment is the same after
	 * translation to device address space.
	 */
780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809
	if (host->flags & SDHCI_REQ_USE_DMA) {
		int broken, i;
		struct scatterlist *sg;

		broken = 0;
		if (host->flags & SDHCI_USE_ADMA) {
			/*
			 * As we use 3 byte chunks to work around
			 * alignment problems, we need to check this
			 * quirk.
			 */
			if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
				broken = 1;
		} else {
			if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
				broken = 1;
		}

		if (unlikely(broken)) {
			for_each_sg(data->sg, sg, data->sg_len, i) {
				if (sg->offset & 0x3) {
					DBG("Reverting to PIO because of "
						"bad alignment\n");
					host->flags &= ~SDHCI_REQ_USE_DMA;
					break;
				}
			}
		}
	}

810 811 812 813 814 815 816 817 818
	if (host->flags & SDHCI_REQ_USE_DMA) {
		if (host->flags & SDHCI_USE_ADMA) {
			ret = sdhci_adma_table_pre(host, data);
			if (ret) {
				/*
				 * This only happens when someone fed
				 * us an invalid request.
				 */
				WARN_ON(1);
819
				host->flags &= ~SDHCI_REQ_USE_DMA;
820
			} else {
821 822
				sdhci_writel(host, host->adma_addr,
					SDHCI_ADMA_ADDRESS);
823 824
			}
		} else {
825
			int sg_cnt;
826

827
			sg_cnt = dma_map_sg(mmc_dev(host->mmc),
828 829 830 831
					data->sg, data->sg_len,
					(data->flags & MMC_DATA_READ) ?
						DMA_FROM_DEVICE :
						DMA_TO_DEVICE);
832
			if (sg_cnt == 0) {
833 834 835 836 837
				/*
				 * This only happens when someone fed
				 * us an invalid request.
				 */
				WARN_ON(1);
838
				host->flags &= ~SDHCI_REQ_USE_DMA;
839
			} else {
840
				WARN_ON(sg_cnt != 1);
841 842
				sdhci_writel(host, sg_dma_address(data->sg),
					SDHCI_DMA_ADDRESS);
843 844 845 846
			}
		}
	}

847 848 849 850 851 852
	/*
	 * Always adjust the DMA selection as some controllers
	 * (e.g. JMicron) can't do PIO properly when the selection
	 * is ADMA.
	 */
	if (host->version >= SDHCI_SPEC_200) {
853
		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
854 855 856 857 858 859
		ctrl &= ~SDHCI_CTRL_DMA_MASK;
		if ((host->flags & SDHCI_REQ_USE_DMA) &&
			(host->flags & SDHCI_USE_ADMA))
			ctrl |= SDHCI_CTRL_ADMA32;
		else
			ctrl |= SDHCI_CTRL_SDMA;
860
		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
861 862
	}

863
	if (!(host->flags & SDHCI_REQ_USE_DMA)) {
864 865 866 867 868 869 870 871
		int flags;

		flags = SG_MITER_ATOMIC;
		if (host->data->flags & MMC_DATA_READ)
			flags |= SG_MITER_TO_SG;
		else
			flags |= SG_MITER_FROM_SG;
		sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
872
		host->blocks = data->blocks;
873
	}
874

875 876
	sdhci_set_transfer_irqs(host);

877 878 879
	/* Set the DMA boundary value and block size */
	sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
		data->blksz), SDHCI_BLOCK_SIZE);
880
	sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
881 882 883
}

static void sdhci_set_transfer_mode(struct sdhci_host *host,
884
	struct mmc_command *cmd)
885 886
{
	u16 mode;
887
	struct mmc_data *data = cmd->data;
888 889 890 891

	if (data == NULL)
		return;

892 893
	WARN_ON(!host->data);

894
	mode = SDHCI_TRNS_BLK_CNT_EN;
895 896 897 898 899 900 901 902
	if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
		mode |= SDHCI_TRNS_MULTI;
		/*
		 * If we are sending CMD23, CMD12 never gets sent
		 * on successful completion (so no Auto-CMD12).
		 */
		if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
			mode |= SDHCI_TRNS_AUTO_CMD12;
903 904 905 906
		else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
			mode |= SDHCI_TRNS_AUTO_CMD23;
			sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
		}
907
	}
908

909 910
	if (data->flags & MMC_DATA_READ)
		mode |= SDHCI_TRNS_READ;
911
	if (host->flags & SDHCI_REQ_USE_DMA)
912 913
		mode |= SDHCI_TRNS_DMA;

914
	sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
915 916 917 918 919 920 921 922 923 924 925
}

static void sdhci_finish_data(struct sdhci_host *host)
{
	struct mmc_data *data;

	BUG_ON(!host->data);

	data = host->data;
	host->data = NULL;

926
	if (host->flags & SDHCI_REQ_USE_DMA) {
927 928 929 930 931 932 933
		if (host->flags & SDHCI_USE_ADMA)
			sdhci_adma_table_post(host, data);
		else {
			dma_unmap_sg(mmc_dev(host->mmc), data->sg,
				data->sg_len, (data->flags & MMC_DATA_READ) ?
					DMA_FROM_DEVICE : DMA_TO_DEVICE);
		}
934 935 936
	}

	/*
937 938 939 940 941
	 * The specification states that the block count register must
	 * be updated, but it does not specify at what point in the
	 * data flow. That makes the register entirely useless to read
	 * back so we have to assume that nothing made it to the card
	 * in the event of an error.
942
	 */
943 944
	if (data->error)
		data->bytes_xfered = 0;
945
	else
946
		data->bytes_xfered = data->blksz * data->blocks;
947

948 949 950 951 952 953 954 955 956
	/*
	 * Need to send CMD12 if -
	 * a) open-ended multiblock transfer (no CMD23)
	 * b) error in multiblock transfer
	 */
	if (data->stop &&
	    (data->error ||
	     !host->mrq->sbc)) {

957 958 959 960
		/*
		 * The controller needs a reset of internal state machines
		 * upon error conditions.
		 */
P
Pierre Ossman 已提交
961
		if (data->error) {
962 963 964 965 966 967 968 969 970 971 972 973
			sdhci_reset(host, SDHCI_RESET_CMD);
			sdhci_reset(host, SDHCI_RESET_DATA);
		}

		sdhci_send_command(host, data->stop);
	} else
		tasklet_schedule(&host->finish_tasklet);
}

static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
{
	int flags;
974
	u32 mask;
975
	unsigned long timeout;
976 977 978 979

	WARN_ON(host->cmd);

	/* Wait max 10 ms */
980
	timeout = 10;
981 982 983 984 985 986 987 988 989 990

	mask = SDHCI_CMD_INHIBIT;
	if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
		mask |= SDHCI_DATA_INHIBIT;

	/* We shouldn't wait for data inihibit for stop commands, even
	   though they might use busy signaling */
	if (host->mrq->data && (cmd == host->mrq->data->stop))
		mask &= ~SDHCI_DATA_INHIBIT;

991
	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
992
		if (timeout == 0) {
993
			pr_err("%s: Controller never released "
P
Pierre Ossman 已提交
994
				"inhibit bit(s).\n", mmc_hostname(host->mmc));
995
			sdhci_dumpregs(host);
P
Pierre Ossman 已提交
996
			cmd->error = -EIO;
997 998 999
			tasklet_schedule(&host->finish_tasklet);
			return;
		}
1000 1001 1002
		timeout--;
		mdelay(1);
	}
1003 1004 1005 1006 1007

	mod_timer(&host->timer, jiffies + 10 * HZ);

	host->cmd = cmd;

1008
	sdhci_prepare_data(host, cmd);
1009

1010
	sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1011

1012
	sdhci_set_transfer_mode(host, cmd);
1013

1014
	if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1015
		pr_err("%s: Unsupported response type!\n",
1016
			mmc_hostname(host->mmc));
P
Pierre Ossman 已提交
1017
		cmd->error = -EINVAL;
1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034
		tasklet_schedule(&host->finish_tasklet);
		return;
	}

	if (!(cmd->flags & MMC_RSP_PRESENT))
		flags = SDHCI_CMD_RESP_NONE;
	else if (cmd->flags & MMC_RSP_136)
		flags = SDHCI_CMD_RESP_LONG;
	else if (cmd->flags & MMC_RSP_BUSY)
		flags = SDHCI_CMD_RESP_SHORT_BUSY;
	else
		flags = SDHCI_CMD_RESP_SHORT;

	if (cmd->flags & MMC_RSP_CRC)
		flags |= SDHCI_CMD_CRC;
	if (cmd->flags & MMC_RSP_OPCODE)
		flags |= SDHCI_CMD_INDEX;
1035 1036

	/* CMD19 is special in that the Data Present Select should be set */
1037 1038
	if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
	    cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1039 1040
		flags |= SDHCI_CMD_DATA;

1041
	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053
}

static void sdhci_finish_command(struct sdhci_host *host)
{
	int i;

	BUG_ON(host->cmd == NULL);

	if (host->cmd->flags & MMC_RSP_PRESENT) {
		if (host->cmd->flags & MMC_RSP_136) {
			/* CRC is stripped so we need to do some shifting. */
			for (i = 0;i < 4;i++) {
1054
				host->cmd->resp[i] = sdhci_readl(host,
1055 1056 1057
					SDHCI_RESPONSE + (3-i)*4) << 8;
				if (i != 3)
					host->cmd->resp[i] |=
1058
						sdhci_readb(host,
1059 1060 1061
						SDHCI_RESPONSE + (3-i)*4-1);
			}
		} else {
1062
			host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1063 1064 1065
		}
	}

P
Pierre Ossman 已提交
1066
	host->cmd->error = 0;
1067

1068 1069 1070 1071 1072
	/* Finished CMD23, now send actual command. */
	if (host->cmd == host->mrq->sbc) {
		host->cmd = NULL;
		sdhci_send_command(host, host->mrq->cmd);
	} else {
1073

1074 1075 1076
		/* Processed actual command. */
		if (host->data && host->data_early)
			sdhci_finish_data(host);
1077

1078 1079 1080 1081 1082
		if (!host->cmd->data)
			tasklet_schedule(&host->finish_tasklet);

		host->cmd = NULL;
	}
1083 1084 1085 1086
}

static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
{
1087
	int div = 0; /* Initialized for compiler warning */
1088
	int real_div = div, clk_mul = 1;
1089
	u16 clk = 0;
1090
	unsigned long timeout;
1091

1092
	if (clock && clock == host->clock)
1093 1094
		return;

1095 1096
	host->mmc->actual_clock = 0;

1097 1098 1099 1100 1101 1102
	if (host->ops->set_clock) {
		host->ops->set_clock(host, clock);
		if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
			return;
	}

1103
	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1104 1105 1106 1107

	if (clock == 0)
		goto out;

1108
	if (host->version >= SDHCI_SPEC_300) {
1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133
		/*
		 * Check if the Host Controller supports Programmable Clock
		 * Mode.
		 */
		if (host->clk_mul) {
			u16 ctrl;

			/*
			 * We need to figure out whether the Host Driver needs
			 * to select Programmable Clock Mode, or the value can
			 * be set automatically by the Host Controller based on
			 * the Preset Value registers.
			 */
			ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
			if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
				for (div = 1; div <= 1024; div++) {
					if (((host->max_clk * host->clk_mul) /
					      div) <= clock)
						break;
				}
				/*
				 * Set Programmable Clock Mode in the Clock
				 * Control register.
				 */
				clk = SDHCI_PROG_CLOCK_MODE;
1134 1135
				real_div = div;
				clk_mul = host->clk_mul;
1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147
				div--;
			}
		} else {
			/* Version 3.00 divisors must be a multiple of 2. */
			if (host->max_clk <= clock)
				div = 1;
			else {
				for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
				     div += 2) {
					if ((host->max_clk / div) <= clock)
						break;
				}
1148
			}
1149
			real_div = div;
1150
			div >>= 1;
1151 1152 1153
		}
	} else {
		/* Version 2.00 divisors must be a power of 2. */
1154
		for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1155 1156 1157
			if ((host->max_clk / div) <= clock)
				break;
		}
1158
		real_div = div;
1159
		div >>= 1;
1160 1161
	}

1162 1163 1164
	if (real_div)
		host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;

1165
	clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1166 1167
	clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
		<< SDHCI_DIVIDER_HI_SHIFT;
1168
	clk |= SDHCI_CLOCK_INT_EN;
1169
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1170

1171 1172
	/* Wait max 20 ms */
	timeout = 20;
1173
	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1174 1175
		& SDHCI_CLOCK_INT_STABLE)) {
		if (timeout == 0) {
1176
			pr_err("%s: Internal clock never "
P
Pierre Ossman 已提交
1177
				"stabilised.\n", mmc_hostname(host->mmc));
1178 1179 1180
			sdhci_dumpregs(host);
			return;
		}
1181 1182 1183
		timeout--;
		mdelay(1);
	}
1184 1185

	clk |= SDHCI_CLOCK_CARD_EN;
1186
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1187 1188 1189 1190 1191

out:
	host->clock = clock;
}

A
Adrian Hunter 已提交
1192
static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1193
{
1194
	u8 pwr = 0;
1195

1196
	if (power != (unsigned short)-1) {
1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214
		switch (1 << power) {
		case MMC_VDD_165_195:
			pwr = SDHCI_POWER_180;
			break;
		case MMC_VDD_29_30:
		case MMC_VDD_30_31:
			pwr = SDHCI_POWER_300;
			break;
		case MMC_VDD_32_33:
		case MMC_VDD_33_34:
			pwr = SDHCI_POWER_330;
			break;
		default:
			BUG();
		}
	}

	if (host->pwr == pwr)
A
Adrian Hunter 已提交
1215
		return -1;
1216

1217 1218 1219
	host->pwr = pwr;

	if (pwr == 0) {
1220
		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
A
Adrian Hunter 已提交
1221
		return 0;
1222 1223 1224 1225 1226 1227
	}

	/*
	 * Spec says that we should clear the power reg before setting
	 * a new value. Some controllers don't seem to like this though.
	 */
1228
	if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1229
		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1230

1231
	/*
1232
	 * At least the Marvell CaFe chip gets confused if we set the voltage
1233 1234
	 * and set turn on power at the same time, so set the voltage first.
	 */
1235
	if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1236
		sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1237

1238
	pwr |= SDHCI_POWER_ON;
1239

1240
	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1241 1242 1243 1244 1245

	/*
	 * Some controllers need an extra 10ms delay of 10ms before they
	 * can apply clock after applying power
	 */
1246
	if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1247
		mdelay(10);
A
Adrian Hunter 已提交
1248 1249

	return power;
1250 1251
}

1252 1253 1254 1255 1256 1257 1258 1259 1260
/*****************************************************************************\
 *                                                                           *
 * MMC callbacks                                                             *
 *                                                                           *
\*****************************************************************************/

static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
	struct sdhci_host *host;
1261
	bool present;
1262
	unsigned long flags;
1263
	u32 tuning_opcode;
1264 1265 1266

	host = mmc_priv(mmc);

1267 1268
	sdhci_runtime_pm_get(host);

1269 1270 1271 1272
	spin_lock_irqsave(&host->lock, flags);

	WARN_ON(host->mrq != NULL);

1273
#ifndef SDHCI_USE_LEDS_CLASS
1274
	sdhci_activate_led(host);
1275
#endif
1276 1277 1278 1279 1280 1281

	/*
	 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
	 * requests if Auto-CMD12 is enabled.
	 */
	if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1282 1283 1284 1285 1286
		if (mrq->stop) {
			mrq->data->stop = NULL;
			mrq->stop = NULL;
		}
	}
1287 1288 1289

	host->mrq = mrq;

1290 1291 1292 1293 1294 1295 1296
	/* If polling, assume that the card is always present. */
	if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
		present = true;
	else
		present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
				SDHCI_CARD_PRESENT;

1297 1298 1299 1300 1301 1302 1303
	/* If we're using a cd-gpio, testing the presence bit might fail. */
	if (!present) {
		int ret = mmc_gpio_get_cd(host->mmc);
		if (ret > 0)
			present = true;
	}

1304
	if (!present || host->flags & SDHCI_DEVICE_DEAD) {
P
Pierre Ossman 已提交
1305
		host->mrq->cmd->error = -ENOMEDIUM;
1306
		tasklet_schedule(&host->finish_tasklet);
1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317
	} else {
		u32 present_state;

		present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
		/*
		 * Check if the re-tuning timer has already expired and there
		 * is no on-going data transfer. If so, we need to execute
		 * tuning procedure before sending command.
		 */
		if ((host->flags & SDHCI_NEEDS_RETUNING) &&
		    !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1318 1319 1320 1321
			/* eMMC uses cmd21 while sd and sdio use cmd19 */
			tuning_opcode = mmc->card->type == MMC_TYPE_MMC ?
				MMC_SEND_TUNING_BLOCK_HS200 :
				MMC_SEND_TUNING_BLOCK;
1322
			spin_unlock_irqrestore(&host->lock, flags);
1323
			sdhci_execute_tuning(mmc, tuning_opcode);
1324 1325 1326 1327 1328 1329
			spin_lock_irqsave(&host->lock, flags);

			/* Restore original mmc_request structure */
			host->mrq = mrq;
		}

1330
		if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1331 1332 1333
			sdhci_send_command(host, mrq->sbc);
		else
			sdhci_send_command(host, mrq->cmd);
1334
	}
1335

1336
	mmiowb();
1337 1338 1339
	spin_unlock_irqrestore(&host->lock, flags);
}

1340
static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1341 1342
{
	unsigned long flags;
A
Adrian Hunter 已提交
1343
	int vdd_bit = -1;
1344 1345 1346 1347
	u8 ctrl;

	spin_lock_irqsave(&host->lock, flags);

A
Adrian Hunter 已提交
1348 1349 1350 1351 1352 1353
	if (host->flags & SDHCI_DEVICE_DEAD) {
		spin_unlock_irqrestore(&host->lock, flags);
		if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
			mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
		return;
	}
P
Pierre Ossman 已提交
1354

1355 1356 1357 1358 1359
	/*
	 * Reset the chip on each power off.
	 * Should clear out any weird states.
	 */
	if (ios->power_mode == MMC_POWER_OFF) {
1360
		sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1361
		sdhci_reinit(host);
1362 1363 1364 1365 1366
	}

	sdhci_set_clock(host, ios->clock);

	if (ios->power_mode == MMC_POWER_OFF)
A
Adrian Hunter 已提交
1367
		vdd_bit = sdhci_set_power(host, -1);
1368
	else
A
Adrian Hunter 已提交
1369 1370 1371 1372 1373 1374 1375
		vdd_bit = sdhci_set_power(host, ios->vdd);

	if (host->vmmc && vdd_bit != -1) {
		spin_unlock_irqrestore(&host->lock, flags);
		mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
		spin_lock_irqsave(&host->lock, flags);
	}
1376

1377 1378 1379
	if (host->ops->platform_send_init_74_clocks)
		host->ops->platform_send_init_74_clocks(host, ios->power_mode);

1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402
	/*
	 * If your platform has 8-bit width support but is not a v3 controller,
	 * or if it requires special setup code, you should implement that in
	 * platform_8bit_width().
	 */
	if (host->ops->platform_8bit_width)
		host->ops->platform_8bit_width(host, ios->bus_width);
	else {
		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
		if (ios->bus_width == MMC_BUS_WIDTH_8) {
			ctrl &= ~SDHCI_CTRL_4BITBUS;
			if (host->version >= SDHCI_SPEC_300)
				ctrl |= SDHCI_CTRL_8BITBUS;
		} else {
			if (host->version >= SDHCI_SPEC_300)
				ctrl &= ~SDHCI_CTRL_8BITBUS;
			if (ios->bus_width == MMC_BUS_WIDTH_4)
				ctrl |= SDHCI_CTRL_4BITBUS;
			else
				ctrl &= ~SDHCI_CTRL_4BITBUS;
		}
		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
	}
1403

1404
	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1405

1406 1407 1408
	if ((ios->timing == MMC_TIMING_SD_HS ||
	     ios->timing == MMC_TIMING_MMC_HS)
	    && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1409 1410 1411 1412
		ctrl |= SDHCI_CTRL_HISPD;
	else
		ctrl &= ~SDHCI_CTRL_HISPD;

1413
	if (host->version >= SDHCI_SPEC_300) {
1414 1415 1416 1417
		u16 clk, ctrl_2;
		unsigned int clock;

		/* In case of UHS-I modes, set High Speed Enable */
1418 1419
		if ((ios->timing == MMC_TIMING_MMC_HS200) ||
		    (ios->timing == MMC_TIMING_UHS_SDR50) ||
1420 1421
		    (ios->timing == MMC_TIMING_UHS_SDR104) ||
		    (ios->timing == MMC_TIMING_UHS_DDR50) ||
1422
		    (ios->timing == MMC_TIMING_UHS_SDR25))
1423
			ctrl |= SDHCI_CTRL_HISPD;
1424 1425 1426

		ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
		if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1427
			sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438
			/*
			 * We only need to set Driver Strength if the
			 * preset value enable is not set.
			 */
			ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
			if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
				ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
			else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
				ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;

			sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457
		} else {
			/*
			 * According to SDHC Spec v3.00, if the Preset Value
			 * Enable in the Host Control 2 register is set, we
			 * need to reset SD Clock Enable before changing High
			 * Speed Enable to avoid generating clock gliches.
			 */

			/* Reset SD Clock Enable */
			clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
			clk &= ~SDHCI_CLOCK_CARD_EN;
			sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

			sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);

			/* Re-enable SD Clock */
			clock = host->clock;
			host->clock = 0;
			sdhci_set_clock(host, clock);
1458
		}
1459 1460 1461 1462 1463 1464 1465


		/* Reset SD Clock Enable */
		clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
		clk &= ~SDHCI_CLOCK_CARD_EN;
		sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

1466 1467 1468 1469 1470 1471
		if (host->ops->set_uhs_signaling)
			host->ops->set_uhs_signaling(host, ios->timing);
		else {
			ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
			/* Select Bus Speed Mode for host */
			ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1472 1473 1474
			if (ios->timing == MMC_TIMING_MMC_HS200)
				ctrl_2 |= SDHCI_CTRL_HS_SDR200;
			else if (ios->timing == MMC_TIMING_UHS_SDR12)
1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485
				ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
			else if (ios->timing == MMC_TIMING_UHS_SDR25)
				ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
			else if (ios->timing == MMC_TIMING_UHS_SDR50)
				ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
			else if (ios->timing == MMC_TIMING_UHS_SDR104)
				ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
			else if (ios->timing == MMC_TIMING_UHS_DDR50)
				ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
			sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
		}
1486 1487 1488 1489 1490

		/* Re-enable SD Clock */
		clock = host->clock;
		host->clock = 0;
		sdhci_set_clock(host, clock);
1491 1492
	} else
		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1493

1494 1495 1496 1497 1498
	/*
	 * Some (ENE) controllers go apeshit on some ios operation,
	 * signalling timeout and CRC errors even on CMD0. Resetting
	 * it on each ios seems to solve the problem.
	 */
1499
	if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1500 1501
		sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);

1502
	mmiowb();
1503 1504 1505
	spin_unlock_irqrestore(&host->lock, flags);
}

1506 1507 1508 1509 1510 1511 1512 1513 1514 1515
static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
	struct sdhci_host *host = mmc_priv(mmc);

	sdhci_runtime_pm_get(host);
	sdhci_do_set_ios(host, ios);
	sdhci_runtime_pm_put(host);
}

static int sdhci_check_ro(struct sdhci_host *host)
1516 1517
{
	unsigned long flags;
1518
	int is_readonly;
1519 1520 1521

	spin_lock_irqsave(&host->lock, flags);

P
Pierre Ossman 已提交
1522
	if (host->flags & SDHCI_DEVICE_DEAD)
1523 1524 1525
		is_readonly = 0;
	else if (host->ops->get_ro)
		is_readonly = host->ops->get_ro(host);
P
Pierre Ossman 已提交
1526
	else
1527 1528
		is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
				& SDHCI_WRITE_PROTECT);
1529 1530 1531

	spin_unlock_irqrestore(&host->lock, flags);

1532 1533 1534
	/* This quirk needs to be replaced by a callback-function later */
	return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
		!is_readonly : is_readonly;
1535 1536
}

1537 1538
#define SAMPLE_COUNT	5

1539
static int sdhci_do_get_ro(struct sdhci_host *host)
1540 1541 1542 1543
{
	int i, ro_count;

	if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1544
		return sdhci_check_ro(host);
1545 1546 1547

	ro_count = 0;
	for (i = 0; i < SAMPLE_COUNT; i++) {
1548
		if (sdhci_check_ro(host)) {
1549 1550 1551 1552 1553 1554 1555 1556
			if (++ro_count > SAMPLE_COUNT / 2)
				return 1;
		}
		msleep(30);
	}
	return 0;
}

1557 1558 1559 1560 1561 1562 1563 1564
static void sdhci_hw_reset(struct mmc_host *mmc)
{
	struct sdhci_host *host = mmc_priv(mmc);

	if (host->ops && host->ops->hw_reset)
		host->ops->hw_reset(host);
}

1565
static int sdhci_get_ro(struct mmc_host *mmc)
P
Pierre Ossman 已提交
1566
{
1567 1568
	struct sdhci_host *host = mmc_priv(mmc);
	int ret;
P
Pierre Ossman 已提交
1569

1570 1571 1572 1573 1574
	sdhci_runtime_pm_get(host);
	ret = sdhci_do_get_ro(host);
	sdhci_runtime_pm_put(host);
	return ret;
}
P
Pierre Ossman 已提交
1575

1576 1577
static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
{
P
Pierre Ossman 已提交
1578 1579 1580
	if (host->flags & SDHCI_DEVICE_DEAD)
		goto out;

1581 1582 1583 1584 1585 1586 1587 1588 1589
	if (enable)
		host->flags |= SDHCI_SDIO_IRQ_ENABLED;
	else
		host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;

	/* SDIO IRQ will be enabled as appropriate in runtime resume */
	if (host->runtime_suspended)
		goto out;

P
Pierre Ossman 已提交
1590
	if (enable)
1591 1592 1593
		sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
	else
		sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
P
Pierre Ossman 已提交
1594
out:
P
Pierre Ossman 已提交
1595
	mmiowb();
1596 1597 1598 1599 1600 1601
}

static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
{
	struct sdhci_host *host = mmc_priv(mmc);
	unsigned long flags;
P
Pierre Ossman 已提交
1602

1603 1604
	spin_lock_irqsave(&host->lock, flags);
	sdhci_enable_sdio_irq_nolock(host, enable);
P
Pierre Ossman 已提交
1605 1606 1607
	spin_unlock_irqrestore(&host->lock, flags);
}

1608 1609
static int sdhci_do_3_3v_signal_voltage_switch(struct sdhci_host *host,
						u16 ctrl)
1610
{
1611
	int ret;
1612

1613 1614 1615
	/* Set 1.8V Signal Enable in the Host Control2 register to 0 */
	ctrl &= ~SDHCI_CTRL_VDD_180;
	sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1616

1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628
	if (host->vqmmc) {
		ret = regulator_set_voltage(host->vqmmc, 3300000, 3300000);
		if (ret) {
			pr_warning("%s: Switching to 3.3V signalling voltage "
				   " failed\n", mmc_hostname(host->mmc));
			return -EIO;
		}
	}
	/* Wait for 5ms */
	usleep_range(5000, 5500);

	/* 3.3V regulator output should be stable within 5 ms */
1629
	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1630 1631
	if (!(ctrl & SDHCI_CTRL_VDD_180))
		return 0;
1632

1633 1634
	pr_warning("%s: 3.3V regulator output did not became stable\n",
		   mmc_hostname(host->mmc));
1635

1636 1637
	return -EIO;
}
1638

1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666
static int sdhci_do_1_8v_signal_voltage_switch(struct sdhci_host *host,
						u16 ctrl)
{
	u8 pwr;
	u16 clk;
	u32 present_state;
	int ret;

	/* Stop SDCLK */
	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
	clk &= ~SDHCI_CLOCK_CARD_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

	/* Check whether DAT[3:0] is 0000 */
	present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
	if (!((present_state & SDHCI_DATA_LVL_MASK) >>
	       SDHCI_DATA_LVL_SHIFT)) {
		/*
		 * Enable 1.8V Signal Enable in the Host Control2
		 * register
		 */
		if (host->vqmmc)
			ret = regulator_set_voltage(host->vqmmc,
				1800000, 1800000);
		else
			ret = 0;

		if (!ret) {
1667 1668 1669 1670 1671 1672 1673 1674
			ctrl |= SDHCI_CTRL_VDD_180;
			sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);

			/* Wait for 5ms */
			usleep_range(5000, 5500);

			ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
			if (ctrl & SDHCI_CTRL_VDD_180) {
1675
				/* Provide SDCLK again and wait for 1ms */
1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691
				clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
				clk |= SDHCI_CLOCK_CARD_EN;
				sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
				usleep_range(1000, 1500);

				/*
				 * If DAT[3:0] level is 1111b, then the card
				 * was successfully switched to 1.8V signaling.
				 */
				present_state = sdhci_readl(host,
							SDHCI_PRESENT_STATE);
				if ((present_state & SDHCI_DATA_LVL_MASK) ==
				     SDHCI_DATA_LVL_MASK)
					return 0;
			}
		}
1692
	}
1693

1694 1695 1696 1697 1698 1699 1700 1701 1702 1703
	/*
	 * If we are here, that means the switch to 1.8V signaling
	 * failed. We power cycle the card, and retry initialization
	 * sequence by setting S18R to 0.
	 */
	pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
	pwr &= ~SDHCI_POWER_ON;
	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
	if (host->vmmc)
		regulator_disable(host->vmmc);
1704

1705 1706 1707 1708 1709 1710
	/* Wait for 1ms as per the spec */
	usleep_range(1000, 1500);
	pwr |= SDHCI_POWER_ON;
	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
	if (host->vmmc)
		regulator_enable(host->vmmc);
1711

1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740
	pr_warning("%s: Switching to 1.8V signalling voltage failed, "
		   "retrying with S18R set to 0\n", mmc_hostname(host->mmc));

	return -EAGAIN;
}

static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
						struct mmc_ios *ios)
{
	u16 ctrl;

	/*
	 * Signal Voltage Switching is only applicable for Host Controllers
	 * v3.00 and above.
	 */
	if (host->version < SDHCI_SPEC_300)
		return 0;

	/*
	 * We first check whether the request is to set signalling voltage
	 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
	 */
	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
		return sdhci_do_3_3v_signal_voltage_switch(host, ctrl);
	else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
			(ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180))
		return sdhci_do_1_8v_signal_voltage_switch(host, ctrl);
	else
1741 1742 1743 1744
		/* No signal voltage switch required */
		return 0;
}

1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758
static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
	struct mmc_ios *ios)
{
	struct sdhci_host *host = mmc_priv(mmc);
	int err;

	if (host->version < SDHCI_SPEC_300)
		return 0;
	sdhci_runtime_pm_get(host);
	err = sdhci_do_start_signal_voltage_switch(host, ios);
	sdhci_runtime_pm_put(host);
	return err;
}

1759
static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1760 1761 1762 1763 1764 1765 1766
{
	struct sdhci_host *host;
	u16 ctrl;
	u32 ier;
	int tuning_loop_counter = MAX_TUNING_LOOP;
	unsigned long timeout;
	int err = 0;
1767
	bool requires_tuning_nonuhs = false;
1768 1769 1770

	host = mmc_priv(mmc);

1771
	sdhci_runtime_pm_get(host);
1772 1773 1774 1775 1776 1777
	disable_irq(host->irq);
	spin_lock(&host->lock);

	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);

	/*
1778 1779
	 * The Host Controller needs tuning only in case of SDR104 mode
	 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1780
	 * Capabilities register.
1781 1782
	 * If the Host Controller supports the HS200 mode then the
	 * tuning function has to be executed.
1783
	 */
1784 1785 1786 1787 1788
	if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
	    (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
	     host->flags & SDHCI_HS200_NEEDS_TUNING))
		requires_tuning_nonuhs = true;

1789
	if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1790
	    requires_tuning_nonuhs)
1791 1792 1793 1794
		ctrl |= SDHCI_CTRL_EXEC_TUNING;
	else {
		spin_unlock(&host->lock);
		enable_irq(host->irq);
1795
		sdhci_runtime_pm_put(host);
1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820
		return 0;
	}

	sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);

	/*
	 * As per the Host Controller spec v3.00, tuning command
	 * generates Buffer Read Ready interrupt, so enable that.
	 *
	 * Note: The spec clearly says that when tuning sequence
	 * is being performed, the controller does not generate
	 * interrupts other than Buffer Read Ready interrupt. But
	 * to make sure we don't hit a controller bug, we _only_
	 * enable Buffer Read Ready interrupt here.
	 */
	ier = sdhci_readl(host, SDHCI_INT_ENABLE);
	sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);

	/*
	 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
	 * of loops reaches 40 times or a timeout of 150ms occurs.
	 */
	timeout = 150;
	do {
		struct mmc_command cmd = {0};
1821
		struct mmc_request mrq = {NULL};
1822 1823 1824 1825

		if (!tuning_loop_counter && !timeout)
			break;

1826
		cmd.opcode = opcode;
1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840
		cmd.arg = 0;
		cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
		cmd.retries = 0;
		cmd.data = NULL;
		cmd.error = 0;

		mrq.cmd = &cmd;
		host->mrq = &mrq;

		/*
		 * In response to CMD19, the card sends 64 bytes of tuning
		 * block to the Host Controller. So we set the block size
		 * to 64 here.
		 */
1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851
		if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
			if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
				sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
					     SDHCI_BLOCK_SIZE);
			else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
				sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
					     SDHCI_BLOCK_SIZE);
		} else {
			sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
				     SDHCI_BLOCK_SIZE);
		}
1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876

		/*
		 * The tuning block is sent by the card to the host controller.
		 * So we set the TRNS_READ bit in the Transfer Mode register.
		 * This also takes care of setting DMA Enable and Multi Block
		 * Select in the same register to 0.
		 */
		sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);

		sdhci_send_command(host, &cmd);

		host->cmd = NULL;
		host->mrq = NULL;

		spin_unlock(&host->lock);
		enable_irq(host->irq);

		/* Wait for Buffer Read Ready interrupt */
		wait_event_interruptible_timeout(host->buf_ready_int,
					(host->tuning_done == 1),
					msecs_to_jiffies(50));
		disable_irq(host->irq);
		spin_lock(&host->lock);

		if (!host->tuning_done) {
1877
			pr_info(DRIVER_NAME ": Timeout waiting for "
1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906
				"Buffer Read Ready interrupt during tuning "
				"procedure, falling back to fixed sampling "
				"clock\n");
			ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
			ctrl &= ~SDHCI_CTRL_TUNED_CLK;
			ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
			sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);

			err = -EIO;
			goto out;
		}

		host->tuning_done = 0;

		ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
		tuning_loop_counter--;
		timeout--;
		mdelay(1);
	} while (ctrl & SDHCI_CTRL_EXEC_TUNING);

	/*
	 * The Host Driver has exhausted the maximum number of loops allowed,
	 * so use fixed sampling frequency.
	 */
	if (!tuning_loop_counter || !timeout) {
		ctrl &= ~SDHCI_CTRL_TUNED_CLK;
		sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
	} else {
		if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1907
			pr_info(DRIVER_NAME ": Tuning procedure"
1908 1909 1910 1911 1912 1913 1914
				" failed, falling back to fixed sampling"
				" clock\n");
			err = -EIO;
		}
	}

out:
1915 1916 1917 1918 1919 1920 1921 1922
	/*
	 * If this is the very first time we are here, we start the retuning
	 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
	 * flag won't be set, we check this condition before actually starting
	 * the timer.
	 */
	if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
	    (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1923
		host->flags |= SDHCI_USING_RETUNING_TIMER;
1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940
		mod_timer(&host->tuning_timer, jiffies +
			host->tuning_count * HZ);
		/* Tuning mode 1 limits the maximum data length to 4MB */
		mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
	} else {
		host->flags &= ~SDHCI_NEEDS_RETUNING;
		/* Reload the new initial value for timer */
		if (host->tuning_mode == SDHCI_TUNING_MODE_1)
			mod_timer(&host->tuning_timer, jiffies +
				host->tuning_count * HZ);
	}

	/*
	 * In case tuning fails, host controllers which support re-tuning can
	 * try tuning again at a later time, when the re-tuning timer expires.
	 * So for these controllers, we return 0. Since there might be other
	 * controllers who do not have this capability, we return error for
1941 1942
	 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
	 * a retuning timer to do the retuning for the card.
1943
	 */
1944
	if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
1945 1946
		err = 0;

1947 1948 1949
	sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
	spin_unlock(&host->lock);
	enable_irq(host->irq);
1950
	sdhci_runtime_pm_put(host);
1951 1952 1953 1954

	return err;
}

1955
static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974
{
	u16 ctrl;
	unsigned long flags;

	/* Host Controller v3.00 defines preset value registers */
	if (host->version < SDHCI_SPEC_300)
		return;

	spin_lock_irqsave(&host->lock, flags);

	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);

	/*
	 * We only enable or disable Preset Value if they are not already
	 * enabled or disabled respectively. Otherwise, we bail out.
	 */
	if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
		ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
		sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1975
		host->flags |= SDHCI_PV_ENABLED;
1976 1977 1978
	} else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
		ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
		sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1979
		host->flags &= ~SDHCI_PV_ENABLED;
1980 1981 1982 1983 1984
	}

	spin_unlock_irqrestore(&host->lock, flags);
}

1985 1986 1987 1988 1989 1990 1991 1992 1993
static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
{
	struct sdhci_host *host = mmc_priv(mmc);

	sdhci_runtime_pm_get(host);
	sdhci_do_enable_preset_value(host, enable);
	sdhci_runtime_pm_put(host);
}

1994
static const struct mmc_host_ops sdhci_ops = {
1995 1996 1997
	.request	= sdhci_request,
	.set_ios	= sdhci_set_ios,
	.get_ro		= sdhci_get_ro,
1998
	.hw_reset	= sdhci_hw_reset,
P
Pierre Ossman 已提交
1999
	.enable_sdio_irq = sdhci_enable_sdio_irq,
2000
	.start_signal_voltage_switch	= sdhci_start_signal_voltage_switch,
2001
	.execute_tuning			= sdhci_execute_tuning,
2002
	.enable_preset_value		= sdhci_enable_preset_value,
2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019
};

/*****************************************************************************\
 *                                                                           *
 * Tasklets                                                                  *
 *                                                                           *
\*****************************************************************************/

static void sdhci_tasklet_card(unsigned long param)
{
	struct sdhci_host *host;
	unsigned long flags;

	host = (struct sdhci_host*)param;

	spin_lock_irqsave(&host->lock, flags);

2020 2021 2022
	/* Check host->mrq first in case we are runtime suspended */
	if (host->mrq &&
	    !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
2023
		pr_err("%s: Card removed during transfer!\n",
2024
			mmc_hostname(host->mmc));
2025
		pr_err("%s: Resetting controller.\n",
2026
			mmc_hostname(host->mmc));
2027

2028 2029
		sdhci_reset(host, SDHCI_RESET_CMD);
		sdhci_reset(host, SDHCI_RESET_DATA);
2030

2031 2032
		host->mrq->cmd->error = -ENOMEDIUM;
		tasklet_schedule(&host->finish_tasklet);
2033 2034 2035 2036
	}

	spin_unlock_irqrestore(&host->lock, flags);

P
Pierre Ossman 已提交
2037
	mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2038 2039 2040 2041 2042 2043 2044 2045 2046 2047
}

static void sdhci_tasklet_finish(unsigned long param)
{
	struct sdhci_host *host;
	unsigned long flags;
	struct mmc_request *mrq;

	host = (struct sdhci_host*)param;

2048 2049
	spin_lock_irqsave(&host->lock, flags);

2050 2051 2052 2053
        /*
         * If this tasklet gets rescheduled while running, it will
         * be run again afterwards but without any active request.
         */
2054 2055
	if (!host->mrq) {
		spin_unlock_irqrestore(&host->lock, flags);
2056
		return;
2057
	}
2058 2059 2060 2061 2062 2063 2064 2065 2066

	del_timer(&host->timer);

	mrq = host->mrq;

	/*
	 * The controller needs a reset of internal state machines
	 * upon error conditions.
	 */
P
Pierre Ossman 已提交
2067
	if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2068
	    ((mrq->cmd && mrq->cmd->error) ||
P
Pierre Ossman 已提交
2069 2070 2071
		 (mrq->data && (mrq->data->error ||
		  (mrq->data->stop && mrq->data->stop->error))) ||
		   (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2072 2073

		/* Some controllers need this kick or reset won't work here */
2074
		if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
2075 2076 2077 2078 2079 2080 2081 2082 2083 2084
			unsigned int clock;

			/* This is to force an update */
			clock = host->clock;
			host->clock = 0;
			sdhci_set_clock(host, clock);
		}

		/* Spec says we should do both at the same time, but Ricoh
		   controllers do not like that. */
2085 2086 2087 2088 2089 2090 2091 2092
		sdhci_reset(host, SDHCI_RESET_CMD);
		sdhci_reset(host, SDHCI_RESET_DATA);
	}

	host->mrq = NULL;
	host->cmd = NULL;
	host->data = NULL;

2093
#ifndef SDHCI_USE_LEDS_CLASS
2094
	sdhci_deactivate_led(host);
2095
#endif
2096

2097
	mmiowb();
2098 2099 2100
	spin_unlock_irqrestore(&host->lock, flags);

	mmc_request_done(host->mmc, mrq);
2101
	sdhci_runtime_pm_put(host);
2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113
}

static void sdhci_timeout_timer(unsigned long data)
{
	struct sdhci_host *host;
	unsigned long flags;

	host = (struct sdhci_host*)data;

	spin_lock_irqsave(&host->lock, flags);

	if (host->mrq) {
2114
		pr_err("%s: Timeout waiting for hardware "
P
Pierre Ossman 已提交
2115
			"interrupt.\n", mmc_hostname(host->mmc));
2116 2117 2118
		sdhci_dumpregs(host);

		if (host->data) {
P
Pierre Ossman 已提交
2119
			host->data->error = -ETIMEDOUT;
2120 2121 2122
			sdhci_finish_data(host);
		} else {
			if (host->cmd)
P
Pierre Ossman 已提交
2123
				host->cmd->error = -ETIMEDOUT;
2124
			else
P
Pierre Ossman 已提交
2125
				host->mrq->cmd->error = -ETIMEDOUT;
2126 2127 2128 2129 2130

			tasklet_schedule(&host->finish_tasklet);
		}
	}

2131
	mmiowb();
2132 2133 2134
	spin_unlock_irqrestore(&host->lock, flags);
}

2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148
static void sdhci_tuning_timer(unsigned long data)
{
	struct sdhci_host *host;
	unsigned long flags;

	host = (struct sdhci_host *)data;

	spin_lock_irqsave(&host->lock, flags);

	host->flags |= SDHCI_NEEDS_RETUNING;

	spin_unlock_irqrestore(&host->lock, flags);
}

2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159
/*****************************************************************************\
 *                                                                           *
 * Interrupt handling                                                        *
 *                                                                           *
\*****************************************************************************/

static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
{
	BUG_ON(intmask == 0);

	if (!host->cmd) {
2160
		pr_err("%s: Got command interrupt 0x%08x even "
2161 2162
			"though no command operation was in progress.\n",
			mmc_hostname(host->mmc), (unsigned)intmask);
2163 2164 2165 2166
		sdhci_dumpregs(host);
		return;
	}

2167
	if (intmask & SDHCI_INT_TIMEOUT)
P
Pierre Ossman 已提交
2168 2169 2170 2171
		host->cmd->error = -ETIMEDOUT;
	else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
			SDHCI_INT_INDEX))
		host->cmd->error = -EILSEQ;
2172

2173
	if (host->cmd->error) {
2174
		tasklet_schedule(&host->finish_tasklet);
2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192
		return;
	}

	/*
	 * The host can send and interrupt when the busy state has
	 * ended, allowing us to wait without wasting CPU cycles.
	 * Unfortunately this is overloaded on the "data complete"
	 * interrupt, so we need to take some care when handling
	 * it.
	 *
	 * Note: The 1.0 specification is a bit ambiguous about this
	 *       feature so there might be some problems with older
	 *       controllers.
	 */
	if (host->cmd->flags & MMC_RSP_BUSY) {
		if (host->cmd->data)
			DBG("Cannot wait for busy signal when also "
				"doing a data transfer");
2193
		else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2194
			return;
2195 2196 2197

		/* The controller does not support the end-of-busy IRQ,
		 * fall through and take the SDHCI_INT_RESPONSE */
2198 2199 2200
	}

	if (intmask & SDHCI_INT_RESPONSE)
2201
		sdhci_finish_command(host);
2202 2203
}

2204
#ifdef CONFIG_MMC_DEBUG
2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232
static void sdhci_show_adma_error(struct sdhci_host *host)
{
	const char *name = mmc_hostname(host->mmc);
	u8 *desc = host->adma_desc;
	__le32 *dma;
	__le16 *len;
	u8 attr;

	sdhci_dumpregs(host);

	while (true) {
		dma = (__le32 *)(desc + 4);
		len = (__le16 *)(desc + 2);
		attr = *desc;

		DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
		    name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);

		desc += 8;

		if (attr & 2)
			break;
	}
}
#else
static void sdhci_show_adma_error(struct sdhci_host *host) { }
#endif

2233 2234
static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
{
2235
	u32 command;
2236 2237
	BUG_ON(intmask == 0);

2238 2239
	/* CMD19 generates _only_ Buffer Read Ready interrupt */
	if (intmask & SDHCI_INT_DATA_AVAIL) {
2240 2241 2242
		command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
		if (command == MMC_SEND_TUNING_BLOCK ||
		    command == MMC_SEND_TUNING_BLOCK_HS200) {
2243 2244 2245 2246 2247 2248
			host->tuning_done = 1;
			wake_up(&host->buf_ready_int);
			return;
		}
	}

2249 2250
	if (!host->data) {
		/*
2251 2252 2253
		 * The "data complete" interrupt is also used to
		 * indicate that a busy state has ended. See comment
		 * above in sdhci_cmd_irq().
2254
		 */
2255 2256 2257 2258 2259 2260
		if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
			if (intmask & SDHCI_INT_DATA_END) {
				sdhci_finish_command(host);
				return;
			}
		}
2261

2262
		pr_err("%s: Got data interrupt 0x%08x even "
2263 2264
			"though no data operation was in progress.\n",
			mmc_hostname(host->mmc), (unsigned)intmask);
2265 2266 2267 2268 2269 2270
		sdhci_dumpregs(host);

		return;
	}

	if (intmask & SDHCI_INT_DATA_TIMEOUT)
P
Pierre Ossman 已提交
2271
		host->data->error = -ETIMEDOUT;
2272 2273 2274 2275 2276
	else if (intmask & SDHCI_INT_DATA_END_BIT)
		host->data->error = -EILSEQ;
	else if ((intmask & SDHCI_INT_DATA_CRC) &&
		SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
			!= MMC_BUS_TEST_R)
P
Pierre Ossman 已提交
2277
		host->data->error = -EILSEQ;
2278
	else if (intmask & SDHCI_INT_ADMA_ERROR) {
2279
		pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2280
		sdhci_show_adma_error(host);
2281
		host->data->error = -EIO;
2282
	}
2283

P
Pierre Ossman 已提交
2284
	if (host->data->error)
2285 2286
		sdhci_finish_data(host);
	else {
P
Pierre Ossman 已提交
2287
		if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2288 2289
			sdhci_transfer_pio(host);

2290 2291 2292 2293
		/*
		 * We currently don't do anything fancy with DMA
		 * boundaries, but as we can't disable the feature
		 * we need to at least restart the transfer.
2294 2295 2296 2297
		 *
		 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
		 * should return a valid address to continue from, but as
		 * some controllers are faulty, don't trust them.
2298
		 */
2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315
		if (intmask & SDHCI_INT_DMA_END) {
			u32 dmastart, dmanow;
			dmastart = sg_dma_address(host->data->sg);
			dmanow = dmastart + host->data->bytes_xfered;
			/*
			 * Force update to the next DMA block boundary.
			 */
			dmanow = (dmanow &
				~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
				SDHCI_DEFAULT_BOUNDARY_SIZE;
			host->data->bytes_xfered = dmanow - dmastart;
			DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
				" next 0x%08x\n",
				mmc_hostname(host->mmc), dmastart,
				host->data->bytes_xfered, dmanow);
			sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
		}
2316

2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328
		if (intmask & SDHCI_INT_DATA_END) {
			if (host->cmd) {
				/*
				 * Data managed to finish before the
				 * command completed. Make sure we do
				 * things in the proper order.
				 */
				host->data_early = 1;
			} else {
				sdhci_finish_data(host);
			}
		}
2329 2330 2331
	}
}

2332
static irqreturn_t sdhci_irq(int irq, void *dev_id)
2333 2334
{
	irqreturn_t result;
2335
	struct sdhci_host *host = dev_id;
2336 2337
	u32 intmask, unexpected = 0;
	int cardint = 0, max_loops = 16;
2338 2339 2340

	spin_lock(&host->lock);

2341 2342
	if (host->runtime_suspended) {
		spin_unlock(&host->lock);
2343
		pr_warning("%s: got irq while runtime suspended\n",
2344 2345 2346 2347
		       mmc_hostname(host->mmc));
		return IRQ_HANDLED;
	}

2348
	intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2349

2350
	if (!intmask || intmask == 0xffffffff) {
2351 2352 2353 2354
		result = IRQ_NONE;
		goto out;
	}

2355
again:
2356 2357
	DBG("*** %s got interrupt: 0x%08x\n",
		mmc_hostname(host->mmc), intmask);
2358

2359
	if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377
		u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
			      SDHCI_CARD_PRESENT;

		/*
		 * There is a observation on i.mx esdhc.  INSERT bit will be
		 * immediately set again when it gets cleared, if a card is
		 * inserted.  We have to mask the irq to prevent interrupt
		 * storm which will freeze the system.  And the REMOVE gets
		 * the same situation.
		 *
		 * More testing are needed here to ensure it works for other
		 * platforms though.
		 */
		sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
						SDHCI_INT_CARD_REMOVE);
		sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
						  SDHCI_INT_CARD_INSERT);

2378
		sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2379 2380
			     SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
		intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2381
		tasklet_schedule(&host->card_tasklet);
2382
	}
2383

2384
	if (intmask & SDHCI_INT_CMD_MASK) {
2385 2386
		sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
			SDHCI_INT_STATUS);
2387
		sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2388 2389 2390
	}

	if (intmask & SDHCI_INT_DATA_MASK) {
2391 2392
		sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
			SDHCI_INT_STATUS);
2393
		sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2394 2395 2396 2397
	}

	intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);

2398 2399
	intmask &= ~SDHCI_INT_ERROR;

2400
	if (intmask & SDHCI_INT_BUS_POWER) {
2401
		pr_err("%s: Card is consuming too much power!\n",
2402
			mmc_hostname(host->mmc));
2403
		sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2404 2405
	}

2406
	intmask &= ~SDHCI_INT_BUS_POWER;
2407

P
Pierre Ossman 已提交
2408 2409 2410 2411 2412
	if (intmask & SDHCI_INT_CARD_INT)
		cardint = 1;

	intmask &= ~SDHCI_INT_CARD_INT;

2413
	if (intmask) {
2414
		unexpected |= intmask;
2415
		sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2416
	}
2417 2418 2419

	result = IRQ_HANDLED;

2420 2421 2422
	intmask = sdhci_readl(host, SDHCI_INT_STATUS);
	if (intmask && --max_loops)
		goto again;
2423 2424 2425
out:
	spin_unlock(&host->lock);

2426 2427 2428 2429 2430
	if (unexpected) {
		pr_err("%s: Unexpected interrupt 0x%08x.\n",
			   mmc_hostname(host->mmc), unexpected);
		sdhci_dumpregs(host);
	}
P
Pierre Ossman 已提交
2431 2432 2433 2434 2435 2436
	/*
	 * We have to delay this as it calls back into the driver.
	 */
	if (cardint)
		mmc_signal_sdio_irq(host->mmc);

2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447
	return result;
}

/*****************************************************************************\
 *                                                                           *
 * Suspend/resume                                                            *
 *                                                                           *
\*****************************************************************************/

#ifdef CONFIG_PM

2448
int sdhci_suspend_host(struct sdhci_host *host)
2449
{
2450
	int ret;
2451

2452 2453 2454
	if (host->ops->platform_suspend)
		host->ops->platform_suspend(host);

2455 2456
	sdhci_disable_card_detection(host);

2457
	/* Disable tuning since we are suspending */
2458
	if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2459
		del_timer_sync(&host->tuning_timer);
2460 2461 2462
		host->flags &= ~SDHCI_NEEDS_RETUNING;
	}

2463
	ret = mmc_suspend_host(host->mmc);
2464
	if (ret) {
2465
		if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2466 2467 2468 2469 2470 2471 2472
			host->flags |= SDHCI_NEEDS_RETUNING;
			mod_timer(&host->tuning_timer, jiffies +
					host->tuning_count * HZ);
		}

		sdhci_enable_card_detection(host);

2473
		return ret;
2474
	}
2475

2476
	free_irq(host->irq, host);
2477

M
Marek Szyprowski 已提交
2478
	return ret;
2479 2480
}

2481
EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2482

2483 2484 2485
int sdhci_resume_host(struct sdhci_host *host)
{
	int ret;
2486

2487
	if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2488 2489 2490
		if (host->ops->enable_dma)
			host->ops->enable_dma(host);
	}
2491

2492 2493
	ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
			  mmc_hostname(host->mmc), host);
2494 2495
	if (ret)
		return ret;
2496

2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507
	if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
	    (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
		/* Card keeps power but host controller does not */
		sdhci_init(host, 0);
		host->pwr = 0;
		host->clock = 0;
		sdhci_do_set_ios(host, &host->mmc->ios);
	} else {
		sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
		mmiowb();
	}
2508 2509

	ret = mmc_resume_host(host->mmc);
2510 2511
	sdhci_enable_card_detection(host);

2512 2513 2514
	if (host->ops->platform_resume)
		host->ops->platform_resume(host);

2515
	/* Set the re-tuning expiration flag */
2516
	if (host->flags & SDHCI_USING_RETUNING_TIMER)
2517 2518
		host->flags |= SDHCI_NEEDS_RETUNING;

2519
	return ret;
2520 2521
}

2522
EXPORT_SYMBOL_GPL(sdhci_resume_host);
2523

2524 2525 2526 2527 2528 2529 2530 2531 2532 2533
void sdhci_enable_irq_wakeups(struct sdhci_host *host)
{
	u8 val;
	val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
	val |= SDHCI_WAKE_ON_INT;
	sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
}

EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);

2534 2535
#endif /* CONFIG_PM */

2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554
#ifdef CONFIG_PM_RUNTIME

static int sdhci_runtime_pm_get(struct sdhci_host *host)
{
	return pm_runtime_get_sync(host->mmc->parent);
}

static int sdhci_runtime_pm_put(struct sdhci_host *host)
{
	pm_runtime_mark_last_busy(host->mmc->parent);
	return pm_runtime_put_autosuspend(host->mmc->parent);
}

int sdhci_runtime_suspend_host(struct sdhci_host *host)
{
	unsigned long flags;
	int ret = 0;

	/* Disable tuning since we are suspending */
2555
	if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595
		del_timer_sync(&host->tuning_timer);
		host->flags &= ~SDHCI_NEEDS_RETUNING;
	}

	spin_lock_irqsave(&host->lock, flags);
	sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
	spin_unlock_irqrestore(&host->lock, flags);

	synchronize_irq(host->irq);

	spin_lock_irqsave(&host->lock, flags);
	host->runtime_suspended = true;
	spin_unlock_irqrestore(&host->lock, flags);

	return ret;
}
EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);

int sdhci_runtime_resume_host(struct sdhci_host *host)
{
	unsigned long flags;
	int ret = 0, host_flags = host->flags;

	if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
		if (host->ops->enable_dma)
			host->ops->enable_dma(host);
	}

	sdhci_init(host, 0);

	/* Force clock and power re-program */
	host->pwr = 0;
	host->clock = 0;
	sdhci_do_set_ios(host, &host->mmc->ios);

	sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
	if (host_flags & SDHCI_PV_ENABLED)
		sdhci_do_enable_preset_value(host, true);

	/* Set the re-tuning expiration flag */
2596
	if (host->flags & SDHCI_USING_RETUNING_TIMER)
2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617
		host->flags |= SDHCI_NEEDS_RETUNING;

	spin_lock_irqsave(&host->lock, flags);

	host->runtime_suspended = false;

	/* Enable SDIO IRQ */
	if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
		sdhci_enable_sdio_irq_nolock(host, true);

	/* Enable Card Detection */
	sdhci_enable_card_detection(host);

	spin_unlock_irqrestore(&host->lock, flags);

	return ret;
}
EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);

#endif

2618 2619
/*****************************************************************************\
 *                                                                           *
2620
 * Device allocation/registration                                            *
2621 2622 2623
 *                                                                           *
\*****************************************************************************/

2624 2625
struct sdhci_host *sdhci_alloc_host(struct device *dev,
	size_t priv_size)
2626 2627 2628 2629
{
	struct mmc_host *mmc;
	struct sdhci_host *host;

2630
	WARN_ON(dev == NULL);
2631

2632
	mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2633
	if (!mmc)
2634
		return ERR_PTR(-ENOMEM);
2635 2636 2637 2638

	host = mmc_priv(mmc);
	host->mmc = mmc;

2639 2640
	return host;
}
2641

2642
EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2643

2644 2645 2646
int sdhci_add_host(struct sdhci_host *host)
{
	struct mmc_host *mmc;
2647
	u32 caps[2] = {0, 0};
2648 2649
	u32 max_current_caps;
	unsigned int ocr_avail;
2650
	int ret;
2651

2652 2653 2654
	WARN_ON(host == NULL);
	if (host == NULL)
		return -EINVAL;
2655

2656
	mmc = host->mmc;
2657

2658 2659
	if (debug_quirks)
		host->quirks = debug_quirks;
2660 2661
	if (debug_quirks2)
		host->quirks2 = debug_quirks2;
2662

2663 2664
	sdhci_reset(host, SDHCI_RESET_ALL);

2665
	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2666 2667
	host->version = (host->version & SDHCI_SPEC_VER_MASK)
				>> SDHCI_SPEC_VER_SHIFT;
2668
	if (host->version > SDHCI_SPEC_300) {
2669
		pr_err("%s: Unknown controller version (%d). "
2670
			"You may experience problems.\n", mmc_hostname(mmc),
2671
			host->version);
2672 2673
	}

2674
	caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2675
		sdhci_readl(host, SDHCI_CAPABILITIES);
2676

2677 2678 2679 2680
	if (host->version >= SDHCI_SPEC_300)
		caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
			host->caps1 :
			sdhci_readl(host, SDHCI_CAPABILITIES_1);
2681

2682
	if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2683
		host->flags |= SDHCI_USE_SDMA;
2684
	else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2685
		DBG("Controller doesn't have SDMA capability\n");
2686
	else
2687
		host->flags |= SDHCI_USE_SDMA;
2688

2689
	if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2690
		(host->flags & SDHCI_USE_SDMA)) {
R
Rolf Eike Beer 已提交
2691
		DBG("Disabling DMA as it is marked broken\n");
2692
		host->flags &= ~SDHCI_USE_SDMA;
2693 2694
	}

2695 2696
	if ((host->version >= SDHCI_SPEC_200) &&
		(caps[0] & SDHCI_CAN_DO_ADMA2))
2697
		host->flags |= SDHCI_USE_ADMA;
2698 2699 2700 2701 2702 2703 2704

	if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
		(host->flags & SDHCI_USE_ADMA)) {
		DBG("Disabling ADMA as it is marked broken\n");
		host->flags &= ~SDHCI_USE_ADMA;
	}

2705
	if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2706 2707
		if (host->ops->enable_dma) {
			if (host->ops->enable_dma(host)) {
2708
				pr_warning("%s: No suitable DMA "
2709 2710
					"available. Falling back to PIO.\n",
					mmc_hostname(mmc));
2711 2712
				host->flags &=
					~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2713
			}
2714 2715 2716
		}
	}

2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727
	if (host->flags & SDHCI_USE_ADMA) {
		/*
		 * We need to allocate descriptors for all sg entries
		 * (128) and potentially one alignment transfer for
		 * each of those entries.
		 */
		host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
		host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
		if (!host->adma_desc || !host->align_buffer) {
			kfree(host->adma_desc);
			kfree(host->align_buffer);
2728
			pr_warning("%s: Unable to allocate ADMA "
2729 2730 2731 2732 2733 2734
				"buffers. Falling back to standard DMA.\n",
				mmc_hostname(mmc));
			host->flags &= ~SDHCI_USE_ADMA;
		}
	}

2735 2736 2737 2738 2739
	/*
	 * If we use DMA, then it's up to the caller to set the DMA
	 * mask, but PIO does not need the hw shim so we set a new
	 * mask here in that case.
	 */
2740
	if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2741 2742 2743
		host->dma_mask = DMA_BIT_MASK(64);
		mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
	}
2744

2745
	if (host->version >= SDHCI_SPEC_300)
2746
		host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2747 2748
			>> SDHCI_CLOCK_BASE_SHIFT;
	else
2749
		host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2750 2751
			>> SDHCI_CLOCK_BASE_SHIFT;

2752
	host->max_clk *= 1000000;
2753 2754
	if (host->max_clk == 0 || host->quirks &
			SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2755
		if (!host->ops->get_max_clock) {
2756
			pr_err("%s: Hardware doesn't specify base clock "
2757 2758 2759 2760
			       "frequency.\n", mmc_hostname(mmc));
			return -ENODEV;
		}
		host->max_clk = host->ops->get_max_clock(host);
2761
	}
2762

2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778
	/*
	 * In case of Host Controller v3.00, find out whether clock
	 * multiplier is supported.
	 */
	host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
			SDHCI_CLOCK_MUL_SHIFT;

	/*
	 * In case the value in Clock Multiplier is 0, then programmable
	 * clock mode is not supported, otherwise the actual clock
	 * multiplier is one more than the value of Clock Multiplier
	 * in the Capabilities Register.
	 */
	if (host->clk_mul)
		host->clk_mul += 1;

2779 2780 2781 2782
	/*
	 * Set host parameters.
	 */
	mmc->ops = &sdhci_ops;
2783
	mmc->f_max = host->max_clk;
2784
	if (host->ops->get_min_clock)
2785
		mmc->f_min = host->ops->get_min_clock(host);
2786 2787 2788 2789 2790 2791 2792
	else if (host->version >= SDHCI_SPEC_300) {
		if (host->clk_mul) {
			mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
			mmc->f_max = host->max_clk * host->clk_mul;
		} else
			mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
	} else
2793
		mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2794

2795 2796 2797 2798 2799 2800 2801
	host->timeout_clk =
		(caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
	if (host->timeout_clk == 0) {
		if (host->ops->get_timeout_clock) {
			host->timeout_clk = host->ops->get_timeout_clock(host);
		} else if (!(host->quirks &
				SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2802
			pr_err("%s: Hardware doesn't specify timeout clock "
2803 2804 2805 2806 2807 2808 2809 2810
			       "frequency.\n", mmc_hostname(mmc));
			return -ENODEV;
		}
	}
	if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
		host->timeout_clk *= 1000;

	if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2811
		host->timeout_clk = mmc->f_max / 1000;
2812

2813
	mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2814

2815 2816 2817 2818
	mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;

	if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
		host->flags |= SDHCI_AUTO_CMD12;
2819

2820
	/* Auto-CMD23 stuff only works in ADMA or PIO. */
A
Andrei Warkentin 已提交
2821
	if ((host->version >= SDHCI_SPEC_300) &&
2822
	    ((host->flags & SDHCI_USE_ADMA) ||
A
Andrei Warkentin 已提交
2823
	     !(host->flags & SDHCI_USE_SDMA))) {
2824 2825 2826 2827 2828 2829
		host->flags |= SDHCI_AUTO_CMD23;
		DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
	} else {
		DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
	}

2830 2831 2832 2833 2834 2835 2836
	/*
	 * A controller may support 8-bit width, but the board itself
	 * might not have the pins brought out.  Boards that support
	 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
	 * their platform code before calling sdhci_add_host(), and we
	 * won't assume 8-bit width for hosts without that CAP.
	 */
2837
	if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2838
		mmc->caps |= MMC_CAP_4_BIT_DATA;
2839

2840 2841 2842
	if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
		mmc->caps &= ~MMC_CAP_CMD23;

2843
	if (caps[0] & SDHCI_CAN_DO_HISPD)
2844
		mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2845

2846
	if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2847
	    !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
2848 2849
		mmc->caps |= MMC_CAP_NEEDS_POLL;

2850 2851
	/* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
	host->vqmmc = regulator_get(mmc_dev(mmc), "vqmmc");
2852 2853 2854 2855 2856 2857
	if (IS_ERR_OR_NULL(host->vqmmc)) {
		if (PTR_ERR(host->vqmmc) < 0) {
			pr_info("%s: no vqmmc regulator found\n",
				mmc_hostname(mmc));
			host->vqmmc = NULL;
		}
2858 2859 2860 2861 2862 2863 2864
	}
	else if (regulator_is_supported_voltage(host->vqmmc, 1800000, 1800000))
		regulator_enable(host->vqmmc);
	else
		caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
		       SDHCI_SUPPORT_DDR50);

2865 2866 2867
	/* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
	if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
		       SDHCI_SUPPORT_DDR50))
2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878
		mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;

	/* SDR104 supports also implies SDR50 support */
	if (caps[1] & SDHCI_SUPPORT_SDR104)
		mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
	else if (caps[1] & SDHCI_SUPPORT_SDR50)
		mmc->caps |= MMC_CAP_UHS_SDR50;

	if (caps[1] & SDHCI_SUPPORT_DDR50)
		mmc->caps |= MMC_CAP_UHS_DDR50;

2879
	/* Does the host need tuning for SDR50? */
2880 2881 2882
	if (caps[1] & SDHCI_USE_SDR50_TUNING)
		host->flags |= SDHCI_SDR50_NEEDS_TUNING;

2883 2884 2885 2886
	/* Does the host need tuning for HS200? */
	if (mmc->caps2 & MMC_CAP2_HS200)
		host->flags |= SDHCI_HS200_NEEDS_TUNING;

2887 2888 2889 2890 2891 2892 2893 2894
	/* Driver Type(s) (A, C, D) supported by the host */
	if (caps[1] & SDHCI_DRIVER_TYPE_A)
		mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
	if (caps[1] & SDHCI_DRIVER_TYPE_C)
		mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
	if (caps[1] & SDHCI_DRIVER_TYPE_D)
		mmc->caps |= MMC_CAP_DRIVER_TYPE_D;

2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909
	/* Initial value for re-tuning timer count */
	host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
			      SDHCI_RETUNING_TIMER_COUNT_SHIFT;

	/*
	 * In case Re-tuning Timer is not disabled, the actual value of
	 * re-tuning timer will be 2 ^ (n - 1).
	 */
	if (host->tuning_count)
		host->tuning_count = 1 << (host->tuning_count - 1);

	/* Re-tuning mode supported by the Host Controller */
	host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
			     SDHCI_RETUNING_MODE_SHIFT;

2910
	ocr_avail = 0;
2911 2912

	host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2913 2914 2915 2916 2917 2918
	if (IS_ERR_OR_NULL(host->vmmc)) {
		if (PTR_ERR(host->vmmc) < 0) {
			pr_info("%s: no vmmc regulator found\n",
				mmc_hostname(mmc));
			host->vmmc = NULL;
		}
2919 2920
	} else
		regulator_enable(host->vmmc);
2921

2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938
#ifdef CONFIG_REGULATOR
	if (host->vmmc) {
		ret = regulator_is_supported_voltage(host->vmmc, 3300000,
			3300000);
		if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
			caps[0] &= ~SDHCI_CAN_VDD_330;
		ret = regulator_is_supported_voltage(host->vmmc, 3000000,
			3000000);
		if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
			caps[0] &= ~SDHCI_CAN_VDD_300;
		ret = regulator_is_supported_voltage(host->vmmc, 1800000,
			1800000);
		if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
			caps[0] &= ~SDHCI_CAN_VDD_180;
	}
#endif /* CONFIG_REGULATOR */

2939 2940 2941 2942 2943 2944 2945 2946
	/*
	 * According to SD Host Controller spec v3.00, if the Host System
	 * can afford more than 150mA, Host Driver should set XPC to 1. Also
	 * the value is meaningful only if Voltage Support in the Capabilities
	 * register is set. The actual current value is 4 times the register
	 * value.
	 */
	max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961
	if (!max_current_caps && host->vmmc) {
		u32 curr = regulator_get_current_limit(host->vmmc);
		if (curr > 0) {

			/* convert to SDHCI_MAX_CURRENT format */
			curr = curr/1000;  /* convert to mA */
			curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;

			curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
			max_current_caps =
				(curr << SDHCI_MAX_CURRENT_330_SHIFT) |
				(curr << SDHCI_MAX_CURRENT_300_SHIFT) |
				(curr << SDHCI_MAX_CURRENT_180_SHIFT);
		}
	}
2962 2963

	if (caps[0] & SDHCI_CAN_VDD_330) {
2964
		ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2965

A
Aaron Lu 已提交
2966
		mmc->max_current_330 = ((max_current_caps &
2967 2968 2969 2970 2971
				   SDHCI_MAX_CURRENT_330_MASK) >>
				   SDHCI_MAX_CURRENT_330_SHIFT) *
				   SDHCI_MAX_CURRENT_MULTIPLIER;
	}
	if (caps[0] & SDHCI_CAN_VDD_300) {
2972
		ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2973

A
Aaron Lu 已提交
2974
		mmc->max_current_300 = ((max_current_caps &
2975 2976 2977 2978 2979
				   SDHCI_MAX_CURRENT_300_MASK) >>
				   SDHCI_MAX_CURRENT_300_SHIFT) *
				   SDHCI_MAX_CURRENT_MULTIPLIER;
	}
	if (caps[0] & SDHCI_CAN_VDD_180) {
2980 2981
		ocr_avail |= MMC_VDD_165_195;

A
Aaron Lu 已提交
2982
		mmc->max_current_180 = ((max_current_caps &
2983 2984 2985 2986 2987
				   SDHCI_MAX_CURRENT_180_MASK) >>
				   SDHCI_MAX_CURRENT_180_SHIFT) *
				   SDHCI_MAX_CURRENT_MULTIPLIER;
	}

2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999
	mmc->ocr_avail = ocr_avail;
	mmc->ocr_avail_sdio = ocr_avail;
	if (host->ocr_avail_sdio)
		mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
	mmc->ocr_avail_sd = ocr_avail;
	if (host->ocr_avail_sd)
		mmc->ocr_avail_sd &= host->ocr_avail_sd;
	else /* normal SD controllers don't support 1.8V */
		mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
	mmc->ocr_avail_mmc = ocr_avail;
	if (host->ocr_avail_mmc)
		mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3000 3001

	if (mmc->ocr_avail == 0) {
3002
		pr_err("%s: Hardware doesn't report any "
3003
			"support voltages.\n", mmc_hostname(mmc));
3004
		return -ENODEV;
3005 3006
	}

3007 3008 3009
	spin_lock_init(&host->lock);

	/*
3010 3011
	 * Maximum number of segments. Depends on if the hardware
	 * can do scatter/gather or not.
3012
	 */
3013
	if (host->flags & SDHCI_USE_ADMA)
3014
		mmc->max_segs = 128;
3015
	else if (host->flags & SDHCI_USE_SDMA)
3016
		mmc->max_segs = 1;
3017
	else /* PIO */
3018
		mmc->max_segs = 128;
3019 3020

	/*
3021
	 * Maximum number of sectors in one transfer. Limited by DMA boundary
3022
	 * size (512KiB).
3023
	 */
3024
	mmc->max_req_size = 524288;
3025 3026 3027

	/*
	 * Maximum segment size. Could be one segment with the maximum number
3028 3029
	 * of bytes. When doing hardware scatter/gather, each entry cannot
	 * be larger than 64 KiB though.
3030
	 */
3031 3032 3033 3034 3035 3036
	if (host->flags & SDHCI_USE_ADMA) {
		if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
			mmc->max_seg_size = 65535;
		else
			mmc->max_seg_size = 65536;
	} else {
3037
		mmc->max_seg_size = mmc->max_req_size;
3038
	}
3039

3040 3041 3042 3043
	/*
	 * Maximum block size. This varies from controller to controller and
	 * is specified in the capabilities register.
	 */
3044 3045 3046
	if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
		mmc->max_blk_size = 2;
	} else {
3047
		mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3048 3049
				SDHCI_MAX_BLOCK_SHIFT;
		if (mmc->max_blk_size >= 3) {
3050
			pr_warning("%s: Invalid maximum block size, "
3051 3052 3053 3054 3055 3056
				"assuming 512 bytes\n", mmc_hostname(mmc));
			mmc->max_blk_size = 0;
		}
	}

	mmc->max_blk_size = 512 << mmc->max_blk_size;
3057

3058 3059 3060
	/*
	 * Maximum block count.
	 */
3061
	mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3062

3063 3064 3065 3066 3067 3068 3069 3070
	/*
	 * Init tasklets.
	 */
	tasklet_init(&host->card_tasklet,
		sdhci_tasklet_card, (unsigned long)host);
	tasklet_init(&host->finish_tasklet,
		sdhci_tasklet_finish, (unsigned long)host);

3071
	setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3072

3073
	if (host->version >= SDHCI_SPEC_300) {
3074 3075
		init_waitqueue_head(&host->buf_ready_int);

3076 3077 3078 3079 3080 3081
		/* Initialize re-tuning timer */
		init_timer(&host->tuning_timer);
		host->tuning_timer.data = (unsigned long)host;
		host->tuning_timer.function = sdhci_tuning_timer;
	}

3082
	ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
3083
		mmc_hostname(mmc), host);
3084 3085 3086
	if (ret) {
		pr_err("%s: Failed to request IRQ %d: %d\n",
		       mmc_hostname(mmc), host->irq, ret);
3087
		goto untasklet;
3088
	}
3089

3090
	sdhci_init(host, 0);
3091 3092 3093 3094 3095

#ifdef CONFIG_MMC_DEBUG
	sdhci_dumpregs(host);
#endif

3096
#ifdef SDHCI_USE_LEDS_CLASS
H
Helmut Schaa 已提交
3097 3098 3099
	snprintf(host->led_name, sizeof(host->led_name),
		"%s::", mmc_hostname(mmc));
	host->led.name = host->led_name;
3100 3101 3102 3103
	host->led.brightness = LED_OFF;
	host->led.default_trigger = mmc_hostname(mmc);
	host->led.brightness_set = sdhci_led_control;

3104
	ret = led_classdev_register(mmc_dev(mmc), &host->led);
3105 3106 3107
	if (ret) {
		pr_err("%s: Failed to register LED device: %d\n",
		       mmc_hostname(mmc), ret);
3108
		goto reset;
3109
	}
3110 3111
#endif

3112 3113
	mmiowb();

3114 3115
	mmc_add_host(mmc);

3116
	pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3117
		mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3118 3119
		(host->flags & SDHCI_USE_ADMA) ? "ADMA" :
		(host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3120

3121 3122
	sdhci_enable_card_detection(host);

3123 3124
	return 0;

3125
#ifdef SDHCI_USE_LEDS_CLASS
3126 3127 3128 3129
reset:
	sdhci_reset(host, SDHCI_RESET_ALL);
	free_irq(host->irq, host);
#endif
3130
untasklet:
3131 3132 3133 3134 3135 3136
	tasklet_kill(&host->card_tasklet);
	tasklet_kill(&host->finish_tasklet);

	return ret;
}

3137
EXPORT_SYMBOL_GPL(sdhci_add_host);
3138

P
Pierre Ossman 已提交
3139
void sdhci_remove_host(struct sdhci_host *host, int dead)
3140
{
P
Pierre Ossman 已提交
3141 3142 3143 3144 3145 3146 3147 3148
	unsigned long flags;

	if (dead) {
		spin_lock_irqsave(&host->lock, flags);

		host->flags |= SDHCI_DEVICE_DEAD;

		if (host->mrq) {
3149
			pr_err("%s: Controller removed during "
P
Pierre Ossman 已提交
3150 3151 3152 3153 3154 3155 3156 3157 3158
				" transfer!\n", mmc_hostname(host->mmc));

			host->mrq->cmd->error = -ENOMEDIUM;
			tasklet_schedule(&host->finish_tasklet);
		}

		spin_unlock_irqrestore(&host->lock, flags);
	}

3159 3160
	sdhci_disable_card_detection(host);

3161
	mmc_remove_host(host->mmc);
3162

3163
#ifdef SDHCI_USE_LEDS_CLASS
3164 3165 3166
	led_classdev_unregister(&host->led);
#endif

P
Pierre Ossman 已提交
3167 3168
	if (!dead)
		sdhci_reset(host, SDHCI_RESET_ALL);
3169 3170 3171 3172 3173 3174 3175

	free_irq(host->irq, host);

	del_timer_sync(&host->timer);

	tasklet_kill(&host->card_tasklet);
	tasklet_kill(&host->finish_tasklet);
3176

3177 3178
	if (host->vmmc) {
		regulator_disable(host->vmmc);
M
Marek Szyprowski 已提交
3179
		regulator_put(host->vmmc);
3180
	}
M
Marek Szyprowski 已提交
3181

3182 3183 3184 3185 3186
	if (host->vqmmc) {
		regulator_disable(host->vqmmc);
		regulator_put(host->vqmmc);
	}

3187 3188 3189 3190 3191
	kfree(host->adma_desc);
	kfree(host->align_buffer);

	host->adma_desc = NULL;
	host->align_buffer = NULL;
3192 3193
}

3194
EXPORT_SYMBOL_GPL(sdhci_remove_host);
3195

3196
void sdhci_free_host(struct sdhci_host *host)
3197
{
3198
	mmc_free_host(host->mmc);
3199 3200
}

3201
EXPORT_SYMBOL_GPL(sdhci_free_host);
3202 3203 3204 3205 3206 3207 3208 3209 3210

/*****************************************************************************\
 *                                                                           *
 * Driver init/exit                                                          *
 *                                                                           *
\*****************************************************************************/

static int __init sdhci_drv_init(void)
{
3211
	pr_info(DRIVER_NAME
3212
		": Secure Digital Host Controller Interface driver\n");
3213
	pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3214

3215
	return 0;
3216 3217 3218 3219 3220 3221 3222 3223 3224
}

static void __exit sdhci_drv_exit(void)
{
}

module_init(sdhci_drv_init);
module_exit(sdhci_drv_exit);

3225
module_param(debug_quirks, uint, 0444);
3226
module_param(debug_quirks2, uint, 0444);
3227

3228
MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3229
MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3230
MODULE_LICENSE("GPL");
3231

3232
MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3233
MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");