sdhci.c 73.2 KB
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/*
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Pierre Ossman 已提交
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 *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
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 *
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 *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
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 *
 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
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 *
 * Thanks to the following companies for their support:
 *
 *     - JMicron (hardware and technical support)
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 */

#include <linux/delay.h>
#include <linux/highmem.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/scatterlist.h>
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#include <linux/regulator/consumer.h>
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#include <linux/leds.h>

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#include <linux/mmc/mmc.h>
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#include <linux/mmc/host.h>

#include "sdhci.h"

#define DRIVER_NAME "sdhci"

#define DBG(f, x...) \
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	pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
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#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
	defined(CONFIG_MMC_SDHCI_MODULE))
#define SDHCI_USE_LEDS_CLASS
#endif

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#define MAX_TUNING_LOOP 40

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static unsigned int debug_quirks = 0;
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static void sdhci_finish_data(struct sdhci_host *);

static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
static void sdhci_finish_command(struct sdhci_host *);
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static int sdhci_execute_tuning(struct mmc_host *mmc);
static void sdhci_tuning_timer(unsigned long data);
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static void sdhci_dumpregs(struct sdhci_host *host)
{
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	printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
		mmc_hostname(host->mmc));
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	printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
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		sdhci_readl(host, SDHCI_DMA_ADDRESS),
		sdhci_readw(host, SDHCI_HOST_VERSION));
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	printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
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		sdhci_readw(host, SDHCI_BLOCK_SIZE),
		sdhci_readw(host, SDHCI_BLOCK_COUNT));
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	printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
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		sdhci_readl(host, SDHCI_ARGUMENT),
		sdhci_readw(host, SDHCI_TRANSFER_MODE));
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	printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
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		sdhci_readl(host, SDHCI_PRESENT_STATE),
		sdhci_readb(host, SDHCI_HOST_CONTROL));
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	printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
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		sdhci_readb(host, SDHCI_POWER_CONTROL),
		sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
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	printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
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		sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
		sdhci_readw(host, SDHCI_CLOCK_CONTROL));
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	printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
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		sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
		sdhci_readl(host, SDHCI_INT_STATUS));
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	printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
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		sdhci_readl(host, SDHCI_INT_ENABLE),
		sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
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	printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
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		sdhci_readw(host, SDHCI_ACMD12_ERR),
		sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
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	printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
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		sdhci_readl(host, SDHCI_CAPABILITIES),
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		sdhci_readl(host, SDHCI_CAPABILITIES_1));
	printk(KERN_DEBUG DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
		sdhci_readw(host, SDHCI_COMMAND),
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		sdhci_readl(host, SDHCI_MAX_CURRENT));
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	printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n",
		sdhci_readw(host, SDHCI_HOST_CONTROL2));
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	if (host->flags & SDHCI_USE_ADMA)
		printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
		       readl(host->ioaddr + SDHCI_ADMA_ERROR),
		       readl(host->ioaddr + SDHCI_ADMA_ADDRESS));

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	printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
}

/*****************************************************************************\
 *                                                                           *
 * Low level functions                                                       *
 *                                                                           *
\*****************************************************************************/

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static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
{
	u32 ier;

	ier = sdhci_readl(host, SDHCI_INT_ENABLE);
	ier &= ~clear;
	ier |= set;
	sdhci_writel(host, ier, SDHCI_INT_ENABLE);
	sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
}

static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
{
	sdhci_clear_set_irqs(host, 0, irqs);
}

static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
{
	sdhci_clear_set_irqs(host, irqs, 0);
}

static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
{
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	u32 present, irqs;
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	if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
		return;

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	present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
			      SDHCI_CARD_PRESENT;
	irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;

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	if (enable)
		sdhci_unmask_irqs(host, irqs);
	else
		sdhci_mask_irqs(host, irqs);
}

static void sdhci_enable_card_detection(struct sdhci_host *host)
{
	sdhci_set_card_detection(host, true);
}

static void sdhci_disable_card_detection(struct sdhci_host *host)
{
	sdhci_set_card_detection(host, false);
}

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static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
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	unsigned long timeout;
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	u32 uninitialized_var(ier);
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160
	if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
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		if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
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			SDHCI_CARD_PRESENT))
			return;
	}

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	if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
		ier = sdhci_readl(host, SDHCI_INT_ENABLE);

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	if (host->ops->platform_reset_enter)
		host->ops->platform_reset_enter(host, mask);

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	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
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	if (mask & SDHCI_RESET_ALL)
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		host->clock = 0;

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	/* Wait max 100 ms */
	timeout = 100;

	/* hw clears the bit when it's done */
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	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
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		if (timeout == 0) {
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			printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
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				mmc_hostname(host->mmc), (int)mask);
			sdhci_dumpregs(host);
			return;
		}
		timeout--;
		mdelay(1);
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	}
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	if (host->ops->platform_reset_exit)
		host->ops->platform_reset_exit(host, mask);

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	if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
		sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
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}

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static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);

static void sdhci_init(struct sdhci_host *host, int soft)
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{
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	if (soft)
		sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
	else
		sdhci_reset(host, SDHCI_RESET_ALL);
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	sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
		SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
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		SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
		SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
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		SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
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	if (soft) {
		/* force clock reconfiguration */
		host->clock = 0;
		sdhci_set_ios(host->mmc, &host->mmc->ios);
	}
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}
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static void sdhci_reinit(struct sdhci_host *host)
{
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	sdhci_init(host, 0);
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	sdhci_enable_card_detection(host);
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}

static void sdhci_activate_led(struct sdhci_host *host)
{
	u8 ctrl;

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	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
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	ctrl |= SDHCI_CTRL_LED;
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	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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}

static void sdhci_deactivate_led(struct sdhci_host *host)
{
	u8 ctrl;

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	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
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	ctrl &= ~SDHCI_CTRL_LED;
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	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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}

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#ifdef SDHCI_USE_LEDS_CLASS
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static void sdhci_led_control(struct led_classdev *led,
	enum led_brightness brightness)
{
	struct sdhci_host *host = container_of(led, struct sdhci_host, led);
	unsigned long flags;

	spin_lock_irqsave(&host->lock, flags);

	if (brightness == LED_OFF)
		sdhci_deactivate_led(host);
	else
		sdhci_activate_led(host);

	spin_unlock_irqrestore(&host->lock, flags);
}
#endif

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/*****************************************************************************\
 *                                                                           *
 * Core functions                                                            *
 *                                                                           *
\*****************************************************************************/

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static void sdhci_read_block_pio(struct sdhci_host *host)
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{
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	unsigned long flags;
	size_t blksize, len, chunk;
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	u32 uninitialized_var(scratch);
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	u8 *buf;
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	DBG("PIO reading\n");
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	blksize = host->data->blksz;
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	chunk = 0;
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	local_irq_save(flags);
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	while (blksize) {
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		if (!sg_miter_next(&host->sg_miter))
			BUG();
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		len = min(host->sg_miter.length, blksize);
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		blksize -= len;
		host->sg_miter.consumed = len;
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292
		buf = host->sg_miter.addr;
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		while (len) {
			if (chunk == 0) {
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				scratch = sdhci_readl(host, SDHCI_BUFFER);
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				chunk = 4;
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			}
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			*buf = scratch & 0xFF;

			buf++;
			scratch >>= 8;
			chunk--;
			len--;
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		}
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	}
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	sg_miter_stop(&host->sg_miter);

	local_irq_restore(flags);
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}
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static void sdhci_write_block_pio(struct sdhci_host *host)
{
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	unsigned long flags;
	size_t blksize, len, chunk;
	u32 scratch;
	u8 *buf;
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	DBG("PIO writing\n");

	blksize = host->data->blksz;
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	chunk = 0;
	scratch = 0;
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	local_irq_save(flags);
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	while (blksize) {
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		if (!sg_miter_next(&host->sg_miter))
			BUG();
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		len = min(host->sg_miter.length, blksize);

		blksize -= len;
		host->sg_miter.consumed = len;

		buf = host->sg_miter.addr;
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		while (len) {
			scratch |= (u32)*buf << (chunk * 8);

			buf++;
			chunk++;
			len--;

			if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
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				sdhci_writel(host, scratch, SDHCI_BUFFER);
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				chunk = 0;
				scratch = 0;
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			}
		}
	}
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	sg_miter_stop(&host->sg_miter);

	local_irq_restore(flags);
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}

static void sdhci_transfer_pio(struct sdhci_host *host)
{
	u32 mask;

	BUG_ON(!host->data);

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	if (host->blocks == 0)
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		return;

	if (host->data->flags & MMC_DATA_READ)
		mask = SDHCI_DATA_AVAILABLE;
	else
		mask = SDHCI_SPACE_AVAILABLE;

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	/*
	 * Some controllers (JMicron JMB38x) mess up the buffer bits
	 * for transfers < 4 bytes. As long as it is just one block,
	 * we can ignore the bits.
	 */
	if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
		(host->data->blocks == 1))
		mask = ~0;

383
	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
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		if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
			udelay(100);

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		if (host->data->flags & MMC_DATA_READ)
			sdhci_read_block_pio(host);
		else
			sdhci_write_block_pio(host);
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		host->blocks--;
		if (host->blocks == 0)
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			break;
	}
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	DBG("PIO transfer complete.\n");
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}

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static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
{
	local_irq_save(*flags);
	return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
}

static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
{
	kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
	local_irq_restore(*flags);
}

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static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
{
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	__le32 *dataddr = (__le32 __force *)(desc + 4);
	__le16 *cmdlen = (__le16 __force *)desc;
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	/* SDHCI specification says ADMA descriptors should be 4 byte
	 * aligned, so using 16 or 32bit operations should be safe. */
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	cmdlen[0] = cpu_to_le16(cmd);
	cmdlen[1] = cpu_to_le16(len);

	dataddr[0] = cpu_to_le32(addr);
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}

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static int sdhci_adma_table_pre(struct sdhci_host *host,
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	struct mmc_data *data)
{
	int direction;

	u8 *desc;
	u8 *align;
	dma_addr_t addr;
	dma_addr_t align_addr;
	int len, offset;

	struct scatterlist *sg;
	int i;
	char *buffer;
	unsigned long flags;

	/*
	 * The spec does not specify endianness of descriptor table.
	 * We currently guess that it is LE.
	 */

	if (data->flags & MMC_DATA_READ)
		direction = DMA_FROM_DEVICE;
	else
		direction = DMA_TO_DEVICE;

	/*
	 * The ADMA descriptor table is mapped further down as we
	 * need to fill it with data first.
	 */

	host->align_addr = dma_map_single(mmc_dev(host->mmc),
		host->align_buffer, 128 * 4, direction);
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	if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
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		goto fail;
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	BUG_ON(host->align_addr & 0x3);

	host->sg_count = dma_map_sg(mmc_dev(host->mmc),
		data->sg, data->sg_len, direction);
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	if (host->sg_count == 0)
		goto unmap_align;
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	desc = host->adma_desc;
	align = host->align_buffer;

	align_addr = host->align_addr;

	for_each_sg(data->sg, sg, host->sg_count, i) {
		addr = sg_dma_address(sg);
		len = sg_dma_len(sg);

		/*
		 * The SDHCI specification states that ADMA
		 * addresses must be 32-bit aligned. If they
		 * aren't, then we use a bounce buffer for
		 * the (up to three) bytes that screw up the
		 * alignment.
		 */
		offset = (4 - (addr & 0x3)) & 0x3;
		if (offset) {
			if (data->flags & MMC_DATA_WRITE) {
				buffer = sdhci_kmap_atomic(sg, &flags);
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				WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
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				memcpy(align, buffer, offset);
				sdhci_kunmap_atomic(buffer, &flags);
			}

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			/* tran, valid */
			sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
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			BUG_ON(offset > 65536);

			align += 4;
			align_addr += 4;

			desc += 8;

			addr += offset;
			len -= offset;
		}

		BUG_ON(len > 65536);

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		/* tran, valid */
		sdhci_set_adma_desc(desc, addr, len, 0x21);
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		desc += 8;

		/*
		 * If this triggers then we have a calculation bug
		 * somewhere. :/
		 */
		WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
	}

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	if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
		/*
		* Mark the last descriptor as the terminating descriptor
		*/
		if (desc != host->adma_desc) {
			desc -= 8;
			desc[0] |= 0x2; /* end */
		}
	} else {
		/*
		* Add a terminating entry.
		*/
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		/* nop, end, valid */
		sdhci_set_adma_desc(desc, 0, 0, 0x3);
	}
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	/*
	 * Resync align buffer as we might have changed it.
	 */
	if (data->flags & MMC_DATA_WRITE) {
		dma_sync_single_for_device(mmc_dev(host->mmc),
			host->align_addr, 128 * 4, direction);
	}

	host->adma_addr = dma_map_single(mmc_dev(host->mmc),
		host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
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	if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
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		goto unmap_entries;
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	BUG_ON(host->adma_addr & 0x3);
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	return 0;

unmap_entries:
	dma_unmap_sg(mmc_dev(host->mmc), data->sg,
		data->sg_len, direction);
unmap_align:
	dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
		128 * 4, direction);
fail:
	return -EINVAL;
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}

static void sdhci_adma_table_post(struct sdhci_host *host,
	struct mmc_data *data)
{
	int direction;

	struct scatterlist *sg;
	int i, size;
	u8 *align;
	char *buffer;
	unsigned long flags;

	if (data->flags & MMC_DATA_READ)
		direction = DMA_FROM_DEVICE;
	else
		direction = DMA_TO_DEVICE;

	dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
		(128 * 2 + 1) * 4, DMA_TO_DEVICE);

	dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
		128 * 4, direction);

	if (data->flags & MMC_DATA_READ) {
		dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
			data->sg_len, direction);

		align = host->align_buffer;

		for_each_sg(data->sg, sg, host->sg_count, i) {
			if (sg_dma_address(sg) & 0x3) {
				size = 4 - (sg_dma_address(sg) & 0x3);

				buffer = sdhci_kmap_atomic(sg, &flags);
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				WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
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				memcpy(buffer, align, size);
				sdhci_kunmap_atomic(buffer, &flags);

				align += 4;
			}
		}
	}

	dma_unmap_sg(mmc_dev(host->mmc), data->sg,
		data->sg_len, direction);
}

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static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
610
{
611
	u8 count;
612
	struct mmc_data *data = cmd->data;
613
	unsigned target_timeout, current_timeout;
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	/*
	 * If the host controller provides us with an incorrect timeout
	 * value, just skip the check and use 0xE.  The hardware may take
	 * longer to time out, but that's much better than having a too-short
	 * timeout value.
	 */
621
	if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
622
		return 0xE;
623

624 625 626
	/* Unspecified timeout, assume max */
	if (!data && !cmd->cmd_timeout_ms)
		return 0xE;
627

628 629 630
	/* timeout in us */
	if (!data)
		target_timeout = cmd->cmd_timeout_ms * 1000;
631 632 633 634 635
	else {
		target_timeout = data->timeout_ns / 1000;
		if (host->clock)
			target_timeout += data->timeout_clks / host->clock;
	}
636

637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656
	/*
	 * Figure out needed cycles.
	 * We do this in steps in order to fit inside a 32 bit int.
	 * The first step is the minimum timeout, which will have a
	 * minimum resolution of 6 bits:
	 * (1) 2^13*1000 > 2^22,
	 * (2) host->timeout_clk < 2^16
	 *     =>
	 *     (1) / (2) > 2^6
	 */
	count = 0;
	current_timeout = (1 << 13) * 1000 / host->timeout_clk;
	while (current_timeout < target_timeout) {
		count++;
		current_timeout <<= 1;
		if (count >= 0xF)
			break;
	}

	if (count >= 0xF) {
657 658
		printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
		       mmc_hostname(host->mmc), cmd->opcode);
659 660 661
		count = 0xE;
	}

662 663 664
	return count;
}

665 666 667 668 669 670 671 672 673 674 675
static void sdhci_set_transfer_irqs(struct sdhci_host *host)
{
	u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
	u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;

	if (host->flags & SDHCI_REQ_USE_DMA)
		sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
	else
		sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
}

676
static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
677 678
{
	u8 count;
679
	u8 ctrl;
680
	struct mmc_data *data = cmd->data;
681
	int ret;
682 683 684

	WARN_ON(host->data);

685 686 687 688 689 690
	if (data || (cmd->flags & MMC_RSP_BUSY)) {
		count = sdhci_calc_timeout(host, cmd);
		sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
	}

	if (!data)
691 692 693 694 695 696 697 698 699
		return;

	/* Sanity checks */
	BUG_ON(data->blksz * data->blocks > 524288);
	BUG_ON(data->blksz > host->mmc->max_blk_size);
	BUG_ON(data->blocks > 65535);

	host->data = data;
	host->data_early = 0;
700
	host->data->bytes_xfered = 0;
701

702
	if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
703 704
		host->flags |= SDHCI_REQ_USE_DMA;

705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732
	/*
	 * FIXME: This doesn't account for merging when mapping the
	 * scatterlist.
	 */
	if (host->flags & SDHCI_REQ_USE_DMA) {
		int broken, i;
		struct scatterlist *sg;

		broken = 0;
		if (host->flags & SDHCI_USE_ADMA) {
			if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
				broken = 1;
		} else {
			if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
				broken = 1;
		}

		if (unlikely(broken)) {
			for_each_sg(data->sg, sg, data->sg_len, i) {
				if (sg->length & 0x3) {
					DBG("Reverting to PIO because of "
						"transfer size (%d)\n",
						sg->length);
					host->flags &= ~SDHCI_REQ_USE_DMA;
					break;
				}
			}
		}
733 734 735 736 737 738
	}

	/*
	 * The assumption here being that alignment is the same after
	 * translation to device address space.
	 */
739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768
	if (host->flags & SDHCI_REQ_USE_DMA) {
		int broken, i;
		struct scatterlist *sg;

		broken = 0;
		if (host->flags & SDHCI_USE_ADMA) {
			/*
			 * As we use 3 byte chunks to work around
			 * alignment problems, we need to check this
			 * quirk.
			 */
			if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
				broken = 1;
		} else {
			if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
				broken = 1;
		}

		if (unlikely(broken)) {
			for_each_sg(data->sg, sg, data->sg_len, i) {
				if (sg->offset & 0x3) {
					DBG("Reverting to PIO because of "
						"bad alignment\n");
					host->flags &= ~SDHCI_REQ_USE_DMA;
					break;
				}
			}
		}
	}

769 770 771 772 773 774 775 776 777
	if (host->flags & SDHCI_REQ_USE_DMA) {
		if (host->flags & SDHCI_USE_ADMA) {
			ret = sdhci_adma_table_pre(host, data);
			if (ret) {
				/*
				 * This only happens when someone fed
				 * us an invalid request.
				 */
				WARN_ON(1);
778
				host->flags &= ~SDHCI_REQ_USE_DMA;
779
			} else {
780 781
				sdhci_writel(host, host->adma_addr,
					SDHCI_ADMA_ADDRESS);
782 783
			}
		} else {
784
			int sg_cnt;
785

786
			sg_cnt = dma_map_sg(mmc_dev(host->mmc),
787 788 789 790
					data->sg, data->sg_len,
					(data->flags & MMC_DATA_READ) ?
						DMA_FROM_DEVICE :
						DMA_TO_DEVICE);
791
			if (sg_cnt == 0) {
792 793 794 795 796
				/*
				 * This only happens when someone fed
				 * us an invalid request.
				 */
				WARN_ON(1);
797
				host->flags &= ~SDHCI_REQ_USE_DMA;
798
			} else {
799
				WARN_ON(sg_cnt != 1);
800 801
				sdhci_writel(host, sg_dma_address(data->sg),
					SDHCI_DMA_ADDRESS);
802 803 804 805
			}
		}
	}

806 807 808 809 810 811
	/*
	 * Always adjust the DMA selection as some controllers
	 * (e.g. JMicron) can't do PIO properly when the selection
	 * is ADMA.
	 */
	if (host->version >= SDHCI_SPEC_200) {
812
		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
813 814 815 816 817 818
		ctrl &= ~SDHCI_CTRL_DMA_MASK;
		if ((host->flags & SDHCI_REQ_USE_DMA) &&
			(host->flags & SDHCI_USE_ADMA))
			ctrl |= SDHCI_CTRL_ADMA32;
		else
			ctrl |= SDHCI_CTRL_SDMA;
819
		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
820 821
	}

822
	if (!(host->flags & SDHCI_REQ_USE_DMA)) {
823 824 825 826 827 828 829 830
		int flags;

		flags = SG_MITER_ATOMIC;
		if (host->data->flags & MMC_DATA_READ)
			flags |= SG_MITER_TO_SG;
		else
			flags |= SG_MITER_FROM_SG;
		sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
831
		host->blocks = data->blocks;
832
	}
833

834 835
	sdhci_set_transfer_irqs(host);

836 837 838
	/* Set the DMA boundary value and block size */
	sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
		data->blksz), SDHCI_BLOCK_SIZE);
839
	sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
840 841 842
}

static void sdhci_set_transfer_mode(struct sdhci_host *host,
843
	struct mmc_command *cmd)
844 845
{
	u16 mode;
846
	struct mmc_data *data = cmd->data;
847 848 849 850

	if (data == NULL)
		return;

851 852
	WARN_ON(!host->data);

853
	mode = SDHCI_TRNS_BLK_CNT_EN;
854 855 856 857 858 859 860 861
	if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
		mode |= SDHCI_TRNS_MULTI;
		/*
		 * If we are sending CMD23, CMD12 never gets sent
		 * on successful completion (so no Auto-CMD12).
		 */
		if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
			mode |= SDHCI_TRNS_AUTO_CMD12;
862 863 864 865
		else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
			mode |= SDHCI_TRNS_AUTO_CMD23;
			sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
		}
866
	}
867

868 869
	if (data->flags & MMC_DATA_READ)
		mode |= SDHCI_TRNS_READ;
870
	if (host->flags & SDHCI_REQ_USE_DMA)
871 872
		mode |= SDHCI_TRNS_DMA;

873
	sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
874 875 876 877 878 879 880 881 882 883 884
}

static void sdhci_finish_data(struct sdhci_host *host)
{
	struct mmc_data *data;

	BUG_ON(!host->data);

	data = host->data;
	host->data = NULL;

885
	if (host->flags & SDHCI_REQ_USE_DMA) {
886 887 888 889 890 891 892
		if (host->flags & SDHCI_USE_ADMA)
			sdhci_adma_table_post(host, data);
		else {
			dma_unmap_sg(mmc_dev(host->mmc), data->sg,
				data->sg_len, (data->flags & MMC_DATA_READ) ?
					DMA_FROM_DEVICE : DMA_TO_DEVICE);
		}
893 894 895
	}

	/*
896 897 898 899 900
	 * The specification states that the block count register must
	 * be updated, but it does not specify at what point in the
	 * data flow. That makes the register entirely useless to read
	 * back so we have to assume that nothing made it to the card
	 * in the event of an error.
901
	 */
902 903
	if (data->error)
		data->bytes_xfered = 0;
904
	else
905
		data->bytes_xfered = data->blksz * data->blocks;
906

907 908 909 910 911 912 913 914 915
	/*
	 * Need to send CMD12 if -
	 * a) open-ended multiblock transfer (no CMD23)
	 * b) error in multiblock transfer
	 */
	if (data->stop &&
	    (data->error ||
	     !host->mrq->sbc)) {

916 917 918 919
		/*
		 * The controller needs a reset of internal state machines
		 * upon error conditions.
		 */
P
Pierre Ossman 已提交
920
		if (data->error) {
921 922 923 924 925 926 927 928 929 930 931 932
			sdhci_reset(host, SDHCI_RESET_CMD);
			sdhci_reset(host, SDHCI_RESET_DATA);
		}

		sdhci_send_command(host, data->stop);
	} else
		tasklet_schedule(&host->finish_tasklet);
}

static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
{
	int flags;
933
	u32 mask;
934
	unsigned long timeout;
935 936 937 938

	WARN_ON(host->cmd);

	/* Wait max 10 ms */
939
	timeout = 10;
940 941 942 943 944 945 946 947 948 949

	mask = SDHCI_CMD_INHIBIT;
	if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
		mask |= SDHCI_DATA_INHIBIT;

	/* We shouldn't wait for data inihibit for stop commands, even
	   though they might use busy signaling */
	if (host->mrq->data && (cmd == host->mrq->data->stop))
		mask &= ~SDHCI_DATA_INHIBIT;

950
	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
951
		if (timeout == 0) {
952
			printk(KERN_ERR "%s: Controller never released "
P
Pierre Ossman 已提交
953
				"inhibit bit(s).\n", mmc_hostname(host->mmc));
954
			sdhci_dumpregs(host);
P
Pierre Ossman 已提交
955
			cmd->error = -EIO;
956 957 958
			tasklet_schedule(&host->finish_tasklet);
			return;
		}
959 960 961
		timeout--;
		mdelay(1);
	}
962 963 964 965 966

	mod_timer(&host->timer, jiffies + 10 * HZ);

	host->cmd = cmd;

967
	sdhci_prepare_data(host, cmd);
968

969
	sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
970

971
	sdhci_set_transfer_mode(host, cmd);
972

973
	if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
P
Pierre Ossman 已提交
974
		printk(KERN_ERR "%s: Unsupported response type!\n",
975
			mmc_hostname(host->mmc));
P
Pierre Ossman 已提交
976
		cmd->error = -EINVAL;
977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993
		tasklet_schedule(&host->finish_tasklet);
		return;
	}

	if (!(cmd->flags & MMC_RSP_PRESENT))
		flags = SDHCI_CMD_RESP_NONE;
	else if (cmd->flags & MMC_RSP_136)
		flags = SDHCI_CMD_RESP_LONG;
	else if (cmd->flags & MMC_RSP_BUSY)
		flags = SDHCI_CMD_RESP_SHORT_BUSY;
	else
		flags = SDHCI_CMD_RESP_SHORT;

	if (cmd->flags & MMC_RSP_CRC)
		flags |= SDHCI_CMD_CRC;
	if (cmd->flags & MMC_RSP_OPCODE)
		flags |= SDHCI_CMD_INDEX;
994 995 996

	/* CMD19 is special in that the Data Present Select should be set */
	if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
997 998
		flags |= SDHCI_CMD_DATA;

999
	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011
}

static void sdhci_finish_command(struct sdhci_host *host)
{
	int i;

	BUG_ON(host->cmd == NULL);

	if (host->cmd->flags & MMC_RSP_PRESENT) {
		if (host->cmd->flags & MMC_RSP_136) {
			/* CRC is stripped so we need to do some shifting. */
			for (i = 0;i < 4;i++) {
1012
				host->cmd->resp[i] = sdhci_readl(host,
1013 1014 1015
					SDHCI_RESPONSE + (3-i)*4) << 8;
				if (i != 3)
					host->cmd->resp[i] |=
1016
						sdhci_readb(host,
1017 1018 1019
						SDHCI_RESPONSE + (3-i)*4-1);
			}
		} else {
1020
			host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1021 1022 1023
		}
	}

P
Pierre Ossman 已提交
1024
	host->cmd->error = 0;
1025

1026 1027 1028 1029 1030
	/* Finished CMD23, now send actual command. */
	if (host->cmd == host->mrq->sbc) {
		host->cmd = NULL;
		sdhci_send_command(host, host->mrq->cmd);
	} else {
1031

1032 1033 1034
		/* Processed actual command. */
		if (host->data && host->data_early)
			sdhci_finish_data(host);
1035

1036 1037 1038 1039 1040
		if (!host->cmd->data)
			tasklet_schedule(&host->finish_tasklet);

		host->cmd = NULL;
	}
1041 1042 1043 1044
}

static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
{
1045 1046
	int div = 0; /* Initialized for compiler warning */
	u16 clk = 0;
1047
	unsigned long timeout;
1048 1049 1050 1051

	if (clock == host->clock)
		return;

1052 1053 1054 1055 1056 1057
	if (host->ops->set_clock) {
		host->ops->set_clock(host, clock);
		if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
			return;
	}

1058
	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1059 1060 1061 1062

	if (clock == 0)
		goto out;

1063
	if (host->version >= SDHCI_SPEC_300) {
1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100
		/*
		 * Check if the Host Controller supports Programmable Clock
		 * Mode.
		 */
		if (host->clk_mul) {
			u16 ctrl;

			/*
			 * We need to figure out whether the Host Driver needs
			 * to select Programmable Clock Mode, or the value can
			 * be set automatically by the Host Controller based on
			 * the Preset Value registers.
			 */
			ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
			if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
				for (div = 1; div <= 1024; div++) {
					if (((host->max_clk * host->clk_mul) /
					      div) <= clock)
						break;
				}
				/*
				 * Set Programmable Clock Mode in the Clock
				 * Control register.
				 */
				clk = SDHCI_PROG_CLOCK_MODE;
				div--;
			}
		} else {
			/* Version 3.00 divisors must be a multiple of 2. */
			if (host->max_clk <= clock)
				div = 1;
			else {
				for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
				     div += 2) {
					if ((host->max_clk / div) <= clock)
						break;
				}
1101
			}
1102
			div >>= 1;
1103 1104 1105
		}
	} else {
		/* Version 2.00 divisors must be a power of 2. */
1106
		for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1107 1108 1109
			if ((host->max_clk / div) <= clock)
				break;
		}
1110
		div >>= 1;
1111 1112
	}

1113
	clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1114 1115
	clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
		<< SDHCI_DIVIDER_HI_SHIFT;
1116
	clk |= SDHCI_CLOCK_INT_EN;
1117
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1118

1119 1120
	/* Wait max 20 ms */
	timeout = 20;
1121
	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1122 1123
		& SDHCI_CLOCK_INT_STABLE)) {
		if (timeout == 0) {
P
Pierre Ossman 已提交
1124 1125
			printk(KERN_ERR "%s: Internal clock never "
				"stabilised.\n", mmc_hostname(host->mmc));
1126 1127 1128
			sdhci_dumpregs(host);
			return;
		}
1129 1130 1131
		timeout--;
		mdelay(1);
	}
1132 1133

	clk |= SDHCI_CLOCK_CARD_EN;
1134
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1135 1136 1137 1138 1139

out:
	host->clock = clock;
}

1140 1141
static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
{
1142
	u8 pwr = 0;
1143

1144
	if (power != (unsigned short)-1) {
1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162
		switch (1 << power) {
		case MMC_VDD_165_195:
			pwr = SDHCI_POWER_180;
			break;
		case MMC_VDD_29_30:
		case MMC_VDD_30_31:
			pwr = SDHCI_POWER_300;
			break;
		case MMC_VDD_32_33:
		case MMC_VDD_33_34:
			pwr = SDHCI_POWER_330;
			break;
		default:
			BUG();
		}
	}

	if (host->pwr == pwr)
1163 1164
		return;

1165 1166 1167
	host->pwr = pwr;

	if (pwr == 0) {
1168
		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1169
		return;
1170 1171 1172 1173 1174 1175
	}

	/*
	 * Spec says that we should clear the power reg before setting
	 * a new value. Some controllers don't seem to like this though.
	 */
1176
	if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1177
		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1178

1179
	/*
1180
	 * At least the Marvell CaFe chip gets confused if we set the voltage
1181 1182
	 * and set turn on power at the same time, so set the voltage first.
	 */
1183
	if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1184
		sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1185

1186
	pwr |= SDHCI_POWER_ON;
1187

1188
	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1189 1190 1191 1192 1193

	/*
	 * Some controllers need an extra 10ms delay of 10ms before they
	 * can apply clock after applying power
	 */
1194
	if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1195
		mdelay(10);
1196 1197
}

1198 1199 1200 1201 1202 1203 1204 1205 1206
/*****************************************************************************\
 *                                                                           *
 * MMC callbacks                                                             *
 *                                                                           *
\*****************************************************************************/

static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
	struct sdhci_host *host;
1207
	bool present;
1208 1209 1210 1211 1212 1213 1214 1215
	unsigned long flags;

	host = mmc_priv(mmc);

	spin_lock_irqsave(&host->lock, flags);

	WARN_ON(host->mrq != NULL);

1216
#ifndef SDHCI_USE_LEDS_CLASS
1217
	sdhci_activate_led(host);
1218
#endif
1219 1220 1221 1222 1223 1224

	/*
	 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
	 * requests if Auto-CMD12 is enabled.
	 */
	if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1225 1226 1227 1228 1229
		if (mrq->stop) {
			mrq->data->stop = NULL;
			mrq->stop = NULL;
		}
	}
1230 1231 1232

	host->mrq = mrq;

1233 1234 1235 1236 1237 1238 1239 1240
	/* If polling, assume that the card is always present. */
	if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
		present = true;
	else
		present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
				SDHCI_CARD_PRESENT;

	if (!present || host->flags & SDHCI_DEVICE_DEAD) {
P
Pierre Ossman 已提交
1241
		host->mrq->cmd->error = -ENOMEDIUM;
1242
		tasklet_schedule(&host->finish_tasklet);
1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261
	} else {
		u32 present_state;

		present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
		/*
		 * Check if the re-tuning timer has already expired and there
		 * is no on-going data transfer. If so, we need to execute
		 * tuning procedure before sending command.
		 */
		if ((host->flags & SDHCI_NEEDS_RETUNING) &&
		    !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
			spin_unlock_irqrestore(&host->lock, flags);
			sdhci_execute_tuning(mmc);
			spin_lock_irqsave(&host->lock, flags);

			/* Restore original mmc_request structure */
			host->mrq = mrq;
		}

1262
		if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1263 1264 1265
			sdhci_send_command(host, mrq->sbc);
		else
			sdhci_send_command(host, mrq->cmd);
1266
	}
1267

1268
	mmiowb();
1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281
	spin_unlock_irqrestore(&host->lock, flags);
}

static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
	struct sdhci_host *host;
	unsigned long flags;
	u8 ctrl;

	host = mmc_priv(mmc);

	spin_lock_irqsave(&host->lock, flags);

P
Pierre Ossman 已提交
1282 1283 1284
	if (host->flags & SDHCI_DEVICE_DEAD)
		goto out;

1285 1286 1287 1288 1289
	/*
	 * Reset the chip on each power off.
	 * Should clear out any weird states.
	 */
	if (ios->power_mode == MMC_POWER_OFF) {
1290
		sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1291
		sdhci_reinit(host);
1292 1293 1294 1295 1296
	}

	sdhci_set_clock(host, ios->clock);

	if (ios->power_mode == MMC_POWER_OFF)
1297
		sdhci_set_power(host, -1);
1298
	else
1299
		sdhci_set_power(host, ios->vdd);
1300

1301 1302 1303
	if (host->ops->platform_send_init_74_clocks)
		host->ops->platform_send_init_74_clocks(host, ios->power_mode);

1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326
	/*
	 * If your platform has 8-bit width support but is not a v3 controller,
	 * or if it requires special setup code, you should implement that in
	 * platform_8bit_width().
	 */
	if (host->ops->platform_8bit_width)
		host->ops->platform_8bit_width(host, ios->bus_width);
	else {
		ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
		if (ios->bus_width == MMC_BUS_WIDTH_8) {
			ctrl &= ~SDHCI_CTRL_4BITBUS;
			if (host->version >= SDHCI_SPEC_300)
				ctrl |= SDHCI_CTRL_8BITBUS;
		} else {
			if (host->version >= SDHCI_SPEC_300)
				ctrl &= ~SDHCI_CTRL_8BITBUS;
			if (ios->bus_width == MMC_BUS_WIDTH_4)
				ctrl |= SDHCI_CTRL_4BITBUS;
			else
				ctrl &= ~SDHCI_CTRL_4BITBUS;
		}
		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
	}
1327

1328
	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1329

1330 1331 1332
	if ((ios->timing == MMC_TIMING_SD_HS ||
	     ios->timing == MMC_TIMING_MMC_HS)
	    && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1333 1334 1335 1336
		ctrl |= SDHCI_CTRL_HISPD;
	else
		ctrl &= ~SDHCI_CTRL_HISPD;

1337
	if (host->version >= SDHCI_SPEC_300) {
1338 1339 1340 1341 1342 1343 1344 1345 1346 1347
		u16 clk, ctrl_2;
		unsigned int clock;

		/* In case of UHS-I modes, set High Speed Enable */
		if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
		    (ios->timing == MMC_TIMING_UHS_SDR104) ||
		    (ios->timing == MMC_TIMING_UHS_DDR50) ||
		    (ios->timing == MMC_TIMING_UHS_SDR25) ||
		    (ios->timing == MMC_TIMING_UHS_SDR12))
			ctrl |= SDHCI_CTRL_HISPD;
1348 1349 1350

		ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
		if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1351
			sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362
			/*
			 * We only need to set Driver Strength if the
			 * preset value enable is not set.
			 */
			ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
			if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
				ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
			else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
				ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;

			sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381
		} else {
			/*
			 * According to SDHC Spec v3.00, if the Preset Value
			 * Enable in the Host Control 2 register is set, we
			 * need to reset SD Clock Enable before changing High
			 * Speed Enable to avoid generating clock gliches.
			 */

			/* Reset SD Clock Enable */
			clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
			clk &= ~SDHCI_CLOCK_CARD_EN;
			sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

			sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);

			/* Re-enable SD Clock */
			clock = host->clock;
			host->clock = 0;
			sdhci_set_clock(host, clock);
1382
		}
1383 1384 1385 1386 1387 1388 1389


		/* Reset SD Clock Enable */
		clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
		clk &= ~SDHCI_CLOCK_CARD_EN;
		sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407
		if (host->ops->set_uhs_signaling)
			host->ops->set_uhs_signaling(host, ios->timing);
		else {
			ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
			/* Select Bus Speed Mode for host */
			ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
			if (ios->timing == MMC_TIMING_UHS_SDR12)
				ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
			else if (ios->timing == MMC_TIMING_UHS_SDR25)
				ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
			else if (ios->timing == MMC_TIMING_UHS_SDR50)
				ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
			else if (ios->timing == MMC_TIMING_UHS_SDR104)
				ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
			else if (ios->timing == MMC_TIMING_UHS_DDR50)
				ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
			sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
		}
1408 1409 1410 1411 1412

		/* Re-enable SD Clock */
		clock = host->clock;
		host->clock = 0;
		sdhci_set_clock(host, clock);
1413 1414
	} else
		sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1415

1416 1417 1418 1419 1420
	/*
	 * Some (ENE) controllers go apeshit on some ios operation,
	 * signalling timeout and CRC errors even on CMD0. Resetting
	 * it on each ios seems to solve the problem.
	 */
1421
	if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1422 1423
		sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);

P
Pierre Ossman 已提交
1424
out:
1425
	mmiowb();
1426 1427 1428
	spin_unlock_irqrestore(&host->lock, flags);
}

1429
static int check_ro(struct sdhci_host *host)
1430 1431
{
	unsigned long flags;
1432
	int is_readonly;
1433 1434 1435

	spin_lock_irqsave(&host->lock, flags);

P
Pierre Ossman 已提交
1436
	if (host->flags & SDHCI_DEVICE_DEAD)
1437 1438 1439
		is_readonly = 0;
	else if (host->ops->get_ro)
		is_readonly = host->ops->get_ro(host);
P
Pierre Ossman 已提交
1440
	else
1441 1442
		is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
				& SDHCI_WRITE_PROTECT);
1443 1444 1445

	spin_unlock_irqrestore(&host->lock, flags);

1446 1447 1448
	/* This quirk needs to be replaced by a callback-function later */
	return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
		!is_readonly : is_readonly;
1449 1450
}

1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473
#define SAMPLE_COUNT	5

static int sdhci_get_ro(struct mmc_host *mmc)
{
	struct sdhci_host *host;
	int i, ro_count;

	host = mmc_priv(mmc);

	if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
		return check_ro(host);

	ro_count = 0;
	for (i = 0; i < SAMPLE_COUNT; i++) {
		if (check_ro(host)) {
			if (++ro_count > SAMPLE_COUNT / 2)
				return 1;
		}
		msleep(30);
	}
	return 0;
}

P
Pierre Ossman 已提交
1474 1475 1476 1477 1478 1479 1480 1481 1482
static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
{
	struct sdhci_host *host;
	unsigned long flags;

	host = mmc_priv(mmc);

	spin_lock_irqsave(&host->lock, flags);

P
Pierre Ossman 已提交
1483 1484 1485
	if (host->flags & SDHCI_DEVICE_DEAD)
		goto out;

P
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1486
	if (enable)
1487 1488 1489
		sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
	else
		sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
P
Pierre Ossman 已提交
1490
out:
P
Pierre Ossman 已提交
1491 1492 1493 1494 1495
	mmiowb();

	spin_unlock_irqrestore(&host->lock, flags);
}

1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597
static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
	struct mmc_ios *ios)
{
	struct sdhci_host *host;
	u8 pwr;
	u16 clk, ctrl;
	u32 present_state;

	host = mmc_priv(mmc);

	/*
	 * Signal Voltage Switching is only applicable for Host Controllers
	 * v3.00 and above.
	 */
	if (host->version < SDHCI_SPEC_300)
		return 0;

	/*
	 * We first check whether the request is to set signalling voltage
	 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
	 */
	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
		/* Set 1.8V Signal Enable in the Host Control2 register to 0 */
		ctrl &= ~SDHCI_CTRL_VDD_180;
		sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);

		/* Wait for 5ms */
		usleep_range(5000, 5500);

		/* 3.3V regulator output should be stable within 5 ms */
		ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
		if (!(ctrl & SDHCI_CTRL_VDD_180))
			return 0;
		else {
			printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V "
				"signalling voltage failed\n");
			return -EIO;
		}
	} else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
		  (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
		/* Stop SDCLK */
		clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
		clk &= ~SDHCI_CLOCK_CARD_EN;
		sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

		/* Check whether DAT[3:0] is 0000 */
		present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
		if (!((present_state & SDHCI_DATA_LVL_MASK) >>
		       SDHCI_DATA_LVL_SHIFT)) {
			/*
			 * Enable 1.8V Signal Enable in the Host Control2
			 * register
			 */
			ctrl |= SDHCI_CTRL_VDD_180;
			sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);

			/* Wait for 5ms */
			usleep_range(5000, 5500);

			ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
			if (ctrl & SDHCI_CTRL_VDD_180) {
				/* Provide SDCLK again and wait for 1ms*/
				clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
				clk |= SDHCI_CLOCK_CARD_EN;
				sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
				usleep_range(1000, 1500);

				/*
				 * If DAT[3:0] level is 1111b, then the card
				 * was successfully switched to 1.8V signaling.
				 */
				present_state = sdhci_readl(host,
							SDHCI_PRESENT_STATE);
				if ((present_state & SDHCI_DATA_LVL_MASK) ==
				     SDHCI_DATA_LVL_MASK)
					return 0;
			}
		}

		/*
		 * If we are here, that means the switch to 1.8V signaling
		 * failed. We power cycle the card, and retry initialization
		 * sequence by setting S18R to 0.
		 */
		pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
		pwr &= ~SDHCI_POWER_ON;
		sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);

		/* Wait for 1ms as per the spec */
		usleep_range(1000, 1500);
		pwr |= SDHCI_POWER_ON;
		sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);

		printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling "
			"voltage failed, retrying with S18R set to 0\n");
		return -EAGAIN;
	} else
		/* No signal voltage switch required */
		return 0;
}

1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734
static int sdhci_execute_tuning(struct mmc_host *mmc)
{
	struct sdhci_host *host;
	u16 ctrl;
	u32 ier;
	int tuning_loop_counter = MAX_TUNING_LOOP;
	unsigned long timeout;
	int err = 0;

	host = mmc_priv(mmc);

	disable_irq(host->irq);
	spin_lock(&host->lock);

	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);

	/*
	 * Host Controller needs tuning only in case of SDR104 mode
	 * and for SDR50 mode when Use Tuning for SDR50 is set in
	 * Capabilities register.
	 */
	if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
	    (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
	    (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
		ctrl |= SDHCI_CTRL_EXEC_TUNING;
	else {
		spin_unlock(&host->lock);
		enable_irq(host->irq);
		return 0;
	}

	sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);

	/*
	 * As per the Host Controller spec v3.00, tuning command
	 * generates Buffer Read Ready interrupt, so enable that.
	 *
	 * Note: The spec clearly says that when tuning sequence
	 * is being performed, the controller does not generate
	 * interrupts other than Buffer Read Ready interrupt. But
	 * to make sure we don't hit a controller bug, we _only_
	 * enable Buffer Read Ready interrupt here.
	 */
	ier = sdhci_readl(host, SDHCI_INT_ENABLE);
	sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);

	/*
	 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
	 * of loops reaches 40 times or a timeout of 150ms occurs.
	 */
	timeout = 150;
	do {
		struct mmc_command cmd = {0};
		struct mmc_request mrq = {0};

		if (!tuning_loop_counter && !timeout)
			break;

		cmd.opcode = MMC_SEND_TUNING_BLOCK;
		cmd.arg = 0;
		cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
		cmd.retries = 0;
		cmd.data = NULL;
		cmd.error = 0;

		mrq.cmd = &cmd;
		host->mrq = &mrq;

		/*
		 * In response to CMD19, the card sends 64 bytes of tuning
		 * block to the Host Controller. So we set the block size
		 * to 64 here.
		 */
		sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);

		/*
		 * The tuning block is sent by the card to the host controller.
		 * So we set the TRNS_READ bit in the Transfer Mode register.
		 * This also takes care of setting DMA Enable and Multi Block
		 * Select in the same register to 0.
		 */
		sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);

		sdhci_send_command(host, &cmd);

		host->cmd = NULL;
		host->mrq = NULL;

		spin_unlock(&host->lock);
		enable_irq(host->irq);

		/* Wait for Buffer Read Ready interrupt */
		wait_event_interruptible_timeout(host->buf_ready_int,
					(host->tuning_done == 1),
					msecs_to_jiffies(50));
		disable_irq(host->irq);
		spin_lock(&host->lock);

		if (!host->tuning_done) {
			printk(KERN_INFO DRIVER_NAME ": Timeout waiting for "
				"Buffer Read Ready interrupt during tuning "
				"procedure, falling back to fixed sampling "
				"clock\n");
			ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
			ctrl &= ~SDHCI_CTRL_TUNED_CLK;
			ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
			sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);

			err = -EIO;
			goto out;
		}

		host->tuning_done = 0;

		ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
		tuning_loop_counter--;
		timeout--;
		mdelay(1);
	} while (ctrl & SDHCI_CTRL_EXEC_TUNING);

	/*
	 * The Host Driver has exhausted the maximum number of loops allowed,
	 * so use fixed sampling frequency.
	 */
	if (!tuning_loop_counter || !timeout) {
		ctrl &= ~SDHCI_CTRL_TUNED_CLK;
		sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
	} else {
		if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
			printk(KERN_INFO DRIVER_NAME ": Tuning procedure"
				" failed, falling back to fixed sampling"
				" clock\n");
			err = -EIO;
		}
	}

out:
1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765
	/*
	 * If this is the very first time we are here, we start the retuning
	 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
	 * flag won't be set, we check this condition before actually starting
	 * the timer.
	 */
	if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
	    (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
		mod_timer(&host->tuning_timer, jiffies +
			host->tuning_count * HZ);
		/* Tuning mode 1 limits the maximum data length to 4MB */
		mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
	} else {
		host->flags &= ~SDHCI_NEEDS_RETUNING;
		/* Reload the new initial value for timer */
		if (host->tuning_mode == SDHCI_TUNING_MODE_1)
			mod_timer(&host->tuning_timer, jiffies +
				host->tuning_count * HZ);
	}

	/*
	 * In case tuning fails, host controllers which support re-tuning can
	 * try tuning again at a later time, when the re-tuning timer expires.
	 * So for these controllers, we return 0. Since there might be other
	 * controllers who do not have this capability, we return error for
	 * them.
	 */
	if (err && host->tuning_count &&
	    host->tuning_mode == SDHCI_TUNING_MODE_1)
		err = 0;

1766 1767 1768 1769 1770 1771 1772
	sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
	spin_unlock(&host->lock);
	enable_irq(host->irq);

	return err;
}

1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803
static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
{
	struct sdhci_host *host;
	u16 ctrl;
	unsigned long flags;

	host = mmc_priv(mmc);

	/* Host Controller v3.00 defines preset value registers */
	if (host->version < SDHCI_SPEC_300)
		return;

	spin_lock_irqsave(&host->lock, flags);

	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);

	/*
	 * We only enable or disable Preset Value if they are not already
	 * enabled or disabled respectively. Otherwise, we bail out.
	 */
	if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
		ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
		sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
	} else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
		ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
		sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
	}

	spin_unlock_irqrestore(&host->lock, flags);
}

1804
static const struct mmc_host_ops sdhci_ops = {
1805 1806 1807
	.request	= sdhci_request,
	.set_ios	= sdhci_set_ios,
	.get_ro		= sdhci_get_ro,
P
Pierre Ossman 已提交
1808
	.enable_sdio_irq = sdhci_enable_sdio_irq,
1809
	.start_signal_voltage_switch	= sdhci_start_signal_voltage_switch,
1810
	.execute_tuning			= sdhci_execute_tuning,
1811
	.enable_preset_value		= sdhci_enable_preset_value,
1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828
};

/*****************************************************************************\
 *                                                                           *
 * Tasklets                                                                  *
 *                                                                           *
\*****************************************************************************/

static void sdhci_tasklet_card(unsigned long param)
{
	struct sdhci_host *host;
	unsigned long flags;

	host = (struct sdhci_host*)param;

	spin_lock_irqsave(&host->lock, flags);

1829
	if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1830 1831 1832 1833 1834 1835 1836 1837 1838
		if (host->mrq) {
			printk(KERN_ERR "%s: Card removed during transfer!\n",
				mmc_hostname(host->mmc));
			printk(KERN_ERR "%s: Resetting controller.\n",
				mmc_hostname(host->mmc));

			sdhci_reset(host, SDHCI_RESET_CMD);
			sdhci_reset(host, SDHCI_RESET_DATA);

P
Pierre Ossman 已提交
1839
			host->mrq->cmd->error = -ENOMEDIUM;
1840 1841 1842 1843 1844 1845
			tasklet_schedule(&host->finish_tasklet);
		}
	}

	spin_unlock_irqrestore(&host->lock, flags);

P
Pierre Ossman 已提交
1846
	mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1847 1848 1849 1850 1851 1852 1853 1854 1855 1856
}

static void sdhci_tasklet_finish(unsigned long param)
{
	struct sdhci_host *host;
	unsigned long flags;
	struct mmc_request *mrq;

	host = (struct sdhci_host*)param;

1857 1858 1859 1860 1861 1862 1863
        /*
         * If this tasklet gets rescheduled while running, it will
         * be run again afterwards but without any active request.
         */
	if (!host->mrq)
		return;

1864 1865 1866 1867 1868 1869 1870 1871 1872 1873
	spin_lock_irqsave(&host->lock, flags);

	del_timer(&host->timer);

	mrq = host->mrq;

	/*
	 * The controller needs a reset of internal state machines
	 * upon error conditions.
	 */
P
Pierre Ossman 已提交
1874
	if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1875
	    ((mrq->cmd && mrq->cmd->error) ||
P
Pierre Ossman 已提交
1876 1877 1878
		 (mrq->data && (mrq->data->error ||
		  (mrq->data->stop && mrq->data->stop->error))) ||
		   (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1879 1880

		/* Some controllers need this kick or reset won't work here */
1881
		if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1882 1883 1884 1885 1886 1887 1888 1889 1890 1891
			unsigned int clock;

			/* This is to force an update */
			clock = host->clock;
			host->clock = 0;
			sdhci_set_clock(host, clock);
		}

		/* Spec says we should do both at the same time, but Ricoh
		   controllers do not like that. */
1892 1893 1894 1895 1896 1897 1898 1899
		sdhci_reset(host, SDHCI_RESET_CMD);
		sdhci_reset(host, SDHCI_RESET_DATA);
	}

	host->mrq = NULL;
	host->cmd = NULL;
	host->data = NULL;

1900
#ifndef SDHCI_USE_LEDS_CLASS
1901
	sdhci_deactivate_led(host);
1902
#endif
1903

1904
	mmiowb();
1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919
	spin_unlock_irqrestore(&host->lock, flags);

	mmc_request_done(host->mmc, mrq);
}

static void sdhci_timeout_timer(unsigned long data)
{
	struct sdhci_host *host;
	unsigned long flags;

	host = (struct sdhci_host*)data;

	spin_lock_irqsave(&host->lock, flags);

	if (host->mrq) {
P
Pierre Ossman 已提交
1920 1921
		printk(KERN_ERR "%s: Timeout waiting for hardware "
			"interrupt.\n", mmc_hostname(host->mmc));
1922 1923 1924
		sdhci_dumpregs(host);

		if (host->data) {
P
Pierre Ossman 已提交
1925
			host->data->error = -ETIMEDOUT;
1926 1927 1928
			sdhci_finish_data(host);
		} else {
			if (host->cmd)
P
Pierre Ossman 已提交
1929
				host->cmd->error = -ETIMEDOUT;
1930
			else
P
Pierre Ossman 已提交
1931
				host->mrq->cmd->error = -ETIMEDOUT;
1932 1933 1934 1935 1936

			tasklet_schedule(&host->finish_tasklet);
		}
	}

1937
	mmiowb();
1938 1939 1940
	spin_unlock_irqrestore(&host->lock, flags);
}

1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954
static void sdhci_tuning_timer(unsigned long data)
{
	struct sdhci_host *host;
	unsigned long flags;

	host = (struct sdhci_host *)data;

	spin_lock_irqsave(&host->lock, flags);

	host->flags |= SDHCI_NEEDS_RETUNING;

	spin_unlock_irqrestore(&host->lock, flags);
}

1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965
/*****************************************************************************\
 *                                                                           *
 * Interrupt handling                                                        *
 *                                                                           *
\*****************************************************************************/

static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
{
	BUG_ON(intmask == 0);

	if (!host->cmd) {
1966 1967 1968
		printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
			"though no command operation was in progress.\n",
			mmc_hostname(host->mmc), (unsigned)intmask);
1969 1970 1971 1972
		sdhci_dumpregs(host);
		return;
	}

1973
	if (intmask & SDHCI_INT_TIMEOUT)
P
Pierre Ossman 已提交
1974 1975 1976 1977
		host->cmd->error = -ETIMEDOUT;
	else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
			SDHCI_INT_INDEX))
		host->cmd->error = -EILSEQ;
1978

1979
	if (host->cmd->error) {
1980
		tasklet_schedule(&host->finish_tasklet);
1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998
		return;
	}

	/*
	 * The host can send and interrupt when the busy state has
	 * ended, allowing us to wait without wasting CPU cycles.
	 * Unfortunately this is overloaded on the "data complete"
	 * interrupt, so we need to take some care when handling
	 * it.
	 *
	 * Note: The 1.0 specification is a bit ambiguous about this
	 *       feature so there might be some problems with older
	 *       controllers.
	 */
	if (host->cmd->flags & MMC_RSP_BUSY) {
		if (host->cmd->data)
			DBG("Cannot wait for busy signal when also "
				"doing a data transfer");
1999
		else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2000
			return;
2001 2002 2003

		/* The controller does not support the end-of-busy IRQ,
		 * fall through and take the SDHCI_INT_RESPONSE */
2004 2005 2006
	}

	if (intmask & SDHCI_INT_RESPONSE)
2007
		sdhci_finish_command(host);
2008 2009
}

2010
#ifdef CONFIG_MMC_DEBUG
2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038
static void sdhci_show_adma_error(struct sdhci_host *host)
{
	const char *name = mmc_hostname(host->mmc);
	u8 *desc = host->adma_desc;
	__le32 *dma;
	__le16 *len;
	u8 attr;

	sdhci_dumpregs(host);

	while (true) {
		dma = (__le32 *)(desc + 4);
		len = (__le16 *)(desc + 2);
		attr = *desc;

		DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
		    name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);

		desc += 8;

		if (attr & 2)
			break;
	}
}
#else
static void sdhci_show_adma_error(struct sdhci_host *host) { }
#endif

2039 2040 2041 2042
static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
{
	BUG_ON(intmask == 0);

2043 2044 2045 2046 2047 2048 2049 2050 2051 2052
	/* CMD19 generates _only_ Buffer Read Ready interrupt */
	if (intmask & SDHCI_INT_DATA_AVAIL) {
		if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
		    MMC_SEND_TUNING_BLOCK) {
			host->tuning_done = 1;
			wake_up(&host->buf_ready_int);
			return;
		}
	}

2053 2054
	if (!host->data) {
		/*
2055 2056 2057
		 * The "data complete" interrupt is also used to
		 * indicate that a busy state has ended. See comment
		 * above in sdhci_cmd_irq().
2058
		 */
2059 2060 2061 2062 2063 2064
		if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
			if (intmask & SDHCI_INT_DATA_END) {
				sdhci_finish_command(host);
				return;
			}
		}
2065

2066 2067 2068
		printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
			"though no data operation was in progress.\n",
			mmc_hostname(host->mmc), (unsigned)intmask);
2069 2070 2071 2072 2073 2074
		sdhci_dumpregs(host);

		return;
	}

	if (intmask & SDHCI_INT_DATA_TIMEOUT)
P
Pierre Ossman 已提交
2075
		host->data->error = -ETIMEDOUT;
2076 2077 2078 2079 2080
	else if (intmask & SDHCI_INT_DATA_END_BIT)
		host->data->error = -EILSEQ;
	else if ((intmask & SDHCI_INT_DATA_CRC) &&
		SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
			!= MMC_BUS_TEST_R)
P
Pierre Ossman 已提交
2081
		host->data->error = -EILSEQ;
2082 2083 2084
	else if (intmask & SDHCI_INT_ADMA_ERROR) {
		printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
		sdhci_show_adma_error(host);
2085
		host->data->error = -EIO;
2086
	}
2087

P
Pierre Ossman 已提交
2088
	if (host->data->error)
2089 2090
		sdhci_finish_data(host);
	else {
P
Pierre Ossman 已提交
2091
		if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2092 2093
			sdhci_transfer_pio(host);

2094 2095 2096 2097
		/*
		 * We currently don't do anything fancy with DMA
		 * boundaries, but as we can't disable the feature
		 * we need to at least restart the transfer.
2098 2099 2100 2101
		 *
		 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
		 * should return a valid address to continue from, but as
		 * some controllers are faulty, don't trust them.
2102
		 */
2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119
		if (intmask & SDHCI_INT_DMA_END) {
			u32 dmastart, dmanow;
			dmastart = sg_dma_address(host->data->sg);
			dmanow = dmastart + host->data->bytes_xfered;
			/*
			 * Force update to the next DMA block boundary.
			 */
			dmanow = (dmanow &
				~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
				SDHCI_DEFAULT_BOUNDARY_SIZE;
			host->data->bytes_xfered = dmanow - dmastart;
			DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
				" next 0x%08x\n",
				mmc_hostname(host->mmc), dmastart,
				host->data->bytes_xfered, dmanow);
			sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
		}
2120

2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132
		if (intmask & SDHCI_INT_DATA_END) {
			if (host->cmd) {
				/*
				 * Data managed to finish before the
				 * command completed. Make sure we do
				 * things in the proper order.
				 */
				host->data_early = 1;
			} else {
				sdhci_finish_data(host);
			}
		}
2133 2134 2135
	}
}

2136
static irqreturn_t sdhci_irq(int irq, void *dev_id)
2137 2138 2139 2140
{
	irqreturn_t result;
	struct sdhci_host* host = dev_id;
	u32 intmask;
P
Pierre Ossman 已提交
2141
	int cardint = 0;
2142 2143 2144

	spin_lock(&host->lock);

2145
	intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2146

2147
	if (!intmask || intmask == 0xffffffff) {
2148 2149 2150 2151
		result = IRQ_NONE;
		goto out;
	}

2152 2153
	DBG("*** %s got interrupt: 0x%08x\n",
		mmc_hostname(host->mmc), intmask);
2154

2155
	if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173
		u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
			      SDHCI_CARD_PRESENT;

		/*
		 * There is a observation on i.mx esdhc.  INSERT bit will be
		 * immediately set again when it gets cleared, if a card is
		 * inserted.  We have to mask the irq to prevent interrupt
		 * storm which will freeze the system.  And the REMOVE gets
		 * the same situation.
		 *
		 * More testing are needed here to ensure it works for other
		 * platforms though.
		 */
		sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
						SDHCI_INT_CARD_REMOVE);
		sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
						  SDHCI_INT_CARD_INSERT);

2174
		sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2175 2176
			     SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
		intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2177
		tasklet_schedule(&host->card_tasklet);
2178
	}
2179

2180
	if (intmask & SDHCI_INT_CMD_MASK) {
2181 2182
		sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
			SDHCI_INT_STATUS);
2183
		sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2184 2185 2186
	}

	if (intmask & SDHCI_INT_DATA_MASK) {
2187 2188
		sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
			SDHCI_INT_STATUS);
2189
		sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2190 2191 2192 2193
	}

	intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);

2194 2195
	intmask &= ~SDHCI_INT_ERROR;

2196
	if (intmask & SDHCI_INT_BUS_POWER) {
2197
		printk(KERN_ERR "%s: Card is consuming too much power!\n",
2198
			mmc_hostname(host->mmc));
2199
		sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2200 2201
	}

2202
	intmask &= ~SDHCI_INT_BUS_POWER;
2203

P
Pierre Ossman 已提交
2204 2205 2206 2207 2208
	if (intmask & SDHCI_INT_CARD_INT)
		cardint = 1;

	intmask &= ~SDHCI_INT_CARD_INT;

2209
	if (intmask) {
P
Pierre Ossman 已提交
2210
		printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
2211
			mmc_hostname(host->mmc), intmask);
2212 2213
		sdhci_dumpregs(host);

2214
		sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2215
	}
2216 2217 2218

	result = IRQ_HANDLED;

2219
	mmiowb();
2220 2221 2222
out:
	spin_unlock(&host->lock);

P
Pierre Ossman 已提交
2223 2224 2225 2226 2227 2228
	/*
	 * We have to delay this as it calls back into the driver.
	 */
	if (cardint)
		mmc_signal_sdio_irq(host->mmc);

2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239
	return result;
}

/*****************************************************************************\
 *                                                                           *
 * Suspend/resume                                                            *
 *                                                                           *
\*****************************************************************************/

#ifdef CONFIG_PM

2240
int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
2241
{
2242
	int ret;
2243

2244 2245
	sdhci_disable_card_detection(host);

2246 2247 2248 2249 2250 2251 2252 2253
	/* Disable tuning since we are suspending */
	if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
	    host->tuning_mode == SDHCI_TUNING_MODE_1) {
		host->flags &= ~SDHCI_NEEDS_RETUNING;
		mod_timer(&host->tuning_timer, jiffies +
			host->tuning_count * HZ);
	}

2254
	ret = mmc_suspend_host(host->mmc);
2255 2256
	if (ret)
		return ret;
2257

2258
	free_irq(host->irq, host);
2259

M
Marek Szyprowski 已提交
2260 2261 2262 2263
	if (host->vmmc)
		ret = regulator_disable(host->vmmc);

	return ret;
2264 2265
}

2266
EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2267

2268 2269 2270
int sdhci_resume_host(struct sdhci_host *host)
{
	int ret;
2271

M
Marek Szyprowski 已提交
2272 2273 2274 2275 2276 2277 2278
	if (host->vmmc) {
		int ret = regulator_enable(host->vmmc);
		if (ret)
			return ret;
	}


2279
	if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2280 2281 2282
		if (host->ops->enable_dma)
			host->ops->enable_dma(host);
	}
2283

2284 2285
	ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
			  mmc_hostname(host->mmc), host);
2286 2287
	if (ret)
		return ret;
2288

2289
	sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2290 2291 2292
	mmiowb();

	ret = mmc_resume_host(host->mmc);
2293 2294
	sdhci_enable_card_detection(host);

2295 2296 2297 2298 2299
	/* Set the re-tuning expiration flag */
	if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
	    (host->tuning_mode == SDHCI_TUNING_MODE_1))
		host->flags |= SDHCI_NEEDS_RETUNING;

2300
	return ret;
2301 2302
}

2303
EXPORT_SYMBOL_GPL(sdhci_resume_host);
2304

2305 2306 2307 2308 2309 2310 2311 2312 2313 2314
void sdhci_enable_irq_wakeups(struct sdhci_host *host)
{
	u8 val;
	val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
	val |= SDHCI_WAKE_ON_INT;
	sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
}

EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);

2315 2316 2317 2318
#endif /* CONFIG_PM */

/*****************************************************************************\
 *                                                                           *
2319
 * Device allocation/registration                                            *
2320 2321 2322
 *                                                                           *
\*****************************************************************************/

2323 2324
struct sdhci_host *sdhci_alloc_host(struct device *dev,
	size_t priv_size)
2325 2326 2327 2328
{
	struct mmc_host *mmc;
	struct sdhci_host *host;

2329
	WARN_ON(dev == NULL);
2330

2331
	mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2332
	if (!mmc)
2333
		return ERR_PTR(-ENOMEM);
2334 2335 2336 2337

	host = mmc_priv(mmc);
	host->mmc = mmc;

2338 2339
	return host;
}
2340

2341
EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2342

2343 2344 2345
int sdhci_add_host(struct sdhci_host *host)
{
	struct mmc_host *mmc;
2346 2347 2348
	u32 caps[2];
	u32 max_current_caps;
	unsigned int ocr_avail;
2349
	int ret;
2350

2351 2352 2353
	WARN_ON(host == NULL);
	if (host == NULL)
		return -EINVAL;
2354

2355
	mmc = host->mmc;
2356

2357 2358
	if (debug_quirks)
		host->quirks = debug_quirks;
2359

2360 2361
	sdhci_reset(host, SDHCI_RESET_ALL);

2362
	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2363 2364
	host->version = (host->version & SDHCI_SPEC_VER_MASK)
				>> SDHCI_SPEC_VER_SHIFT;
2365
	if (host->version > SDHCI_SPEC_300) {
2366
		printk(KERN_ERR "%s: Unknown controller version (%d). "
2367
			"You may experience problems.\n", mmc_hostname(mmc),
2368
			host->version);
2369 2370
	}

2371
	caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2372
		sdhci_readl(host, SDHCI_CAPABILITIES);
2373

2374 2375 2376
	caps[1] = (host->version >= SDHCI_SPEC_300) ?
		sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;

2377
	if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2378
		host->flags |= SDHCI_USE_SDMA;
2379
	else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2380
		DBG("Controller doesn't have SDMA capability\n");
2381
	else
2382
		host->flags |= SDHCI_USE_SDMA;
2383

2384
	if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2385
		(host->flags & SDHCI_USE_SDMA)) {
R
Rolf Eike Beer 已提交
2386
		DBG("Disabling DMA as it is marked broken\n");
2387
		host->flags &= ~SDHCI_USE_SDMA;
2388 2389
	}

2390 2391
	if ((host->version >= SDHCI_SPEC_200) &&
		(caps[0] & SDHCI_CAN_DO_ADMA2))
2392
		host->flags |= SDHCI_USE_ADMA;
2393 2394 2395 2396 2397 2398 2399

	if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
		(host->flags & SDHCI_USE_ADMA)) {
		DBG("Disabling ADMA as it is marked broken\n");
		host->flags &= ~SDHCI_USE_ADMA;
	}

2400
	if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2401 2402 2403 2404 2405
		if (host->ops->enable_dma) {
			if (host->ops->enable_dma(host)) {
				printk(KERN_WARNING "%s: No suitable DMA "
					"available. Falling back to PIO.\n",
					mmc_hostname(mmc));
2406 2407
				host->flags &=
					~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2408
			}
2409 2410 2411
		}
	}

2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429
	if (host->flags & SDHCI_USE_ADMA) {
		/*
		 * We need to allocate descriptors for all sg entries
		 * (128) and potentially one alignment transfer for
		 * each of those entries.
		 */
		host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
		host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
		if (!host->adma_desc || !host->align_buffer) {
			kfree(host->adma_desc);
			kfree(host->align_buffer);
			printk(KERN_WARNING "%s: Unable to allocate ADMA "
				"buffers. Falling back to standard DMA.\n",
				mmc_hostname(mmc));
			host->flags &= ~SDHCI_USE_ADMA;
		}
	}

2430 2431 2432 2433 2434
	/*
	 * If we use DMA, then it's up to the caller to set the DMA
	 * mask, but PIO does not need the hw shim so we set a new
	 * mask here in that case.
	 */
2435
	if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2436 2437 2438
		host->dma_mask = DMA_BIT_MASK(64);
		mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
	}
2439

2440
	if (host->version >= SDHCI_SPEC_300)
2441
		host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2442 2443
			>> SDHCI_CLOCK_BASE_SHIFT;
	else
2444
		host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2445 2446
			>> SDHCI_CLOCK_BASE_SHIFT;

2447
	host->max_clk *= 1000000;
2448 2449
	if (host->max_clk == 0 || host->quirks &
			SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2450 2451 2452 2453 2454 2455 2456
		if (!host->ops->get_max_clock) {
			printk(KERN_ERR
			       "%s: Hardware doesn't specify base clock "
			       "frequency.\n", mmc_hostname(mmc));
			return -ENODEV;
		}
		host->max_clk = host->ops->get_max_clock(host);
2457
	}
2458

2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474
	/*
	 * In case of Host Controller v3.00, find out whether clock
	 * multiplier is supported.
	 */
	host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
			SDHCI_CLOCK_MUL_SHIFT;

	/*
	 * In case the value in Clock Multiplier is 0, then programmable
	 * clock mode is not supported, otherwise the actual clock
	 * multiplier is one more than the value of Clock Multiplier
	 * in the Capabilities Register.
	 */
	if (host->clk_mul)
		host->clk_mul += 1;

2475 2476 2477 2478
	/*
	 * Set host parameters.
	 */
	mmc->ops = &sdhci_ops;
2479
	mmc->f_max = host->max_clk;
2480
	if (host->ops->get_min_clock)
2481
		mmc->f_min = host->ops->get_min_clock(host);
2482 2483 2484 2485 2486 2487 2488
	else if (host->version >= SDHCI_SPEC_300) {
		if (host->clk_mul) {
			mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
			mmc->f_max = host->max_clk * host->clk_mul;
		} else
			mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
	} else
2489
		mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2490

2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507
	host->timeout_clk =
		(caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
	if (host->timeout_clk == 0) {
		if (host->ops->get_timeout_clock) {
			host->timeout_clk = host->ops->get_timeout_clock(host);
		} else if (!(host->quirks &
				SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
			printk(KERN_ERR
			       "%s: Hardware doesn't specify timeout clock "
			       "frequency.\n", mmc_hostname(mmc));
			return -ENODEV;
		}
	}
	if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
		host->timeout_clk *= 1000;

	if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2508
		host->timeout_clk = mmc->f_max / 1000;
2509

2510
	mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2511

2512 2513 2514 2515
	mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;

	if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
		host->flags |= SDHCI_AUTO_CMD12;
2516

2517
	/* Auto-CMD23 stuff only works in ADMA or PIO. */
A
Andrei Warkentin 已提交
2518
	if ((host->version >= SDHCI_SPEC_300) &&
2519
	    ((host->flags & SDHCI_USE_ADMA) ||
A
Andrei Warkentin 已提交
2520
	     !(host->flags & SDHCI_USE_SDMA))) {
2521 2522 2523 2524 2525 2526
		host->flags |= SDHCI_AUTO_CMD23;
		DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
	} else {
		DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
	}

2527 2528 2529 2530 2531 2532 2533
	/*
	 * A controller may support 8-bit width, but the board itself
	 * might not have the pins brought out.  Boards that support
	 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
	 * their platform code before calling sdhci_add_host(), and we
	 * won't assume 8-bit width for hosts without that CAP.
	 */
2534
	if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2535
		mmc->caps |= MMC_CAP_4_BIT_DATA;
2536

2537
	if (caps[0] & SDHCI_CAN_DO_HISPD)
2538
		mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2539

2540 2541
	if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
	    mmc_card_is_removable(mmc))
2542 2543
		mmc->caps |= MMC_CAP_NEEDS_POLL;

2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556
	/* UHS-I mode(s) supported by the host controller. */
	if (host->version >= SDHCI_SPEC_300)
		mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;

	/* SDR104 supports also implies SDR50 support */
	if (caps[1] & SDHCI_SUPPORT_SDR104)
		mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
	else if (caps[1] & SDHCI_SUPPORT_SDR50)
		mmc->caps |= MMC_CAP_UHS_SDR50;

	if (caps[1] & SDHCI_SUPPORT_DDR50)
		mmc->caps |= MMC_CAP_UHS_DDR50;

2557 2558 2559 2560
	/* Does the host needs tuning for SDR50? */
	if (caps[1] & SDHCI_USE_SDR50_TUNING)
		host->flags |= SDHCI_SDR50_NEEDS_TUNING;

2561 2562 2563 2564 2565 2566 2567 2568
	/* Driver Type(s) (A, C, D) supported by the host */
	if (caps[1] & SDHCI_DRIVER_TYPE_A)
		mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
	if (caps[1] & SDHCI_DRIVER_TYPE_C)
		mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
	if (caps[1] & SDHCI_DRIVER_TYPE_D)
		mmc->caps |= MMC_CAP_DRIVER_TYPE_D;

2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583
	/* Initial value for re-tuning timer count */
	host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
			      SDHCI_RETUNING_TIMER_COUNT_SHIFT;

	/*
	 * In case Re-tuning Timer is not disabled, the actual value of
	 * re-tuning timer will be 2 ^ (n - 1).
	 */
	if (host->tuning_count)
		host->tuning_count = 1 << (host->tuning_count - 1);

	/* Re-tuning mode supported by the Host Controller */
	host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
			     SDHCI_RETUNING_MODE_SHIFT;

2584
	ocr_avail = 0;
2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596
	/*
	 * According to SD Host Controller spec v3.00, if the Host System
	 * can afford more than 150mA, Host Driver should set XPC to 1. Also
	 * the value is meaningful only if Voltage Support in the Capabilities
	 * register is set. The actual current value is 4 times the register
	 * value.
	 */
	max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);

	if (caps[0] & SDHCI_CAN_VDD_330) {
		int max_current_330;

2597
		ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609

		max_current_330 = ((max_current_caps &
				   SDHCI_MAX_CURRENT_330_MASK) >>
				   SDHCI_MAX_CURRENT_330_SHIFT) *
				   SDHCI_MAX_CURRENT_MULTIPLIER;

		if (max_current_330 > 150)
			mmc->caps |= MMC_CAP_SET_XPC_330;
	}
	if (caps[0] & SDHCI_CAN_VDD_300) {
		int max_current_300;

2610
		ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622

		max_current_300 = ((max_current_caps &
				   SDHCI_MAX_CURRENT_300_MASK) >>
				   SDHCI_MAX_CURRENT_300_SHIFT) *
				   SDHCI_MAX_CURRENT_MULTIPLIER;

		if (max_current_300 > 150)
			mmc->caps |= MMC_CAP_SET_XPC_300;
	}
	if (caps[0] & SDHCI_CAN_VDD_180) {
		int max_current_180;

2623 2624
		ocr_avail |= MMC_VDD_165_195;

2625 2626 2627 2628 2629 2630 2631
		max_current_180 = ((max_current_caps &
				   SDHCI_MAX_CURRENT_180_MASK) >>
				   SDHCI_MAX_CURRENT_180_SHIFT) *
				   SDHCI_MAX_CURRENT_MULTIPLIER;

		if (max_current_180 > 150)
			mmc->caps |= MMC_CAP_SET_XPC_180;
2632 2633 2634 2635 2636 2637 2638 2639 2640 2641

		/* Maximum current capabilities of the host at 1.8V */
		if (max_current_180 >= 800)
			mmc->caps |= MMC_CAP_MAX_CURRENT_800;
		else if (max_current_180 >= 600)
			mmc->caps |= MMC_CAP_MAX_CURRENT_600;
		else if (max_current_180 >= 400)
			mmc->caps |= MMC_CAP_MAX_CURRENT_400;
		else
			mmc->caps |= MMC_CAP_MAX_CURRENT_200;
2642 2643
	}

2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655
	mmc->ocr_avail = ocr_avail;
	mmc->ocr_avail_sdio = ocr_avail;
	if (host->ocr_avail_sdio)
		mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
	mmc->ocr_avail_sd = ocr_avail;
	if (host->ocr_avail_sd)
		mmc->ocr_avail_sd &= host->ocr_avail_sd;
	else /* normal SD controllers don't support 1.8V */
		mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
	mmc->ocr_avail_mmc = ocr_avail;
	if (host->ocr_avail_mmc)
		mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2656 2657 2658

	if (mmc->ocr_avail == 0) {
		printk(KERN_ERR "%s: Hardware doesn't report any "
2659
			"support voltages.\n", mmc_hostname(mmc));
2660
		return -ENODEV;
2661 2662
	}

2663 2664 2665
	spin_lock_init(&host->lock);

	/*
2666 2667
	 * Maximum number of segments. Depends on if the hardware
	 * can do scatter/gather or not.
2668
	 */
2669
	if (host->flags & SDHCI_USE_ADMA)
2670
		mmc->max_segs = 128;
2671
	else if (host->flags & SDHCI_USE_SDMA)
2672
		mmc->max_segs = 1;
2673
	else /* PIO */
2674
		mmc->max_segs = 128;
2675 2676

	/*
2677
	 * Maximum number of sectors in one transfer. Limited by DMA boundary
2678
	 * size (512KiB).
2679
	 */
2680
	mmc->max_req_size = 524288;
2681 2682 2683

	/*
	 * Maximum segment size. Could be one segment with the maximum number
2684 2685
	 * of bytes. When doing hardware scatter/gather, each entry cannot
	 * be larger than 64 KiB though.
2686
	 */
2687 2688 2689 2690 2691 2692
	if (host->flags & SDHCI_USE_ADMA) {
		if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
			mmc->max_seg_size = 65535;
		else
			mmc->max_seg_size = 65536;
	} else {
2693
		mmc->max_seg_size = mmc->max_req_size;
2694
	}
2695

2696 2697 2698 2699
	/*
	 * Maximum block size. This varies from controller to controller and
	 * is specified in the capabilities register.
	 */
2700 2701 2702
	if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
		mmc->max_blk_size = 2;
	} else {
2703
		mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
2704 2705 2706 2707 2708 2709 2710 2711 2712
				SDHCI_MAX_BLOCK_SHIFT;
		if (mmc->max_blk_size >= 3) {
			printk(KERN_WARNING "%s: Invalid maximum block size, "
				"assuming 512 bytes\n", mmc_hostname(mmc));
			mmc->max_blk_size = 0;
		}
	}

	mmc->max_blk_size = 512 << mmc->max_blk_size;
2713

2714 2715 2716
	/*
	 * Maximum block count.
	 */
2717
	mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
2718

2719 2720 2721 2722 2723 2724 2725 2726
	/*
	 * Init tasklets.
	 */
	tasklet_init(&host->card_tasklet,
		sdhci_tasklet_card, (unsigned long)host);
	tasklet_init(&host->finish_tasklet,
		sdhci_tasklet_finish, (unsigned long)host);

2727
	setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
2728

2729
	if (host->version >= SDHCI_SPEC_300) {
2730 2731
		init_waitqueue_head(&host->buf_ready_int);

2732 2733 2734 2735 2736 2737
		/* Initialize re-tuning timer */
		init_timer(&host->tuning_timer);
		host->tuning_timer.data = (unsigned long)host;
		host->tuning_timer.function = sdhci_tuning_timer;
	}

2738
	ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2739
		mmc_hostname(mmc), host);
2740
	if (ret)
2741
		goto untasklet;
2742

M
Marek Szyprowski 已提交
2743 2744 2745 2746 2747 2748 2749 2750
	host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
	if (IS_ERR(host->vmmc)) {
		printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
		host->vmmc = NULL;
	} else {
		regulator_enable(host->vmmc);
	}

2751
	sdhci_init(host, 0);
2752 2753 2754 2755 2756

#ifdef CONFIG_MMC_DEBUG
	sdhci_dumpregs(host);
#endif

2757
#ifdef SDHCI_USE_LEDS_CLASS
H
Helmut Schaa 已提交
2758 2759 2760
	snprintf(host->led_name, sizeof(host->led_name),
		"%s::", mmc_hostname(mmc));
	host->led.name = host->led_name;
2761 2762 2763 2764
	host->led.brightness = LED_OFF;
	host->led.default_trigger = mmc_hostname(mmc);
	host->led.brightness_set = sdhci_led_control;

2765
	ret = led_classdev_register(mmc_dev(mmc), &host->led);
2766 2767 2768 2769
	if (ret)
		goto reset;
#endif

2770 2771
	mmiowb();

2772 2773
	mmc_add_host(mmc);

2774
	printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
2775
		mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2776 2777
		(host->flags & SDHCI_USE_ADMA) ? "ADMA" :
		(host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
2778

2779 2780
	sdhci_enable_card_detection(host);

2781 2782
	return 0;

2783
#ifdef SDHCI_USE_LEDS_CLASS
2784 2785 2786 2787
reset:
	sdhci_reset(host, SDHCI_RESET_ALL);
	free_irq(host->irq, host);
#endif
2788
untasklet:
2789 2790 2791 2792 2793 2794
	tasklet_kill(&host->card_tasklet);
	tasklet_kill(&host->finish_tasklet);

	return ret;
}

2795
EXPORT_SYMBOL_GPL(sdhci_add_host);
2796

P
Pierre Ossman 已提交
2797
void sdhci_remove_host(struct sdhci_host *host, int dead)
2798
{
P
Pierre Ossman 已提交
2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816
	unsigned long flags;

	if (dead) {
		spin_lock_irqsave(&host->lock, flags);

		host->flags |= SDHCI_DEVICE_DEAD;

		if (host->mrq) {
			printk(KERN_ERR "%s: Controller removed during "
				" transfer!\n", mmc_hostname(host->mmc));

			host->mrq->cmd->error = -ENOMEDIUM;
			tasklet_schedule(&host->finish_tasklet);
		}

		spin_unlock_irqrestore(&host->lock, flags);
	}

2817 2818
	sdhci_disable_card_detection(host);

2819
	mmc_remove_host(host->mmc);
2820

2821
#ifdef SDHCI_USE_LEDS_CLASS
2822 2823 2824
	led_classdev_unregister(&host->led);
#endif

P
Pierre Ossman 已提交
2825 2826
	if (!dead)
		sdhci_reset(host, SDHCI_RESET_ALL);
2827 2828 2829 2830

	free_irq(host->irq, host);

	del_timer_sync(&host->timer);
2831 2832
	if (host->version >= SDHCI_SPEC_300)
		del_timer_sync(&host->tuning_timer);
2833 2834 2835

	tasklet_kill(&host->card_tasklet);
	tasklet_kill(&host->finish_tasklet);
2836

M
Marek Szyprowski 已提交
2837 2838 2839 2840 2841
	if (host->vmmc) {
		regulator_disable(host->vmmc);
		regulator_put(host->vmmc);
	}

2842 2843 2844 2845 2846
	kfree(host->adma_desc);
	kfree(host->align_buffer);

	host->adma_desc = NULL;
	host->align_buffer = NULL;
2847 2848
}

2849
EXPORT_SYMBOL_GPL(sdhci_remove_host);
2850

2851
void sdhci_free_host(struct sdhci_host *host)
2852
{
2853
	mmc_free_host(host->mmc);
2854 2855
}

2856
EXPORT_SYMBOL_GPL(sdhci_free_host);
2857 2858 2859 2860 2861 2862 2863 2864 2865 2866

/*****************************************************************************\
 *                                                                           *
 * Driver init/exit                                                          *
 *                                                                           *
\*****************************************************************************/

static int __init sdhci_drv_init(void)
{
	printk(KERN_INFO DRIVER_NAME
2867
		": Secure Digital Host Controller Interface driver\n");
2868 2869
	printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");

2870
	return 0;
2871 2872 2873 2874 2875 2876 2877 2878 2879
}

static void __exit sdhci_drv_exit(void)
{
}

module_init(sdhci_drv_init);
module_exit(sdhci_drv_exit);

2880
module_param(debug_quirks, uint, 0444);
2881

2882
MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2883
MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2884
MODULE_LICENSE("GPL");
2885

2886
MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");