- 22 3月, 2021 1 次提交
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由 Lemover 提交于
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- 19 3月, 2021 2 次提交
- 14 3月, 2021 1 次提交
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由 Steve Gou 提交于
* add perf counters for btb and ubtb * update btb only on not hit or jalr mispredicts to reduce write stalls
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- 13 3月, 2021 3 次提交
- 12 3月, 2021 3 次提交
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由 Lemover 提交于
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由 zhanglinjuan 提交于
* DCacheWrapper: MainPipe use read port 1 to ease congestion * MainPipe: do not consider congestion with ldu0 read when disabling fast wakeup
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由 Lemover 提交于
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- 11 3月, 2021 6 次提交
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由 Yinan Xu 提交于
Previously we use numactl to specify both nodes and cpus for emu. However, when other processes are using the same cpu, verilated emu suffers from huge performance degradation. To avoid these scenarios, we only specify the numa node to achieve a more stable performance.
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由 Yinan Xu 提交于
In this commit, we add support for a simpler version of move elimination. The original instruction sequences are: move r1, r0 add r2, r1, r3 The optimized sequnces are: move pr1, pr0 add pr2, pr0, pr3 # instead of add pr2, pr1, pr3 In this way, add can be issued once r0 is ready and move seems to be eliminated.
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由 Yinan Xu 提交于
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由 Lemover 提交于
* MainPipe/LoadPipe: disable fast wakeup when data sram is to be written * RS: set EnableLoadFastWakeUp true * LoadPipe: add perf cnt for disabling ld fast wakeup speculatively * MainPipe: disable ld fast wakeup when s1 read data in MainPipe Co-authored-by: Nzhanglinjuan <zhanglinjuan16@mails.ucas.ac.cn>
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由 Yinan Xu 提交于
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由 Steve Gou 提交于
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- 10 3月, 2021 6 次提交
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由 zhanglinjuan 提交于
* DCache: fix bug in failing to update access info of plru replacement * DCache: add performance counters
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由 zhanglinjuan 提交于
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由 Yinan Xu 提交于
* Top: remove extra axi ID bits * Re-add AXI4UserYanker Co-authored-by: NLinJiawei <linjiav@outlook.com>
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由 Steve Gou 提交于
previously the biggest problem was using '+' instead of '+&' to do sums
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由 Lemover 提交于
* LoadUnit: generate fastUop in load_s1 * RS/Load: add load to fast wakeup when cache hit, while maintain its slow * RS: remove legacy assert that doesn't work for load has fast and slow * LoadUnit: fix bug that fastUops's valid forgets load_s1.io.in.valid * MemBlock: fix bug of loadUnit's fast and slow connect IPC of coremark 10 cycles raise from 1.63 to 1.70 * RS: RegNext srcUpdate to use it at next cycle * RS: add param EnableLoadFastWakeUp and set default to false Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
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由 Lemover 提交于
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- 09 3月, 2021 6 次提交
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由 Jay 提交于
* L1I/L1+: Add performance counters for each way. * Replacement: fix that lfsr always changes in random.
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由 ljw 提交于
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由 Yinan Xu 提交于
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由 Lemover 提交于
* TLB&PTW: add replace perf count * PTW: remove set's perf count, just way's * PTW: fix bug that puts perf inside when * TLB&PTW: add access perf count
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由 Yinan Xu 提交于
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由 Lemover 提交于
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- 08 3月, 2021 3 次提交
- 07 3月, 2021 4 次提交
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由 Yinan Xu 提交于
* MySoc: verilog top * MySoc: connect mmio * MySoc: fix some bugs * wip * TopMain: remove to top * WIP: add dma port * Update XSTop for FPGA/ASIC platform * Top: add rocket-chip source * Append SRAM to generated verilog Co-authored-by: NLinJiawei <linjiav@outlook.com>
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由 Lemover 提交于
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由 zhanglinjuan 提交于
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由 Yinan Xu 提交于
Previously, we use !flushPipe to reduce serveral or gates. However, when an instruction has instruction page fault or access fault, the instruction may be decoded as any instructions, which possibly generates flushPipe. Thus, previously an instruction with exceptions may trigger a flushPipe instead of exceptions. Now we use exceptionVec.asUInt.orR to see whether it has exceptions.
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- 06 3月, 2021 5 次提交
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由 zhanglinjuan 提交于
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由 zhanglinjuan 提交于
This reverts commit 1c6ad6d0.
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由 zhanglinjuan 提交于
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由 zhanglinjuan 提交于
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由 Steve Gou 提交于
* core: enable sc * sc: calculate sum again on update * sc: clean ups * sc: add some debug info * sc, tage, bim: fix wrbypass logic, add wrbypass for SC * sc: restrict threshold update conditions and prevent overflow problem * sc: use seperative thresholds for each bank * sc: update debug info * sc: use adaptive threshold algorithm from the original O-GEHL * tage, bim, sc: optimize wrbypass logic * sc: initialize threshold to 60 * loop: remove unuseful RegNext on redirect * ifu: add perf counters * Perf: Add loopPredictor perf counters * sc: fix perf logics Co-authored-by: Njinyue110 <jinyue161@mails.ucas.ac.cn> Co-authored-by: Nzoujr <18870680299@163.com>
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