L1I/L1+: Add performance counters for each way. (#670)

* L1I/L1+:  Add performance counters for each way.

* Replacement: fix that lfsr always changes in random.

src/main/scala/utils/Replacement.scala

@@ -47,7 +47,7 @@ object ReplacementPolicy {
 
 class RandomReplacement(n_ways: Int) extends ReplacementPolicy {
   private val replace = Wire(Bool())
-  replace := true.B
+  replace := false.B
   def nBits = 16
   def perSet = false
   private val lfsr = LFSR(nBits, replace)
@@ -340,8 +340,8 @@ class SetAssocRandom(n_sets : Int, n_ways: Int) extends SetAssocReplacementPolic
   def miss(set: UInt) =  random.miss 
   def way(set: UInt) = random.way
 
-  def access(set: UInt, touch_way: UInt) = {}
-  def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = {}
+  def access(set: UInt, touch_way: UInt) = random.access(touch_way)
+  def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = random.access(touch_ways)
 
 }
 

src/main/scala/xiangshan/cache/ICache.scala

@@ -483,6 +483,13 @@ class ICache extends ICacheModule
   touch_ways(1).valid := icacheMissQueue.io.meta_write.valid
   touch_ways(1).bits  := wayNum
 
+  (0 until nWays).map{ w => 
+    XSPerf("hit_way_" + Integer.toString(w, 10),  s2_hit && OHToUInt(hitVec)  === w.U)
+    XSPerf("refill_way_" + Integer.toString(w, 10), icacheMissQueue.io.meta_write.valid && wayNum === w.U)
+    XSPerf("access_way_" + Integer.toString(w, 10), (icacheMissQueue.io.meta_write.valid && wayNum === w.U) || (s2_hit && OHToUInt(hitVec)  === w.U))
+  }
+
+
   val validPtr = Cat(metaWriteReq.meta_write_idx,wayNum)
   when(icacheMissQueue.io.meta_write.valid && !cacheflushed){
     validArray := validArray.bitSet(validPtr, true.B)

src/main/scala/xiangshan/cache/L1plusCache.scala

@@ -605,10 +605,15 @@ class L1plusCachePipe extends L1plusCacheModule
   io.miss_req.bits.addr   := s2_req.addr
   io.miss_req.bits.way_en := replaced_way_en
 
+  val wayNum =  OHToUInt(io.miss_meta_write.bits.way_en.asUInt)
   touch_sets(1)       := io.miss_meta_write.bits.tagIdx
   touch_ways(1).valid := io.miss_meta_write.valid
-  touch_ways(1).bits  := OHToUInt(io.miss_meta_write.bits.way_en.asUInt)
-
+  touch_ways(1).bits  := wayNum
+  (0 until nWays).map{ w => 
+    XSPerf("hit_way_" + Integer.toString(w, 10),  s2_valid && s2_hit && s2_hit_way === w.U)
+    XSPerf("refill_way_" + Integer.toString(w, 10), io.miss_meta_write.valid && wayNum === w.U)
+    XSPerf("access_way_" + Integer.toString(w, 10), (io.miss_meta_write.valid && wayNum === w.U) || (s2_valid && s2_hit && s2_hit_way === w.U))
+  }
 
   s2_passdown := s2_valid && ((s2_hit && io.resp.ready) || (!s2_hit && io.miss_req.ready))