RS,DCache: optimize timing and enable load fast wake up (#678)

* MainPipe/LoadPipe: disable fast wakeup when data sram is to be written

* RS: set EnableLoadFastWakeUp true

* LoadPipe: add perf cnt for disabling ld fast wakeup speculatively

* MainPipe: disable ld fast wakeup when s1 read data in MainPipe
Co-authored-by: Nzhanglinjuan <zhanglinjuan16@mails.ucas.ac.cn>

src/main/scala/xiangshan/XSCore.scala

@@ -65,7 +65,7 @@ case class XSCoreParameters
   CommitWidth: Int = 6,
   BrqSize: Int = 32,
   FtqSize: Int = 48,
-  EnableLoadFastWakeUp: Boolean = false, // NOTE: not supported now, make it false
+  EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false
   IssQueSize: Int = 12,
   NRPhyRegs: Int = 160,
   NRIntReadPorts: Int = 14,

src/main/scala/xiangshan/cache/DCacheWrapper.scala

@@ -89,6 +89,7 @@ class DCacheLoadIO extends DCacheWordIO
   // cycle 1: physical address: s1_paddr
   val s1_paddr = Output(UInt(PAddrBits.W))
   val s1_hit_way = Input(UInt(nWays.W))
+  val s1_disable_fast_wakeup = Input(Bool())
 }
 
 class DCacheLineIO extends DCacheBundle
@@ -218,6 +219,8 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
     // replay and nack not needed anymore
     // TODO: remove replay and nack
     ldu(w).io.nack := false.B
+
+    ldu(w).io.disable_ld_fast_wakeup := mainPipe.io.disable_ld_fast_wakeup
   }
 
   //----------------------------------------

src/main/scala/xiangshan/cache/LoadPipe.scala

@@ -31,6 +31,9 @@ class LoadPipe extends DCacheModule {
 
     // update state vec in replacement algo
     val replace_access = ValidIO(new ReplacementAccessBundle)
+
+    // load fast wakeup should be disabled when data read is not ready
+    val disable_ld_fast_wakeup = Input(Bool())
   })
 
   val s1_ready = Wire(Bool())
@@ -197,6 +200,7 @@ class LoadPipe extends DCacheModule {
   }
 
   io.lsu.s1_hit_way := s1_tag_match_way
+  io.lsu.s1_disable_fast_wakeup := io.disable_ld_fast_wakeup
   assert(RegNext(s1_ready && s2_ready), "load pipeline should never be blocked")
 
   // -------
@@ -224,4 +228,6 @@ class LoadPipe extends DCacheModule {
   XSPerf("load_replay_for_no_mshr", io.lsu.resp.fire() && resp.bits.replay && s2_nack_no_mshr)
   XSPerf("load_hit", io.lsu.resp.fire() && !resp.bits.miss)
   XSPerf("load_miss", io.lsu.resp.fire() && resp.bits.miss)
+  XSPerf("actual_ld_fast_wakeup", s1_fire && s1_tag_match && !io.disable_ld_fast_wakeup)
+  XSPerf("ideal_ld_fast_wakeup", io.data_read.fire() && s1_tag_match)
 }

src/main/scala/xiangshan/cache/MainPipe.scala

@@ -87,6 +87,9 @@ class MainPipe extends DCacheModule {
 
     // update state vec in replacement algo
     val replace_access = Flipped(Vec(LoadPipelineWidth, ValidIO(new ReplacementAccessBundle)))
+
+    // load fast wakeup should be disabled when data read is not ready
+    val disable_ld_fast_wakeup = Output(Bool())
   })
 
   def getMeta(encMeta: UInt): UInt = {
@@ -581,6 +584,10 @@ class MainPipe extends DCacheModule {
                          (!update_meta || io.meta_write.ready) &&
                          (!need_write_data || io.data_write.ready)*/
 
+  // Technically, load fast wakeup should be disabled when data_write.valid is true,
+  // but for timing purpose, we loose the condition to s3_valid, ignoring whether wb is ready or not.
+  io.disable_ld_fast_wakeup := need_write_data && s3_valid || s1_need_data && s1_valid
+
   // --------------------------------------------------------------------------------
   // update replacement policy
   val access_bundle = Wire(ValidIO(new ReplacementAccessBundle))

src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala

@@ -306,7 +306,7 @@ class LoadUnit extends XSModule with HasLoadHelper {
   // load_s2.io.dcacheResp.bits.data := Mux1H(RegNext(io.dcache.s1_hit_way), RegNext(io.dcache.s1_data))
   // assert(load_s2.io.dcacheResp.bits.data === io.dcache.resp.bits.data)
 
-  io.fastUop.valid := io.dcache.s1_hit_way.orR && load_s1.io.in.valid
+  io.fastUop.valid := io.dcache.s1_hit_way.orR && !io.dcache.s1_disable_fast_wakeup && load_s1.io.in.valid
   io.fastUop.bits := load_s1.io.out.bits.uop
 
   XSDebug(load_s0.io.out.valid,