DCache: optimize situations when ldu and mainPipe contend for read port (#688)

* DCacheWrapper: MainPipe use read port 1 to ease congestion

* MainPipe: do not consider congestion with ldu0 read when disabling fast wakeup

src/main/scala/xiangshan/cache/DCacheWrapper.scala

@@ -169,15 +169,15 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
 
   val metaReadArb = Module(new Arbiter(new L1MetaReadReq, MetaReadPortCount))
 
-  metaReadArb.io.in(LoadPipeMetaReadPort) <> ldu(0).io.meta_read
+  metaReadArb.io.in(LoadPipeMetaReadPort) <> ldu(LoadPipelineWidth - 1).io.meta_read
   metaReadArb.io.in(MainPipeMetaReadPort) <> mainPipe.io.meta_read
 
-  metaArray.io.read(0) <> metaReadArb.io.out
+  metaArray.io.read(LoadPipelineWidth - 1) <> metaReadArb.io.out
 
-  ldu(0).io.meta_resp    <>  metaArray.io.resp(0)
-  mainPipe.io.meta_resp  <>  metaArray.io.resp(0)
+  ldu(LoadPipelineWidth - 1).io.meta_resp <> metaArray.io.resp(LoadPipelineWidth - 1)
+  mainPipe.io.meta_resp <> metaArray.io.resp(LoadPipelineWidth - 1)
 
-  for (w <- 1 until LoadPipelineWidth) {
+  for (w <- 0 until (LoadPipelineWidth - 1)) {
     metaArray.io.read(w) <> ldu(w).io.meta_read
     ldu(w).io.meta_resp <> metaArray.io.resp(w)
   }
@@ -196,15 +196,15 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
 
   val dataReadArb = Module(new Arbiter(new L1DataReadReq, DataReadPortCount))
 
-  dataReadArb.io.in(LoadPipeDataReadPort)  <> ldu(0).io.data_read
+  dataReadArb.io.in(LoadPipeDataReadPort)  <> ldu(LoadPipelineWidth - 1).io.data_read
   dataReadArb.io.in(MainPipeDataReadPort)  <> mainPipe.io.data_read
 
-  dataArray.io.read(0) <> dataReadArb.io.out
+  dataArray.io.read(LoadPipelineWidth - 1) <> dataReadArb.io.out
 
-  dataArray.io.resp(0) <> ldu(0).io.data_resp
-  dataArray.io.resp(0) <> mainPipe.io.data_resp
+  dataArray.io.resp(LoadPipelineWidth - 1) <> ldu(LoadPipelineWidth - 1).io.data_resp
+  dataArray.io.resp(LoadPipelineWidth - 1) <> mainPipe.io.data_resp
 
-  for (w <- 1 until LoadPipelineWidth) {
+  for (w <- 0 until (LoadPipelineWidth - 1)) {
     dataArray.io.read(w) <> ldu(w).io.data_read
     dataArray.io.resp(w) <> ldu(w).io.data_resp
   }
@@ -220,7 +220,7 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
     // TODO: remove replay and nack
     ldu(w).io.nack := false.B
 
-    ldu(w).io.disable_ld_fast_wakeup := mainPipe.io.disable_ld_fast_wakeup
+    ldu(w).io.disable_ld_fast_wakeup := mainPipe.io.disable_ld_fast_wakeup(w)
   }
 
   //----------------------------------------

src/main/scala/xiangshan/cache/MainPipe.scala

@@ -89,7 +89,7 @@ class MainPipe extends DCacheModule {
     val replace_access = Flipped(Vec(LoadPipelineWidth, ValidIO(new ReplacementAccessBundle)))
 
     // load fast wakeup should be disabled when data read is not ready
-    val disable_ld_fast_wakeup = Output(Bool())
+    val disable_ld_fast_wakeup = Output(Vec(LoadPipelineWidth, Bool()))
   })
 
   def getMeta(encMeta: UInt): UInt = {
@@ -586,7 +586,10 @@ class MainPipe extends DCacheModule {
 
   // Technically, load fast wakeup should be disabled when data_write.valid is true,
   // but for timing purpose, we loose the condition to s3_valid, ignoring whether wb is ready or not.
-  io.disable_ld_fast_wakeup := need_write_data && s3_valid || s1_need_data && s1_valid
+  for (i <- 0 until (LoadPipelineWidth - 1)) {
+    io.disable_ld_fast_wakeup(i) := need_write_data && s3_valid
+  }
+  io.disable_ld_fast_wakeup(LoadPipelineWidth - 1) := need_write_data && s3_valid || s1_need_data && s1_valid
 
   // --------------------------------------------------------------------------------
   // update replacement policy