* timing: use single ported SRAMs, invalidating read responses on write
* performance:
-- shortening history length to accelerate training
-- use a predictor to reduce s2_redirects on FTB not hit

* IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still be occupied even when ICache miss

* Shut down IPrefetch

* IPrefetch: fix Hint not set PreferCache bit

* bump HuanCun

* IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still be occupied even when ICache miss

* Shut down IPrefetch

* IPrefetch: fix Hint not set PreferCache bit

* bump HuanCun

* Add Naive Instruction Prefetch

* Add instruction prefetch module in ICache

* send Hint to L2 (prefetched data stores in L2)

* Ftq: add prefetchPtr and prefetch interface

* Fix IPrefetch PMP Port preempting problem

* Fix merge conflict

* dcache: let ecc error and l2 corrupt raise load af

If CSR.smblockctl.cache_error_enable is disabled, ecc error and l2 corrupt
will not raise any exception.

* mem: enable cache error by default

* mem: support store ecc check, add ecc error csr

Support store / atom ecc check (early version)
Add ecc error csr to distingush ecc error and other access fault

Timing opt and unit tests to be added.

* memblock: regnext ptw's resp

* pmp: timing optimization from tlb.sram.ppn to pmp, add static pmp check

long latency: tlb's sram may be slow to gen ppn, ppn to pmp may be
long latency.
Solution: add static pmp check.

Fatal problem: pmp grain is smalled than TLB pages(4KB, 2MB, 1GB)
Solution: increase pmp'grain to 4K, for 4K entries, pre-check pmp and
store the result into tlb storage. For super pages, still dynamic check
that translation and check.

* pmp: change pmp grain to 4KB, change pma relative init config

* bump ready-to-run, update nemu so for pmp grain

* bump ready-to-run, update nemu so for pmp grain again

  update pmp unit test. The old test assumes that pmp grain is less than 512bit.

* ICache: add ReplacePipe for Probe & Release

* remove ProbeUnit

* Probe & Release enter ReplacePipe

* fix bugs when running Linux on MinimalConfig

* TODO: set conflict for ReplacePipe

* ICache: fix ReplacePipe invalid write bug

* chores: code clean up

* IFU: optimize timing

* PreDecode: separate into 2 module for timing optimization

* IBuffer: add enqEnable to replace valid for timing

* IFU/ITLB: optimize timing

* IFU: calculate cut_ptr in f1

* TLB: send req in f1 and wait resp in f2

* ICacheMainPipe: add tlb miss logic in s0

* Optimize IFU timing

* IFU: fix lastHalfRVI bug

* IFU: fix performance bug

* IFU: optimize MMIO commit timing

* IFU: optmize trigger timing and add frontendTrigger

* fix compile error

* IFU: fix mmio stuck bug

This commit optimizes the coding style and timing for hardware
performance counters.

By default, performance counters are RegNext(RegNext(_)).

* SoC: add axi4spliter

* pmp: add apply method to reduce loc

* pma: add PMA used in axi4's spliter

* Fix package import

* pma: re-write tl-pma, put tl-pma into AXI4Spliter

* pma: add memory mapped pma

* soc: rm dma port, rm axi4spliter, mv mmpma out of spliter

* Remove unused files

* update dma pma check port at SimTop.scala; update pll lock defalt value to 1
Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
Co-authored-by: Nrvcoresjw <shangjiawei@rvcore.com>

* ICache: add ReplacePipe for Probe & Release

* remove ProbeUnit

* Probe & Release enter ReplacePipe

* fix bugs when running Linux on MinimalConfig

* TODO: set conflict for ReplacePipe

* ICache: add Block logic for ReplacePipe

* ReplacePipe: change probe assert condition

* support Probe NToN (Probe not hit in ICache)

* ICache: fix a bug in meta_write_arb

* sbuffer: do flush correctly while draining sbuffer

* mem: disable EnableFastForward for timing reasons

* sbuffer: optimize forward mask gen timing

* dcache: block main pipe req if refill req is valid

Refill req comes from refill arbiter. There is not time left for index
conflict check. Now we block all main pipe req when refill
req comes from miss queue.

* dcache: delay some resp signals for better timing

* dcache: optimize wbq enq entry select timing

* dcache: decouple missq req.valid to valid & cancel

* valid is fast, it is used to select which miss req will be sent to
miss queue
* cancel can be slow to generate, it will cancel miss queue req in the
last moment

* sbuffer: optimize noSameBlockInflight check timing

* ICache: metaArray & dataArray use bank interleave

* ICache: add bank interleave

* ICache: add parity check for meta and data arrays

* IFU: fix bug in secondary miss

* secondary miss doesn't send miss request to miss queue

* ICache: write back cancled miss request

* ICacheMissEntry: add second miss merge

* deal with situations that this entry has been flushed, and the next miss req just
requests the same cachline.

* ICache: add acquireBlock and GrantAck support

* refact: move icache modules to frontend modules

* ICache: add release surport and meta coh

* ICache: change Get to AcquireBlock for A channel

* rebuild: change ICachePara package for other file

* ICache: add tilelogger for L1I

* ICahce: add ProbeQueue and Probe Process Unit

* ICache: add support for ProbeData

* ICahceParameter: change tag code to ECC

* ICahce: fix bugs in connect and ProbeUnit

* metaArray/dataArray responses are not connected

* ProbeUnit use reg so data and req are not synchronized

* RealeaseUnit: write back mata when voluntary

* Add ICache CacheInstruction

* move ICache to xiangshan.frontend.icache._

* ICache: add CacheOpDecoder

* change ICacheMissQueue to ICacheMissUnit

* ProbeUnit: fix meta data not latch bug

* IFU: delete releaseSlot and add missSlot

* IFU: fix bugs in missSlot state machine

* IFU: fix some bugs in miss Slot

* IFU: move out fetch to ICache Array logic

* ReleaseUnit: delete release write logic

* MissUnit: send Release to ReleaseUnit after GAck

* ICacheMainPipe: add mainpipe and stop logic

* when f3_ready is low, stop the pipeline

* IFU: move tlb and array access to mainpipe

* Modify Frontend and ICache top for mainpipe

* ReleaseUnit: add probe merge status register

* ICache: add victim info and release in mainpipe

* ICahche: add set-conflict logic

* Release: do not invalid meta after sending release

* bump Huancun: fix probe problem

* bump huancun for MinimalConfig combinational loop

* ICache: add LICENSE for new files

* Chore: remove debug code and add perf counter

* Bump huancun for bug fix

* Bump HuanCun for alias bug

* ICache: add dirty state for CliendMeta

This commit changes how isFreed is calculated. Instead of using
refCounter in the next, we compute it at this cycle and RegNext it.

* FDivSqrt: use hierarchy API to avoid dedup bug

* Dedup: use hartId from io port instead of core parameters

* Bump fudian

* fix a bug of wrongly discarding some new bits to be xored
* ghr should be longer in default config to avoid falsely overriding
* move TageBanks to top, and fix SC folded history config

* fix a bug of wrongly discarding some new bits to be xored
* ghr should be longer in default config to avoid falsely overriding
* move TageBanks to top, and fix SC folded history config

* difftest: add basic difftest features for releases

This commit adds basic difftest features for every release, no matter
it's for simulation or physical design. The macro SYNTHESIS is used to
skip these logics when synthesizing the design. This commit aims at
allowing designs for physical design to be verified.

* bump ready-to-run

* difftest: add int and fp writeback data

* modify the largest history length to be 65 in order to avoid
  2 level xors on speculative update

* update ittage parameters to be an optimized one

bpu: bring folded history into use, and use previous ghr to do difftest; move tage and ittage config to top

* use compressed info to do redirects
* implement folded history class

* tlb: timing optimization, when nWays is 1, divide hit and data(rm hitMux)

* pmp: add param to control leave ParallelMux into next cycle, default n.

The whole pmp match logic seems too long and takes more than
a half cycle.
Add this param and set it default false.

* tlb: timing optimization, when level enable, move ppn gen to first cycle

* tlb: fix bug of saveLevel and add it to TLBParameters

* disable log as default
* code clean up

* dcache: do not check readline rmask

This should opt bank_conflict check timing

* dcache: block replace if store s1 valid

It takes quite long to generate way_en in mainpipe s1. As a result,
use s1 way_en to judge if replace should be blocked will cause severe
timing problem

Now we simply block replace if mainpipe.s1.valid

Refill timing to be optmized later

* sbuffer: delay sbuffer enqueue for 1 cycle

With store queue growing larger, read data from datamodule nearly
costs a whole cycle. Hence we delay sbuffer enqueue for 1 cycle
for better timing.

* dcache: reduce probe queue size

* dcache: replace probe pipe req RRArbiter with Arbiter

* dcache: reduce writeback queue size for timing opt

* dcache: delay wbqueue enqueue req for 1 cycle

Addr enqueue req will compare its addr with addrs in all writeback
entries to check if it should be blocked. Delay enqueue req will
give that process more time.

* dcache: set default replacer to setplru

It does not change current design

* dcache: fix wbqueue req_delayed deadlock

We delayed writeback queue enq for 1 cycle, missQ req does not
depend on wbQ enqueue. As a result, missQ req may be blocked
in req_delayed. When grant comes, that req should also be updated

* dcache: remove outdated require

* dcache: replace missReqArb RRArbiter with Arbiter

* perf: add detailed histogram for low dcache latency

* dcache: fix wbqueue entry alloc logic

* dcache: opt probe req timing

In current design, resv_set is maintained in dcache. All probe req
will be blocked if that addr is in resv_set.

However, checking if that addr is in resv_set costs almost half a cycle,
which causes severe timing problem.

Now when we update update_resv_set, all probe reqs will be blocked
in the next cycle. It should give Probe reservation set addr compare an
independent cycle, which will lead to better timing

* Add cache ctrl node

* L2/L3: Reduce client dir size

* Ctrl: connect soft reset from L3 to core

* Add pll

* Config: seperate SocParams and CoreParams to get correct number of cores

* Bump huancun

* Add pll output

* Fix inclusive cache config

* Add one more pll ctrl reg

* Bump huancun

remove the old hard-wired pma and turn to pmp-like csr registers. the pma config is writen in pma register.
1. pma are m-priv csr, so only m-mode csrrw can change pma
2. even in m-mode, pma should be always checked, no matter lock or not
3. so carefully write pma, make sure not to "suicide"

* pma: add pmp-like pma, just module/bundle added, not to circuit

use reserved 2 bits as atomic and cached

* pma: add pmp-like pma into pmp module

pma have two more attribute than pmp
1. atmoic;
2. c/cache, if false, go to mmio.

pma uses 16+4 machine-level custom ready write csr.
pma will always be checked even in m-mode.

* pma: remove the old MemMap in tlb, mmio arrives next cycle

* pma: ptw raise af when mmio

* pma: fix bug of match's zip with last entry

* pma: fix bug of pass reset signal through method's parameter

strange bug, want to reset, pass reset signal to a method, does not
work.
import chisel3.Module.reset, the method can access reset it's self.

* pma: move some method to trait and fix bug of pma_init value

* pma: fix bug of pma init value assign way

* tlb: fix stupid bug that pf.ld not & fault_valid

* loadunit: fix bug that uop is flushed, pmp's dcache kill failed also

* ifu: mmio access needs f2_valid now

* loadunit: if mmio and have sent fastUop, flush pipe when commit

* storeunit: stu->lsq at stage1 and re-in lsq at stage2 to update mmio

* Add perf counters
* add reg from hpm counter source
* add print perfcounter enable

* mem: support ld-ld violation check
* mem: do not fast wakeup if ld vio check failed
* mem: disable ld-ld vio check after core reset